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target/arm: Hoist store to cs_base in cpu_get_tb_cpu_state
[qemu.git]
/
hw
/
riscv
/
Kconfig
blob
fb19b2df3a54e224314cb022d4923bb3d6c738e6
1
config HTIF
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bool
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config HART
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bool
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config SIFIVE
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bool
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select MSI_NONBROKEN
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config SIFIVE_E
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bool
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select HART
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select SIFIVE
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select UNIMP
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config SIFIVE_U
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bool
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select CADENCE
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select HART
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select SIFIVE
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select UNIMP
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config SPIKE
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bool
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select HART
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select HTIF
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select SIFIVE
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config RISCV_VIRT
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bool
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imply PCI_DEVICES
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imply TEST_DEVICES
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select PCI
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select HART
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select SERIAL
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select VIRTIO_MMIO
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select PCI_EXPRESS_GENERIC_BRIDGE
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select SIFIVE