hw/ppc_newworld.c

   1 /*
   2  * QEMU PowerPC CHRP (currently NewWorld PowerMac) hardware System Emulator
   3  *
   4  * Copyright (c) 2004-2007 Fabrice Bellard
   5  * Copyright (c) 2007 Jocelyn Mayer
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a copy
   8  * of this software and associated documentation files (the "Software"), to deal
   9  * in the Software without restriction, including without limitation the rights
  10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11  * copies of the Software, and to permit persons to whom the Software is
  12  * furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included in
  15  * all copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23  * THE SOFTWARE.
  24  *
  25  * PCI bus layout on a real G5 (U3 based):
  26  *
  27  * 0000:f0:0b.0 Host bridge [0600]: Apple Computer Inc. U3 AGP [106b:004b]
  28  * 0000:f0:10.0 VGA compatible controller [0300]: ATI Technologies Inc RV350 AP [Radeon 9600] [1002:4150]
  29  * 0001:00:00.0 Host bridge [0600]: Apple Computer Inc. CPC945 HT Bridge [106b:004a]
  30  * 0001:00:01.0 PCI bridge [0604]: Advanced Micro Devices [AMD] AMD-8131 PCI-X Bridge [1022:7450] (rev 12)
  31  * 0001:00:02.0 PCI bridge [0604]: Advanced Micro Devices [AMD] AMD-8131 PCI-X Bridge [1022:7450] (rev 12)
  32  * 0001:00:03.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0045]
  33  * 0001:00:04.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0046]
  34  * 0001:00:05.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0047]
  35  * 0001:00:06.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0048]
  36  * 0001:00:07.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0049]
  37  * 0001:01:07.0 Class [ff00]: Apple Computer Inc. K2 KeyLargo Mac/IO [106b:0041] (rev 20)
  38  * 0001:01:08.0 USB Controller [0c03]: Apple Computer Inc. K2 KeyLargo USB [106b:0040]
  39  * 0001:01:09.0 USB Controller [0c03]: Apple Computer Inc. K2 KeyLargo USB [106b:0040]
  40  * 0001:02:0b.0 USB Controller [0c03]: NEC Corporation USB [1033:0035] (rev 43)
  41  * 0001:02:0b.1 USB Controller [0c03]: NEC Corporation USB [1033:0035] (rev 43)
  42  * 0001:02:0b.2 USB Controller [0c03]: NEC Corporation USB 2.0 [1033:00e0] (rev 04)
  43  * 0001:03:0d.0 Class [ff00]: Apple Computer Inc. K2 ATA/100 [106b:0043]
  44  * 0001:03:0e.0 FireWire (IEEE 1394) [0c00]: Apple Computer Inc. K2 FireWire [106b:0042]
  45  * 0001:04:0f.0 Ethernet controller [0200]: Apple Computer Inc. K2 GMAC (Sun GEM) [106b:004c]
  46  * 0001:05:0c.0 IDE interface [0101]: Broadcom K2 SATA [1166:0240]
  47  *
  48  */
  49 #include "hw.h"
  50 #include "ppc.h"
  51 #include "ppc_mac.h"
  52 #include "adb.h"
  53 #include "mac_dbdma.h"
  54 #include "nvram.h"
  55 #include "pc.h"
  56 #include "pci.h"
  57 #include "usb-ohci.h"
  58 #include "net.h"
  59 #include "sysemu.h"
  60 #include "boards.h"
  61 #include "fw_cfg.h"
  62 #include "escc.h"
  63 #include "openpic.h"
  64 #include "ide.h"
  65 #include "loader.h"
  66 #include "elf.h"
  67 #include "kvm.h"
  68 #include "kvm_ppc.h"
  69 #include "hw/usb.h"
  70 #include "blockdev.h"
  71 #include "exec-memory.h"
  72
  73 #define MAX_IDE_BUS 2
  74 #define CFG_ADDR 0xf0000510
  75
  76 /* debug UniNorth */
  77 //#define DEBUG_UNIN
  78
  79 #ifdef DEBUG_UNIN
  80 #define UNIN_DPRINTF(fmt, ...)                                  \
  81     do { printf("UNIN: " fmt , ## __VA_ARGS__); } while (0)
  82 #else
  83 #define UNIN_DPRINTF(fmt, ...)
  84 #endif
  85
  86 /* UniN device */
  87 static void unin_write(void *opaque, target_phys_addr_t addr, uint64_t value,
  88                        unsigned size)
  89 {
  90     UNIN_DPRINTF("write addr " TARGET_FMT_plx " val %"PRIx64"\n", addr, value);
  91 }
  92
  93 static uint64_t unin_read(void *opaque, target_phys_addr_t addr, unsigned size)
  94 {
  95     uint32_t value;
  96
  97     value = 0;
  98     UNIN_DPRINTF("readl addr " TARGET_FMT_plx " val %x\n", addr, value);
  99
 100     return value;
 101 }
 102
 103 static const MemoryRegionOps unin_ops = {
 104     .read = unin_read,
 105     .write = unin_write,
 106     .endianness = DEVICE_NATIVE_ENDIAN,
 107 };
 108
 109 static int fw_cfg_boot_set(void *opaque, const char *boot_device)
 110 {
 111     fw_cfg_add_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
 112     return 0;
 113 }
 114
 115 static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
 116 {
 117     return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR;
 118 }
 119
 120 static target_phys_addr_t round_page(target_phys_addr_t addr)
 121 {
 122     return (addr + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK;
 123 }
 124
 125 /* PowerPC Mac99 hardware initialisation */
 126 static void ppc_core99_init (ram_addr_t ram_size,
 127                              const char *boot_device,
 128                              const char *kernel_filename,
 129                              const char *kernel_cmdline,
 130                              const char *initrd_filename,
 131                              const char *cpu_model)
 132 {
 133     CPUState *env = NULL;
 134     char *filename;
 135     qemu_irq *pic, **openpic_irqs;
 136     MemoryRegion *unin_memory = g_new(MemoryRegion, 1);
 137     int linux_boot, i;
 138     MemoryRegion *ram = g_new(MemoryRegion, 1), *bios = g_new(MemoryRegion, 1);
 139     target_phys_addr_t kernel_base, initrd_base, cmdline_base = 0;
 140     long kernel_size, initrd_size;
 141     PCIBus *pci_bus;
 142     MacIONVRAMState *nvr;
 143     int bios_size;
 144     MemoryRegion *pic_mem, *dbdma_mem, *cuda_mem, *escc_mem;
 145     MemoryRegion *escc_bar = g_new(MemoryRegion, 1);
 146     MemoryRegion *ide_mem[3];
 147     int ppc_boot_device;
 148     DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
 149     void *fw_cfg;
 150     void *dbdma;
 151     int machine_arch;
 152
 153     linux_boot = (kernel_filename != NULL);
 154
 155     /* init CPUs */
 156     if (cpu_model == NULL)
 157 #ifdef TARGET_PPC64
 158         cpu_model = "970fx";
 159 #else
 160         cpu_model = "G4";
 161 #endif
 162     for (i = 0; i < smp_cpus; i++) {
 163         env = cpu_init(cpu_model);
 164         if (!env) {
 165             fprintf(stderr, "Unable to find PowerPC CPU definition\n");
 166             exit(1);
 167         }
 168         /* Set time-base frequency to 100 Mhz */
 169         cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL);
 170         qemu_register_reset((QEMUResetHandler*)&cpu_reset, env);
 171     }
 172
 173     /* allocate RAM */
 174     memory_region_init_ram(ram, NULL, "ppc_core99.ram", ram_size);
 175     memory_region_add_subregion(get_system_memory(), 0, ram);
 176
 177     /* allocate and load BIOS */
 178     memory_region_init_ram(bios, NULL, "ppc_core99.bios", BIOS_SIZE);
 179     if (bios_name == NULL)
 180         bios_name = PROM_FILENAME;
 181     filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
 182     memory_region_set_readonly(bios, true);
 183     memory_region_add_subregion(get_system_memory(), PROM_ADDR, bios);
 184
 185     /* Load OpenBIOS (ELF) */
 186     if (filename) {
 187         bios_size = load_elf(filename, NULL, NULL, NULL,
 188                              NULL, NULL, 1, ELF_MACHINE, 0);
 189
 190         g_free(filename);
 191     } else {
 192         bios_size = -1;
 193     }
 194     if (bios_size < 0 || bios_size > BIOS_SIZE) {
 195         hw_error("qemu: could not load PowerPC bios '%s'\n", bios_name);
 196         exit(1);
 197     }
 198
 199     if (linux_boot) {
 200         uint64_t lowaddr = 0;
 201         int bswap_needed;
 202
 203 #ifdef BSWAP_NEEDED
 204         bswap_needed = 1;
 205 #else
 206         bswap_needed = 0;
 207 #endif
 208         kernel_base = KERNEL_LOAD_ADDR;
 209
 210         kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL,
 211                                NULL, &lowaddr, NULL, 1, ELF_MACHINE, 0);
 212         if (kernel_size < 0)
 213             kernel_size = load_aout(kernel_filename, kernel_base,
 214                                     ram_size - kernel_base, bswap_needed,
 215                                     TARGET_PAGE_SIZE);
 216         if (kernel_size < 0)
 217             kernel_size = load_image_targphys(kernel_filename,
 218                                               kernel_base,
 219                                               ram_size - kernel_base);
 220         if (kernel_size < 0) {
 221             hw_error("qemu: could not load kernel '%s'\n", kernel_filename);
 222             exit(1);
 223         }
 224         /* load initrd */
 225         if (initrd_filename) {
 226             initrd_base = round_page(kernel_base + kernel_size + KERNEL_GAP);
 227             initrd_size = load_image_targphys(initrd_filename, initrd_base,
 228                                               ram_size - initrd_base);
 229             if (initrd_size < 0) {
 230                 hw_error("qemu: could not load initial ram disk '%s'\n",
 231                          initrd_filename);
 232                 exit(1);
 233             }
 234             cmdline_base = round_page(initrd_base + initrd_size);
 235         } else {
 236             initrd_base = 0;
 237             initrd_size = 0;
 238             cmdline_base = round_page(kernel_base + kernel_size + KERNEL_GAP);
 239         }
 240         ppc_boot_device = 'm';
 241     } else {
 242         kernel_base = 0;
 243         kernel_size = 0;
 244         initrd_base = 0;
 245         initrd_size = 0;
 246         ppc_boot_device = '\0';
 247         /* We consider that NewWorld PowerMac never have any floppy drive
 248          * For now, OHW cannot boot from the network.
 249          */
 250         for (i = 0; boot_device[i] != '\0'; i++) {
 251             if (boot_device[i] >= 'c' && boot_device[i] <= 'f') {
 252                 ppc_boot_device = boot_device[i];
 253                 break;
 254             }
 255         }
 256         if (ppc_boot_device == '\0') {
 257             fprintf(stderr, "No valid boot device for Mac99 machine\n");
 258             exit(1);
 259         }
 260     }
 261
 262     /* Register 8 MB of ISA IO space */
 263     isa_mmio_init(0xf2000000, 0x00800000);
 264
 265     /* UniN init */
 266     memory_region_init_io(unin_memory, &unin_ops, NULL, "unin", 0x1000);
 267     memory_region_add_subregion(get_system_memory(), 0xf8000000, unin_memory);
 268
 269     openpic_irqs = g_malloc0(smp_cpus * sizeof(qemu_irq *));
 270     openpic_irqs[0] =
 271         g_malloc0(smp_cpus * sizeof(qemu_irq) * OPENPIC_OUTPUT_NB);
 272     for (i = 0; i < smp_cpus; i++) {
 273         /* Mac99 IRQ connection between OpenPIC outputs pins
 274          * and PowerPC input pins
 275          */
 276         switch (PPC_INPUT(env)) {
 277         case PPC_FLAGS_INPUT_6xx:
 278             openpic_irqs[i] = openpic_irqs[0] + (i * OPENPIC_OUTPUT_NB);
 279             openpic_irqs[i][OPENPIC_OUTPUT_INT] =
 280                 ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT];
 281             openpic_irqs[i][OPENPIC_OUTPUT_CINT] =
 282                 ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT];
 283             openpic_irqs[i][OPENPIC_OUTPUT_MCK] =
 284                 ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_MCP];
 285             /* Not connected ? */
 286             openpic_irqs[i][OPENPIC_OUTPUT_DEBUG] = NULL;
 287             /* Check this */
 288             openpic_irqs[i][OPENPIC_OUTPUT_RESET] =
 289                 ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_HRESET];
 290             break;
 291 #if defined(TARGET_PPC64)
 292         case PPC_FLAGS_INPUT_970:
 293             openpic_irqs[i] = openpic_irqs[0] + (i * OPENPIC_OUTPUT_NB);
 294             openpic_irqs[i][OPENPIC_OUTPUT_INT] =
 295                 ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_INT];
 296             openpic_irqs[i][OPENPIC_OUTPUT_CINT] =
 297                 ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_INT];
 298             openpic_irqs[i][OPENPIC_OUTPUT_MCK] =
 299                 ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_MCP];
 300             /* Not connected ? */
 301             openpic_irqs[i][OPENPIC_OUTPUT_DEBUG] = NULL;
 302             /* Check this */
 303             openpic_irqs[i][OPENPIC_OUTPUT_RESET] =
 304                 ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_HRESET];
 305             break;
 306 #endif /* defined(TARGET_PPC64) */
 307         default:
 308             hw_error("Bus model not supported on mac99 machine\n");
 309             exit(1);
 310         }
 311     }
 312     pic = openpic_init(NULL, &pic_mem, smp_cpus, openpic_irqs, NULL);
 313     if (PPC_INPUT(env) == PPC_FLAGS_INPUT_970) {
 314         /* 970 gets a U3 bus */
 315         pci_bus = pci_pmac_u3_init(pic, get_system_memory(), get_system_io());
 316         machine_arch = ARCH_MAC99_U3;
 317     } else {
 318         pci_bus = pci_pmac_init(pic, get_system_memory(), get_system_io());
 319         machine_arch = ARCH_MAC99;
 320     }
 321     /* init basic PC hardware */
 322     pci_vga_init(pci_bus);
 323
 324     escc_mem = escc_init(0, pic[0x25], pic[0x24],
 325                          serial_hds[0], serial_hds[1], ESCC_CLOCK, 4);
 326     memory_region_init_alias(escc_bar, "escc-bar",
 327                              escc_mem, 0, memory_region_size(escc_mem));
 328
 329     for(i = 0; i < nb_nics; i++)
 330         pci_nic_init_nofail(&nd_table[i], "ne2k_pci", NULL);
 331
 332     ide_drive_get(hd, MAX_IDE_BUS);
 333     dbdma = DBDMA_init(&dbdma_mem);
 334
 335     /* We only emulate 2 out of 3 IDE controllers for now */
 336     ide_mem[0] = NULL;
 337     ide_mem[1] = pmac_ide_init(hd, pic[0x0d], dbdma, 0x16, pic[0x02]);
 338     ide_mem[2] = pmac_ide_init(&hd[MAX_IDE_DEVS], pic[0x0e], dbdma, 0x1a, pic[0x02]);
 339
 340     /* cuda also initialize ADB */
 341     if (machine_arch == ARCH_MAC99_U3) {
 342         usb_enabled = 1;
 343     }
 344     cuda_init(&cuda_mem, pic[0x19]);
 345
 346     adb_kbd_init(&adb_bus);
 347     adb_mouse_init(&adb_bus);
 348
 349     macio_init(pci_bus, PCI_DEVICE_ID_APPLE_UNI_N_KEYL, 0, pic_mem,
 350                dbdma_mem, cuda_mem, NULL, 3, ide_mem, escc_bar);
 351
 352     if (usb_enabled) {
 353         usb_ohci_init_pci(pci_bus, -1);
 354     }
 355
 356     /* U3 needs to use USB for input because Linux doesn't support via-cuda
 357        on PPC64 */
 358     if (machine_arch == ARCH_MAC99_U3) {
 359         usbdevice_create("keyboard");
 360         usbdevice_create("mouse");
 361     }
 362
 363     if (graphic_depth != 15 && graphic_depth != 32 && graphic_depth != 8)
 364         graphic_depth = 15;
 365
 366     /* The NewWorld NVRAM is not located in the MacIO device */
 367     nvr = macio_nvram_init(0x2000, 1);
 368     pmac_format_nvram_partition(nvr, 0x2000);
 369     macio_nvram_setup_bar(nvr, get_system_memory(), 0xFFF04000);
 370     /* No PCI init: the BIOS will do it */
 371
 372     fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
 373     fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
 374     fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
 375     fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, machine_arch);
 376     fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_base);
 377     fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
 378     if (kernel_cmdline) {
 379         fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, cmdline_base);
 380         pstrcpy_targphys("cmdline", cmdline_base, TARGET_PAGE_SIZE, kernel_cmdline);
 381     } else {
 382         fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
 383     }
 384     fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_base);
 385     fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
 386     fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, ppc_boot_device);
 387
 388     fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_WIDTH, graphic_width);
 389     fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_HEIGHT, graphic_height);
 390     fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_DEPTH, graphic_depth);
 391
 392     fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_IS_KVM, kvm_enabled());
 393     if (kvm_enabled()) {
 394 #ifdef CONFIG_KVM
 395         uint8_t *hypercall;
 396
 397         fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, kvmppc_get_tbfreq());
 398         hypercall = g_malloc(16);
 399         kvmppc_get_hypercall(env, hypercall, 16);
 400         fw_cfg_add_bytes(fw_cfg, FW_CFG_PPC_KVM_HC, hypercall, 16);
 401         fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_KVM_PID, getpid());
 402 #endif
 403     } else {
 404         fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, get_ticks_per_sec());
 405     }
 406
 407     qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
 408 }
 409
 410 static QEMUMachine core99_machine = {
 411     .name = "mac99",
 412     .desc = "Mac99 based PowerMAC",
 413     .init = ppc_core99_init,
 414     .max_cpus = MAX_CPUS,
 415 #ifdef TARGET_PPC64
 416     .is_default = 1,
 417 #endif
 418 };
 419
 420 static void core99_machine_init(void)
 421 {
 422     qemu_register_machine(&core99_machine);
 423 }
 424
 425 machine_init(core99_machine_init);