target-ppc/misc_helper.c

   1 /*
   2  * Miscellaneous PowerPC emulation helpers for QEMU.
   3  *
   4  *  Copyright (c) 2003-2007 Jocelyn Mayer
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #include "cpu.h"
  20 #include "exec/helper-proto.h"
  21
  22 #include "helper_regs.h"
  23
  24 /*****************************************************************************/
  25 /* SPR accesses */
  26 void helper_load_dump_spr(CPUPPCState *env, uint32_t sprn)
  27 {
  28     qemu_log("Read SPR %d %03x => " TARGET_FMT_lx "\n", sprn, sprn,
  29              env->spr[sprn]);
  30 }
  31
  32 void helper_store_dump_spr(CPUPPCState *env, uint32_t sprn)
  33 {
  34     qemu_log("Write SPR %d %03x <= " TARGET_FMT_lx "\n", sprn, sprn,
  35              env->spr[sprn]);
  36 }
  37
  38 #ifdef TARGET_PPC64
  39 static void raise_fu_exception(CPUPPCState *env, uint32_t bit,
  40                                uint32_t sprn, uint32_t cause)
  41 {
  42     qemu_log("Facility SPR %d is unavailable (SPR FSCR:%d)\n", sprn, bit);
  43
  44     env->spr[SPR_FSCR] &= ~((target_ulong)FSCR_IC_MASK << FSCR_IC_POS);
  45     cause &= FSCR_IC_MASK;
  46     env->spr[SPR_FSCR] |= (target_ulong)cause << FSCR_IC_POS;
  47
  48     helper_raise_exception_err(env, POWERPC_EXCP_FU, 0);
  49 }
  50 #endif
  51
  52 void helper_fscr_facility_check(CPUPPCState *env, uint32_t bit,
  53                                 uint32_t sprn, uint32_t cause)
  54 {
  55 #ifdef TARGET_PPC64
  56     if (env->spr[SPR_FSCR] & (1ULL << bit)) {
  57         /* Facility is enabled, continue */
  58         return;
  59     }
  60     raise_fu_exception(env, bit, sprn, cause);
  61 #endif
  62 }
  63
  64 void helper_msr_facility_check(CPUPPCState *env, uint32_t bit,
  65                                uint32_t sprn, uint32_t cause)
  66 {
  67 #ifdef TARGET_PPC64
  68     if (env->msr & (1ULL << bit)) {
  69         /* Facility is enabled, continue */
  70         return;
  71     }
  72     raise_fu_exception(env, bit, sprn, cause);
  73 #endif
  74 }
  75
  76 #if !defined(CONFIG_USER_ONLY)
  77
  78 void helper_store_sdr1(CPUPPCState *env, target_ulong val)
  79 {
  80     PowerPCCPU *cpu = ppc_env_get_cpu(env);
  81
  82     if (!env->external_htab) {
  83         if (env->spr[SPR_SDR1] != val) {
  84             ppc_store_sdr1(env, val);
  85             tlb_flush(CPU(cpu), 1);
  86         }
  87     }
  88 }
  89
  90 void helper_store_hid0_601(CPUPPCState *env, target_ulong val)
  91 {
  92     target_ulong hid0;
  93
  94     hid0 = env->spr[SPR_HID0];
  95     if ((val ^ hid0) & 0x00000008) {
  96         /* Change current endianness */
  97         env->hflags &= ~(1 << MSR_LE);
  98         env->hflags_nmsr &= ~(1 << MSR_LE);
  99         env->hflags_nmsr |= (1 << MSR_LE) & (((val >> 3) & 1) << MSR_LE);
 100         env->hflags |= env->hflags_nmsr;
 101         qemu_log("%s: set endianness to %c => " TARGET_FMT_lx "\n", __func__,
 102                  val & 0x8 ? 'l' : 'b', env->hflags);
 103     }
 104     env->spr[SPR_HID0] = (uint32_t)val;
 105 }
 106
 107 void helper_store_403_pbr(CPUPPCState *env, uint32_t num, target_ulong value)
 108 {
 109     PowerPCCPU *cpu = ppc_env_get_cpu(env);
 110
 111     if (likely(env->pb[num] != value)) {
 112         env->pb[num] = value;
 113         /* Should be optimized */
 114         tlb_flush(CPU(cpu), 1);
 115     }
 116 }
 117
 118 void helper_store_40x_dbcr0(CPUPPCState *env, target_ulong val)
 119 {
 120     store_40x_dbcr0(env, val);
 121 }
 122
 123 void helper_store_40x_sler(CPUPPCState *env, target_ulong val)
 124 {
 125     store_40x_sler(env, val);
 126 }
 127 #endif
 128 /*****************************************************************************/
 129 /* PowerPC 601 specific instructions (POWER bridge) */
 130
 131 target_ulong helper_clcs(CPUPPCState *env, uint32_t arg)
 132 {
 133     switch (arg) {
 134     case 0x0CUL:
 135         /* Instruction cache line size */
 136         return env->icache_line_size;
 137         break;
 138     case 0x0DUL:
 139         /* Data cache line size */
 140         return env->dcache_line_size;
 141         break;
 142     case 0x0EUL:
 143         /* Minimum cache line size */
 144         return (env->icache_line_size < env->dcache_line_size) ?
 145             env->icache_line_size : env->dcache_line_size;
 146         break;
 147     case 0x0FUL:
 148         /* Maximum cache line size */
 149         return (env->icache_line_size > env->dcache_line_size) ?
 150             env->icache_line_size : env->dcache_line_size;
 151         break;
 152     default:
 153         /* Undefined */
 154         return 0;
 155         break;
 156     }
 157 }
 158
 159 /*****************************************************************************/
 160 /* Special registers manipulation */
 161
 162 /* GDBstub can read and write MSR... */
 163 void ppc_store_msr(CPUPPCState *env, target_ulong value)
 164 {
 165     hreg_store_msr(env, value, 0);
 166 }