target-microblaze: Allow the stack protection to be disabled
[qemu.git] / target-ppc / helper_regs.h
blob271fddf17f0aa4862ef6503f679bf35c0b3c4315
1 /*
2 * PowerPC emulation special registers manipulation helpers for qemu.
4 * Copyright (c) 2003-2007 Jocelyn Mayer
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 #if !defined(__HELPER_REGS_H__)
21 #define __HELPER_REGS_H__
23 /* Swap temporary saved registers with GPRs */
24 static inline void hreg_swap_gpr_tgpr(CPUPPCState *env)
26 target_ulong tmp;
28 tmp = env->gpr[0];
29 env->gpr[0] = env->tgpr[0];
30 env->tgpr[0] = tmp;
31 tmp = env->gpr[1];
32 env->gpr[1] = env->tgpr[1];
33 env->tgpr[1] = tmp;
34 tmp = env->gpr[2];
35 env->gpr[2] = env->tgpr[2];
36 env->tgpr[2] = tmp;
37 tmp = env->gpr[3];
38 env->gpr[3] = env->tgpr[3];
39 env->tgpr[3] = tmp;
42 static inline void hreg_compute_mem_idx(CPUPPCState *env)
44 /* Precompute MMU index */
45 if (msr_pr == 0 && msr_hv != 0) {
46 env->mmu_idx = 2;
47 } else {
48 env->mmu_idx = 1 - msr_pr;
52 static inline void hreg_compute_hflags(CPUPPCState *env)
54 target_ulong hflags_mask;
56 /* We 'forget' FE0 & FE1: we'll never generate imprecise exceptions */
57 hflags_mask = (1 << MSR_VR) | (1 << MSR_AP) | (1 << MSR_SA) |
58 (1 << MSR_PR) | (1 << MSR_FP) | (1 << MSR_SE) | (1 << MSR_BE) |
59 (1 << MSR_LE) | (1 << MSR_VSX);
60 hflags_mask |= (1ULL << MSR_CM) | (1ULL << MSR_SF) | MSR_HVB;
61 hreg_compute_mem_idx(env);
62 env->hflags = env->msr & hflags_mask;
63 /* Merge with hflags coming from other registers */
64 env->hflags |= env->hflags_nmsr;
67 static inline int hreg_store_msr(CPUPPCState *env, target_ulong value,
68 int alter_hv)
70 int excp;
71 #if !defined(CONFIG_USER_ONLY)
72 CPUState *cs = CPU(ppc_env_get_cpu(env));
73 #endif
75 excp = 0;
76 value &= env->msr_mask;
77 #if !defined(CONFIG_USER_ONLY)
78 if (!alter_hv) {
79 /* mtmsr cannot alter the hypervisor state */
80 value &= ~MSR_HVB;
81 value |= env->msr & MSR_HVB;
83 if (((value >> MSR_IR) & 1) != msr_ir ||
84 ((value >> MSR_DR) & 1) != msr_dr) {
85 /* Flush all tlb when changing translation mode */
86 tlb_flush(cs, 1);
87 excp = POWERPC_EXCP_NONE;
88 cs->interrupt_request |= CPU_INTERRUPT_EXITTB;
90 if (unlikely((env->flags & POWERPC_FLAG_TGPR) &&
91 ((value ^ env->msr) & (1 << MSR_TGPR)))) {
92 /* Swap temporary saved registers with GPRs */
93 hreg_swap_gpr_tgpr(env);
95 if (unlikely((value >> MSR_EP) & 1) != msr_ep) {
96 /* Change the exception prefix on PowerPC 601 */
97 env->excp_prefix = ((value >> MSR_EP) & 1) * 0xFFF00000;
99 #endif
100 env->msr = value;
101 hreg_compute_hflags(env);
102 #if !defined(CONFIG_USER_ONLY)
103 if (unlikely(msr_pow == 1)) {
104 if (!env->pending_interrupts && (*env->check_pow)(env)) {
105 cs->halted = 1;
106 excp = EXCP_HALTED;
109 #endif
111 return excp;
114 #endif /* !defined(__HELPER_REGS_H__) */