pcihp: make pci_read() mmio calback compatible with legacy ACPI hotplug
[qemu.git] / hw / acpi / pcihp.c
blob974f01c114593c849f40c2ae54a36a3fd7d45624
1 /*
2 * QEMU<->ACPI BIOS PCI hotplug interface
4 * QEMU supports PCI hotplug via ACPI. This module
5 * implements the interface between QEMU and the ACPI BIOS.
6 * Interface specification - see docs/specs/acpi_pci_hotplug.txt
8 * Copyright (c) 2013, Red Hat Inc, Michael S. Tsirkin (mst@redhat.com)
9 * Copyright (c) 2006 Fabrice Bellard
11 * This library is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU Lesser General Public
13 * License version 2 as published by the Free Software Foundation.
15 * This library is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 * Lesser General Public License for more details.
20 * You should have received a copy of the GNU Lesser General Public
21 * License along with this library; if not, see <http://www.gnu.org/licenses/>
23 * Contributions after 2012-01-13 are licensed under the terms of the
24 * GNU GPL, version 2 or (at your option) any later version.
27 #include "hw/acpi/pcihp.h"
29 #include "hw/hw.h"
30 #include "hw/i386/pc.h"
31 #include "hw/pci/pci.h"
32 #include "hw/acpi/acpi.h"
33 #include "sysemu/sysemu.h"
34 #include "qemu/range.h"
35 #include "exec/ioport.h"
36 #include "exec/address-spaces.h"
37 #include "hw/pci/pci_bus.h"
38 #include "qom/qom-qobject.h"
39 #include "qapi/qmp/qint.h"
41 //#define DEBUG
43 #ifdef DEBUG
44 # define ACPI_PCIHP_DPRINTF(format, ...) printf(format, ## __VA_ARGS__)
45 #else
46 # define ACPI_PCIHP_DPRINTF(format, ...) do { } while (0)
47 #endif
49 #define PCI_HOTPLUG_ADDR 0xae00
50 #define PCI_HOTPLUG_SIZE 0x0014
51 #define PCI_UP_BASE 0x0000
52 #define PCI_DOWN_BASE 0x0004
53 #define PCI_EJ_BASE 0x0008
54 #define PCI_RMV_BASE 0x000c
55 #define PCI_SEL_BASE 0x0010
57 typedef struct AcpiPciHpFind {
58 int bsel;
59 PCIBus *bus;
60 } AcpiPciHpFind;
62 static int acpi_pcihp_get_bsel(PCIBus *bus)
64 QObject *o = object_property_get_qobject(OBJECT(bus),
65 ACPI_PCIHP_PROP_BSEL, NULL);
66 int64_t bsel = -1;
67 if (o) {
68 bsel = qint_get_int(qobject_to_qint(o));
70 if (bsel < 0) {
71 return -1;
73 return bsel;
76 static void acpi_pcihp_test_hotplug_bus(PCIBus *bus, void *opaque)
78 AcpiPciHpFind *find = opaque;
79 if (find->bsel == acpi_pcihp_get_bsel(bus)) {
80 find->bus = bus;
84 static PCIBus *acpi_pcihp_find_hotplug_bus(AcpiPciHpState *s, int bsel)
86 AcpiPciHpFind find = { .bsel = bsel, .bus = NULL };
88 if (bsel < 0) {
89 return NULL;
92 pci_for_each_bus(s->root, acpi_pcihp_test_hotplug_bus, &find);
94 /* Make bsel 0 eject root bus if bsel property is not set,
95 * for compatibility with non acpi setups.
96 * TODO: really needed?
98 if (!bsel && !find.bus) {
99 find.bus = s->root;
101 return find.bus;
104 static bool acpi_pcihp_pc_no_hotplug(AcpiPciHpState *s, PCIDevice *dev)
106 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev);
108 * ACPI doesn't allow hotplug of bridge devices. Don't allow
109 * hot-unplug of bridge devices unless they were added by hotplug
110 * (and so, not described by acpi).
112 return (pc->is_bridge && !dev->qdev.hotplugged) || pc->no_hotplug;
115 static void acpi_pcihp_eject_slot(AcpiPciHpState *s, unsigned bsel, unsigned slots)
117 BusChild *kid, *next;
118 int slot = ffs(slots) - 1;
119 PCIBus *bus = acpi_pcihp_find_hotplug_bus(s, bsel);
121 if (!bus) {
122 return;
125 /* Mark request as complete */
126 s->acpi_pcihp_pci_status[bsel].down &= ~(1U << slot);
127 s->acpi_pcihp_pci_status[bsel].up &= ~(1U << slot);
129 QTAILQ_FOREACH_SAFE(kid, &bus->qbus.children, sibling, next) {
130 DeviceState *qdev = kid->child;
131 PCIDevice *dev = PCI_DEVICE(qdev);
132 if (PCI_SLOT(dev->devfn) == slot) {
133 if (!acpi_pcihp_pc_no_hotplug(s, dev)) {
134 object_unparent(OBJECT(qdev));
140 static void acpi_pcihp_update_hotplug_bus(AcpiPciHpState *s, int bsel)
142 BusChild *kid, *next;
143 PCIBus *bus = acpi_pcihp_find_hotplug_bus(s, bsel);
145 /* Execute any pending removes during reset */
146 while (s->acpi_pcihp_pci_status[bsel].down) {
147 acpi_pcihp_eject_slot(s, bsel, s->acpi_pcihp_pci_status[bsel].down);
150 s->acpi_pcihp_pci_status[bsel].hotplug_enable = ~0;
152 if (!bus) {
153 return;
155 QTAILQ_FOREACH_SAFE(kid, &bus->qbus.children, sibling, next) {
156 DeviceState *qdev = kid->child;
157 PCIDevice *pdev = PCI_DEVICE(qdev);
158 int slot = PCI_SLOT(pdev->devfn);
160 if (acpi_pcihp_pc_no_hotplug(s, pdev)) {
161 s->acpi_pcihp_pci_status[bsel].hotplug_enable &= ~(1U << slot);
166 static void acpi_pcihp_update(AcpiPciHpState *s)
168 int i;
170 for (i = 0; i < ACPI_PCIHP_MAX_HOTPLUG_BUS; ++i) {
171 acpi_pcihp_update_hotplug_bus(s, i);
175 void acpi_pcihp_reset(AcpiPciHpState *s)
177 acpi_pcihp_update(s);
180 int acpi_pcihp_device_hotplug(AcpiPciHpState *s, PCIDevice *dev,
181 PCIHotplugState state)
183 int slot = PCI_SLOT(dev->devfn);
184 int bsel = acpi_pcihp_get_bsel(dev->bus);
185 if (bsel < 0) {
186 return -1;
189 /* Don't send event when device is enabled during qemu machine creation:
190 * it is present on boot, no hotplug event is necessary. We do send an
191 * event when the device is disabled later. */
192 if (state == PCI_COLDPLUG_ENABLED) {
193 return 0;
196 if (state == PCI_HOTPLUG_ENABLED) {
197 s->acpi_pcihp_pci_status[bsel].up |= (1U << slot);
198 } else {
199 s->acpi_pcihp_pci_status[bsel].down |= (1U << slot);
202 return 0;
205 static uint64_t pci_read(void *opaque, hwaddr addr, unsigned int size)
207 AcpiPciHpState *s = opaque;
208 uint32_t val = 0;
209 int bsel = s->hotplug_select;
211 if (bsel < 0 || bsel > ACPI_PCIHP_MAX_HOTPLUG_BUS) {
212 return 0;
215 switch (addr) {
216 case PCI_UP_BASE:
217 val = s->acpi_pcihp_pci_status[bsel].up;
218 if (!s->legacy_piix) {
219 s->acpi_pcihp_pci_status[bsel].up = 0;
221 ACPI_PCIHP_DPRINTF("pci_up_read %" PRIu32 "\n", val);
222 break;
223 case PCI_DOWN_BASE:
224 val = s->acpi_pcihp_pci_status[bsel].down;
225 ACPI_PCIHP_DPRINTF("pci_down_read %" PRIu32 "\n", val);
226 break;
227 case PCI_EJ_BASE:
228 /* No feature defined yet */
229 ACPI_PCIHP_DPRINTF("pci_features_read %" PRIu32 "\n", val);
230 break;
231 case PCI_RMV_BASE:
232 val = s->acpi_pcihp_pci_status[bsel].hotplug_enable;
233 ACPI_PCIHP_DPRINTF("pci_rmv_read %" PRIu32 "\n", val);
234 break;
235 case PCI_SEL_BASE:
236 val = s->hotplug_select;
237 ACPI_PCIHP_DPRINTF("pci_sel_read %" PRIu32 "\n", val);
238 default:
239 break;
242 return val;
245 static void pci_write(void *opaque, hwaddr addr, uint64_t data,
246 unsigned int size)
248 AcpiPciHpState *s = opaque;
249 switch (addr) {
250 case PCI_EJ_BASE:
251 if (s->hotplug_select >= ACPI_PCIHP_MAX_HOTPLUG_BUS) {
252 break;
254 acpi_pcihp_eject_slot(s, s->hotplug_select, data);
255 ACPI_PCIHP_DPRINTF("pciej write %" HWADDR_PRIx " <== %" PRIu64 "\n",
256 addr, data);
257 break;
258 case PCI_SEL_BASE:
259 s->hotplug_select = data;
260 ACPI_PCIHP_DPRINTF("pcisel write %" HWADDR_PRIx " <== %" PRIu64 "\n",
261 addr, data);
262 default:
263 break;
267 static const MemoryRegionOps acpi_pcihp_io_ops = {
268 .read = pci_read,
269 .write = pci_write,
270 .endianness = DEVICE_LITTLE_ENDIAN,
271 .valid = {
272 .min_access_size = 4,
273 .max_access_size = 4,
277 void acpi_pcihp_init(AcpiPciHpState *s, PCIBus *root_bus,
278 MemoryRegion *address_space_io, bool bridges_enabled)
280 s->root= root_bus;
281 s->legacy_piix = !bridges_enabled;
282 memory_region_init_io(&s->io, NULL, &acpi_pcihp_io_ops, s,
283 "acpi-pci-hotplug",
284 PCI_HOTPLUG_SIZE);
285 memory_region_add_subregion(address_space_io, PCI_HOTPLUG_ADDR, &s->io);
288 const VMStateDescription vmstate_acpi_pcihp_pci_status = {
289 .name = "acpi_pcihp_pci_status",
290 .version_id = 1,
291 .minimum_version_id = 1,
292 .minimum_version_id_old = 1,
293 .fields = (VMStateField []) {
294 VMSTATE_UINT32(up, AcpiPciHpPciStatus),
295 VMSTATE_UINT32(down, AcpiPciHpPciStatus),
296 VMSTATE_END_OF_LIST()