include/disas/dis-asm.h

   1 /* Interface between the opcode library and its callers.
   2    Written by Cygnus Support, 1993.
   3
   4    The opcode library (libopcodes.a) provides instruction decoders for
   5    a large variety of instruction sets, callable with an identical
   6    interface, for making instruction-processing programs more independent
   7    of the instruction set being processed.  */
   8
   9 #ifndef DISAS_DIS_ASM_H
  10 #define DISAS_DIS_ASM_H
  11
  12 #include "qemu/bswap.h"
  13
  14 #ifdef __cplusplus
  15 extern "C" {
  16 #endif
  17
  18 typedef void *PTR;
  19 typedef uint64_t bfd_vma;
  20 typedef int64_t bfd_signed_vma;
  21 typedef uint8_t bfd_byte;
  22 #define sprintf_vma(s,x) sprintf (s, "%0" PRIx64, x)
  23 #define snprintf_vma(s,ss,x) snprintf (s, ss, "%0" PRIx64, x)
  24
  25 #define BFD64
  26
  27 enum bfd_flavour {
  28   bfd_target_unknown_flavour,
  29   bfd_target_aout_flavour,
  30   bfd_target_coff_flavour,
  31   bfd_target_ecoff_flavour,
  32   bfd_target_elf_flavour,
  33   bfd_target_ieee_flavour,
  34   bfd_target_nlm_flavour,
  35   bfd_target_oasys_flavour,
  36   bfd_target_tekhex_flavour,
  37   bfd_target_srec_flavour,
  38   bfd_target_ihex_flavour,
  39   bfd_target_som_flavour,
  40   bfd_target_os9k_flavour,
  41   bfd_target_versados_flavour,
  42   bfd_target_msdos_flavour,
  43   bfd_target_evax_flavour
  44 };
  45
  46 enum bfd_endian { BFD_ENDIAN_BIG, BFD_ENDIAN_LITTLE, BFD_ENDIAN_UNKNOWN };
  47
  48 enum bfd_architecture
  49 {
  50   bfd_arch_unknown,    /* File arch not known */
  51   bfd_arch_obscure,    /* Arch known, not one of these */
  52   bfd_arch_m68k,       /* Motorola 68xxx */
  53 #define bfd_mach_m68000 1
  54 #define bfd_mach_m68008 2
  55 #define bfd_mach_m68010 3
  56 #define bfd_mach_m68020 4
  57 #define bfd_mach_m68030 5
  58 #define bfd_mach_m68040 6
  59 #define bfd_mach_m68060 7
  60 #define bfd_mach_cpu32  8
  61 #define bfd_mach_mcf5200  9
  62 #define bfd_mach_mcf5206e 10
  63 #define bfd_mach_mcf5307  11
  64 #define bfd_mach_mcf5407  12
  65 #define bfd_mach_mcf528x  13
  66 #define bfd_mach_mcfv4e   14
  67 #define bfd_mach_mcf521x   15
  68 #define bfd_mach_mcf5249   16
  69 #define bfd_mach_mcf547x   17
  70 #define bfd_mach_mcf548x   18
  71   bfd_arch_vax,        /* DEC Vax */
  72   bfd_arch_i960,       /* Intel 960 */
  73      /* The order of the following is important.
  74        lower number indicates a machine type that
  75        only accepts a subset of the instructions
  76        available to machines with higher numbers.
  77        The exception is the "ca", which is
  78        incompatible with all other machines except
  79        "core". */
  80
  81 #define bfd_mach_i960_core      1
  82 #define bfd_mach_i960_ka_sa     2
  83 #define bfd_mach_i960_kb_sb     3
  84 #define bfd_mach_i960_mc        4
  85 #define bfd_mach_i960_xa        5
  86 #define bfd_mach_i960_ca        6
  87 #define bfd_mach_i960_jx        7
  88 #define bfd_mach_i960_hx        8
  89
  90   bfd_arch_a29k,       /* AMD 29000 */
  91   bfd_arch_sparc,      /* SPARC */
  92 #define bfd_mach_sparc                 1
  93 /* The difference between v8plus and v9 is that v9 is a true 64 bit env.  */
  94 #define bfd_mach_sparc_sparclet        2
  95 #define bfd_mach_sparc_sparclite       3
  96 #define bfd_mach_sparc_v8plus          4
  97 #define bfd_mach_sparc_v8plusa         5 /* with ultrasparc add'ns.  */
  98 #define bfd_mach_sparc_sparclite_le    6
  99 #define bfd_mach_sparc_v9              7
 100 #define bfd_mach_sparc_v9a             8 /* with ultrasparc add'ns.  */
 101 #define bfd_mach_sparc_v8plusb         9 /* with cheetah add'ns.  */
 102 #define bfd_mach_sparc_v9b             10 /* with cheetah add'ns.  */
 103 /* Nonzero if MACH has the v9 instruction set.  */
 104 #define bfd_mach_sparc_v9_p(mach) \
 105   ((mach) >= bfd_mach_sparc_v8plus && (mach) <= bfd_mach_sparc_v9b \
 106    && (mach) != bfd_mach_sparc_sparclite_le)
 107   bfd_arch_mips,       /* MIPS Rxxxx */
 108 #define bfd_mach_mips3000              3000
 109 #define bfd_mach_mips3900              3900
 110 #define bfd_mach_mips4000              4000
 111 #define bfd_mach_mips4010              4010
 112 #define bfd_mach_mips4100              4100
 113 #define bfd_mach_mips4300              4300
 114 #define bfd_mach_mips4400              4400
 115 #define bfd_mach_mips4600              4600
 116 #define bfd_mach_mips4650              4650
 117 #define bfd_mach_mips5000              5000
 118 #define bfd_mach_mips6000              6000
 119 #define bfd_mach_mips8000              8000
 120 #define bfd_mach_mips10000             10000
 121 #define bfd_mach_mips16                16
 122   bfd_arch_i386,       /* Intel 386 */
 123 #define bfd_mach_i386_i386 0
 124 #define bfd_mach_i386_i8086 1
 125 #define bfd_mach_i386_i386_intel_syntax 2
 126 #define bfd_mach_x86_64 3
 127 #define bfd_mach_x86_64_intel_syntax 4
 128   bfd_arch_we32k,      /* AT&T WE32xxx */
 129   bfd_arch_tahoe,      /* CCI/Harris Tahoe */
 130   bfd_arch_i860,       /* Intel 860 */
 131   bfd_arch_romp,       /* IBM ROMP PC/RT */
 132   bfd_arch_alliant,    /* Alliant */
 133   bfd_arch_convex,     /* Convex */
 134   bfd_arch_m88k,       /* Motorola 88xxx */
 135   bfd_arch_pyramid,    /* Pyramid Technology */
 136   bfd_arch_h8300,      /* Hitachi H8/300 */
 137 #define bfd_mach_h8300   1
 138 #define bfd_mach_h8300h  2
 139 #define bfd_mach_h8300s  3
 140   bfd_arch_powerpc,    /* PowerPC */
 141 #define bfd_mach_ppc           0
 142 #define bfd_mach_ppc64         1
 143 #define bfd_mach_ppc_403       403
 144 #define bfd_mach_ppc_403gc     4030
 145 #define bfd_mach_ppc_e500      500
 146 #define bfd_mach_ppc_505       505
 147 #define bfd_mach_ppc_601       601
 148 #define bfd_mach_ppc_602       602
 149 #define bfd_mach_ppc_603       603
 150 #define bfd_mach_ppc_ec603e    6031
 151 #define bfd_mach_ppc_604       604
 152 #define bfd_mach_ppc_620       620
 153 #define bfd_mach_ppc_630       630
 154 #define bfd_mach_ppc_750       750
 155 #define bfd_mach_ppc_860       860
 156 #define bfd_mach_ppc_a35       35
 157 #define bfd_mach_ppc_rs64ii    642
 158 #define bfd_mach_ppc_rs64iii   643
 159 #define bfd_mach_ppc_7400      7400
 160   bfd_arch_rs6000,     /* IBM RS/6000 */
 161   bfd_arch_hppa,       /* HP PA RISC */
 162 #define bfd_mach_hppa10        10
 163 #define bfd_mach_hppa11        11
 164 #define bfd_mach_hppa20        20
 165 #define bfd_mach_hppa20w       25
 166   bfd_arch_d10v,       /* Mitsubishi D10V */
 167   bfd_arch_z8k,        /* Zilog Z8000 */
 168 #define bfd_mach_z8001         1
 169 #define bfd_mach_z8002         2
 170   bfd_arch_h8500,      /* Hitachi H8/500 */
 171   bfd_arch_sh,         /* Hitachi SH */
 172 #define bfd_mach_sh            1
 173 #define bfd_mach_sh2        0x20
 174 #define bfd_mach_sh_dsp     0x2d
 175 #define bfd_mach_sh2a       0x2a
 176 #define bfd_mach_sh2a_nofpu 0x2b
 177 #define bfd_mach_sh2e       0x2e
 178 #define bfd_mach_sh3        0x30
 179 #define bfd_mach_sh3_nommu  0x31
 180 #define bfd_mach_sh3_dsp    0x3d
 181 #define bfd_mach_sh3e       0x3e
 182 #define bfd_mach_sh4        0x40
 183 #define bfd_mach_sh4_nofpu  0x41
 184 #define bfd_mach_sh4_nommu_nofpu  0x42
 185 #define bfd_mach_sh4a       0x4a
 186 #define bfd_mach_sh4a_nofpu 0x4b
 187 #define bfd_mach_sh4al_dsp  0x4d
 188 #define bfd_mach_sh5        0x50
 189   bfd_arch_alpha,      /* Dec Alpha */
 190 #define bfd_mach_alpha 1
 191 #define bfd_mach_alpha_ev4  0x10
 192 #define bfd_mach_alpha_ev5  0x20
 193 #define bfd_mach_alpha_ev6  0x30
 194   bfd_arch_arm,        /* Advanced Risc Machines ARM */
 195 #define bfd_mach_arm_unknown    0
 196 #define bfd_mach_arm_2          1
 197 #define bfd_mach_arm_2a         2
 198 #define bfd_mach_arm_3          3
 199 #define bfd_mach_arm_3M         4
 200 #define bfd_mach_arm_4          5
 201 #define bfd_mach_arm_4T         6
 202 #define bfd_mach_arm_5          7
 203 #define bfd_mach_arm_5T         8
 204 #define bfd_mach_arm_5TE        9
 205 #define bfd_mach_arm_XScale     10
 206 #define bfd_mach_arm_ep9312     11
 207 #define bfd_mach_arm_iWMMXt     12
 208 #define bfd_mach_arm_iWMMXt2    13
 209   bfd_arch_ns32k,      /* National Semiconductors ns32000 */
 210   bfd_arch_w65,        /* WDC 65816 */
 211   bfd_arch_tic30,      /* Texas Instruments TMS320C30 */
 212   bfd_arch_v850,       /* NEC V850 */
 213 #define bfd_mach_v850          0
 214   bfd_arch_arc,        /* Argonaut RISC Core */
 215 #define bfd_mach_arc_base 0
 216   bfd_arch_m32r,       /* Mitsubishi M32R/D */
 217 #define bfd_mach_m32r          0  /* backwards compatibility */
 218   bfd_arch_mn10200,    /* Matsushita MN10200 */
 219   bfd_arch_mn10300,    /* Matsushita MN10300 */
 220   bfd_arch_avr,        /* AVR microcontrollers */
 221 #define bfd_mach_avr1       1
 222 #define bfd_mach_avr2       2
 223 #define bfd_mach_avr25      25
 224 #define bfd_mach_avr3       3
 225 #define bfd_mach_avr31      31
 226 #define bfd_mach_avr35      35
 227 #define bfd_mach_avr4       4
 228 #define bfd_mach_avr5       5
 229 #define bfd_mach_avr51      51
 230 #define bfd_mach_avr6       6
 231 #define bfd_mach_avrtiny    100
 232 #define bfd_mach_avrxmega1  101
 233 #define bfd_mach_avrxmega2  102
 234 #define bfd_mach_avrxmega3  103
 235 #define bfd_mach_avrxmega4  104
 236 #define bfd_mach_avrxmega5  105
 237 #define bfd_mach_avrxmega6  106
 238 #define bfd_mach_avrxmega7  107
 239   bfd_arch_cris,       /* Axis CRIS */
 240 #define bfd_mach_cris_v0_v10   255
 241 #define bfd_mach_cris_v32      32
 242 #define bfd_mach_cris_v10_v32  1032
 243   bfd_arch_microblaze, /* Xilinx MicroBlaze.  */
 244   bfd_arch_moxie,      /* The Moxie core.  */
 245   bfd_arch_ia64,      /* HP/Intel ia64 */
 246 #define bfd_mach_ia64_elf64    64
 247 #define bfd_mach_ia64_elf32    32
 248   bfd_arch_nios2,       /* Nios II */
 249 #define bfd_mach_nios2          0
 250 #define bfd_mach_nios2r1        1
 251 #define bfd_mach_nios2r2        2
 252   bfd_arch_rx,       /* Renesas RX */
 253 #define bfd_mach_rx            0x75
 254 #define bfd_mach_rx_v2         0x76
 255 #define bfd_mach_rx_v3         0x77
 256   bfd_arch_last
 257   };
 258 #define bfd_mach_s390_31 31
 259 #define bfd_mach_s390_64 64
 260
 261 typedef struct symbol_cache_entry
 262 {
 263     const char *name;
 264     union
 265     {
 266         PTR p;
 267         bfd_vma i;
 268     } udata;
 269 } asymbol;
 270
 271 typedef int (*fprintf_function)(FILE *f, const char *fmt, ...)
 272     GCC_FMT_ATTR(2, 3);
 273
 274 enum dis_insn_type {
 275   dis_noninsn,                  /* Not a valid instruction */
 276   dis_nonbranch,                /* Not a branch instruction */
 277   dis_branch,                   /* Unconditional branch */
 278   dis_condbranch,               /* Conditional branch */
 279   dis_jsr,                      /* Jump to subroutine */
 280   dis_condjsr,                  /* Conditional jump to subroutine */
 281   dis_dref,                     /* Data reference instruction */
 282   dis_dref2                     /* Two data references in instruction */
 283 };
 284
 285 /* This struct is passed into the instruction decoding routine,
 286    and is passed back out into each callback.  The various fields are used
 287    for conveying information from your main routine into your callbacks,
 288    for passing information into the instruction decoders (such as the
 289    addresses of the callback functions), or for passing information
 290    back from the instruction decoders to their callers.
 291
 292    It must be initialized before it is first passed; this can be done
 293    by hand, or using one of the initialization macros below.  */
 294
 295 typedef struct disassemble_info {
 296   fprintf_function fprintf_func;
 297   FILE *stream;
 298   PTR application_data;
 299
 300   /* Target description.  We could replace this with a pointer to the bfd,
 301      but that would require one.  There currently isn't any such requirement
 302      so to avoid introducing one we record these explicitly.  */
 303   /* The bfd_flavour.  This can be bfd_target_unknown_flavour.  */
 304   enum bfd_flavour flavour;
 305   /* The bfd_arch value.  */
 306   enum bfd_architecture arch;
 307   /* The bfd_mach value.  */
 308   unsigned long mach;
 309   /* Endianness (for bi-endian cpus).  Mono-endian cpus can ignore this.  */
 310   enum bfd_endian endian;
 311
 312   /* An array of pointers to symbols either at the location being disassembled
 313      or at the start of the function being disassembled.  The array is sorted
 314      so that the first symbol is intended to be the one used.  The others are
 315      present for any misc. purposes.  This is not set reliably, but if it is
 316      not NULL, it is correct.  */
 317   asymbol **symbols;
 318   /* Number of symbols in array.  */
 319   int num_symbols;
 320
 321   /* For use by the disassembler.
 322      The top 16 bits are reserved for public use (and are documented here).
 323      The bottom 16 bits are for the internal use of the disassembler.  */
 324   unsigned long flags;
 325 #define INSN_HAS_RELOC  0x80000000
 326 #define INSN_ARM_BE32   0x00010000
 327   PTR private_data;
 328
 329   /* Function used to get bytes to disassemble.  MEMADDR is the
 330      address of the stuff to be disassembled, MYADDR is the address to
 331      put the bytes in, and LENGTH is the number of bytes to read.
 332      INFO is a pointer to this struct.
 333      Returns an errno value or 0 for success.  */
 334   int (*read_memory_func)
 335     (bfd_vma memaddr, bfd_byte *myaddr, int length,
 336              struct disassemble_info *info);
 337
 338   /* Function which should be called if we get an error that we can't
 339      recover from.  STATUS is the errno value from read_memory_func and
 340      MEMADDR is the address that we were trying to read.  INFO is a
 341      pointer to this struct.  */
 342   void (*memory_error_func)
 343     (int status, bfd_vma memaddr, struct disassemble_info *info);
 344
 345   /* Function called to print ADDR.  */
 346   void (*print_address_func)
 347     (bfd_vma addr, struct disassemble_info *info);
 348
 349     /* Function called to print an instruction. The function is architecture
 350      * specific.
 351      */
 352     int (*print_insn)(bfd_vma addr, struct disassemble_info *info);
 353
 354   /* Function called to determine if there is a symbol at the given ADDR.
 355      If there is, the function returns 1, otherwise it returns 0.
 356      This is used by ports which support an overlay manager where
 357      the overlay number is held in the top part of an address.  In
 358      some circumstances we want to include the overlay number in the
 359      address, (normally because there is a symbol associated with
 360      that address), but sometimes we want to mask out the overlay bits.  */
 361   int (* symbol_at_address_func)
 362     (bfd_vma addr, struct disassemble_info * info);
 363
 364   /* These are for buffer_read_memory.  */
 365   const bfd_byte *buffer;
 366   bfd_vma buffer_vma;
 367   int buffer_length;
 368
 369   /* This variable may be set by the instruction decoder.  It suggests
 370       the number of bytes objdump should display on a single line.  If
 371       the instruction decoder sets this, it should always set it to
 372       the same value in order to get reasonable looking output.  */
 373   int bytes_per_line;
 374
 375   /* the next two variables control the way objdump displays the raw data */
 376   /* For example, if bytes_per_line is 8 and bytes_per_chunk is 4, the */
 377   /* output will look like this:
 378      00:   00000000 00000000
 379      with the chunks displayed according to "display_endian". */
 380   int bytes_per_chunk;
 381   enum bfd_endian display_endian;
 382
 383   /* Results from instruction decoders.  Not all decoders yet support
 384      this information.  This info is set each time an instruction is
 385      decoded, and is only valid for the last such instruction.
 386
 387      To determine whether this decoder supports this information, set
 388      insn_info_valid to 0, decode an instruction, then check it.  */
 389
 390   char insn_info_valid;         /* Branch info has been set. */
 391   char branch_delay_insns;      /* How many sequential insn's will run before
 392                                    a branch takes effect.  (0 = normal) */
 393   char data_size;               /* Size of data reference in insn, in bytes */
 394   enum dis_insn_type insn_type; /* Type of instruction */
 395   bfd_vma target;               /* Target address of branch or dref, if known;
 396                                    zero if unknown.  */
 397   bfd_vma target2;              /* Second target address for dref2 */
 398
 399   /* Command line options specific to the target disassembler.  */
 400   char * disassembler_options;
 401
 402   /* Field intended to be used by targets in any way they deem suitable.  */
 403   int64_t target_info;
 404
 405   /* Options for Capstone disassembly.  */
 406   int cap_arch;
 407   int cap_mode;
 408   int cap_insn_unit;
 409   int cap_insn_split;
 410
 411 } disassemble_info;
 412
 413 /* Standard disassemblers.  Disassemble one instruction at the given
 414    target address.  Return number of bytes processed.  */
 415 typedef int (*disassembler_ftype) (bfd_vma, disassemble_info *);
 416
 417 int print_insn_tci(bfd_vma, disassemble_info*);
 418 int print_insn_big_mips         (bfd_vma, disassemble_info*);
 419 int print_insn_little_mips      (bfd_vma, disassemble_info*);
 420 int print_insn_nanomips         (bfd_vma, disassemble_info*);
 421 int print_insn_i386             (bfd_vma, disassemble_info*);
 422 int print_insn_m68k             (bfd_vma, disassemble_info*);
 423 int print_insn_z8001            (bfd_vma, disassemble_info*);
 424 int print_insn_z8002            (bfd_vma, disassemble_info*);
 425 int print_insn_h8300            (bfd_vma, disassemble_info*);
 426 int print_insn_h8300h           (bfd_vma, disassemble_info*);
 427 int print_insn_h8300s           (bfd_vma, disassemble_info*);
 428 int print_insn_h8500            (bfd_vma, disassemble_info*);
 429 int print_insn_arm_a64          (bfd_vma, disassemble_info*);
 430 int print_insn_alpha            (bfd_vma, disassemble_info*);
 431 disassembler_ftype arc_get_disassembler (int, int);
 432 int print_insn_arm              (bfd_vma, disassemble_info*);
 433 int print_insn_sparc            (bfd_vma, disassemble_info*);
 434 int print_insn_big_a29k         (bfd_vma, disassemble_info*);
 435 int print_insn_little_a29k      (bfd_vma, disassemble_info*);
 436 int print_insn_i960             (bfd_vma, disassemble_info*);
 437 int print_insn_sh               (bfd_vma, disassemble_info*);
 438 int print_insn_shl              (bfd_vma, disassemble_info*);
 439 int print_insn_hppa             (bfd_vma, disassemble_info*);
 440 int print_insn_m32r             (bfd_vma, disassemble_info*);
 441 int print_insn_m88k             (bfd_vma, disassemble_info*);
 442 int print_insn_mn10200          (bfd_vma, disassemble_info*);
 443 int print_insn_mn10300          (bfd_vma, disassemble_info*);
 444 int print_insn_ns32k            (bfd_vma, disassemble_info*);
 445 int print_insn_big_powerpc      (bfd_vma, disassemble_info*);
 446 int print_insn_little_powerpc   (bfd_vma, disassemble_info*);
 447 int print_insn_rs6000           (bfd_vma, disassemble_info*);
 448 int print_insn_w65              (bfd_vma, disassemble_info*);
 449 int print_insn_d10v             (bfd_vma, disassemble_info*);
 450 int print_insn_v850             (bfd_vma, disassemble_info*);
 451 int print_insn_tic30            (bfd_vma, disassemble_info*);
 452 int print_insn_ppc              (bfd_vma, disassemble_info*);
 453 int print_insn_s390             (bfd_vma, disassemble_info*);
 454 int print_insn_crisv32          (bfd_vma, disassemble_info*);
 455 int print_insn_crisv10          (bfd_vma, disassemble_info*);
 456 int print_insn_microblaze       (bfd_vma, disassemble_info*);
 457 int print_insn_ia64             (bfd_vma, disassemble_info*);
 458 int print_insn_big_nios2        (bfd_vma, disassemble_info*);
 459 int print_insn_little_nios2     (bfd_vma, disassemble_info*);
 460 int print_insn_xtensa           (bfd_vma, disassemble_info*);
 461 int print_insn_riscv32          (bfd_vma, disassemble_info*);
 462 int print_insn_riscv64          (bfd_vma, disassemble_info*);
 463 int print_insn_rx(bfd_vma, disassemble_info *);
 464 int print_insn_hexagon(bfd_vma, disassemble_info *);
 465
 466 #ifdef CONFIG_CAPSTONE
 467 bool cap_disas_target(disassemble_info *info, uint64_t pc, size_t size);
 468 bool cap_disas_host(disassemble_info *info, const void *code, size_t size);
 469 bool cap_disas_monitor(disassemble_info *info, uint64_t pc, int count);
 470 bool cap_disas_plugin(disassemble_info *info, uint64_t pc, size_t size);
 471 #else
 472 # define cap_disas_target(i, p, s)  false
 473 # define cap_disas_host(i, p, s)    false
 474 # define cap_disas_monitor(i, p, c) false
 475 # define cap_disas_plugin(i, p, c)  false
 476 #endif /* CONFIG_CAPSTONE */
 477
 478 #ifndef ATTRIBUTE_UNUSED
 479 #define ATTRIBUTE_UNUSED __attribute__((unused))
 480 #endif
 481
 482 /* from libbfd */
 483
 484 static inline bfd_vma bfd_getl64(const bfd_byte *addr)
 485 {
 486     return ldq_le_p(addr);
 487 }
 488
 489 static inline bfd_vma bfd_getl32(const bfd_byte *addr)
 490 {
 491     return (uint32_t)ldl_le_p(addr);
 492 }
 493
 494 static inline bfd_vma bfd_getl16(const bfd_byte *addr)
 495 {
 496     return lduw_le_p(addr);
 497 }
 498
 499 static inline bfd_vma bfd_getb32(const bfd_byte *addr)
 500 {
 501     return (uint32_t)ldl_be_p(addr);
 502 }
 503
 504 static inline bfd_vma bfd_getb16(const bfd_byte *addr)
 505 {
 506     return lduw_be_p(addr);
 507 }
 508
 509 typedef bool bfd_boolean;
 510
 511 #ifdef __cplusplus
 512 }
 513 #endif
 514
 515 #endif /* DISAS_DIS_ASM_H */