target-mips/cpu.c

   1 /*
   2  * QEMU MIPS CPU
   3  *
   4  * Copyright (c) 2012 SUSE LINUX Products GmbH
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2.1 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see
  18  * <http://www.gnu.org/licenses/lgpl-2.1.html>
  19  */
  20
  21 #include "cpu.h"
  22 #include "qemu-common.h"
  23
  24
  25 static void mips_cpu_set_pc(CPUState *cs, vaddr value)
  26 {
  27     MIPSCPU *cpu = MIPS_CPU(cs);
  28     CPUMIPSState *env = &cpu->env;
  29
  30     env->active_tc.PC = value & ~(target_ulong)1;
  31     if (value & 1) {
  32         env->hflags |= MIPS_HFLAG_M16;
  33     } else {
  34         env->hflags &= ~(MIPS_HFLAG_M16);
  35     }
  36 }
  37
  38 static void mips_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
  39 {
  40     MIPSCPU *cpu = MIPS_CPU(cs);
  41     CPUMIPSState *env = &cpu->env;
  42
  43     env->active_tc.PC = tb->pc;
  44     env->hflags &= ~MIPS_HFLAG_BMASK;
  45     env->hflags |= tb->flags & MIPS_HFLAG_BMASK;
  46 }
  47
  48 static bool mips_cpu_has_work(CPUState *cs)
  49 {
  50     MIPSCPU *cpu = MIPS_CPU(cs);
  51     CPUMIPSState *env = &cpu->env;
  52     bool has_work = false;
  53
  54     /* It is implementation dependent if non-enabled interrupts
  55        wake-up the CPU, however most of the implementations only
  56        check for interrupts that can be taken. */
  57     if ((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
  58         cpu_mips_hw_interrupts_pending(env)) {
  59         has_work = true;
  60     }
  61
  62     /* MIPS-MT has the ability to halt the CPU.  */
  63     if (env->CP0_Config3 & (1 << CP0C3_MT)) {
  64         /* The QEMU model will issue an _WAKE request whenever the CPUs
  65            should be woken up.  */
  66         if (cs->interrupt_request & CPU_INTERRUPT_WAKE) {
  67             has_work = true;
  68         }
  69
  70         if (!mips_vpe_active(env)) {
  71             has_work = false;
  72         }
  73     }
  74     return has_work;
  75 }
  76
  77 /* CPUClass::reset() */
  78 static void mips_cpu_reset(CPUState *s)
  79 {
  80     MIPSCPU *cpu = MIPS_CPU(s);
  81     MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(cpu);
  82     CPUMIPSState *env = &cpu->env;
  83
  84     mcc->parent_reset(s);
  85
  86     memset(env, 0, offsetof(CPUMIPSState, mvp));
  87     tlb_flush(s, 1);
  88
  89     cpu_state_reset(env);
  90 }
  91
  92 static void mips_cpu_realizefn(DeviceState *dev, Error **errp)
  93 {
  94     CPUState *cs = CPU(dev);
  95     MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(dev);
  96
  97     cpu_reset(cs);
  98     qemu_init_vcpu(cs);
  99
 100     mcc->parent_realize(dev, errp);
 101 }
 102
 103 static void mips_cpu_initfn(Object *obj)
 104 {
 105     CPUState *cs = CPU(obj);
 106     MIPSCPU *cpu = MIPS_CPU(obj);
 107     CPUMIPSState *env = &cpu->env;
 108
 109     cs->env_ptr = env;
 110     cpu_exec_init(env);
 111
 112     if (tcg_enabled()) {
 113         mips_tcg_init();
 114     }
 115 }
 116
 117 static void mips_cpu_class_init(ObjectClass *c, void *data)
 118 {
 119     MIPSCPUClass *mcc = MIPS_CPU_CLASS(c);
 120     CPUClass *cc = CPU_CLASS(c);
 121     DeviceClass *dc = DEVICE_CLASS(c);
 122
 123     mcc->parent_realize = dc->realize;
 124     dc->realize = mips_cpu_realizefn;
 125
 126     mcc->parent_reset = cc->reset;
 127     cc->reset = mips_cpu_reset;
 128
 129     cc->has_work = mips_cpu_has_work;
 130     cc->do_interrupt = mips_cpu_do_interrupt;
 131     cc->dump_state = mips_cpu_dump_state;
 132     cc->set_pc = mips_cpu_set_pc;
 133     cc->synchronize_from_tb = mips_cpu_synchronize_from_tb;
 134     cc->gdb_read_register = mips_cpu_gdb_read_register;
 135     cc->gdb_write_register = mips_cpu_gdb_write_register;
 136 #ifdef CONFIG_USER_ONLY
 137     cc->handle_mmu_fault = mips_cpu_handle_mmu_fault;
 138 #else
 139     cc->do_unassigned_access = mips_cpu_unassigned_access;
 140     cc->do_unaligned_access = mips_cpu_do_unaligned_access;
 141     cc->get_phys_page_debug = mips_cpu_get_phys_page_debug;
 142 #endif
 143
 144     cc->gdb_num_core_regs = 73;
 145 }
 146
 147 static const TypeInfo mips_cpu_type_info = {
 148     .name = TYPE_MIPS_CPU,
 149     .parent = TYPE_CPU,
 150     .instance_size = sizeof(MIPSCPU),
 151     .instance_init = mips_cpu_initfn,
 152     .abstract = false,
 153     .class_size = sizeof(MIPSCPUClass),
 154     .class_init = mips_cpu_class_init,
 155 };
 156
 157 static void mips_cpu_register_types(void)
 158 {
 159     type_register_static(&mips_cpu_type_info);
 160 }
 161
 162 type_init(mips_cpu_register_types)