qemu-nbd: Fix a memleak in qemu_nbd_client_list()
[qemu.git] / hw / mips / fuloong2e.c
blobbac2adbd5aede692e24cb12749e7d1c78bfe49f0
1 /*
2 * QEMU fuloong 2e mini pc support
4 * Copyright (c) 2008 yajin (yajin@vm-kernel.org)
5 * Copyright (c) 2009 chenming (chenming@rdc.faw.com.cn)
6 * Copyright (c) 2010 Huacai Chen (zltjiangshi@gmail.com)
7 * This code is licensed under the GNU GPL v2.
9 * Contributions after 2012-01-13 are licensed under the terms of the
10 * GNU GPL, version 2 or (at your option) any later version.
14 * Fuloong 2e mini pc is based on ICT/ST Loongson 2e CPU (MIPS III like, 800MHz)
15 * https://www.linux-mips.org/wiki/Fuloong_2E
17 * Loongson 2e manuals:
18 * https://github.com/loongson-community/docs/tree/master/2E
21 #include "qemu/osdep.h"
22 #include "qemu-common.h"
23 #include "qemu/datadir.h"
24 #include "qemu/units.h"
25 #include "qapi/error.h"
26 #include "cpu.h"
27 #include "hw/clock.h"
28 #include "hw/intc/i8259.h"
29 #include "hw/dma/i8257.h"
30 #include "hw/isa/superio.h"
31 #include "net/net.h"
32 #include "hw/boards.h"
33 #include "hw/i2c/smbus_eeprom.h"
34 #include "hw/block/flash.h"
35 #include "hw/mips/mips.h"
36 #include "hw/mips/cpudevs.h"
37 #include "hw/pci/pci.h"
38 #include "qemu/log.h"
39 #include "hw/loader.h"
40 #include "hw/ide/pci.h"
41 #include "elf.h"
42 #include "hw/isa/vt82c686.h"
43 #include "hw/rtc/mc146818rtc.h"
44 #include "hw/timer/i8254.h"
45 #include "exec/address-spaces.h"
46 #include "sysemu/qtest.h"
47 #include "sysemu/reset.h"
48 #include "qemu/error-report.h"
50 #define ENVP_PADDR 0x2000
51 #define ENVP_VADDR cpu_mips_phys_to_kseg0(NULL, ENVP_PADDR)
52 #define ENVP_NB_ENTRIES 16
53 #define ENVP_ENTRY_SIZE 256
55 /* Fuloong 2e has a 512k flash: Winbond W39L040AP70Z */
56 #define BIOS_SIZE (512 * KiB)
57 #define MAX_IDE_BUS 2
60 * PMON is not part of qemu and released with BSD license, anyone
61 * who want to build a pmon binary please first git-clone the source
62 * from the git repository at:
63 * https://github.com/loongson-community/pmon
65 #define FULOONG_BIOSNAME "pmon_2e.bin"
67 /* PCI SLOT in Fuloong 2e */
68 #define FULOONG2E_VIA_SLOT 5
69 #define FULOONG2E_ATI_SLOT 6
70 #define FULOONG2E_RTL8139_SLOT 7
72 static struct _loaderparams {
73 int ram_size;
74 const char *kernel_filename;
75 const char *kernel_cmdline;
76 const char *initrd_filename;
77 } loaderparams;
79 static void GCC_FMT_ATTR(3, 4) prom_set(uint32_t *prom_buf, int index,
80 const char *string, ...)
82 va_list ap;
83 int32_t table_addr;
85 if (index >= ENVP_NB_ENTRIES) {
86 return;
89 if (string == NULL) {
90 prom_buf[index] = 0;
91 return;
94 table_addr = sizeof(int32_t) * ENVP_NB_ENTRIES + index * ENVP_ENTRY_SIZE;
95 prom_buf[index] = tswap32(ENVP_VADDR + table_addr);
97 va_start(ap, string);
98 vsnprintf((char *)prom_buf + table_addr, ENVP_ENTRY_SIZE, string, ap);
99 va_end(ap);
102 static uint64_t load_kernel(MIPSCPU *cpu)
104 uint64_t kernel_entry, kernel_high, initrd_size;
105 int index = 0;
106 long kernel_size;
107 ram_addr_t initrd_offset;
108 uint32_t *prom_buf;
109 long prom_size;
111 kernel_size = load_elf(loaderparams.kernel_filename, NULL,
112 cpu_mips_kseg0_to_phys, NULL,
113 &kernel_entry, NULL,
114 &kernel_high, NULL,
115 0, EM_MIPS, 1, 0);
116 if (kernel_size < 0) {
117 error_report("could not load kernel '%s': %s",
118 loaderparams.kernel_filename,
119 load_elf_strerror(kernel_size));
120 exit(1);
123 /* load initrd */
124 initrd_size = 0;
125 initrd_offset = 0;
126 if (loaderparams.initrd_filename) {
127 initrd_size = get_image_size(loaderparams.initrd_filename);
128 if (initrd_size > 0) {
129 initrd_offset = ROUND_UP(kernel_high, INITRD_PAGE_SIZE);
130 if (initrd_offset + initrd_size > loaderparams.ram_size) {
131 error_report("memory too small for initial ram disk '%s'",
132 loaderparams.initrd_filename);
133 exit(1);
135 initrd_size = load_image_targphys(loaderparams.initrd_filename,
136 initrd_offset,
137 loaderparams.ram_size - initrd_offset);
139 if (initrd_size == (target_ulong) -1) {
140 error_report("could not load initial ram disk '%s'",
141 loaderparams.initrd_filename);
142 exit(1);
146 /* Setup prom parameters. */
147 prom_size = ENVP_NB_ENTRIES * (sizeof(int32_t) + ENVP_ENTRY_SIZE);
148 prom_buf = g_malloc(prom_size);
150 prom_set(prom_buf, index++, "%s", loaderparams.kernel_filename);
151 if (initrd_size > 0) {
152 prom_set(prom_buf, index++,
153 "rd_start=0x%" PRIx64 " rd_size=%" PRId64 " %s",
154 cpu_mips_phys_to_kseg0(NULL, initrd_offset),
155 initrd_size, loaderparams.kernel_cmdline);
156 } else {
157 prom_set(prom_buf, index++, "%s", loaderparams.kernel_cmdline);
160 /* Setup minimum environment variables */
161 prom_set(prom_buf, index++, "busclock=33000000");
162 prom_set(prom_buf, index++, "cpuclock=%u", clock_get_hz(cpu->clock));
163 prom_set(prom_buf, index++, "memsize=%"PRIi64, loaderparams.ram_size / MiB);
164 prom_set(prom_buf, index++, NULL);
166 rom_add_blob_fixed("prom", prom_buf, prom_size, ENVP_PADDR);
168 g_free(prom_buf);
169 return kernel_entry;
172 static void write_bootloader(CPUMIPSState *env, uint8_t *base,
173 uint64_t kernel_addr)
175 uint32_t *p;
177 /* Small bootloader */
178 p = (uint32_t *)base;
180 /* j 0x1fc00040 */
181 stl_p(p++, 0x0bf00010);
182 /* nop */
183 stl_p(p++, 0x00000000);
185 /* Second part of the bootloader */
186 p = (uint32_t *)(base + 0x040);
188 /* lui a0, 0 */
189 stl_p(p++, 0x3c040000);
190 /* ori a0, a0, 2 */
191 stl_p(p++, 0x34840002);
192 /* lui a1, high(ENVP_VADDR) */
193 stl_p(p++, 0x3c050000 | ((ENVP_VADDR >> 16) & 0xffff));
194 /* ori a1, a0, low(ENVP_VADDR) */
195 stl_p(p++, 0x34a50000 | (ENVP_VADDR & 0xffff));
196 /* lui a2, high(ENVP_VADDR + 8) */
197 stl_p(p++, 0x3c060000 | (((ENVP_VADDR + 8) >> 16) & 0xffff));
198 /* ori a2, a2, low(ENVP_VADDR + 8) */
199 stl_p(p++, 0x34c60000 | ((ENVP_VADDR + 8) & 0xffff));
200 /* lui a3, high(env->ram_size) */
201 stl_p(p++, 0x3c070000 | (loaderparams.ram_size >> 16));
202 /* ori a3, a3, low(env->ram_size) */
203 stl_p(p++, 0x34e70000 | (loaderparams.ram_size & 0xffff));
204 /* lui ra, high(kernel_addr) */
205 stl_p(p++, 0x3c1f0000 | ((kernel_addr >> 16) & 0xffff));
206 /* ori ra, ra, low(kernel_addr) */
207 stl_p(p++, 0x37ff0000 | (kernel_addr & 0xffff));
208 /* jr ra */
209 stl_p(p++, 0x03e00008);
210 /* nop */
211 stl_p(p++, 0x00000000);
214 static void main_cpu_reset(void *opaque)
216 MIPSCPU *cpu = opaque;
217 CPUMIPSState *env = &cpu->env;
219 cpu_reset(CPU(cpu));
220 /* TODO: 2E reset stuff */
221 if (loaderparams.kernel_filename) {
222 env->CP0_Status &= ~((1 << CP0St_BEV) | (1 << CP0St_ERL));
226 static void vt82c686b_southbridge_init(PCIBus *pci_bus, int slot, qemu_irq intc,
227 I2CBus **i2c_bus, ISABus **p_isa_bus)
229 qemu_irq *i8259;
230 ISABus *isa_bus;
231 PCIDevice *dev;
233 dev = pci_create_simple_multifunction(pci_bus, PCI_DEVFN(slot, 0), true,
234 TYPE_VT82C686B_ISA);
235 isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(dev), "isa.0"));
236 assert(isa_bus);
237 *p_isa_bus = isa_bus;
238 /* Interrupt controller */
239 /* The 8259 -> IP5 */
240 i8259 = i8259_init(isa_bus, intc);
241 isa_bus_irqs(isa_bus, i8259);
242 /* init other devices */
243 i8254_pit_init(isa_bus, 0x40, 0, NULL);
244 i8257_dma_init(isa_bus, 0);
245 /* Super I/O */
246 isa_create_simple(isa_bus, TYPE_VT82C686B_SUPERIO);
248 dev = pci_create_simple(pci_bus, PCI_DEVFN(slot, 1), "via-ide");
249 pci_ide_create_devs(dev);
251 pci_create_simple(pci_bus, PCI_DEVFN(slot, 2), "vt82c686b-usb-uhci");
252 pci_create_simple(pci_bus, PCI_DEVFN(slot, 3), "vt82c686b-usb-uhci");
254 dev = pci_new(PCI_DEVFN(slot, 4), TYPE_VT82C686B_PM);
255 qdev_prop_set_uint32(DEVICE(dev), "smb_io_base", 0xeee1);
256 pci_realize_and_unref(dev, pci_bus, &error_fatal);
257 *i2c_bus = I2C_BUS(qdev_get_child_bus(DEVICE(dev), "i2c"));
259 /* Audio support */
260 pci_create_simple(pci_bus, PCI_DEVFN(slot, 5), TYPE_VIA_AC97);
261 pci_create_simple(pci_bus, PCI_DEVFN(slot, 6), TYPE_VIA_MC97);
264 /* Network support */
265 static void network_init(PCIBus *pci_bus)
267 int i;
269 for (i = 0; i < nb_nics; i++) {
270 NICInfo *nd = &nd_table[i];
271 const char *default_devaddr = NULL;
273 if (i == 0 && (!nd->model || strcmp(nd->model, "rtl8139") == 0)) {
274 /* The Fuloong board has a RTL8139 card using PCI SLOT 7 */
275 default_devaddr = "07";
278 pci_nic_init_nofail(nd, pci_bus, "rtl8139", default_devaddr);
282 static void mips_fuloong2e_init(MachineState *machine)
284 const char *kernel_filename = machine->kernel_filename;
285 const char *kernel_cmdline = machine->kernel_cmdline;
286 const char *initrd_filename = machine->initrd_filename;
287 char *filename;
288 MemoryRegion *address_space_mem = get_system_memory();
289 MemoryRegion *bios = g_new(MemoryRegion, 1);
290 long bios_size;
291 uint8_t *spd_data;
292 uint64_t kernel_entry;
293 PCIDevice *pci_dev;
294 PCIBus *pci_bus;
295 ISABus *isa_bus;
296 I2CBus *smbus;
297 Clock *cpuclk;
298 MIPSCPU *cpu;
299 CPUMIPSState *env;
300 DeviceState *dev;
302 cpuclk = clock_new(OBJECT(machine), "cpu-refclk");
303 clock_set_hz(cpuclk, 533080000); /* ~533 MHz */
305 /* init CPUs */
306 cpu = mips_cpu_create_with_clock(machine->cpu_type, cpuclk);
307 env = &cpu->env;
309 qemu_register_reset(main_cpu_reset, cpu);
311 /* TODO: support more than 256M RAM as highmem */
312 if (machine->ram_size != 256 * MiB) {
313 error_report("Invalid RAM size, should be 256MB");
314 exit(EXIT_FAILURE);
316 memory_region_add_subregion(address_space_mem, 0, machine->ram);
318 /* Boot ROM */
319 memory_region_init_rom(bios, NULL, "fuloong2e.bios", BIOS_SIZE,
320 &error_fatal);
321 memory_region_add_subregion(address_space_mem, 0x1fc00000LL, bios);
324 * We do not support flash operation, just loading pmon.bin as raw BIOS.
325 * Please use -L to set the BIOS path and -bios to set bios name.
328 if (kernel_filename) {
329 loaderparams.ram_size = machine->ram_size;
330 loaderparams.kernel_filename = kernel_filename;
331 loaderparams.kernel_cmdline = kernel_cmdline;
332 loaderparams.initrd_filename = initrd_filename;
333 kernel_entry = load_kernel(cpu);
334 write_bootloader(env, memory_region_get_ram_ptr(bios), kernel_entry);
335 } else {
336 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS,
337 machine->firmware ?: FULOONG_BIOSNAME);
338 if (filename) {
339 bios_size = load_image_targphys(filename, 0x1fc00000LL,
340 BIOS_SIZE);
341 g_free(filename);
342 } else {
343 bios_size = -1;
346 if ((bios_size < 0 || bios_size > BIOS_SIZE) &&
347 machine->firmware && !qtest_enabled()) {
348 error_report("Could not load MIPS bios '%s'", machine->firmware);
349 exit(1);
353 /* Init internal devices */
354 cpu_mips_irq_init_cpu(cpu);
355 cpu_mips_clock_init(cpu);
357 /* North bridge, Bonito --> IP2 */
358 pci_bus = bonito_init((qemu_irq *)&(env->irq[2]));
360 /* South bridge -> IP5 */
361 vt82c686b_southbridge_init(pci_bus, FULOONG2E_VIA_SLOT, env->irq[5],
362 &smbus, &isa_bus);
364 /* GPU */
365 if (vga_interface_type != VGA_NONE) {
366 pci_dev = pci_new(-1, "ati-vga");
367 dev = DEVICE(pci_dev);
368 qdev_prop_set_uint32(dev, "vgamem_mb", 16);
369 qdev_prop_set_uint16(dev, "x-device-id", 0x5159);
370 pci_realize_and_unref(pci_dev, pci_bus, &error_fatal);
373 /* Populate SPD eeprom data */
374 spd_data = spd_data_generate(DDR, machine->ram_size);
375 smbus_eeprom_init_one(smbus, 0x50, spd_data);
377 mc146818_rtc_init(isa_bus, 2000, NULL);
379 /* Network card: RTL8139D */
380 network_init(pci_bus);
383 static void mips_fuloong2e_machine_init(MachineClass *mc)
385 mc->desc = "Fuloong 2e mini pc";
386 mc->init = mips_fuloong2e_init;
387 mc->block_default_type = IF_IDE;
388 mc->default_cpu_type = MIPS_CPU_TYPE_NAME("Loongson-2E");
389 mc->default_ram_size = 256 * MiB;
390 mc->default_ram_id = "fuloong2e.ram";
391 mc->minimum_page_bits = 14;
394 DEFINE_MACHINE("fuloong2e", mips_fuloong2e_machine_init)