2 * Xilinx Zynq MPSoC emulation
4 * Copyright (C) 2015 Xilinx Inc
5 * Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com>
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 #include "qemu/osdep.h"
19 #include "qapi/error.h"
20 #include "qemu-common.h"
22 #include "hw/arm/xlnx-zynqmp.h"
23 #include "hw/intc/arm_gic_common.h"
24 #include "exec/address-spaces.h"
25 #include "sysemu/kvm.h"
28 #define GIC_NUM_SPI_INTR 160
30 #define ARM_PHYS_TIMER_PPI 30
31 #define ARM_VIRT_TIMER_PPI 27
33 #define GEM_REVISION 0x40070106
35 #define GIC_BASE_ADDR 0xf9000000
36 #define GIC_DIST_ADDR 0xf9010000
37 #define GIC_CPU_ADDR 0xf9020000
40 #define SATA_ADDR 0xFD0C0000
41 #define SATA_NUM_PORTS 2
43 #define DP_ADDR 0xfd4a0000
46 #define DPDMA_ADDR 0xfd4c0000
49 static const uint64_t gem_addr
[XLNX_ZYNQMP_NUM_GEMS
] = {
50 0xFF0B0000, 0xFF0C0000, 0xFF0D0000, 0xFF0E0000,
53 static const int gem_intr
[XLNX_ZYNQMP_NUM_GEMS
] = {
57 static const uint64_t uart_addr
[XLNX_ZYNQMP_NUM_UARTS
] = {
58 0xFF000000, 0xFF010000,
61 static const int uart_intr
[XLNX_ZYNQMP_NUM_UARTS
] = {
65 static const uint64_t sdhci_addr
[XLNX_ZYNQMP_NUM_SDHCI
] = {
66 0xFF160000, 0xFF170000,
69 static const int sdhci_intr
[XLNX_ZYNQMP_NUM_SDHCI
] = {
73 static const uint64_t spi_addr
[XLNX_ZYNQMP_NUM_SPIS
] = {
74 0xFF040000, 0xFF050000,
77 static const int spi_intr
[XLNX_ZYNQMP_NUM_SPIS
] = {
81 typedef struct XlnxZynqMPGICRegion
{
84 } XlnxZynqMPGICRegion
;
86 static const XlnxZynqMPGICRegion xlnx_zynqmp_gic_regions
[] = {
87 { .region_index
= 0, .address
= GIC_DIST_ADDR
, },
88 { .region_index
= 1, .address
= GIC_CPU_ADDR
, },
91 static inline int arm_gic_ppi_index(int cpu_nr
, int ppi_index
)
93 return GIC_NUM_SPI_INTR
+ cpu_nr
* GIC_INTERNAL
+ ppi_index
;
96 static void xlnx_zynqmp_create_rpu(XlnxZynqMPState
*s
, const char *boot_cpu
,
102 for (i
= 0; i
< XLNX_ZYNQMP_NUM_RPU_CPUS
; i
++) {
105 object_initialize(&s
->rpu_cpu
[i
], sizeof(s
->rpu_cpu
[i
]),
106 "cortex-r5-" TYPE_ARM_CPU
);
107 object_property_add_child(OBJECT(s
), "rpu-cpu[*]",
108 OBJECT(&s
->rpu_cpu
[i
]), &error_abort
);
110 name
= object_get_canonical_path_component(OBJECT(&s
->rpu_cpu
[i
]));
111 if (strcmp(name
, boot_cpu
)) {
112 /* Secondary CPUs start in PSCI powered-down state */
113 object_property_set_bool(OBJECT(&s
->rpu_cpu
[i
]), true,
114 "start-powered-off", &error_abort
);
116 s
->boot_cpu_ptr
= &s
->rpu_cpu
[i
];
120 object_property_set_bool(OBJECT(&s
->rpu_cpu
[i
]), true, "reset-hivecs",
122 object_property_set_bool(OBJECT(&s
->rpu_cpu
[i
]), true, "realized",
125 error_propagate(errp
, err
);
131 static void xlnx_zynqmp_init(Object
*obj
)
133 XlnxZynqMPState
*s
= XLNX_ZYNQMP(obj
);
136 for (i
= 0; i
< XLNX_ZYNQMP_NUM_APU_CPUS
; i
++) {
137 object_initialize(&s
->apu_cpu
[i
], sizeof(s
->apu_cpu
[i
]),
138 "cortex-a53-" TYPE_ARM_CPU
);
139 object_property_add_child(obj
, "apu-cpu[*]", OBJECT(&s
->apu_cpu
[i
]),
143 object_property_add_link(obj
, "ddr-ram", TYPE_MEMORY_REGION
,
144 (Object
**)&s
->ddr_ram
,
145 qdev_prop_allow_set_link_before_realize
,
146 OBJ_PROP_LINK_UNREF_ON_RELEASE
, &error_abort
);
148 object_initialize(&s
->gic
, sizeof(s
->gic
), gic_class_name());
149 qdev_set_parent_bus(DEVICE(&s
->gic
), sysbus_get_default());
151 for (i
= 0; i
< XLNX_ZYNQMP_NUM_GEMS
; i
++) {
152 object_initialize(&s
->gem
[i
], sizeof(s
->gem
[i
]), TYPE_CADENCE_GEM
);
153 qdev_set_parent_bus(DEVICE(&s
->gem
[i
]), sysbus_get_default());
156 for (i
= 0; i
< XLNX_ZYNQMP_NUM_UARTS
; i
++) {
157 object_initialize(&s
->uart
[i
], sizeof(s
->uart
[i
]), TYPE_CADENCE_UART
);
158 qdev_set_parent_bus(DEVICE(&s
->uart
[i
]), sysbus_get_default());
161 object_initialize(&s
->sata
, sizeof(s
->sata
), TYPE_SYSBUS_AHCI
);
162 qdev_set_parent_bus(DEVICE(&s
->sata
), sysbus_get_default());
164 for (i
= 0; i
< XLNX_ZYNQMP_NUM_SDHCI
; i
++) {
165 object_initialize(&s
->sdhci
[i
], sizeof(s
->sdhci
[i
]),
167 qdev_set_parent_bus(DEVICE(&s
->sdhci
[i
]),
168 sysbus_get_default());
171 for (i
= 0; i
< XLNX_ZYNQMP_NUM_SPIS
; i
++) {
172 object_initialize(&s
->spi
[i
], sizeof(s
->spi
[i
]),
174 qdev_set_parent_bus(DEVICE(&s
->spi
[i
]), sysbus_get_default());
177 object_initialize(&s
->dp
, sizeof(s
->dp
), TYPE_XLNX_DP
);
178 qdev_set_parent_bus(DEVICE(&s
->dp
), sysbus_get_default());
180 object_initialize(&s
->dpdma
, sizeof(s
->dpdma
), TYPE_XLNX_DPDMA
);
181 qdev_set_parent_bus(DEVICE(&s
->dpdma
), sysbus_get_default());
184 static void xlnx_zynqmp_realize(DeviceState
*dev
, Error
**errp
)
186 XlnxZynqMPState
*s
= XLNX_ZYNQMP(dev
);
187 MemoryRegion
*system_memory
= get_system_memory();
190 const char *boot_cpu
= s
->boot_cpu
? s
->boot_cpu
: "apu-cpu[0]";
191 ram_addr_t ddr_low_size
, ddr_high_size
;
192 qemu_irq gic_spi
[GIC_NUM_SPI_INTR
];
195 ram_size
= memory_region_size(s
->ddr_ram
);
197 /* Create the DDR Memory Regions. User friendly checks should happen at
200 if (ram_size
> XLNX_ZYNQMP_MAX_LOW_RAM_SIZE
) {
201 /* The RAM size is above the maximum available for the low DDR.
202 * Create the high DDR memory region as well.
204 assert(ram_size
<= XLNX_ZYNQMP_MAX_RAM_SIZE
);
205 ddr_low_size
= XLNX_ZYNQMP_MAX_LOW_RAM_SIZE
;
206 ddr_high_size
= ram_size
- XLNX_ZYNQMP_MAX_LOW_RAM_SIZE
;
208 memory_region_init_alias(&s
->ddr_ram_high
, NULL
,
209 "ddr-ram-high", s
->ddr_ram
,
210 ddr_low_size
, ddr_high_size
);
211 memory_region_add_subregion(get_system_memory(),
212 XLNX_ZYNQMP_HIGH_RAM_START
,
215 /* RAM must be non-zero */
217 ddr_low_size
= ram_size
;
220 memory_region_init_alias(&s
->ddr_ram_low
, NULL
,
221 "ddr-ram-low", s
->ddr_ram
,
223 memory_region_add_subregion(get_system_memory(), 0, &s
->ddr_ram_low
);
225 /* Create the four OCM banks */
226 for (i
= 0; i
< XLNX_ZYNQMP_NUM_OCM_BANKS
; i
++) {
227 char *ocm_name
= g_strdup_printf("zynqmp.ocm_ram_bank_%d", i
);
229 memory_region_init_ram(&s
->ocm_ram
[i
], NULL
, ocm_name
,
230 XLNX_ZYNQMP_OCM_RAM_SIZE
, &error_fatal
);
231 memory_region_add_subregion(get_system_memory(),
232 XLNX_ZYNQMP_OCM_RAM_0_ADDRESS
+
233 i
* XLNX_ZYNQMP_OCM_RAM_SIZE
,
239 qdev_prop_set_uint32(DEVICE(&s
->gic
), "num-irq", GIC_NUM_SPI_INTR
+ 32);
240 qdev_prop_set_uint32(DEVICE(&s
->gic
), "revision", 2);
241 qdev_prop_set_uint32(DEVICE(&s
->gic
), "num-cpu", XLNX_ZYNQMP_NUM_APU_CPUS
);
243 /* Realize APUs before realizing the GIC. KVM requires this. */
244 for (i
= 0; i
< XLNX_ZYNQMP_NUM_APU_CPUS
; i
++) {
247 object_property_set_int(OBJECT(&s
->apu_cpu
[i
]), QEMU_PSCI_CONDUIT_SMC
,
248 "psci-conduit", &error_abort
);
250 name
= object_get_canonical_path_component(OBJECT(&s
->apu_cpu
[i
]));
251 if (strcmp(name
, boot_cpu
)) {
252 /* Secondary CPUs start in PSCI powered-down state */
253 object_property_set_bool(OBJECT(&s
->apu_cpu
[i
]), true,
254 "start-powered-off", &error_abort
);
256 s
->boot_cpu_ptr
= &s
->apu_cpu
[i
];
260 object_property_set_bool(OBJECT(&s
->apu_cpu
[i
]),
261 s
->secure
, "has_el3", NULL
);
262 object_property_set_bool(OBJECT(&s
->apu_cpu
[i
]),
263 false, "has_el2", NULL
);
264 object_property_set_int(OBJECT(&s
->apu_cpu
[i
]), GIC_BASE_ADDR
,
265 "reset-cbar", &error_abort
);
266 object_property_set_bool(OBJECT(&s
->apu_cpu
[i
]), true, "realized",
269 error_propagate(errp
, err
);
274 object_property_set_bool(OBJECT(&s
->gic
), true, "realized", &err
);
276 error_propagate(errp
, err
);
280 assert(ARRAY_SIZE(xlnx_zynqmp_gic_regions
) == XLNX_ZYNQMP_GIC_REGIONS
);
281 for (i
= 0; i
< XLNX_ZYNQMP_GIC_REGIONS
; i
++) {
282 SysBusDevice
*gic
= SYS_BUS_DEVICE(&s
->gic
);
283 const XlnxZynqMPGICRegion
*r
= &xlnx_zynqmp_gic_regions
[i
];
284 MemoryRegion
*mr
= sysbus_mmio_get_region(gic
, r
->region_index
);
285 uint32_t addr
= r
->address
;
288 sysbus_mmio_map(gic
, r
->region_index
, addr
);
290 for (j
= 0; j
< XLNX_ZYNQMP_GIC_ALIASES
; j
++) {
291 MemoryRegion
*alias
= &s
->gic_mr
[i
][j
];
293 addr
+= XLNX_ZYNQMP_GIC_REGION_SIZE
;
294 memory_region_init_alias(alias
, OBJECT(s
), "zynqmp-gic-alias", mr
,
295 0, XLNX_ZYNQMP_GIC_REGION_SIZE
);
296 memory_region_add_subregion(system_memory
, addr
, alias
);
300 for (i
= 0; i
< XLNX_ZYNQMP_NUM_APU_CPUS
; i
++) {
303 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->gic
), i
,
304 qdev_get_gpio_in(DEVICE(&s
->apu_cpu
[i
]),
306 irq
= qdev_get_gpio_in(DEVICE(&s
->gic
),
307 arm_gic_ppi_index(i
, ARM_PHYS_TIMER_PPI
));
308 qdev_connect_gpio_out(DEVICE(&s
->apu_cpu
[i
]), 0, irq
);
309 irq
= qdev_get_gpio_in(DEVICE(&s
->gic
),
310 arm_gic_ppi_index(i
, ARM_VIRT_TIMER_PPI
));
311 qdev_connect_gpio_out(DEVICE(&s
->apu_cpu
[i
]), 1, irq
);
315 xlnx_zynqmp_create_rpu(s
, boot_cpu
, &err
);
317 error_propagate(errp
, err
);
322 if (!s
->boot_cpu_ptr
) {
323 error_setg(errp
, "ZynqMP Boot cpu %s not found", boot_cpu
);
327 for (i
= 0; i
< GIC_NUM_SPI_INTR
; i
++) {
328 gic_spi
[i
] = qdev_get_gpio_in(DEVICE(&s
->gic
), i
);
331 for (i
= 0; i
< XLNX_ZYNQMP_NUM_GEMS
; i
++) {
332 NICInfo
*nd
= &nd_table
[i
];
335 qemu_check_nic_model(nd
, TYPE_CADENCE_GEM
);
336 qdev_set_nic_properties(DEVICE(&s
->gem
[i
]), nd
);
338 object_property_set_int(OBJECT(&s
->gem
[i
]), GEM_REVISION
, "revision",
340 object_property_set_int(OBJECT(&s
->gem
[i
]), 2, "num-priority-queues",
342 object_property_set_bool(OBJECT(&s
->gem
[i
]), true, "realized", &err
);
344 error_propagate(errp
, err
);
347 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->gem
[i
]), 0, gem_addr
[i
]);
348 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->gem
[i
]), 0,
349 gic_spi
[gem_intr
[i
]]);
352 for (i
= 0; i
< XLNX_ZYNQMP_NUM_UARTS
; i
++) {
353 qdev_prop_set_chr(DEVICE(&s
->uart
[i
]), "chardev", serial_hds
[i
]);
354 object_property_set_bool(OBJECT(&s
->uart
[i
]), true, "realized", &err
);
356 error_propagate(errp
, err
);
359 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->uart
[i
]), 0, uart_addr
[i
]);
360 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->uart
[i
]), 0,
361 gic_spi
[uart_intr
[i
]]);
364 object_property_set_int(OBJECT(&s
->sata
), SATA_NUM_PORTS
, "num-ports",
366 object_property_set_bool(OBJECT(&s
->sata
), true, "realized", &err
);
368 error_propagate(errp
, err
);
372 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->sata
), 0, SATA_ADDR
);
373 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->sata
), 0, gic_spi
[SATA_INTR
]);
375 for (i
= 0; i
< XLNX_ZYNQMP_NUM_SDHCI
; i
++) {
378 object_property_set_bool(OBJECT(&s
->sdhci
[i
]), true,
381 error_propagate(errp
, err
);
384 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->sdhci
[i
]), 0,
386 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->sdhci
[i
]), 0,
387 gic_spi
[sdhci_intr
[i
]]);
388 /* Alias controller SD bus to the SoC itself */
389 bus_name
= g_strdup_printf("sd-bus%d", i
);
390 object_property_add_alias(OBJECT(s
), bus_name
,
391 OBJECT(&s
->sdhci
[i
]), "sd-bus",
396 for (i
= 0; i
< XLNX_ZYNQMP_NUM_SPIS
; i
++) {
399 object_property_set_bool(OBJECT(&s
->spi
[i
]), true, "realized", &err
);
401 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->spi
[i
]), 0, spi_addr
[i
]);
402 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->spi
[i
]), 0,
403 gic_spi
[spi_intr
[i
]]);
405 /* Alias controller SPI bus to the SoC itself */
406 bus_name
= g_strdup_printf("spi%d", i
);
407 object_property_add_alias(OBJECT(s
), bus_name
,
408 OBJECT(&s
->spi
[i
]), "spi0",
413 object_property_set_bool(OBJECT(&s
->dp
), true, "realized", &err
);
415 error_propagate(errp
, err
);
418 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->dp
), 0, DP_ADDR
);
419 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->dp
), 0, gic_spi
[DP_IRQ
]);
421 object_property_set_bool(OBJECT(&s
->dpdma
), true, "realized", &err
);
423 error_propagate(errp
, err
);
426 object_property_set_link(OBJECT(&s
->dp
), OBJECT(&s
->dpdma
), "dpdma",
428 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->dpdma
), 0, DPDMA_ADDR
);
429 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->dpdma
), 0, gic_spi
[DPDMA_IRQ
]);
432 static Property xlnx_zynqmp_props
[] = {
433 DEFINE_PROP_STRING("boot-cpu", XlnxZynqMPState
, boot_cpu
),
434 DEFINE_PROP_BOOL("secure", XlnxZynqMPState
, secure
, false),
435 DEFINE_PROP_BOOL("has_rpu", XlnxZynqMPState
, has_rpu
, false),
436 DEFINE_PROP_END_OF_LIST()
439 static void xlnx_zynqmp_class_init(ObjectClass
*oc
, void *data
)
441 DeviceClass
*dc
= DEVICE_CLASS(oc
);
443 dc
->props
= xlnx_zynqmp_props
;
444 dc
->realize
= xlnx_zynqmp_realize
;
447 static const TypeInfo xlnx_zynqmp_type_info
= {
448 .name
= TYPE_XLNX_ZYNQMP
,
449 .parent
= TYPE_DEVICE
,
450 .instance_size
= sizeof(XlnxZynqMPState
),
451 .instance_init
= xlnx_zynqmp_init
,
452 .class_init
= xlnx_zynqmp_class_init
,
455 static void xlnx_zynqmp_register_types(void)
457 type_register_static(&xlnx_zynqmp_type_info
);
460 type_init(xlnx_zynqmp_register_types
)