include/hw/southbridge/piix.h

   1 /*
   2  * QEMU PIIX South Bridge Emulation
   3  *
   4  * Copyright (c) 2006 Fabrice Bellard
   5  * Copyright (c) 2018 Hervé Poussineau
   6  *
   7  * This work is licensed under the terms of the GNU GPL, version 2 or later.
   8  * See the COPYING file in the top-level directory.
   9  *
  10  */
  11
  12 #ifndef HW_SOUTHBRIDGE_PIIX_H
  13 #define HW_SOUTHBRIDGE_PIIX_H
  14
  15 #include "hw/pci/pci.h"
  16 #include "qom/object.h"
  17
  18 /* PIRQRC[A:D]: PIRQx Route Control Registers */
  19 #define PIIX_PIRQCA 0x60
  20 #define PIIX_PIRQCB 0x61
  21 #define PIIX_PIRQCC 0x62
  22 #define PIIX_PIRQCD 0x63
  23
  24 /*
  25  * Reset Control Register: PCI-accessible ISA-Compatible Register at address
  26  * 0xcf9, provided by the PCI/ISA bridge (PIIX3 PCI function 0, 8086:7000).
  27  */
  28 #define PIIX_RCR_IOPORT 0xcf9
  29
  30 #define PIIX_NUM_PIC_IRQS       16      /* i8259 * 2 */
  31 #define PIIX_NUM_PIRQS          4ULL    /* PIRQ[A-D] */
  32
  33 struct PIIXState {
  34     PCIDevice dev;
  35
  36     /*
  37      * bitmap to track pic levels.
  38      * The pic level is the logical OR of all the PCI irqs mapped to it
  39      * So one PIC level is tracked by PIIX_NUM_PIRQS bits.
  40      *
  41      * PIRQ is mapped to PIC pins, we track it by
  42      * PIIX_NUM_PIRQS * PIIX_NUM_PIC_IRQS = 64 bits with
  43      * pic_irq * PIIX_NUM_PIRQS + pirq
  44      */
  45 #if PIIX_NUM_PIC_IRQS * PIIX_NUM_PIRQS > 64
  46 #error "unable to encode pic state in 64bit in pic_levels."
  47 #endif
  48     uint64_t pic_levels;
  49
  50     qemu_irq *pic;
  51
  52     /* This member isn't used. Just for save/load compatibility */
  53     int32_t pci_irq_levels_vmstate[PIIX_NUM_PIRQS];
  54
  55     /* Reset Control Register contents */
  56     uint8_t rcr;
  57
  58     /* IO memory region for Reset Control Register (PIIX_RCR_IOPORT) */
  59     MemoryRegion rcr_mem;
  60 };
  61 typedef struct PIIXState PIIX3State;
  62
  63 #define TYPE_PIIX3_PCI_DEVICE "pci-piix3"
  64 DECLARE_INSTANCE_CHECKER(PIIX3State, PIIX3_PCI_DEVICE,
  65                          TYPE_PIIX3_PCI_DEVICE)
  66
  67 #define TYPE_PIIX3_DEVICE "PIIX3"
  68 #define TYPE_PIIX3_XEN_DEVICE "PIIX3-xen"
  69 #define TYPE_PIIX4_PCI_DEVICE "piix4-isa"
  70
  71 #endif