target/ppc/monitor.c

   1 /*
   2  * QEMU monitor
   3  *
   4  * Copyright (c) 2003-2004 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "qemu/osdep.h"
  26 #include "cpu.h"
  27 #include "monitor/monitor.h"
  28 #include "qemu/ctype.h"
  29 #include "monitor/hmp-target.h"
  30 #include "monitor/hmp.h"
  31
  32 static target_long monitor_get_ccr(Monitor *mon, const struct MonitorDef *md,
  33                                    int val)
  34 {
  35     CPUArchState *env = mon_get_cpu_env(mon);
  36     unsigned int u;
  37     int i;
  38
  39     u = 0;
  40     for (i = 0; i < 8; i++) {
  41         u |= env->crf[i] << (32 - (4 * (i + 1)));
  42     }
  43
  44     return u;
  45 }
  46
  47 static target_long monitor_get_xer(Monitor *mon, const struct MonitorDef *md,
  48                                    int val)
  49 {
  50     CPUArchState *env = mon_get_cpu_env(mon);
  51     return cpu_read_xer(env);
  52 }
  53
  54 static target_long monitor_get_decr(Monitor *mon, const struct MonitorDef *md,
  55                                     int val)
  56 {
  57     CPUArchState *env = mon_get_cpu_env(mon);
  58     if (!env->tb_env) {
  59         return 0;
  60     }
  61     return cpu_ppc_load_decr(env);
  62 }
  63
  64 static target_long monitor_get_tbu(Monitor *mon, const struct MonitorDef *md,
  65                                    int val)
  66 {
  67     CPUArchState *env = mon_get_cpu_env(mon);
  68     if (!env->tb_env) {
  69         return 0;
  70     }
  71     return cpu_ppc_load_tbu(env);
  72 }
  73
  74 static target_long monitor_get_tbl(Monitor *mon, const struct MonitorDef *md,
  75                                    int val)
  76 {
  77     CPUArchState *env = mon_get_cpu_env(mon);
  78     if (!env->tb_env) {
  79         return 0;
  80     }
  81     return cpu_ppc_load_tbl(env);
  82 }
  83
  84 void hmp_info_tlb(Monitor *mon, const QDict *qdict)
  85 {
  86     CPUArchState *env1 = mon_get_cpu_env(mon);
  87
  88     if (!env1) {
  89         monitor_printf(mon, "No CPU available\n");
  90         return;
  91     }
  92     dump_mmu(env1);
  93 }
  94
  95 const MonitorDef monitor_defs[] = {
  96     { "fpscr", offsetof(CPUPPCState, fpscr) },
  97     /* Next instruction pointer */
  98     { "nip|pc", offsetof(CPUPPCState, nip) },
  99     { "lr", offsetof(CPUPPCState, lr) },
 100     { "ctr", offsetof(CPUPPCState, ctr) },
 101     { "decr", 0, &monitor_get_decr, },
 102     { "ccr|cr", 0, &monitor_get_ccr, },
 103     /* Machine state register */
 104     { "xer", 0, &monitor_get_xer },
 105     { "msr", offsetof(CPUPPCState, msr) },
 106     { "tbu", 0, &monitor_get_tbu, },
 107     { "tbl", 0, &monitor_get_tbl, },
 108     { NULL },
 109 };
 110
 111 const MonitorDef *target_monitor_defs(void)
 112 {
 113     return monitor_defs;
 114 }
 115
 116 static int ppc_cpu_get_reg_num(const char *numstr, int maxnum, int *pregnum)
 117 {
 118     int regnum;
 119     char *endptr = NULL;
 120
 121     if (!*numstr) {
 122         return false;
 123     }
 124
 125     regnum = strtoul(numstr, &endptr, 10);
 126     if (*endptr || (regnum >= maxnum)) {
 127         return false;
 128     }
 129     *pregnum = regnum;
 130
 131     return true;
 132 }
 133
 134 int target_get_monitor_def(CPUState *cs, const char *name, uint64_t *pval)
 135 {
 136     int i, regnum;
 137     PowerPCCPU *cpu = POWERPC_CPU(cs);
 138     CPUPPCState *env = &cpu->env;
 139
 140     /* General purpose registers */
 141     if ((qemu_tolower(name[0]) == 'r') &&
 142         ppc_cpu_get_reg_num(name + 1, ARRAY_SIZE(env->gpr), &regnum)) {
 143         *pval = env->gpr[regnum];
 144         return 0;
 145     }
 146
 147     /* Floating point registers */
 148     if ((qemu_tolower(name[0]) == 'f') &&
 149         ppc_cpu_get_reg_num(name + 1, 32, &regnum)) {
 150         *pval = *cpu_fpr_ptr(env, regnum);
 151         return 0;
 152     }
 153
 154     /* Special purpose registers */
 155     for (i = 0; i < ARRAY_SIZE(env->spr_cb); ++i) {
 156         ppc_spr_t *spr = &env->spr_cb[i];
 157
 158         if (spr->name && (strcasecmp(name, spr->name) == 0)) {
 159             *pval = env->spr[i];
 160             return 0;
 161         }
 162     }
 163
 164     /* Segment registers */
 165 #if !defined(CONFIG_USER_ONLY)
 166     if ((strncasecmp(name, "sr", 2) == 0) &&
 167         ppc_cpu_get_reg_num(name + 2, ARRAY_SIZE(env->sr), &regnum)) {
 168         *pval = env->sr[regnum];
 169         return 0;
 170     }
 171 #endif
 172
 173     return -EINVAL;
 174 }