2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License, version 2, as
4 * published by the Free Software Foundation.
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
11 * You should have received a copy of the GNU General Public License
12 * along with this program; if not, see <http://www.gnu.org/licenses/>.
14 * Copyright IBM Corp. 2008
16 * Authors: Hollis Blanchard <hollisb@us.ibm.com>
19 /* This file implements emulation of the 32-bit PCI controller found in some
20 * 4xx SoCs, such as the 440EP. */
22 #include "qemu/osdep.h"
24 #include "hw/ppc/ppc.h"
25 #include "hw/ppc/ppc4xx.h"
26 #include "qemu/module.h"
27 #include "hw/pci/pci.h"
28 #include "hw/pci/pci_host.h"
29 #include "exec/address-spaces.h"
44 #define PPC4xx_PCI_HOST_BRIDGE(obj) \
45 OBJECT_CHECK(PPC4xxPCIState, (obj), TYPE_PPC4xx_PCI_HOST_BRIDGE)
47 #define PPC4xx_PCI_NR_PMMS 3
48 #define PPC4xx_PCI_NR_PTMS 2
50 struct PPC4xxPCIState
{
51 PCIHostState parent_obj
;
53 struct PCIMasterMap pmm
[PPC4xx_PCI_NR_PMMS
];
54 struct PCITargetMap ptm
[PPC4xx_PCI_NR_PTMS
];
57 MemoryRegion container
;
60 typedef struct PPC4xxPCIState PPC4xxPCIState
;
62 #define PCIC0_CFGADDR 0x0
63 #define PCIC0_CFGDATA 0x4
65 /* PLB Memory Map (PMM) registers specify which PLB addresses are translated to
67 #define PCIL0_PMM0LA 0x0
68 #define PCIL0_PMM0MA 0x4
69 #define PCIL0_PMM0PCILA 0x8
70 #define PCIL0_PMM0PCIHA 0xc
71 #define PCIL0_PMM1LA 0x10
72 #define PCIL0_PMM1MA 0x14
73 #define PCIL0_PMM1PCILA 0x18
74 #define PCIL0_PMM1PCIHA 0x1c
75 #define PCIL0_PMM2LA 0x20
76 #define PCIL0_PMM2MA 0x24
77 #define PCIL0_PMM2PCILA 0x28
78 #define PCIL0_PMM2PCIHA 0x2c
80 /* PCI Target Map (PTM) registers specify which PCI addresses are translated to
82 #define PCIL0_PTM1MS 0x30
83 #define PCIL0_PTM1LA 0x34
84 #define PCIL0_PTM2MS 0x38
85 #define PCIL0_PTM2LA 0x3c
86 #define PCI_REG_BASE 0x800000
87 #define PCI_REG_SIZE 0x40
89 #define PCI_ALL_SIZE (PCI_REG_BASE + PCI_REG_SIZE)
91 static void ppc4xx_pci_reg_write4(void *opaque
, hwaddr offset
,
92 uint64_t value
, unsigned size
)
94 struct PPC4xxPCIState
*pci
= opaque
;
96 /* We ignore all target attempts at PCI configuration, effectively
97 * assuming a bidirectional 1:1 mapping of PLB and PCI space. */
101 pci
->pmm
[0].la
= value
;
104 pci
->pmm
[0].ma
= value
;
106 case PCIL0_PMM0PCIHA
:
107 pci
->pmm
[0].pciha
= value
;
109 case PCIL0_PMM0PCILA
:
110 pci
->pmm
[0].pcila
= value
;
114 pci
->pmm
[1].la
= value
;
117 pci
->pmm
[1].ma
= value
;
119 case PCIL0_PMM1PCIHA
:
120 pci
->pmm
[1].pciha
= value
;
122 case PCIL0_PMM1PCILA
:
123 pci
->pmm
[1].pcila
= value
;
127 pci
->pmm
[2].la
= value
;
130 pci
->pmm
[2].ma
= value
;
132 case PCIL0_PMM2PCIHA
:
133 pci
->pmm
[2].pciha
= value
;
135 case PCIL0_PMM2PCILA
:
136 pci
->pmm
[2].pcila
= value
;
140 pci
->ptm
[0].ms
= value
;
143 pci
->ptm
[0].la
= value
;
146 pci
->ptm
[1].ms
= value
;
149 pci
->ptm
[1].la
= value
;
153 printf("%s: unhandled PCI internal register 0x%lx\n", __func__
,
154 (unsigned long)offset
);
159 static uint64_t ppc4xx_pci_reg_read4(void *opaque
, hwaddr offset
,
162 struct PPC4xxPCIState
*pci
= opaque
;
167 value
= pci
->pmm
[0].la
;
170 value
= pci
->pmm
[0].ma
;
172 case PCIL0_PMM0PCIHA
:
173 value
= pci
->pmm
[0].pciha
;
175 case PCIL0_PMM0PCILA
:
176 value
= pci
->pmm
[0].pcila
;
180 value
= pci
->pmm
[1].la
;
183 value
= pci
->pmm
[1].ma
;
185 case PCIL0_PMM1PCIHA
:
186 value
= pci
->pmm
[1].pciha
;
188 case PCIL0_PMM1PCILA
:
189 value
= pci
->pmm
[1].pcila
;
193 value
= pci
->pmm
[2].la
;
196 value
= pci
->pmm
[2].ma
;
198 case PCIL0_PMM2PCIHA
:
199 value
= pci
->pmm
[2].pciha
;
201 case PCIL0_PMM2PCILA
:
202 value
= pci
->pmm
[2].pcila
;
206 value
= pci
->ptm
[0].ms
;
209 value
= pci
->ptm
[0].la
;
212 value
= pci
->ptm
[1].ms
;
215 value
= pci
->ptm
[1].la
;
219 printf("%s: invalid PCI internal register 0x%lx\n", __func__
,
220 (unsigned long)offset
);
227 static const MemoryRegionOps pci_reg_ops
= {
228 .read
= ppc4xx_pci_reg_read4
,
229 .write
= ppc4xx_pci_reg_write4
,
230 .endianness
= DEVICE_LITTLE_ENDIAN
,
233 static void ppc4xx_pci_reset(void *opaque
)
235 struct PPC4xxPCIState
*pci
= opaque
;
237 memset(pci
->pmm
, 0, sizeof(pci
->pmm
));
238 memset(pci
->ptm
, 0, sizeof(pci
->ptm
));
241 /* On Bamboo, all pins from each slot are tied to a single board IRQ. This
242 * may need further refactoring for other boards. */
243 static int ppc4xx_pci_map_irq(PCIDevice
*pci_dev
, int irq_num
)
245 int slot
= pci_dev
->devfn
>> 3;
247 trace_ppc4xx_pci_map_irq(pci_dev
->devfn
, irq_num
, slot
);
252 static void ppc4xx_pci_set_irq(void *opaque
, int irq_num
, int level
)
254 qemu_irq
*pci_irqs
= opaque
;
256 trace_ppc4xx_pci_set_irq(irq_num
);
258 fprintf(stderr
, "%s: PCI irq %d\n", __func__
, irq_num
);
261 qemu_set_irq(pci_irqs
[irq_num
], level
);
264 static const VMStateDescription vmstate_pci_master_map
= {
265 .name
= "pci_master_map",
267 .minimum_version_id
= 0,
268 .fields
= (VMStateField
[]) {
269 VMSTATE_UINT32(la
, struct PCIMasterMap
),
270 VMSTATE_UINT32(ma
, struct PCIMasterMap
),
271 VMSTATE_UINT32(pcila
, struct PCIMasterMap
),
272 VMSTATE_UINT32(pciha
, struct PCIMasterMap
),
273 VMSTATE_END_OF_LIST()
277 static const VMStateDescription vmstate_pci_target_map
= {
278 .name
= "pci_target_map",
280 .minimum_version_id
= 0,
281 .fields
= (VMStateField
[]) {
282 VMSTATE_UINT32(ms
, struct PCITargetMap
),
283 VMSTATE_UINT32(la
, struct PCITargetMap
),
284 VMSTATE_END_OF_LIST()
288 static const VMStateDescription vmstate_ppc4xx_pci
= {
289 .name
= "ppc4xx_pci",
291 .minimum_version_id
= 1,
292 .fields
= (VMStateField
[]) {
293 VMSTATE_STRUCT_ARRAY(pmm
, PPC4xxPCIState
, PPC4xx_PCI_NR_PMMS
, 1,
294 vmstate_pci_master_map
,
295 struct PCIMasterMap
),
296 VMSTATE_STRUCT_ARRAY(ptm
, PPC4xxPCIState
, PPC4xx_PCI_NR_PTMS
, 1,
297 vmstate_pci_target_map
,
298 struct PCITargetMap
),
299 VMSTATE_END_OF_LIST()
303 /* XXX Interrupt acknowledge cycles not supported. */
304 static void ppc4xx_pcihost_realize(DeviceState
*dev
, Error
**errp
)
306 SysBusDevice
*sbd
= SYS_BUS_DEVICE(dev
);
312 h
= PCI_HOST_BRIDGE(dev
);
313 s
= PPC4xx_PCI_HOST_BRIDGE(dev
);
315 for (i
= 0; i
< ARRAY_SIZE(s
->irq
); i
++) {
316 sysbus_init_irq(sbd
, &s
->irq
[i
]);
319 b
= pci_register_root_bus(dev
, NULL
, ppc4xx_pci_set_irq
,
320 ppc4xx_pci_map_irq
, s
->irq
, get_system_memory(),
321 get_system_io(), 0, 4, TYPE_PCI_BUS
);
324 pci_create_simple(b
, 0, "ppc4xx-host-bridge");
326 /* XXX split into 2 memory regions, one for config space, one for regs */
327 memory_region_init(&s
->container
, OBJECT(s
), "pci-container", PCI_ALL_SIZE
);
328 memory_region_init_io(&h
->conf_mem
, OBJECT(s
), &pci_host_conf_le_ops
, h
,
330 memory_region_init_io(&h
->data_mem
, OBJECT(s
), &pci_host_data_le_ops
, h
,
332 memory_region_init_io(&s
->iomem
, OBJECT(s
), &pci_reg_ops
, s
,
333 "pci.reg", PCI_REG_SIZE
);
334 memory_region_add_subregion(&s
->container
, PCIC0_CFGADDR
, &h
->conf_mem
);
335 memory_region_add_subregion(&s
->container
, PCIC0_CFGDATA
, &h
->data_mem
);
336 memory_region_add_subregion(&s
->container
, PCI_REG_BASE
, &s
->iomem
);
337 sysbus_init_mmio(sbd
, &s
->container
);
338 qemu_register_reset(ppc4xx_pci_reset
, s
);
341 static void ppc4xx_host_bridge_class_init(ObjectClass
*klass
, void *data
)
343 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
344 DeviceClass
*dc
= DEVICE_CLASS(klass
);
346 dc
->desc
= "Host bridge";
347 k
->vendor_id
= PCI_VENDOR_ID_IBM
;
348 k
->device_id
= PCI_DEVICE_ID_IBM_440GX
;
349 k
->class_id
= PCI_CLASS_BRIDGE_OTHER
;
351 * PCI-facing part of the host bridge, not usable without the
352 * host-facing part, which can't be device_add'ed, yet.
354 dc
->user_creatable
= false;
357 static const TypeInfo ppc4xx_host_bridge_info
= {
358 .name
= "ppc4xx-host-bridge",
359 .parent
= TYPE_PCI_DEVICE
,
360 .instance_size
= sizeof(PCIDevice
),
361 .class_init
= ppc4xx_host_bridge_class_init
,
362 .interfaces
= (InterfaceInfo
[]) {
363 { INTERFACE_CONVENTIONAL_PCI_DEVICE
},
368 static void ppc4xx_pcihost_class_init(ObjectClass
*klass
, void *data
)
370 DeviceClass
*dc
= DEVICE_CLASS(klass
);
372 dc
->realize
= ppc4xx_pcihost_realize
;
373 dc
->vmsd
= &vmstate_ppc4xx_pci
;
376 static const TypeInfo ppc4xx_pcihost_info
= {
377 .name
= TYPE_PPC4xx_PCI_HOST_BRIDGE
,
378 .parent
= TYPE_PCI_HOST_BRIDGE
,
379 .instance_size
= sizeof(PPC4xxPCIState
),
380 .class_init
= ppc4xx_pcihost_class_init
,
383 static void ppc4xx_pci_register_types(void)
385 type_register_static(&ppc4xx_pcihost_info
);
386 type_register_static(&ppc4xx_host_bridge_info
);
389 type_init(ppc4xx_pci_register_types
)