2 * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 * * Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * * Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * * Neither the name of the Open Source and Linux Lab nor the
13 * names of its contributors may be used to endorse or promote products
14 * derived from this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
20 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
23 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
25 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 #include "qemu-common.h"
32 #include "host-utils.h"
33 #if !defined(CONFIG_USER_ONLY)
34 #include "hw/loader.h"
37 void cpu_reset(CPUXtensaState
*env
)
39 env
->exception_taken
= 0;
40 env
->pc
= env
->config
->exception_vector
[EXC_RESET
];
41 env
->sregs
[LITBASE
] &= ~1;
42 env
->sregs
[PS
] = xtensa_option_enabled(env
->config
,
43 XTENSA_OPTION_INTERRUPT
) ? 0x1f : 0x10;
44 env
->sregs
[VECBASE
] = env
->config
->vecbase
;
46 env
->pending_irq_level
= 0;
49 static const XtensaConfig core_config
[] = {
51 .name
= "sample-xtensa-core",
53 (XTENSA_OPTION_BIT(XTENSA_OPTION_HW_ALIGNMENT
) |
54 XTENSA_OPTION_BIT(XTENSA_OPTION_MMU
)),
58 .vecbase
= 0x5fff8400,
60 [EXC_RESET
] = 0x5fff8000,
61 [EXC_WINDOW_OVERFLOW4
] = 0x5fff8400,
62 [EXC_WINDOW_UNDERFLOW4
] = 0x5fff8440,
63 [EXC_WINDOW_OVERFLOW8
] = 0x5fff8480,
64 [EXC_WINDOW_UNDERFLOW8
] = 0x5fff84c0,
65 [EXC_WINDOW_OVERFLOW12
] = 0x5fff8500,
66 [EXC_WINDOW_UNDERFLOW12
] = 0x5fff8540,
67 [EXC_KERNEL
] = 0x5fff861c,
68 [EXC_USER
] = 0x5fff863c,
69 [EXC_DOUBLE
] = 0x5fff865c,
88 .inttype
= INTTYPE_TIMER
,
95 .clock_freq_khz
= 912000,
99 CPUXtensaState
*cpu_xtensa_init(const char *cpu_model
)
101 static int tcg_inited
;
103 const XtensaConfig
*config
= NULL
;
106 for (i
= 0; i
< ARRAY_SIZE(core_config
); ++i
)
107 if (strcmp(core_config
[i
].name
, cpu_model
) == 0) {
108 config
= core_config
+ i
;
112 if (config
== NULL
) {
116 env
= g_malloc0(sizeof(*env
));
117 env
->config
= config
;
122 xtensa_translate_init();
125 xtensa_irq_init(env
);
131 void xtensa_cpu_list(FILE *f
, fprintf_function cpu_fprintf
)
134 cpu_fprintf(f
, "Available CPUs:\n");
135 for (i
= 0; i
< ARRAY_SIZE(core_config
); ++i
) {
136 cpu_fprintf(f
, " %s\n", core_config
[i
].name
);
140 target_phys_addr_t
cpu_get_phys_page_debug(CPUState
*env
, target_ulong addr
)
145 static uint32_t relocated_vector(CPUState
*env
, uint32_t vector
)
147 if (xtensa_option_enabled(env
->config
,
148 XTENSA_OPTION_RELOCATABLE_VECTOR
)) {
149 return vector
- env
->config
->vecbase
+ env
->sregs
[VECBASE
];
156 * Handle penging IRQ.
157 * For the high priority interrupt jump to the corresponding interrupt vector.
158 * For the level-1 interrupt convert it to either user, kernel or double
159 * exception with the 'level-1 interrupt' exception cause.
161 static void handle_interrupt(CPUState
*env
)
163 int level
= env
->pending_irq_level
;
165 if (level
> xtensa_get_cintlevel(env
) &&
166 level
<= env
->config
->nlevel
&&
167 (env
->config
->level_mask
[level
] &
169 env
->sregs
[INTENABLE
])) {
171 env
->sregs
[EPC1
+ level
- 1] = env
->pc
;
172 env
->sregs
[EPS2
+ level
- 2] = env
->sregs
[PS
];
174 (env
->sregs
[PS
] & ~PS_INTLEVEL
) | level
| PS_EXCM
;
175 env
->pc
= relocated_vector(env
,
176 env
->config
->interrupt_vector
[level
]);
178 env
->sregs
[EXCCAUSE
] = LEVEL1_INTERRUPT_CAUSE
;
180 if (env
->sregs
[PS
] & PS_EXCM
) {
181 if (env
->config
->ndepc
) {
182 env
->sregs
[DEPC
] = env
->pc
;
184 env
->sregs
[EPC1
] = env
->pc
;
186 env
->exception_index
= EXC_DOUBLE
;
188 env
->sregs
[EPC1
] = env
->pc
;
189 env
->exception_index
=
190 (env
->sregs
[PS
] & PS_UM
) ? EXC_USER
: EXC_KERNEL
;
192 env
->sregs
[PS
] |= PS_EXCM
;
194 env
->exception_taken
= 1;
198 void do_interrupt(CPUState
*env
)
200 if (env
->exception_index
== EXC_IRQ
) {
201 qemu_log_mask(CPU_LOG_INT
,
202 "%s(EXC_IRQ) level = %d, cintlevel = %d, "
203 "pc = %08x, a0 = %08x, ps = %08x, "
204 "intset = %08x, intenable = %08x, "
206 __func__
, env
->pending_irq_level
, xtensa_get_cintlevel(env
),
207 env
->pc
, env
->regs
[0], env
->sregs
[PS
],
208 env
->sregs
[INTSET
], env
->sregs
[INTENABLE
],
210 handle_interrupt(env
);
213 switch (env
->exception_index
) {
214 case EXC_WINDOW_OVERFLOW4
:
215 case EXC_WINDOW_UNDERFLOW4
:
216 case EXC_WINDOW_OVERFLOW8
:
217 case EXC_WINDOW_UNDERFLOW8
:
218 case EXC_WINDOW_OVERFLOW12
:
219 case EXC_WINDOW_UNDERFLOW12
:
223 qemu_log_mask(CPU_LOG_INT
, "%s(%d) "
224 "pc = %08x, a0 = %08x, ps = %08x, ccount = %08x\n",
225 __func__
, env
->exception_index
,
226 env
->pc
, env
->regs
[0], env
->sregs
[PS
], env
->sregs
[CCOUNT
]);
227 if (env
->config
->exception_vector
[env
->exception_index
]) {
228 env
->pc
= relocated_vector(env
,
229 env
->config
->exception_vector
[env
->exception_index
]);
230 env
->exception_taken
= 1;
232 qemu_log("%s(pc = %08x) bad exception_index: %d\n",
233 __func__
, env
->pc
, env
->exception_index
);
241 qemu_log("%s(pc = %08x) unknown exception_index: %d\n",
242 __func__
, env
->pc
, env
->exception_index
);
245 check_interrupts(env
);