4 * Copyright (c) 2013 Alexander Graf <agraf@suse.de>
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 #include "qemu/osdep.h"
25 #include "translate.h"
26 #include "internals.h"
27 #include "qemu/host-utils.h"
29 #include "exec/semihost.h"
30 #include "exec/gen-icount.h"
32 #include "exec/helper-proto.h"
33 #include "exec/helper-gen.h"
36 #include "trace-tcg.h"
38 static TCGv_i64 cpu_X
[32];
39 static TCGv_i64 cpu_pc
;
41 /* Load/store exclusive handling */
42 static TCGv_i64 cpu_exclusive_high
;
44 static const char *regnames
[] = {
45 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",
46 "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",
47 "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23",
48 "x24", "x25", "x26", "x27", "x28", "x29", "lr", "sp"
52 A64_SHIFT_TYPE_LSL
= 0,
53 A64_SHIFT_TYPE_LSR
= 1,
54 A64_SHIFT_TYPE_ASR
= 2,
55 A64_SHIFT_TYPE_ROR
= 3
58 /* Table based decoder typedefs - used when the relevant bits for decode
59 * are too awkwardly scattered across the instruction (eg SIMD).
61 typedef void AArch64DecodeFn(DisasContext
*s
, uint32_t insn
);
63 typedef struct AArch64DecodeTable
{
66 AArch64DecodeFn
*disas_fn
;
69 /* Function prototype for gen_ functions for calling Neon helpers */
70 typedef void NeonGenOneOpEnvFn(TCGv_i32
, TCGv_ptr
, TCGv_i32
);
71 typedef void NeonGenTwoOpFn(TCGv_i32
, TCGv_i32
, TCGv_i32
);
72 typedef void NeonGenTwoOpEnvFn(TCGv_i32
, TCGv_ptr
, TCGv_i32
, TCGv_i32
);
73 typedef void NeonGenTwo64OpFn(TCGv_i64
, TCGv_i64
, TCGv_i64
);
74 typedef void NeonGenTwo64OpEnvFn(TCGv_i64
, TCGv_ptr
, TCGv_i64
, TCGv_i64
);
75 typedef void NeonGenNarrowFn(TCGv_i32
, TCGv_i64
);
76 typedef void NeonGenNarrowEnvFn(TCGv_i32
, TCGv_ptr
, TCGv_i64
);
77 typedef void NeonGenWidenFn(TCGv_i64
, TCGv_i32
);
78 typedef void NeonGenTwoSingleOPFn(TCGv_i32
, TCGv_i32
, TCGv_i32
, TCGv_ptr
);
79 typedef void NeonGenTwoDoubleOPFn(TCGv_i64
, TCGv_i64
, TCGv_i64
, TCGv_ptr
);
80 typedef void NeonGenOneOpFn(TCGv_i64
, TCGv_i64
);
81 typedef void CryptoTwoOpEnvFn(TCGv_ptr
, TCGv_i32
, TCGv_i32
);
82 typedef void CryptoThreeOpEnvFn(TCGv_ptr
, TCGv_i32
, TCGv_i32
, TCGv_i32
);
84 /* initialize TCG globals. */
85 void a64_translate_init(void)
89 cpu_pc
= tcg_global_mem_new_i64(cpu_env
,
90 offsetof(CPUARMState
, pc
),
92 for (i
= 0; i
< 32; i
++) {
93 cpu_X
[i
] = tcg_global_mem_new_i64(cpu_env
,
94 offsetof(CPUARMState
, xregs
[i
]),
98 cpu_exclusive_high
= tcg_global_mem_new_i64(cpu_env
,
99 offsetof(CPUARMState
, exclusive_high
), "exclusive_high");
102 static inline ARMMMUIdx
get_a64_user_mem_index(DisasContext
*s
)
104 /* Return the mmu_idx to use for A64 "unprivileged load/store" insns:
105 * if EL1, access as if EL0; otherwise access at current EL
107 switch (s
->mmu_idx
) {
108 case ARMMMUIdx_S12NSE1
:
109 return ARMMMUIdx_S12NSE0
;
110 case ARMMMUIdx_S1SE1
:
111 return ARMMMUIdx_S1SE0
;
113 g_assert_not_reached();
119 void aarch64_cpu_dump_state(CPUState
*cs
, FILE *f
,
120 fprintf_function cpu_fprintf
, int flags
)
122 ARMCPU
*cpu
= ARM_CPU(cs
);
123 CPUARMState
*env
= &cpu
->env
;
124 uint32_t psr
= pstate_read(env
);
126 int el
= arm_current_el(env
);
127 const char *ns_status
;
129 cpu_fprintf(f
, "PC=%016"PRIx64
" SP=%016"PRIx64
"\n",
130 env
->pc
, env
->xregs
[31]);
131 for (i
= 0; i
< 31; i
++) {
132 cpu_fprintf(f
, "X%02d=%016"PRIx64
, i
, env
->xregs
[i
]);
134 cpu_fprintf(f
, "\n");
140 if (arm_feature(env
, ARM_FEATURE_EL3
) && el
!= 3) {
141 ns_status
= env
->cp15
.scr_el3
& SCR_NS
? "NS " : "S ";
146 cpu_fprintf(f
, "\nPSTATE=%08x %c%c%c%c %sEL%d%c\n",
148 psr
& PSTATE_N
? 'N' : '-',
149 psr
& PSTATE_Z
? 'Z' : '-',
150 psr
& PSTATE_C
? 'C' : '-',
151 psr
& PSTATE_V
? 'V' : '-',
154 psr
& PSTATE_SP
? 'h' : 't');
156 if (flags
& CPU_DUMP_FPU
) {
158 for (i
= 0; i
< numvfpregs
; i
+= 2) {
159 uint64_t vlo
= float64_val(env
->vfp
.regs
[i
* 2]);
160 uint64_t vhi
= float64_val(env
->vfp
.regs
[(i
* 2) + 1]);
161 cpu_fprintf(f
, "q%02d=%016" PRIx64
":%016" PRIx64
" ",
163 vlo
= float64_val(env
->vfp
.regs
[(i
+ 1) * 2]);
164 vhi
= float64_val(env
->vfp
.regs
[((i
+ 1) * 2) + 1]);
165 cpu_fprintf(f
, "q%02d=%016" PRIx64
":%016" PRIx64
"\n",
168 cpu_fprintf(f
, "FPCR: %08x FPSR: %08x\n",
169 vfp_get_fpcr(env
), vfp_get_fpsr(env
));
173 void gen_a64_set_pc_im(uint64_t val
)
175 tcg_gen_movi_i64(cpu_pc
, val
);
178 typedef struct DisasCompare64
{
183 static void a64_test_cc(DisasCompare64
*c64
, int cc
)
187 arm_test_cc(&c32
, cc
);
189 /* Sign-extend the 32-bit value so that the GE/LT comparisons work
190 * properly. The NE/EQ comparisons are also fine with this choice. */
191 c64
->cond
= c32
.cond
;
192 c64
->value
= tcg_temp_new_i64();
193 tcg_gen_ext_i32_i64(c64
->value
, c32
.value
);
198 static void a64_free_cc(DisasCompare64
*c64
)
200 tcg_temp_free_i64(c64
->value
);
203 static void gen_exception_internal(int excp
)
205 TCGv_i32 tcg_excp
= tcg_const_i32(excp
);
207 assert(excp_is_internal(excp
));
208 gen_helper_exception_internal(cpu_env
, tcg_excp
);
209 tcg_temp_free_i32(tcg_excp
);
212 static void gen_exception(int excp
, uint32_t syndrome
, uint32_t target_el
)
214 TCGv_i32 tcg_excp
= tcg_const_i32(excp
);
215 TCGv_i32 tcg_syn
= tcg_const_i32(syndrome
);
216 TCGv_i32 tcg_el
= tcg_const_i32(target_el
);
218 gen_helper_exception_with_syndrome(cpu_env
, tcg_excp
,
220 tcg_temp_free_i32(tcg_el
);
221 tcg_temp_free_i32(tcg_syn
);
222 tcg_temp_free_i32(tcg_excp
);
225 static void gen_exception_internal_insn(DisasContext
*s
, int offset
, int excp
)
227 gen_a64_set_pc_im(s
->pc
- offset
);
228 gen_exception_internal(excp
);
229 s
->is_jmp
= DISAS_EXC
;
232 static void gen_exception_insn(DisasContext
*s
, int offset
, int excp
,
233 uint32_t syndrome
, uint32_t target_el
)
235 gen_a64_set_pc_im(s
->pc
- offset
);
236 gen_exception(excp
, syndrome
, target_el
);
237 s
->is_jmp
= DISAS_EXC
;
240 static void gen_ss_advance(DisasContext
*s
)
242 /* If the singlestep state is Active-not-pending, advance to
247 gen_helper_clear_pstate_ss(cpu_env
);
251 static void gen_step_complete_exception(DisasContext
*s
)
253 /* We just completed step of an insn. Move from Active-not-pending
254 * to Active-pending, and then also take the swstep exception.
255 * This corresponds to making the (IMPDEF) choice to prioritize
256 * swstep exceptions over asynchronous exceptions taken to an exception
257 * level where debug is disabled. This choice has the advantage that
258 * we do not need to maintain internal state corresponding to the
259 * ISV/EX syndrome bits between completion of the step and generation
260 * of the exception, and our syndrome information is always correct.
263 gen_exception(EXCP_UDEF
, syn_swstep(s
->ss_same_el
, 1, s
->is_ldex
),
264 default_exception_el(s
));
265 s
->is_jmp
= DISAS_EXC
;
268 static inline bool use_goto_tb(DisasContext
*s
, int n
, uint64_t dest
)
270 /* No direct tb linking with singlestep (either QEMU's or the ARM
271 * debug architecture kind) or deterministic io
273 if (s
->singlestep_enabled
|| s
->ss_active
|| (s
->tb
->cflags
& CF_LAST_IO
)) {
277 /* Only link tbs from inside the same guest page */
278 if ((s
->tb
->pc
& TARGET_PAGE_MASK
) != (dest
& TARGET_PAGE_MASK
)) {
285 static inline void gen_goto_tb(DisasContext
*s
, int n
, uint64_t dest
)
287 TranslationBlock
*tb
;
290 if (use_goto_tb(s
, n
, dest
)) {
292 gen_a64_set_pc_im(dest
);
293 tcg_gen_exit_tb((intptr_t)tb
+ n
);
294 s
->is_jmp
= DISAS_TB_JUMP
;
296 gen_a64_set_pc_im(dest
);
298 gen_step_complete_exception(s
);
299 } else if (s
->singlestep_enabled
) {
300 gen_exception_internal(EXCP_DEBUG
);
303 s
->is_jmp
= DISAS_TB_JUMP
;
308 static void unallocated_encoding(DisasContext
*s
)
310 /* Unallocated and reserved encodings are uncategorized */
311 gen_exception_insn(s
, 4, EXCP_UDEF
, syn_uncategorized(),
312 default_exception_el(s
));
315 #define unsupported_encoding(s, insn) \
317 qemu_log_mask(LOG_UNIMP, \
318 "%s:%d: unsupported instruction encoding 0x%08x " \
319 "at pc=%016" PRIx64 "\n", \
320 __FILE__, __LINE__, insn, s->pc - 4); \
321 unallocated_encoding(s); \
324 static void init_tmp_a64_array(DisasContext
*s
)
326 #ifdef CONFIG_DEBUG_TCG
328 for (i
= 0; i
< ARRAY_SIZE(s
->tmp_a64
); i
++) {
329 TCGV_UNUSED_I64(s
->tmp_a64
[i
]);
332 s
->tmp_a64_count
= 0;
335 static void free_tmp_a64(DisasContext
*s
)
338 for (i
= 0; i
< s
->tmp_a64_count
; i
++) {
339 tcg_temp_free_i64(s
->tmp_a64
[i
]);
341 init_tmp_a64_array(s
);
344 static TCGv_i64
new_tmp_a64(DisasContext
*s
)
346 assert(s
->tmp_a64_count
< TMP_A64_MAX
);
347 return s
->tmp_a64
[s
->tmp_a64_count
++] = tcg_temp_new_i64();
350 static TCGv_i64
new_tmp_a64_zero(DisasContext
*s
)
352 TCGv_i64 t
= new_tmp_a64(s
);
353 tcg_gen_movi_i64(t
, 0);
358 * Register access functions
360 * These functions are used for directly accessing a register in where
361 * changes to the final register value are likely to be made. If you
362 * need to use a register for temporary calculation (e.g. index type
363 * operations) use the read_* form.
365 * B1.2.1 Register mappings
367 * In instruction register encoding 31 can refer to ZR (zero register) or
368 * the SP (stack pointer) depending on context. In QEMU's case we map SP
369 * to cpu_X[31] and ZR accesses to a temporary which can be discarded.
370 * This is the point of the _sp forms.
372 static TCGv_i64
cpu_reg(DisasContext
*s
, int reg
)
375 return new_tmp_a64_zero(s
);
381 /* register access for when 31 == SP */
382 static TCGv_i64
cpu_reg_sp(DisasContext
*s
, int reg
)
387 /* read a cpu register in 32bit/64bit mode. Returns a TCGv_i64
388 * representing the register contents. This TCGv is an auto-freed
389 * temporary so it need not be explicitly freed, and may be modified.
391 static TCGv_i64
read_cpu_reg(DisasContext
*s
, int reg
, int sf
)
393 TCGv_i64 v
= new_tmp_a64(s
);
396 tcg_gen_mov_i64(v
, cpu_X
[reg
]);
398 tcg_gen_ext32u_i64(v
, cpu_X
[reg
]);
401 tcg_gen_movi_i64(v
, 0);
406 static TCGv_i64
read_cpu_reg_sp(DisasContext
*s
, int reg
, int sf
)
408 TCGv_i64 v
= new_tmp_a64(s
);
410 tcg_gen_mov_i64(v
, cpu_X
[reg
]);
412 tcg_gen_ext32u_i64(v
, cpu_X
[reg
]);
417 /* We should have at some point before trying to access an FP register
418 * done the necessary access check, so assert that
419 * (a) we did the check and
420 * (b) we didn't then just plough ahead anyway if it failed.
421 * Print the instruction pattern in the abort message so we can figure
422 * out what we need to fix if a user encounters this problem in the wild.
424 static inline void assert_fp_access_checked(DisasContext
*s
)
426 #ifdef CONFIG_DEBUG_TCG
427 if (unlikely(!s
->fp_access_checked
|| s
->fp_excp_el
)) {
428 fprintf(stderr
, "target-arm: FP access check missing for "
429 "instruction 0x%08x\n", s
->insn
);
435 /* Return the offset into CPUARMState of an element of specified
436 * size, 'element' places in from the least significant end of
437 * the FP/vector register Qn.
439 static inline int vec_reg_offset(DisasContext
*s
, int regno
,
440 int element
, TCGMemOp size
)
442 int offs
= offsetof(CPUARMState
, vfp
.regs
[regno
* 2]);
443 #ifdef HOST_WORDS_BIGENDIAN
444 /* This is complicated slightly because vfp.regs[2n] is
445 * still the low half and vfp.regs[2n+1] the high half
446 * of the 128 bit vector, even on big endian systems.
447 * Calculate the offset assuming a fully bigendian 128 bits,
448 * then XOR to account for the order of the two 64 bit halves.
450 offs
+= (16 - ((element
+ 1) * (1 << size
)));
453 offs
+= element
* (1 << size
);
455 assert_fp_access_checked(s
);
459 /* Return the offset into CPUARMState of a slice (from
460 * the least significant end) of FP register Qn (ie
462 * (Note that this is not the same mapping as for A32; see cpu.h)
464 static inline int fp_reg_offset(DisasContext
*s
, int regno
, TCGMemOp size
)
466 int offs
= offsetof(CPUARMState
, vfp
.regs
[regno
* 2]);
467 #ifdef HOST_WORDS_BIGENDIAN
468 offs
+= (8 - (1 << size
));
470 assert_fp_access_checked(s
);
474 /* Offset of the high half of the 128 bit vector Qn */
475 static inline int fp_reg_hi_offset(DisasContext
*s
, int regno
)
477 assert_fp_access_checked(s
);
478 return offsetof(CPUARMState
, vfp
.regs
[regno
* 2 + 1]);
481 /* Convenience accessors for reading and writing single and double
482 * FP registers. Writing clears the upper parts of the associated
483 * 128 bit vector register, as required by the architecture.
484 * Note that unlike the GP register accessors, the values returned
485 * by the read functions must be manually freed.
487 static TCGv_i64
read_fp_dreg(DisasContext
*s
, int reg
)
489 TCGv_i64 v
= tcg_temp_new_i64();
491 tcg_gen_ld_i64(v
, cpu_env
, fp_reg_offset(s
, reg
, MO_64
));
495 static TCGv_i32
read_fp_sreg(DisasContext
*s
, int reg
)
497 TCGv_i32 v
= tcg_temp_new_i32();
499 tcg_gen_ld_i32(v
, cpu_env
, fp_reg_offset(s
, reg
, MO_32
));
503 static void write_fp_dreg(DisasContext
*s
, int reg
, TCGv_i64 v
)
505 TCGv_i64 tcg_zero
= tcg_const_i64(0);
507 tcg_gen_st_i64(v
, cpu_env
, fp_reg_offset(s
, reg
, MO_64
));
508 tcg_gen_st_i64(tcg_zero
, cpu_env
, fp_reg_hi_offset(s
, reg
));
509 tcg_temp_free_i64(tcg_zero
);
512 static void write_fp_sreg(DisasContext
*s
, int reg
, TCGv_i32 v
)
514 TCGv_i64 tmp
= tcg_temp_new_i64();
516 tcg_gen_extu_i32_i64(tmp
, v
);
517 write_fp_dreg(s
, reg
, tmp
);
518 tcg_temp_free_i64(tmp
);
521 static TCGv_ptr
get_fpstatus_ptr(void)
523 TCGv_ptr statusptr
= tcg_temp_new_ptr();
526 /* In A64 all instructions (both FP and Neon) use the FPCR;
527 * there is no equivalent of the A32 Neon "standard FPSCR value"
528 * and all operations use vfp.fp_status.
530 offset
= offsetof(CPUARMState
, vfp
.fp_status
);
531 tcg_gen_addi_ptr(statusptr
, cpu_env
, offset
);
535 /* Set ZF and NF based on a 64 bit result. This is alas fiddlier
536 * than the 32 bit equivalent.
538 static inline void gen_set_NZ64(TCGv_i64 result
)
540 tcg_gen_extr_i64_i32(cpu_ZF
, cpu_NF
, result
);
541 tcg_gen_or_i32(cpu_ZF
, cpu_ZF
, cpu_NF
);
544 /* Set NZCV as for a logical operation: NZ as per result, CV cleared. */
545 static inline void gen_logic_CC(int sf
, TCGv_i64 result
)
548 gen_set_NZ64(result
);
550 tcg_gen_extrl_i64_i32(cpu_ZF
, result
);
551 tcg_gen_mov_i32(cpu_NF
, cpu_ZF
);
553 tcg_gen_movi_i32(cpu_CF
, 0);
554 tcg_gen_movi_i32(cpu_VF
, 0);
557 /* dest = T0 + T1; compute C, N, V and Z flags */
558 static void gen_add_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
561 TCGv_i64 result
, flag
, tmp
;
562 result
= tcg_temp_new_i64();
563 flag
= tcg_temp_new_i64();
564 tmp
= tcg_temp_new_i64();
566 tcg_gen_movi_i64(tmp
, 0);
567 tcg_gen_add2_i64(result
, flag
, t0
, tmp
, t1
, tmp
);
569 tcg_gen_extrl_i64_i32(cpu_CF
, flag
);
571 gen_set_NZ64(result
);
573 tcg_gen_xor_i64(flag
, result
, t0
);
574 tcg_gen_xor_i64(tmp
, t0
, t1
);
575 tcg_gen_andc_i64(flag
, flag
, tmp
);
576 tcg_temp_free_i64(tmp
);
577 tcg_gen_extrh_i64_i32(cpu_VF
, flag
);
579 tcg_gen_mov_i64(dest
, result
);
580 tcg_temp_free_i64(result
);
581 tcg_temp_free_i64(flag
);
583 /* 32 bit arithmetic */
584 TCGv_i32 t0_32
= tcg_temp_new_i32();
585 TCGv_i32 t1_32
= tcg_temp_new_i32();
586 TCGv_i32 tmp
= tcg_temp_new_i32();
588 tcg_gen_movi_i32(tmp
, 0);
589 tcg_gen_extrl_i64_i32(t0_32
, t0
);
590 tcg_gen_extrl_i64_i32(t1_32
, t1
);
591 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, t0_32
, tmp
, t1_32
, tmp
);
592 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
593 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
594 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
595 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tmp
);
596 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
598 tcg_temp_free_i32(tmp
);
599 tcg_temp_free_i32(t0_32
);
600 tcg_temp_free_i32(t1_32
);
604 /* dest = T0 - T1; compute C, N, V and Z flags */
605 static void gen_sub_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
608 /* 64 bit arithmetic */
609 TCGv_i64 result
, flag
, tmp
;
611 result
= tcg_temp_new_i64();
612 flag
= tcg_temp_new_i64();
613 tcg_gen_sub_i64(result
, t0
, t1
);
615 gen_set_NZ64(result
);
617 tcg_gen_setcond_i64(TCG_COND_GEU
, flag
, t0
, t1
);
618 tcg_gen_extrl_i64_i32(cpu_CF
, flag
);
620 tcg_gen_xor_i64(flag
, result
, t0
);
621 tmp
= tcg_temp_new_i64();
622 tcg_gen_xor_i64(tmp
, t0
, t1
);
623 tcg_gen_and_i64(flag
, flag
, tmp
);
624 tcg_temp_free_i64(tmp
);
625 tcg_gen_extrh_i64_i32(cpu_VF
, flag
);
626 tcg_gen_mov_i64(dest
, result
);
627 tcg_temp_free_i64(flag
);
628 tcg_temp_free_i64(result
);
630 /* 32 bit arithmetic */
631 TCGv_i32 t0_32
= tcg_temp_new_i32();
632 TCGv_i32 t1_32
= tcg_temp_new_i32();
635 tcg_gen_extrl_i64_i32(t0_32
, t0
);
636 tcg_gen_extrl_i64_i32(t1_32
, t1
);
637 tcg_gen_sub_i32(cpu_NF
, t0_32
, t1_32
);
638 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
639 tcg_gen_setcond_i32(TCG_COND_GEU
, cpu_CF
, t0_32
, t1_32
);
640 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
641 tmp
= tcg_temp_new_i32();
642 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
643 tcg_temp_free_i32(t0_32
);
644 tcg_temp_free_i32(t1_32
);
645 tcg_gen_and_i32(cpu_VF
, cpu_VF
, tmp
);
646 tcg_temp_free_i32(tmp
);
647 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
651 /* dest = T0 + T1 + CF; do not compute flags. */
652 static void gen_adc(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
654 TCGv_i64 flag
= tcg_temp_new_i64();
655 tcg_gen_extu_i32_i64(flag
, cpu_CF
);
656 tcg_gen_add_i64(dest
, t0
, t1
);
657 tcg_gen_add_i64(dest
, dest
, flag
);
658 tcg_temp_free_i64(flag
);
661 tcg_gen_ext32u_i64(dest
, dest
);
665 /* dest = T0 + T1 + CF; compute C, N, V and Z flags. */
666 static void gen_adc_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
669 TCGv_i64 result
, cf_64
, vf_64
, tmp
;
670 result
= tcg_temp_new_i64();
671 cf_64
= tcg_temp_new_i64();
672 vf_64
= tcg_temp_new_i64();
673 tmp
= tcg_const_i64(0);
675 tcg_gen_extu_i32_i64(cf_64
, cpu_CF
);
676 tcg_gen_add2_i64(result
, cf_64
, t0
, tmp
, cf_64
, tmp
);
677 tcg_gen_add2_i64(result
, cf_64
, result
, cf_64
, t1
, tmp
);
678 tcg_gen_extrl_i64_i32(cpu_CF
, cf_64
);
679 gen_set_NZ64(result
);
681 tcg_gen_xor_i64(vf_64
, result
, t0
);
682 tcg_gen_xor_i64(tmp
, t0
, t1
);
683 tcg_gen_andc_i64(vf_64
, vf_64
, tmp
);
684 tcg_gen_extrh_i64_i32(cpu_VF
, vf_64
);
686 tcg_gen_mov_i64(dest
, result
);
688 tcg_temp_free_i64(tmp
);
689 tcg_temp_free_i64(vf_64
);
690 tcg_temp_free_i64(cf_64
);
691 tcg_temp_free_i64(result
);
693 TCGv_i32 t0_32
, t1_32
, tmp
;
694 t0_32
= tcg_temp_new_i32();
695 t1_32
= tcg_temp_new_i32();
696 tmp
= tcg_const_i32(0);
698 tcg_gen_extrl_i64_i32(t0_32
, t0
);
699 tcg_gen_extrl_i64_i32(t1_32
, t1
);
700 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, t0_32
, tmp
, cpu_CF
, tmp
);
701 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, cpu_NF
, cpu_CF
, t1_32
, tmp
);
703 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
704 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
705 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
706 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tmp
);
707 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
709 tcg_temp_free_i32(tmp
);
710 tcg_temp_free_i32(t1_32
);
711 tcg_temp_free_i32(t0_32
);
716 * Load/Store generators
720 * Store from GPR register to memory.
722 static void do_gpr_st_memidx(DisasContext
*s
, TCGv_i64 source
,
723 TCGv_i64 tcg_addr
, int size
, int memidx
)
726 tcg_gen_qemu_st_i64(source
, tcg_addr
, memidx
, MO_TE
+ size
);
729 static void do_gpr_st(DisasContext
*s
, TCGv_i64 source
,
730 TCGv_i64 tcg_addr
, int size
)
732 do_gpr_st_memidx(s
, source
, tcg_addr
, size
, get_mem_index(s
));
736 * Load from memory to GPR register
738 static void do_gpr_ld_memidx(DisasContext
*s
, TCGv_i64 dest
, TCGv_i64 tcg_addr
,
739 int size
, bool is_signed
, bool extend
, int memidx
)
741 TCGMemOp memop
= MO_TE
+ size
;
749 tcg_gen_qemu_ld_i64(dest
, tcg_addr
, memidx
, memop
);
751 if (extend
&& is_signed
) {
753 tcg_gen_ext32u_i64(dest
, dest
);
757 static void do_gpr_ld(DisasContext
*s
, TCGv_i64 dest
, TCGv_i64 tcg_addr
,
758 int size
, bool is_signed
, bool extend
)
760 do_gpr_ld_memidx(s
, dest
, tcg_addr
, size
, is_signed
, extend
,
765 * Store from FP register to memory
767 static void do_fp_st(DisasContext
*s
, int srcidx
, TCGv_i64 tcg_addr
, int size
)
769 /* This writes the bottom N bits of a 128 bit wide vector to memory */
770 TCGv_i64 tmp
= tcg_temp_new_i64();
771 tcg_gen_ld_i64(tmp
, cpu_env
, fp_reg_offset(s
, srcidx
, MO_64
));
773 tcg_gen_qemu_st_i64(tmp
, tcg_addr
, get_mem_index(s
), MO_TE
+ size
);
775 TCGv_i64 tcg_hiaddr
= tcg_temp_new_i64();
776 tcg_gen_qemu_st_i64(tmp
, tcg_addr
, get_mem_index(s
), MO_TEQ
);
777 tcg_gen_ld_i64(tmp
, cpu_env
, fp_reg_hi_offset(s
, srcidx
));
778 tcg_gen_addi_i64(tcg_hiaddr
, tcg_addr
, 8);
779 tcg_gen_qemu_st_i64(tmp
, tcg_hiaddr
, get_mem_index(s
), MO_TEQ
);
780 tcg_temp_free_i64(tcg_hiaddr
);
783 tcg_temp_free_i64(tmp
);
787 * Load from memory to FP register
789 static void do_fp_ld(DisasContext
*s
, int destidx
, TCGv_i64 tcg_addr
, int size
)
791 /* This always zero-extends and writes to a full 128 bit wide vector */
792 TCGv_i64 tmplo
= tcg_temp_new_i64();
796 TCGMemOp memop
= MO_TE
+ size
;
797 tmphi
= tcg_const_i64(0);
798 tcg_gen_qemu_ld_i64(tmplo
, tcg_addr
, get_mem_index(s
), memop
);
801 tmphi
= tcg_temp_new_i64();
802 tcg_hiaddr
= tcg_temp_new_i64();
804 tcg_gen_qemu_ld_i64(tmplo
, tcg_addr
, get_mem_index(s
), MO_TEQ
);
805 tcg_gen_addi_i64(tcg_hiaddr
, tcg_addr
, 8);
806 tcg_gen_qemu_ld_i64(tmphi
, tcg_hiaddr
, get_mem_index(s
), MO_TEQ
);
807 tcg_temp_free_i64(tcg_hiaddr
);
810 tcg_gen_st_i64(tmplo
, cpu_env
, fp_reg_offset(s
, destidx
, MO_64
));
811 tcg_gen_st_i64(tmphi
, cpu_env
, fp_reg_hi_offset(s
, destidx
));
813 tcg_temp_free_i64(tmplo
);
814 tcg_temp_free_i64(tmphi
);
818 * Vector load/store helpers.
820 * The principal difference between this and a FP load is that we don't
821 * zero extend as we are filling a partial chunk of the vector register.
822 * These functions don't support 128 bit loads/stores, which would be
823 * normal load/store operations.
825 * The _i32 versions are useful when operating on 32 bit quantities
826 * (eg for floating point single or using Neon helper functions).
829 /* Get value of an element within a vector register */
830 static void read_vec_element(DisasContext
*s
, TCGv_i64 tcg_dest
, int srcidx
,
831 int element
, TCGMemOp memop
)
833 int vect_off
= vec_reg_offset(s
, srcidx
, element
, memop
& MO_SIZE
);
836 tcg_gen_ld8u_i64(tcg_dest
, cpu_env
, vect_off
);
839 tcg_gen_ld16u_i64(tcg_dest
, cpu_env
, vect_off
);
842 tcg_gen_ld32u_i64(tcg_dest
, cpu_env
, vect_off
);
845 tcg_gen_ld8s_i64(tcg_dest
, cpu_env
, vect_off
);
848 tcg_gen_ld16s_i64(tcg_dest
, cpu_env
, vect_off
);
851 tcg_gen_ld32s_i64(tcg_dest
, cpu_env
, vect_off
);
855 tcg_gen_ld_i64(tcg_dest
, cpu_env
, vect_off
);
858 g_assert_not_reached();
862 static void read_vec_element_i32(DisasContext
*s
, TCGv_i32 tcg_dest
, int srcidx
,
863 int element
, TCGMemOp memop
)
865 int vect_off
= vec_reg_offset(s
, srcidx
, element
, memop
& MO_SIZE
);
868 tcg_gen_ld8u_i32(tcg_dest
, cpu_env
, vect_off
);
871 tcg_gen_ld16u_i32(tcg_dest
, cpu_env
, vect_off
);
874 tcg_gen_ld8s_i32(tcg_dest
, cpu_env
, vect_off
);
877 tcg_gen_ld16s_i32(tcg_dest
, cpu_env
, vect_off
);
881 tcg_gen_ld_i32(tcg_dest
, cpu_env
, vect_off
);
884 g_assert_not_reached();
888 /* Set value of an element within a vector register */
889 static void write_vec_element(DisasContext
*s
, TCGv_i64 tcg_src
, int destidx
,
890 int element
, TCGMemOp memop
)
892 int vect_off
= vec_reg_offset(s
, destidx
, element
, memop
& MO_SIZE
);
895 tcg_gen_st8_i64(tcg_src
, cpu_env
, vect_off
);
898 tcg_gen_st16_i64(tcg_src
, cpu_env
, vect_off
);
901 tcg_gen_st32_i64(tcg_src
, cpu_env
, vect_off
);
904 tcg_gen_st_i64(tcg_src
, cpu_env
, vect_off
);
907 g_assert_not_reached();
911 static void write_vec_element_i32(DisasContext
*s
, TCGv_i32 tcg_src
,
912 int destidx
, int element
, TCGMemOp memop
)
914 int vect_off
= vec_reg_offset(s
, destidx
, element
, memop
& MO_SIZE
);
917 tcg_gen_st8_i32(tcg_src
, cpu_env
, vect_off
);
920 tcg_gen_st16_i32(tcg_src
, cpu_env
, vect_off
);
923 tcg_gen_st_i32(tcg_src
, cpu_env
, vect_off
);
926 g_assert_not_reached();
930 /* Clear the high 64 bits of a 128 bit vector (in general non-quad
931 * vector ops all need to do this).
933 static void clear_vec_high(DisasContext
*s
, int rd
)
935 TCGv_i64 tcg_zero
= tcg_const_i64(0);
937 write_vec_element(s
, tcg_zero
, rd
, 1, MO_64
);
938 tcg_temp_free_i64(tcg_zero
);
941 /* Store from vector register to memory */
942 static void do_vec_st(DisasContext
*s
, int srcidx
, int element
,
943 TCGv_i64 tcg_addr
, int size
)
945 TCGMemOp memop
= MO_TE
+ size
;
946 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
948 read_vec_element(s
, tcg_tmp
, srcidx
, element
, size
);
949 tcg_gen_qemu_st_i64(tcg_tmp
, tcg_addr
, get_mem_index(s
), memop
);
951 tcg_temp_free_i64(tcg_tmp
);
954 /* Load from memory to vector register */
955 static void do_vec_ld(DisasContext
*s
, int destidx
, int element
,
956 TCGv_i64 tcg_addr
, int size
)
958 TCGMemOp memop
= MO_TE
+ size
;
959 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
961 tcg_gen_qemu_ld_i64(tcg_tmp
, tcg_addr
, get_mem_index(s
), memop
);
962 write_vec_element(s
, tcg_tmp
, destidx
, element
, size
);
964 tcg_temp_free_i64(tcg_tmp
);
967 /* Check that FP/Neon access is enabled. If it is, return
968 * true. If not, emit code to generate an appropriate exception,
969 * and return false; the caller should not emit any code for
970 * the instruction. Note that this check must happen after all
971 * unallocated-encoding checks (otherwise the syndrome information
972 * for the resulting exception will be incorrect).
974 static inline bool fp_access_check(DisasContext
*s
)
976 assert(!s
->fp_access_checked
);
977 s
->fp_access_checked
= true;
979 if (!s
->fp_excp_el
) {
983 gen_exception_insn(s
, 4, EXCP_UDEF
, syn_fp_access_trap(1, 0xe, false),
989 * This utility function is for doing register extension with an
990 * optional shift. You will likely want to pass a temporary for the
991 * destination register. See DecodeRegExtend() in the ARM ARM.
993 static void ext_and_shift_reg(TCGv_i64 tcg_out
, TCGv_i64 tcg_in
,
994 int option
, unsigned int shift
)
996 int extsize
= extract32(option
, 0, 2);
997 bool is_signed
= extract32(option
, 2, 1);
1002 tcg_gen_ext8s_i64(tcg_out
, tcg_in
);
1005 tcg_gen_ext16s_i64(tcg_out
, tcg_in
);
1008 tcg_gen_ext32s_i64(tcg_out
, tcg_in
);
1011 tcg_gen_mov_i64(tcg_out
, tcg_in
);
1017 tcg_gen_ext8u_i64(tcg_out
, tcg_in
);
1020 tcg_gen_ext16u_i64(tcg_out
, tcg_in
);
1023 tcg_gen_ext32u_i64(tcg_out
, tcg_in
);
1026 tcg_gen_mov_i64(tcg_out
, tcg_in
);
1032 tcg_gen_shli_i64(tcg_out
, tcg_out
, shift
);
1036 static inline void gen_check_sp_alignment(DisasContext
*s
)
1038 /* The AArch64 architecture mandates that (if enabled via PSTATE
1039 * or SCTLR bits) there is a check that SP is 16-aligned on every
1040 * SP-relative load or store (with an exception generated if it is not).
1041 * In line with general QEMU practice regarding misaligned accesses,
1042 * we omit these checks for the sake of guest program performance.
1043 * This function is provided as a hook so we can more easily add these
1044 * checks in future (possibly as a "favour catching guest program bugs
1045 * over speed" user selectable option).
1050 * This provides a simple table based table lookup decoder. It is
1051 * intended to be used when the relevant bits for decode are too
1052 * awkwardly placed and switch/if based logic would be confusing and
1053 * deeply nested. Since it's a linear search through the table, tables
1054 * should be kept small.
1056 * It returns the first handler where insn & mask == pattern, or
1057 * NULL if there is no match.
1058 * The table is terminated by an empty mask (i.e. 0)
1060 static inline AArch64DecodeFn
*lookup_disas_fn(const AArch64DecodeTable
*table
,
1063 const AArch64DecodeTable
*tptr
= table
;
1065 while (tptr
->mask
) {
1066 if ((insn
& tptr
->mask
) == tptr
->pattern
) {
1067 return tptr
->disas_fn
;
1075 * the instruction disassembly implemented here matches
1076 * the instruction encoding classifications in chapter 3 (C3)
1077 * of the ARM Architecture Reference Manual (DDI0487A_a)
1080 /* C3.2.7 Unconditional branch (immediate)
1082 * +----+-----------+-------------------------------------+
1083 * | op | 0 0 1 0 1 | imm26 |
1084 * +----+-----------+-------------------------------------+
1086 static void disas_uncond_b_imm(DisasContext
*s
, uint32_t insn
)
1088 uint64_t addr
= s
->pc
+ sextract32(insn
, 0, 26) * 4 - 4;
1090 if (insn
& (1U << 31)) {
1091 /* C5.6.26 BL Branch with link */
1092 tcg_gen_movi_i64(cpu_reg(s
, 30), s
->pc
);
1095 /* C5.6.20 B Branch / C5.6.26 BL Branch with link */
1096 gen_goto_tb(s
, 0, addr
);
1099 /* C3.2.1 Compare & branch (immediate)
1100 * 31 30 25 24 23 5 4 0
1101 * +----+-------------+----+---------------------+--------+
1102 * | sf | 0 1 1 0 1 0 | op | imm19 | Rt |
1103 * +----+-------------+----+---------------------+--------+
1105 static void disas_comp_b_imm(DisasContext
*s
, uint32_t insn
)
1107 unsigned int sf
, op
, rt
;
1109 TCGLabel
*label_match
;
1112 sf
= extract32(insn
, 31, 1);
1113 op
= extract32(insn
, 24, 1); /* 0: CBZ; 1: CBNZ */
1114 rt
= extract32(insn
, 0, 5);
1115 addr
= s
->pc
+ sextract32(insn
, 5, 19) * 4 - 4;
1117 tcg_cmp
= read_cpu_reg(s
, rt
, sf
);
1118 label_match
= gen_new_label();
1120 tcg_gen_brcondi_i64(op
? TCG_COND_NE
: TCG_COND_EQ
,
1121 tcg_cmp
, 0, label_match
);
1123 gen_goto_tb(s
, 0, s
->pc
);
1124 gen_set_label(label_match
);
1125 gen_goto_tb(s
, 1, addr
);
1128 /* C3.2.5 Test & branch (immediate)
1129 * 31 30 25 24 23 19 18 5 4 0
1130 * +----+-------------+----+-------+-------------+------+
1131 * | b5 | 0 1 1 0 1 1 | op | b40 | imm14 | Rt |
1132 * +----+-------------+----+-------+-------------+------+
1134 static void disas_test_b_imm(DisasContext
*s
, uint32_t insn
)
1136 unsigned int bit_pos
, op
, rt
;
1138 TCGLabel
*label_match
;
1141 bit_pos
= (extract32(insn
, 31, 1) << 5) | extract32(insn
, 19, 5);
1142 op
= extract32(insn
, 24, 1); /* 0: TBZ; 1: TBNZ */
1143 addr
= s
->pc
+ sextract32(insn
, 5, 14) * 4 - 4;
1144 rt
= extract32(insn
, 0, 5);
1146 tcg_cmp
= tcg_temp_new_i64();
1147 tcg_gen_andi_i64(tcg_cmp
, cpu_reg(s
, rt
), (1ULL << bit_pos
));
1148 label_match
= gen_new_label();
1149 tcg_gen_brcondi_i64(op
? TCG_COND_NE
: TCG_COND_EQ
,
1150 tcg_cmp
, 0, label_match
);
1151 tcg_temp_free_i64(tcg_cmp
);
1152 gen_goto_tb(s
, 0, s
->pc
);
1153 gen_set_label(label_match
);
1154 gen_goto_tb(s
, 1, addr
);
1157 /* C3.2.2 / C5.6.19 Conditional branch (immediate)
1158 * 31 25 24 23 5 4 3 0
1159 * +---------------+----+---------------------+----+------+
1160 * | 0 1 0 1 0 1 0 | o1 | imm19 | o0 | cond |
1161 * +---------------+----+---------------------+----+------+
1163 static void disas_cond_b_imm(DisasContext
*s
, uint32_t insn
)
1168 if ((insn
& (1 << 4)) || (insn
& (1 << 24))) {
1169 unallocated_encoding(s
);
1172 addr
= s
->pc
+ sextract32(insn
, 5, 19) * 4 - 4;
1173 cond
= extract32(insn
, 0, 4);
1176 /* genuinely conditional branches */
1177 TCGLabel
*label_match
= gen_new_label();
1178 arm_gen_test_cc(cond
, label_match
);
1179 gen_goto_tb(s
, 0, s
->pc
);
1180 gen_set_label(label_match
);
1181 gen_goto_tb(s
, 1, addr
);
1183 /* 0xe and 0xf are both "always" conditions */
1184 gen_goto_tb(s
, 0, addr
);
1189 static void handle_hint(DisasContext
*s
, uint32_t insn
,
1190 unsigned int op1
, unsigned int op2
, unsigned int crm
)
1192 unsigned int selector
= crm
<< 3 | op2
;
1195 unallocated_encoding(s
);
1203 s
->is_jmp
= DISAS_WFI
;
1206 s
->is_jmp
= DISAS_YIELD
;
1209 s
->is_jmp
= DISAS_WFE
;
1213 /* we treat all as NOP at least for now */
1216 /* default specified as NOP equivalent */
1221 static void gen_clrex(DisasContext
*s
, uint32_t insn
)
1223 tcg_gen_movi_i64(cpu_exclusive_addr
, -1);
1226 /* CLREX, DSB, DMB, ISB */
1227 static void handle_sync(DisasContext
*s
, uint32_t insn
,
1228 unsigned int op1
, unsigned int op2
, unsigned int crm
)
1231 unallocated_encoding(s
);
1241 /* We don't emulate caches so barriers are no-ops */
1244 /* We need to break the TB after this insn to execute
1245 * a self-modified code correctly and also to take
1246 * any pending interrupts immediately.
1248 s
->is_jmp
= DISAS_UPDATE
;
1251 unallocated_encoding(s
);
1256 /* C5.6.130 MSR (immediate) - move immediate to processor state field */
1257 static void handle_msr_i(DisasContext
*s
, uint32_t insn
,
1258 unsigned int op1
, unsigned int op2
, unsigned int crm
)
1260 int op
= op1
<< 3 | op2
;
1262 case 0x05: /* SPSel */
1263 if (s
->current_el
== 0) {
1264 unallocated_encoding(s
);
1268 case 0x1e: /* DAIFSet */
1269 case 0x1f: /* DAIFClear */
1271 TCGv_i32 tcg_imm
= tcg_const_i32(crm
);
1272 TCGv_i32 tcg_op
= tcg_const_i32(op
);
1273 gen_a64_set_pc_im(s
->pc
- 4);
1274 gen_helper_msr_i_pstate(cpu_env
, tcg_op
, tcg_imm
);
1275 tcg_temp_free_i32(tcg_imm
);
1276 tcg_temp_free_i32(tcg_op
);
1277 s
->is_jmp
= DISAS_UPDATE
;
1281 unallocated_encoding(s
);
1286 static void gen_get_nzcv(TCGv_i64 tcg_rt
)
1288 TCGv_i32 tmp
= tcg_temp_new_i32();
1289 TCGv_i32 nzcv
= tcg_temp_new_i32();
1291 /* build bit 31, N */
1292 tcg_gen_andi_i32(nzcv
, cpu_NF
, (1U << 31));
1293 /* build bit 30, Z */
1294 tcg_gen_setcondi_i32(TCG_COND_EQ
, tmp
, cpu_ZF
, 0);
1295 tcg_gen_deposit_i32(nzcv
, nzcv
, tmp
, 30, 1);
1296 /* build bit 29, C */
1297 tcg_gen_deposit_i32(nzcv
, nzcv
, cpu_CF
, 29, 1);
1298 /* build bit 28, V */
1299 tcg_gen_shri_i32(tmp
, cpu_VF
, 31);
1300 tcg_gen_deposit_i32(nzcv
, nzcv
, tmp
, 28, 1);
1301 /* generate result */
1302 tcg_gen_extu_i32_i64(tcg_rt
, nzcv
);
1304 tcg_temp_free_i32(nzcv
);
1305 tcg_temp_free_i32(tmp
);
1308 static void gen_set_nzcv(TCGv_i64 tcg_rt
)
1311 TCGv_i32 nzcv
= tcg_temp_new_i32();
1313 /* take NZCV from R[t] */
1314 tcg_gen_extrl_i64_i32(nzcv
, tcg_rt
);
1317 tcg_gen_andi_i32(cpu_NF
, nzcv
, (1U << 31));
1319 tcg_gen_andi_i32(cpu_ZF
, nzcv
, (1 << 30));
1320 tcg_gen_setcondi_i32(TCG_COND_EQ
, cpu_ZF
, cpu_ZF
, 0);
1322 tcg_gen_andi_i32(cpu_CF
, nzcv
, (1 << 29));
1323 tcg_gen_shri_i32(cpu_CF
, cpu_CF
, 29);
1325 tcg_gen_andi_i32(cpu_VF
, nzcv
, (1 << 28));
1326 tcg_gen_shli_i32(cpu_VF
, cpu_VF
, 3);
1327 tcg_temp_free_i32(nzcv
);
1330 /* C5.6.129 MRS - move from system register
1331 * C5.6.131 MSR (register) - move to system register
1334 * These are all essentially the same insn in 'read' and 'write'
1335 * versions, with varying op0 fields.
1337 static void handle_sys(DisasContext
*s
, uint32_t insn
, bool isread
,
1338 unsigned int op0
, unsigned int op1
, unsigned int op2
,
1339 unsigned int crn
, unsigned int crm
, unsigned int rt
)
1341 const ARMCPRegInfo
*ri
;
1344 ri
= get_arm_cp_reginfo(s
->cp_regs
,
1345 ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP
,
1346 crn
, crm
, op0
, op1
, op2
));
1349 /* Unknown register; this might be a guest error or a QEMU
1350 * unimplemented feature.
1352 qemu_log_mask(LOG_UNIMP
, "%s access to unsupported AArch64 "
1353 "system register op0:%d op1:%d crn:%d crm:%d op2:%d\n",
1354 isread
? "read" : "write", op0
, op1
, crn
, crm
, op2
);
1355 unallocated_encoding(s
);
1359 /* Check access permissions */
1360 if (!cp_access_ok(s
->current_el
, ri
, isread
)) {
1361 unallocated_encoding(s
);
1366 /* Emit code to perform further access permissions checks at
1367 * runtime; this may result in an exception.
1370 TCGv_i32 tcg_syn
, tcg_isread
;
1373 gen_a64_set_pc_im(s
->pc
- 4);
1374 tmpptr
= tcg_const_ptr(ri
);
1375 syndrome
= syn_aa64_sysregtrap(op0
, op1
, op2
, crn
, crm
, rt
, isread
);
1376 tcg_syn
= tcg_const_i32(syndrome
);
1377 tcg_isread
= tcg_const_i32(isread
);
1378 gen_helper_access_check_cp_reg(cpu_env
, tmpptr
, tcg_syn
, tcg_isread
);
1379 tcg_temp_free_ptr(tmpptr
);
1380 tcg_temp_free_i32(tcg_syn
);
1381 tcg_temp_free_i32(tcg_isread
);
1384 /* Handle special cases first */
1385 switch (ri
->type
& ~(ARM_CP_FLAG_MASK
& ~ARM_CP_SPECIAL
)) {
1389 tcg_rt
= cpu_reg(s
, rt
);
1391 gen_get_nzcv(tcg_rt
);
1393 gen_set_nzcv(tcg_rt
);
1396 case ARM_CP_CURRENTEL
:
1397 /* Reads as current EL value from pstate, which is
1398 * guaranteed to be constant by the tb flags.
1400 tcg_rt
= cpu_reg(s
, rt
);
1401 tcg_gen_movi_i64(tcg_rt
, s
->current_el
<< 2);
1404 /* Writes clear the aligned block of memory which rt points into. */
1405 tcg_rt
= cpu_reg(s
, rt
);
1406 gen_helper_dc_zva(cpu_env
, tcg_rt
);
1412 if ((s
->tb
->cflags
& CF_USE_ICOUNT
) && (ri
->type
& ARM_CP_IO
)) {
1416 tcg_rt
= cpu_reg(s
, rt
);
1419 if (ri
->type
& ARM_CP_CONST
) {
1420 tcg_gen_movi_i64(tcg_rt
, ri
->resetvalue
);
1421 } else if (ri
->readfn
) {
1423 tmpptr
= tcg_const_ptr(ri
);
1424 gen_helper_get_cp_reg64(tcg_rt
, cpu_env
, tmpptr
);
1425 tcg_temp_free_ptr(tmpptr
);
1427 tcg_gen_ld_i64(tcg_rt
, cpu_env
, ri
->fieldoffset
);
1430 if (ri
->type
& ARM_CP_CONST
) {
1431 /* If not forbidden by access permissions, treat as WI */
1433 } else if (ri
->writefn
) {
1435 tmpptr
= tcg_const_ptr(ri
);
1436 gen_helper_set_cp_reg64(cpu_env
, tmpptr
, tcg_rt
);
1437 tcg_temp_free_ptr(tmpptr
);
1439 tcg_gen_st_i64(tcg_rt
, cpu_env
, ri
->fieldoffset
);
1443 if ((s
->tb
->cflags
& CF_USE_ICOUNT
) && (ri
->type
& ARM_CP_IO
)) {
1444 /* I/O operations must end the TB here (whether read or write) */
1446 s
->is_jmp
= DISAS_UPDATE
;
1447 } else if (!isread
&& !(ri
->type
& ARM_CP_SUPPRESS_TB_END
)) {
1448 /* We default to ending the TB on a coprocessor register write,
1449 * but allow this to be suppressed by the register definition
1450 * (usually only necessary to work around guest bugs).
1452 s
->is_jmp
= DISAS_UPDATE
;
1457 * 31 22 21 20 19 18 16 15 12 11 8 7 5 4 0
1458 * +---------------------+---+-----+-----+-------+-------+-----+------+
1459 * | 1 1 0 1 0 1 0 1 0 0 | L | op0 | op1 | CRn | CRm | op2 | Rt |
1460 * +---------------------+---+-----+-----+-------+-------+-----+------+
1462 static void disas_system(DisasContext
*s
, uint32_t insn
)
1464 unsigned int l
, op0
, op1
, crn
, crm
, op2
, rt
;
1465 l
= extract32(insn
, 21, 1);
1466 op0
= extract32(insn
, 19, 2);
1467 op1
= extract32(insn
, 16, 3);
1468 crn
= extract32(insn
, 12, 4);
1469 crm
= extract32(insn
, 8, 4);
1470 op2
= extract32(insn
, 5, 3);
1471 rt
= extract32(insn
, 0, 5);
1474 if (l
|| rt
!= 31) {
1475 unallocated_encoding(s
);
1479 case 2: /* C5.6.68 HINT */
1480 handle_hint(s
, insn
, op1
, op2
, crm
);
1482 case 3: /* CLREX, DSB, DMB, ISB */
1483 handle_sync(s
, insn
, op1
, op2
, crm
);
1485 case 4: /* C5.6.130 MSR (immediate) */
1486 handle_msr_i(s
, insn
, op1
, op2
, crm
);
1489 unallocated_encoding(s
);
1494 handle_sys(s
, insn
, l
, op0
, op1
, op2
, crn
, crm
, rt
);
1497 /* C3.2.3 Exception generation
1499 * 31 24 23 21 20 5 4 2 1 0
1500 * +-----------------+-----+------------------------+-----+----+
1501 * | 1 1 0 1 0 1 0 0 | opc | imm16 | op2 | LL |
1502 * +-----------------------+------------------------+----------+
1504 static void disas_exc(DisasContext
*s
, uint32_t insn
)
1506 int opc
= extract32(insn
, 21, 3);
1507 int op2_ll
= extract32(insn
, 0, 5);
1508 int imm16
= extract32(insn
, 5, 16);
1513 /* For SVC, HVC and SMC we advance the single-step state
1514 * machine before taking the exception. This is architecturally
1515 * mandated, to ensure that single-stepping a system call
1516 * instruction works properly.
1521 gen_exception_insn(s
, 0, EXCP_SWI
, syn_aa64_svc(imm16
),
1522 default_exception_el(s
));
1525 if (s
->current_el
== 0) {
1526 unallocated_encoding(s
);
1529 /* The pre HVC helper handles cases when HVC gets trapped
1530 * as an undefined insn by runtime configuration.
1532 gen_a64_set_pc_im(s
->pc
- 4);
1533 gen_helper_pre_hvc(cpu_env
);
1535 gen_exception_insn(s
, 0, EXCP_HVC
, syn_aa64_hvc(imm16
), 2);
1538 if (s
->current_el
== 0) {
1539 unallocated_encoding(s
);
1542 gen_a64_set_pc_im(s
->pc
- 4);
1543 tmp
= tcg_const_i32(syn_aa64_smc(imm16
));
1544 gen_helper_pre_smc(cpu_env
, tmp
);
1545 tcg_temp_free_i32(tmp
);
1547 gen_exception_insn(s
, 0, EXCP_SMC
, syn_aa64_smc(imm16
), 3);
1550 unallocated_encoding(s
);
1556 unallocated_encoding(s
);
1560 gen_exception_insn(s
, 4, EXCP_BKPT
, syn_aa64_bkpt(imm16
),
1561 default_exception_el(s
));
1565 unallocated_encoding(s
);
1568 /* HLT. This has two purposes.
1569 * Architecturally, it is an external halting debug instruction.
1570 * Since QEMU doesn't implement external debug, we treat this as
1571 * it is required for halting debug disabled: it will UNDEF.
1572 * Secondly, "HLT 0xf000" is the A64 semihosting syscall instruction.
1574 if (semihosting_enabled() && imm16
== 0xf000) {
1575 #ifndef CONFIG_USER_ONLY
1576 /* In system mode, don't allow userspace access to semihosting,
1577 * to provide some semblance of security (and for consistency
1578 * with our 32-bit semihosting).
1580 if (s
->current_el
== 0) {
1581 unsupported_encoding(s
, insn
);
1585 gen_exception_internal_insn(s
, 0, EXCP_SEMIHOST
);
1587 unsupported_encoding(s
, insn
);
1591 if (op2_ll
< 1 || op2_ll
> 3) {
1592 unallocated_encoding(s
);
1595 /* DCPS1, DCPS2, DCPS3 */
1596 unsupported_encoding(s
, insn
);
1599 unallocated_encoding(s
);
1604 /* C3.2.7 Unconditional branch (register)
1605 * 31 25 24 21 20 16 15 10 9 5 4 0
1606 * +---------------+-------+-------+-------+------+-------+
1607 * | 1 1 0 1 0 1 1 | opc | op2 | op3 | Rn | op4 |
1608 * +---------------+-------+-------+-------+------+-------+
1610 static void disas_uncond_b_reg(DisasContext
*s
, uint32_t insn
)
1612 unsigned int opc
, op2
, op3
, rn
, op4
;
1614 opc
= extract32(insn
, 21, 4);
1615 op2
= extract32(insn
, 16, 5);
1616 op3
= extract32(insn
, 10, 6);
1617 rn
= extract32(insn
, 5, 5);
1618 op4
= extract32(insn
, 0, 5);
1620 if (op4
!= 0x0 || op3
!= 0x0 || op2
!= 0x1f) {
1621 unallocated_encoding(s
);
1628 tcg_gen_mov_i64(cpu_pc
, cpu_reg(s
, rn
));
1631 tcg_gen_mov_i64(cpu_pc
, cpu_reg(s
, rn
));
1632 tcg_gen_movi_i64(cpu_reg(s
, 30), s
->pc
);
1635 if (s
->current_el
== 0) {
1636 unallocated_encoding(s
);
1639 gen_helper_exception_return(cpu_env
);
1640 s
->is_jmp
= DISAS_JUMP
;
1644 unallocated_encoding(s
);
1646 unsupported_encoding(s
, insn
);
1650 unallocated_encoding(s
);
1654 s
->is_jmp
= DISAS_JUMP
;
1657 /* C3.2 Branches, exception generating and system instructions */
1658 static void disas_b_exc_sys(DisasContext
*s
, uint32_t insn
)
1660 switch (extract32(insn
, 25, 7)) {
1661 case 0x0a: case 0x0b:
1662 case 0x4a: case 0x4b: /* Unconditional branch (immediate) */
1663 disas_uncond_b_imm(s
, insn
);
1665 case 0x1a: case 0x5a: /* Compare & branch (immediate) */
1666 disas_comp_b_imm(s
, insn
);
1668 case 0x1b: case 0x5b: /* Test & branch (immediate) */
1669 disas_test_b_imm(s
, insn
);
1671 case 0x2a: /* Conditional branch (immediate) */
1672 disas_cond_b_imm(s
, insn
);
1674 case 0x6a: /* Exception generation / System */
1675 if (insn
& (1 << 24)) {
1676 disas_system(s
, insn
);
1681 case 0x6b: /* Unconditional branch (register) */
1682 disas_uncond_b_reg(s
, insn
);
1685 unallocated_encoding(s
);
1691 * Load/Store exclusive instructions are implemented by remembering
1692 * the value/address loaded, and seeing if these are the same
1693 * when the store is performed. This is not actually the architecturally
1694 * mandated semantics, but it works for typical guest code sequences
1695 * and avoids having to monitor regular stores.
1697 * In system emulation mode only one CPU will be running at once, so
1698 * this sequence is effectively atomic. In user emulation mode we
1699 * throw an exception and handle the atomic operation elsewhere.
1701 static void gen_load_exclusive(DisasContext
*s
, int rt
, int rt2
,
1702 TCGv_i64 addr
, int size
, bool is_pair
)
1704 TCGv_i64 tmp
= tcg_temp_new_i64();
1705 TCGMemOp memop
= MO_TE
+ size
;
1707 g_assert(size
<= 3);
1708 tcg_gen_qemu_ld_i64(tmp
, addr
, get_mem_index(s
), memop
);
1711 TCGv_i64 addr2
= tcg_temp_new_i64();
1712 TCGv_i64 hitmp
= tcg_temp_new_i64();
1714 g_assert(size
>= 2);
1715 tcg_gen_addi_i64(addr2
, addr
, 1 << size
);
1716 tcg_gen_qemu_ld_i64(hitmp
, addr2
, get_mem_index(s
), memop
);
1717 tcg_temp_free_i64(addr2
);
1718 tcg_gen_mov_i64(cpu_exclusive_high
, hitmp
);
1719 tcg_gen_mov_i64(cpu_reg(s
, rt2
), hitmp
);
1720 tcg_temp_free_i64(hitmp
);
1723 tcg_gen_mov_i64(cpu_exclusive_val
, tmp
);
1724 tcg_gen_mov_i64(cpu_reg(s
, rt
), tmp
);
1726 tcg_temp_free_i64(tmp
);
1727 tcg_gen_mov_i64(cpu_exclusive_addr
, addr
);
1730 #ifdef CONFIG_USER_ONLY
1731 static void gen_store_exclusive(DisasContext
*s
, int rd
, int rt
, int rt2
,
1732 TCGv_i64 addr
, int size
, int is_pair
)
1734 tcg_gen_mov_i64(cpu_exclusive_test
, addr
);
1735 tcg_gen_movi_i32(cpu_exclusive_info
,
1736 size
| is_pair
<< 2 | (rd
<< 4) | (rt
<< 9) | (rt2
<< 14));
1737 gen_exception_internal_insn(s
, 4, EXCP_STREX
);
1740 static void gen_store_exclusive(DisasContext
*s
, int rd
, int rt
, int rt2
,
1741 TCGv_i64 inaddr
, int size
, int is_pair
)
1743 /* if (env->exclusive_addr == addr && env->exclusive_val == [addr]
1744 * && (!is_pair || env->exclusive_high == [addr + datasize])) {
1747 * [addr + datasize] = {Rt2};
1753 * env->exclusive_addr = -1;
1755 TCGLabel
*fail_label
= gen_new_label();
1756 TCGLabel
*done_label
= gen_new_label();
1757 TCGv_i64 addr
= tcg_temp_local_new_i64();
1760 /* Copy input into a local temp so it is not trashed when the
1761 * basic block ends at the branch insn.
1763 tcg_gen_mov_i64(addr
, inaddr
);
1764 tcg_gen_brcond_i64(TCG_COND_NE
, addr
, cpu_exclusive_addr
, fail_label
);
1766 tmp
= tcg_temp_new_i64();
1767 tcg_gen_qemu_ld_i64(tmp
, addr
, get_mem_index(s
), MO_TE
+ size
);
1768 tcg_gen_brcond_i64(TCG_COND_NE
, tmp
, cpu_exclusive_val
, fail_label
);
1769 tcg_temp_free_i64(tmp
);
1772 TCGv_i64 addrhi
= tcg_temp_new_i64();
1773 TCGv_i64 tmphi
= tcg_temp_new_i64();
1775 tcg_gen_addi_i64(addrhi
, addr
, 1 << size
);
1776 tcg_gen_qemu_ld_i64(tmphi
, addrhi
, get_mem_index(s
), MO_TE
+ size
);
1777 tcg_gen_brcond_i64(TCG_COND_NE
, tmphi
, cpu_exclusive_high
, fail_label
);
1779 tcg_temp_free_i64(tmphi
);
1780 tcg_temp_free_i64(addrhi
);
1783 /* We seem to still have the exclusive monitor, so do the store */
1784 tcg_gen_qemu_st_i64(cpu_reg(s
, rt
), addr
, get_mem_index(s
), MO_TE
+ size
);
1786 TCGv_i64 addrhi
= tcg_temp_new_i64();
1788 tcg_gen_addi_i64(addrhi
, addr
, 1 << size
);
1789 tcg_gen_qemu_st_i64(cpu_reg(s
, rt2
), addrhi
,
1790 get_mem_index(s
), MO_TE
+ size
);
1791 tcg_temp_free_i64(addrhi
);
1794 tcg_temp_free_i64(addr
);
1796 tcg_gen_movi_i64(cpu_reg(s
, rd
), 0);
1797 tcg_gen_br(done_label
);
1798 gen_set_label(fail_label
);
1799 tcg_gen_movi_i64(cpu_reg(s
, rd
), 1);
1800 gen_set_label(done_label
);
1801 tcg_gen_movi_i64(cpu_exclusive_addr
, -1);
1806 /* C3.3.6 Load/store exclusive
1808 * 31 30 29 24 23 22 21 20 16 15 14 10 9 5 4 0
1809 * +-----+-------------+----+---+----+------+----+-------+------+------+
1810 * | sz | 0 0 1 0 0 0 | o2 | L | o1 | Rs | o0 | Rt2 | Rn | Rt |
1811 * +-----+-------------+----+---+----+------+----+-------+------+------+
1813 * sz: 00 -> 8 bit, 01 -> 16 bit, 10 -> 32 bit, 11 -> 64 bit
1814 * L: 0 -> store, 1 -> load
1815 * o2: 0 -> exclusive, 1 -> not
1816 * o1: 0 -> single register, 1 -> register pair
1817 * o0: 1 -> load-acquire/store-release, 0 -> not
1819 static void disas_ldst_excl(DisasContext
*s
, uint32_t insn
)
1821 int rt
= extract32(insn
, 0, 5);
1822 int rn
= extract32(insn
, 5, 5);
1823 int rt2
= extract32(insn
, 10, 5);
1824 int is_lasr
= extract32(insn
, 15, 1);
1825 int rs
= extract32(insn
, 16, 5);
1826 int is_pair
= extract32(insn
, 21, 1);
1827 int is_store
= !extract32(insn
, 22, 1);
1828 int is_excl
= !extract32(insn
, 23, 1);
1829 int size
= extract32(insn
, 30, 2);
1832 if ((!is_excl
&& !is_pair
&& !is_lasr
) ||
1833 (!is_excl
&& is_pair
) ||
1834 (is_pair
&& size
< 2)) {
1835 unallocated_encoding(s
);
1840 gen_check_sp_alignment(s
);
1842 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
1844 /* Note that since TCG is single threaded load-acquire/store-release
1845 * semantics require no extra if (is_lasr) { ... } handling.
1851 gen_load_exclusive(s
, rt
, rt2
, tcg_addr
, size
, is_pair
);
1853 gen_store_exclusive(s
, rs
, rt
, rt2
, tcg_addr
, size
, is_pair
);
1856 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
1858 do_gpr_st(s
, tcg_rt
, tcg_addr
, size
);
1860 do_gpr_ld(s
, tcg_rt
, tcg_addr
, size
, false, false);
1866 * C3.3.5 Load register (literal)
1868 * 31 30 29 27 26 25 24 23 5 4 0
1869 * +-----+-------+---+-----+-------------------+-------+
1870 * | opc | 0 1 1 | V | 0 0 | imm19 | Rt |
1871 * +-----+-------+---+-----+-------------------+-------+
1873 * V: 1 -> vector (simd/fp)
1874 * opc (non-vector): 00 -> 32 bit, 01 -> 64 bit,
1875 * 10-> 32 bit signed, 11 -> prefetch
1876 * opc (vector): 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit (11 unallocated)
1878 static void disas_ld_lit(DisasContext
*s
, uint32_t insn
)
1880 int rt
= extract32(insn
, 0, 5);
1881 int64_t imm
= sextract32(insn
, 5, 19) << 2;
1882 bool is_vector
= extract32(insn
, 26, 1);
1883 int opc
= extract32(insn
, 30, 2);
1884 bool is_signed
= false;
1886 TCGv_i64 tcg_rt
, tcg_addr
;
1890 unallocated_encoding(s
);
1894 if (!fp_access_check(s
)) {
1899 /* PRFM (literal) : prefetch */
1902 size
= 2 + extract32(opc
, 0, 1);
1903 is_signed
= extract32(opc
, 1, 1);
1906 tcg_rt
= cpu_reg(s
, rt
);
1908 tcg_addr
= tcg_const_i64((s
->pc
- 4) + imm
);
1910 do_fp_ld(s
, rt
, tcg_addr
, size
);
1912 do_gpr_ld(s
, tcg_rt
, tcg_addr
, size
, is_signed
, false);
1914 tcg_temp_free_i64(tcg_addr
);
1918 * C5.6.80 LDNP (Load Pair - non-temporal hint)
1919 * C5.6.81 LDP (Load Pair - non vector)
1920 * C5.6.82 LDPSW (Load Pair Signed Word - non vector)
1921 * C5.6.176 STNP (Store Pair - non-temporal hint)
1922 * C5.6.177 STP (Store Pair - non vector)
1923 * C6.3.165 LDNP (Load Pair of SIMD&FP - non-temporal hint)
1924 * C6.3.165 LDP (Load Pair of SIMD&FP)
1925 * C6.3.284 STNP (Store Pair of SIMD&FP - non-temporal hint)
1926 * C6.3.284 STP (Store Pair of SIMD&FP)
1928 * 31 30 29 27 26 25 24 23 22 21 15 14 10 9 5 4 0
1929 * +-----+-------+---+---+-------+---+-----------------------------+
1930 * | opc | 1 0 1 | V | 0 | index | L | imm7 | Rt2 | Rn | Rt |
1931 * +-----+-------+---+---+-------+---+-------+-------+------+------+
1933 * opc: LDP/STP/LDNP/STNP 00 -> 32 bit, 10 -> 64 bit
1935 * LDP/STP/LDNP/STNP (SIMD) 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit
1936 * V: 0 -> GPR, 1 -> Vector
1937 * idx: 00 -> signed offset with non-temporal hint, 01 -> post-index,
1938 * 10 -> signed offset, 11 -> pre-index
1939 * L: 0 -> Store 1 -> Load
1941 * Rt, Rt2 = GPR or SIMD registers to be stored
1942 * Rn = general purpose register containing address
1943 * imm7 = signed offset (multiple of 4 or 8 depending on size)
1945 static void disas_ldst_pair(DisasContext
*s
, uint32_t insn
)
1947 int rt
= extract32(insn
, 0, 5);
1948 int rn
= extract32(insn
, 5, 5);
1949 int rt2
= extract32(insn
, 10, 5);
1950 uint64_t offset
= sextract64(insn
, 15, 7);
1951 int index
= extract32(insn
, 23, 2);
1952 bool is_vector
= extract32(insn
, 26, 1);
1953 bool is_load
= extract32(insn
, 22, 1);
1954 int opc
= extract32(insn
, 30, 2);
1956 bool is_signed
= false;
1957 bool postindex
= false;
1960 TCGv_i64 tcg_addr
; /* calculated address */
1964 unallocated_encoding(s
);
1971 size
= 2 + extract32(opc
, 1, 1);
1972 is_signed
= extract32(opc
, 0, 1);
1973 if (!is_load
&& is_signed
) {
1974 unallocated_encoding(s
);
1980 case 1: /* post-index */
1985 /* signed offset with "non-temporal" hint. Since we don't emulate
1986 * caches we don't care about hints to the cache system about
1987 * data access patterns, and handle this identically to plain
1991 /* There is no non-temporal-hint version of LDPSW */
1992 unallocated_encoding(s
);
1997 case 2: /* signed offset, rn not updated */
2000 case 3: /* pre-index */
2006 if (is_vector
&& !fp_access_check(s
)) {
2013 gen_check_sp_alignment(s
);
2016 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
2019 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, offset
);
2024 do_fp_ld(s
, rt
, tcg_addr
, size
);
2026 do_fp_st(s
, rt
, tcg_addr
, size
);
2029 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2031 do_gpr_ld(s
, tcg_rt
, tcg_addr
, size
, is_signed
, false);
2033 do_gpr_st(s
, tcg_rt
, tcg_addr
, size
);
2036 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, 1 << size
);
2039 do_fp_ld(s
, rt2
, tcg_addr
, size
);
2041 do_fp_st(s
, rt2
, tcg_addr
, size
);
2044 TCGv_i64 tcg_rt2
= cpu_reg(s
, rt2
);
2046 do_gpr_ld(s
, tcg_rt2
, tcg_addr
, size
, is_signed
, false);
2048 do_gpr_st(s
, tcg_rt2
, tcg_addr
, size
);
2054 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, offset
- (1 << size
));
2056 tcg_gen_subi_i64(tcg_addr
, tcg_addr
, 1 << size
);
2058 tcg_gen_mov_i64(cpu_reg_sp(s
, rn
), tcg_addr
);
2063 * C3.3.8 Load/store (immediate post-indexed)
2064 * C3.3.9 Load/store (immediate pre-indexed)
2065 * C3.3.12 Load/store (unscaled immediate)
2067 * 31 30 29 27 26 25 24 23 22 21 20 12 11 10 9 5 4 0
2068 * +----+-------+---+-----+-----+---+--------+-----+------+------+
2069 * |size| 1 1 1 | V | 0 0 | opc | 0 | imm9 | idx | Rn | Rt |
2070 * +----+-------+---+-----+-----+---+--------+-----+------+------+
2072 * idx = 01 -> post-indexed, 11 pre-indexed, 00 unscaled imm. (no writeback)
2074 * V = 0 -> non-vector
2075 * size: 00 -> 8 bit, 01 -> 16 bit, 10 -> 32 bit, 11 -> 64bit
2076 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
2078 static void disas_ldst_reg_imm9(DisasContext
*s
, uint32_t insn
)
2080 int rt
= extract32(insn
, 0, 5);
2081 int rn
= extract32(insn
, 5, 5);
2082 int imm9
= sextract32(insn
, 12, 9);
2083 int opc
= extract32(insn
, 22, 2);
2084 int size
= extract32(insn
, 30, 2);
2085 int idx
= extract32(insn
, 10, 2);
2086 bool is_signed
= false;
2087 bool is_store
= false;
2088 bool is_extended
= false;
2089 bool is_unpriv
= (idx
== 2);
2090 bool is_vector
= extract32(insn
, 26, 1);
2097 size
|= (opc
& 2) << 1;
2098 if (size
> 4 || is_unpriv
) {
2099 unallocated_encoding(s
);
2102 is_store
= ((opc
& 1) == 0);
2103 if (!fp_access_check(s
)) {
2107 if (size
== 3 && opc
== 2) {
2108 /* PRFM - prefetch */
2110 unallocated_encoding(s
);
2115 if (opc
== 3 && size
> 1) {
2116 unallocated_encoding(s
);
2119 is_store
= (opc
== 0);
2120 is_signed
= opc
& (1<<1);
2121 is_extended
= (size
< 3) && (opc
& 1);
2141 gen_check_sp_alignment(s
);
2143 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
2146 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, imm9
);
2151 do_fp_st(s
, rt
, tcg_addr
, size
);
2153 do_fp_ld(s
, rt
, tcg_addr
, size
);
2156 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2157 int memidx
= is_unpriv
? get_a64_user_mem_index(s
) : get_mem_index(s
);
2160 do_gpr_st_memidx(s
, tcg_rt
, tcg_addr
, size
, memidx
);
2162 do_gpr_ld_memidx(s
, tcg_rt
, tcg_addr
, size
,
2163 is_signed
, is_extended
, memidx
);
2168 TCGv_i64 tcg_rn
= cpu_reg_sp(s
, rn
);
2170 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, imm9
);
2172 tcg_gen_mov_i64(tcg_rn
, tcg_addr
);
2177 * C3.3.10 Load/store (register offset)
2179 * 31 30 29 27 26 25 24 23 22 21 20 16 15 13 12 11 10 9 5 4 0
2180 * +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+
2181 * |size| 1 1 1 | V | 0 0 | opc | 1 | Rm | opt | S| 1 0 | Rn | Rt |
2182 * +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+
2185 * size: 00-> byte, 01 -> 16 bit, 10 -> 32bit, 11 -> 64bit
2186 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
2188 * size is opc<1>:size<1:0> so 100 -> 128 bit; 110 and 111 unallocated
2189 * opc<0>: 0 -> store, 1 -> load
2190 * V: 1 -> vector/simd
2191 * opt: extend encoding (see DecodeRegExtend)
2192 * S: if S=1 then scale (essentially index by sizeof(size))
2193 * Rt: register to transfer into/out of
2194 * Rn: address register or SP for base
2195 * Rm: offset register or ZR for offset
2197 static void disas_ldst_reg_roffset(DisasContext
*s
, uint32_t insn
)
2199 int rt
= extract32(insn
, 0, 5);
2200 int rn
= extract32(insn
, 5, 5);
2201 int shift
= extract32(insn
, 12, 1);
2202 int rm
= extract32(insn
, 16, 5);
2203 int opc
= extract32(insn
, 22, 2);
2204 int opt
= extract32(insn
, 13, 3);
2205 int size
= extract32(insn
, 30, 2);
2206 bool is_signed
= false;
2207 bool is_store
= false;
2208 bool is_extended
= false;
2209 bool is_vector
= extract32(insn
, 26, 1);
2214 if (extract32(opt
, 1, 1) == 0) {
2215 unallocated_encoding(s
);
2220 size
|= (opc
& 2) << 1;
2222 unallocated_encoding(s
);
2225 is_store
= !extract32(opc
, 0, 1);
2226 if (!fp_access_check(s
)) {
2230 if (size
== 3 && opc
== 2) {
2231 /* PRFM - prefetch */
2234 if (opc
== 3 && size
> 1) {
2235 unallocated_encoding(s
);
2238 is_store
= (opc
== 0);
2239 is_signed
= extract32(opc
, 1, 1);
2240 is_extended
= (size
< 3) && extract32(opc
, 0, 1);
2244 gen_check_sp_alignment(s
);
2246 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
2248 tcg_rm
= read_cpu_reg(s
, rm
, 1);
2249 ext_and_shift_reg(tcg_rm
, tcg_rm
, opt
, shift
? size
: 0);
2251 tcg_gen_add_i64(tcg_addr
, tcg_addr
, tcg_rm
);
2255 do_fp_st(s
, rt
, tcg_addr
, size
);
2257 do_fp_ld(s
, rt
, tcg_addr
, size
);
2260 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2262 do_gpr_st(s
, tcg_rt
, tcg_addr
, size
);
2264 do_gpr_ld(s
, tcg_rt
, tcg_addr
, size
, is_signed
, is_extended
);
2270 * C3.3.13 Load/store (unsigned immediate)
2272 * 31 30 29 27 26 25 24 23 22 21 10 9 5
2273 * +----+-------+---+-----+-----+------------+-------+------+
2274 * |size| 1 1 1 | V | 0 1 | opc | imm12 | Rn | Rt |
2275 * +----+-------+---+-----+-----+------------+-------+------+
2278 * size: 00-> byte, 01 -> 16 bit, 10 -> 32bit, 11 -> 64bit
2279 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
2281 * size is opc<1>:size<1:0> so 100 -> 128 bit; 110 and 111 unallocated
2282 * opc<0>: 0 -> store, 1 -> load
2283 * Rn: base address register (inc SP)
2284 * Rt: target register
2286 static void disas_ldst_reg_unsigned_imm(DisasContext
*s
, uint32_t insn
)
2288 int rt
= extract32(insn
, 0, 5);
2289 int rn
= extract32(insn
, 5, 5);
2290 unsigned int imm12
= extract32(insn
, 10, 12);
2291 bool is_vector
= extract32(insn
, 26, 1);
2292 int size
= extract32(insn
, 30, 2);
2293 int opc
= extract32(insn
, 22, 2);
2294 unsigned int offset
;
2299 bool is_signed
= false;
2300 bool is_extended
= false;
2303 size
|= (opc
& 2) << 1;
2305 unallocated_encoding(s
);
2308 is_store
= !extract32(opc
, 0, 1);
2309 if (!fp_access_check(s
)) {
2313 if (size
== 3 && opc
== 2) {
2314 /* PRFM - prefetch */
2317 if (opc
== 3 && size
> 1) {
2318 unallocated_encoding(s
);
2321 is_store
= (opc
== 0);
2322 is_signed
= extract32(opc
, 1, 1);
2323 is_extended
= (size
< 3) && extract32(opc
, 0, 1);
2327 gen_check_sp_alignment(s
);
2329 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
2330 offset
= imm12
<< size
;
2331 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, offset
);
2335 do_fp_st(s
, rt
, tcg_addr
, size
);
2337 do_fp_ld(s
, rt
, tcg_addr
, size
);
2340 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2342 do_gpr_st(s
, tcg_rt
, tcg_addr
, size
);
2344 do_gpr_ld(s
, tcg_rt
, tcg_addr
, size
, is_signed
, is_extended
);
2349 /* Load/store register (all forms) */
2350 static void disas_ldst_reg(DisasContext
*s
, uint32_t insn
)
2352 switch (extract32(insn
, 24, 2)) {
2354 if (extract32(insn
, 21, 1) == 1 && extract32(insn
, 10, 2) == 2) {
2355 disas_ldst_reg_roffset(s
, insn
);
2357 /* Load/store register (unscaled immediate)
2358 * Load/store immediate pre/post-indexed
2359 * Load/store register unprivileged
2361 disas_ldst_reg_imm9(s
, insn
);
2365 disas_ldst_reg_unsigned_imm(s
, insn
);
2368 unallocated_encoding(s
);
2373 /* C3.3.1 AdvSIMD load/store multiple structures
2375 * 31 30 29 23 22 21 16 15 12 11 10 9 5 4 0
2376 * +---+---+---------------+---+-------------+--------+------+------+------+
2377 * | 0 | Q | 0 0 1 1 0 0 0 | L | 0 0 0 0 0 0 | opcode | size | Rn | Rt |
2378 * +---+---+---------------+---+-------------+--------+------+------+------+
2380 * C3.3.2 AdvSIMD load/store multiple structures (post-indexed)
2382 * 31 30 29 23 22 21 20 16 15 12 11 10 9 5 4 0
2383 * +---+---+---------------+---+---+---------+--------+------+------+------+
2384 * | 0 | Q | 0 0 1 1 0 0 1 | L | 0 | Rm | opcode | size | Rn | Rt |
2385 * +---+---+---------------+---+---+---------+--------+------+------+------+
2387 * Rt: first (or only) SIMD&FP register to be transferred
2388 * Rn: base address or SP
2389 * Rm (post-index only): post-index register (when !31) or size dependent #imm
2391 static void disas_ldst_multiple_struct(DisasContext
*s
, uint32_t insn
)
2393 int rt
= extract32(insn
, 0, 5);
2394 int rn
= extract32(insn
, 5, 5);
2395 int size
= extract32(insn
, 10, 2);
2396 int opcode
= extract32(insn
, 12, 4);
2397 bool is_store
= !extract32(insn
, 22, 1);
2398 bool is_postidx
= extract32(insn
, 23, 1);
2399 bool is_q
= extract32(insn
, 30, 1);
2400 TCGv_i64 tcg_addr
, tcg_rn
;
2402 int ebytes
= 1 << size
;
2403 int elements
= (is_q
? 128 : 64) / (8 << size
);
2404 int rpt
; /* num iterations */
2405 int selem
; /* structure elements */
2408 if (extract32(insn
, 31, 1) || extract32(insn
, 21, 1)) {
2409 unallocated_encoding(s
);
2413 /* From the shared decode logic */
2444 unallocated_encoding(s
);
2448 if (size
== 3 && !is_q
&& selem
!= 1) {
2450 unallocated_encoding(s
);
2454 if (!fp_access_check(s
)) {
2459 gen_check_sp_alignment(s
);
2462 tcg_rn
= cpu_reg_sp(s
, rn
);
2463 tcg_addr
= tcg_temp_new_i64();
2464 tcg_gen_mov_i64(tcg_addr
, tcg_rn
);
2466 for (r
= 0; r
< rpt
; r
++) {
2468 for (e
= 0; e
< elements
; e
++) {
2469 int tt
= (rt
+ r
) % 32;
2471 for (xs
= 0; xs
< selem
; xs
++) {
2473 do_vec_st(s
, tt
, e
, tcg_addr
, size
);
2475 do_vec_ld(s
, tt
, e
, tcg_addr
, size
);
2477 /* For non-quad operations, setting a slice of the low
2478 * 64 bits of the register clears the high 64 bits (in
2479 * the ARM ARM pseudocode this is implicit in the fact
2480 * that 'rval' is a 64 bit wide variable). We optimize
2481 * by noticing that we only need to do this the first
2482 * time we touch a register.
2484 if (!is_q
&& e
== 0 && (r
== 0 || xs
== selem
- 1)) {
2485 clear_vec_high(s
, tt
);
2488 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, ebytes
);
2495 int rm
= extract32(insn
, 16, 5);
2497 tcg_gen_mov_i64(tcg_rn
, tcg_addr
);
2499 tcg_gen_add_i64(tcg_rn
, tcg_rn
, cpu_reg(s
, rm
));
2502 tcg_temp_free_i64(tcg_addr
);
2505 /* C3.3.3 AdvSIMD load/store single structure
2507 * 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 0
2508 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
2509 * | 0 | Q | 0 0 1 1 0 1 0 | L R | 0 0 0 0 0 | opc | S | size | Rn | Rt |
2510 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
2512 * C3.3.4 AdvSIMD load/store single structure (post-indexed)
2514 * 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 0
2515 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
2516 * | 0 | Q | 0 0 1 1 0 1 1 | L R | Rm | opc | S | size | Rn | Rt |
2517 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
2519 * Rt: first (or only) SIMD&FP register to be transferred
2520 * Rn: base address or SP
2521 * Rm (post-index only): post-index register (when !31) or size dependent #imm
2522 * index = encoded in Q:S:size dependent on size
2524 * lane_size = encoded in R, opc
2525 * transfer width = encoded in opc, S, size
2527 static void disas_ldst_single_struct(DisasContext
*s
, uint32_t insn
)
2529 int rt
= extract32(insn
, 0, 5);
2530 int rn
= extract32(insn
, 5, 5);
2531 int size
= extract32(insn
, 10, 2);
2532 int S
= extract32(insn
, 12, 1);
2533 int opc
= extract32(insn
, 13, 3);
2534 int R
= extract32(insn
, 21, 1);
2535 int is_load
= extract32(insn
, 22, 1);
2536 int is_postidx
= extract32(insn
, 23, 1);
2537 int is_q
= extract32(insn
, 30, 1);
2539 int scale
= extract32(opc
, 1, 2);
2540 int selem
= (extract32(opc
, 0, 1) << 1 | R
) + 1;
2541 bool replicate
= false;
2542 int index
= is_q
<< 3 | S
<< 2 | size
;
2544 TCGv_i64 tcg_addr
, tcg_rn
;
2548 if (!is_load
|| S
) {
2549 unallocated_encoding(s
);
2558 if (extract32(size
, 0, 1)) {
2559 unallocated_encoding(s
);
2565 if (extract32(size
, 1, 1)) {
2566 unallocated_encoding(s
);
2569 if (!extract32(size
, 0, 1)) {
2573 unallocated_encoding(s
);
2581 g_assert_not_reached();
2584 if (!fp_access_check(s
)) {
2588 ebytes
= 1 << scale
;
2591 gen_check_sp_alignment(s
);
2594 tcg_rn
= cpu_reg_sp(s
, rn
);
2595 tcg_addr
= tcg_temp_new_i64();
2596 tcg_gen_mov_i64(tcg_addr
, tcg_rn
);
2598 for (xs
= 0; xs
< selem
; xs
++) {
2600 /* Load and replicate to all elements */
2602 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
2604 tcg_gen_qemu_ld_i64(tcg_tmp
, tcg_addr
,
2605 get_mem_index(s
), MO_TE
+ scale
);
2608 mulconst
= 0x0101010101010101ULL
;
2611 mulconst
= 0x0001000100010001ULL
;
2614 mulconst
= 0x0000000100000001ULL
;
2620 g_assert_not_reached();
2623 tcg_gen_muli_i64(tcg_tmp
, tcg_tmp
, mulconst
);
2625 write_vec_element(s
, tcg_tmp
, rt
, 0, MO_64
);
2627 write_vec_element(s
, tcg_tmp
, rt
, 1, MO_64
);
2629 clear_vec_high(s
, rt
);
2631 tcg_temp_free_i64(tcg_tmp
);
2633 /* Load/store one element per register */
2635 do_vec_ld(s
, rt
, index
, tcg_addr
, MO_TE
+ scale
);
2637 do_vec_st(s
, rt
, index
, tcg_addr
, MO_TE
+ scale
);
2640 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, ebytes
);
2645 int rm
= extract32(insn
, 16, 5);
2647 tcg_gen_mov_i64(tcg_rn
, tcg_addr
);
2649 tcg_gen_add_i64(tcg_rn
, tcg_rn
, cpu_reg(s
, rm
));
2652 tcg_temp_free_i64(tcg_addr
);
2655 /* C3.3 Loads and stores */
2656 static void disas_ldst(DisasContext
*s
, uint32_t insn
)
2658 switch (extract32(insn
, 24, 6)) {
2659 case 0x08: /* Load/store exclusive */
2660 disas_ldst_excl(s
, insn
);
2662 case 0x18: case 0x1c: /* Load register (literal) */
2663 disas_ld_lit(s
, insn
);
2665 case 0x28: case 0x29:
2666 case 0x2c: case 0x2d: /* Load/store pair (all forms) */
2667 disas_ldst_pair(s
, insn
);
2669 case 0x38: case 0x39:
2670 case 0x3c: case 0x3d: /* Load/store register (all forms) */
2671 disas_ldst_reg(s
, insn
);
2673 case 0x0c: /* AdvSIMD load/store multiple structures */
2674 disas_ldst_multiple_struct(s
, insn
);
2676 case 0x0d: /* AdvSIMD load/store single structure */
2677 disas_ldst_single_struct(s
, insn
);
2680 unallocated_encoding(s
);
2685 /* C3.4.6 PC-rel. addressing
2686 * 31 30 29 28 24 23 5 4 0
2687 * +----+-------+-----------+-------------------+------+
2688 * | op | immlo | 1 0 0 0 0 | immhi | Rd |
2689 * +----+-------+-----------+-------------------+------+
2691 static void disas_pc_rel_adr(DisasContext
*s
, uint32_t insn
)
2693 unsigned int page
, rd
;
2697 page
= extract32(insn
, 31, 1);
2698 /* SignExtend(immhi:immlo) -> offset */
2699 offset
= sextract64(insn
, 5, 19);
2700 offset
= offset
<< 2 | extract32(insn
, 29, 2);
2701 rd
= extract32(insn
, 0, 5);
2705 /* ADRP (page based) */
2710 tcg_gen_movi_i64(cpu_reg(s
, rd
), base
+ offset
);
2714 * C3.4.1 Add/subtract (immediate)
2716 * 31 30 29 28 24 23 22 21 10 9 5 4 0
2717 * +--+--+--+-----------+-----+-------------+-----+-----+
2718 * |sf|op| S| 1 0 0 0 1 |shift| imm12 | Rn | Rd |
2719 * +--+--+--+-----------+-----+-------------+-----+-----+
2721 * sf: 0 -> 32bit, 1 -> 64bit
2722 * op: 0 -> add , 1 -> sub
2724 * shift: 00 -> LSL imm by 0, 01 -> LSL imm by 12
2726 static void disas_add_sub_imm(DisasContext
*s
, uint32_t insn
)
2728 int rd
= extract32(insn
, 0, 5);
2729 int rn
= extract32(insn
, 5, 5);
2730 uint64_t imm
= extract32(insn
, 10, 12);
2731 int shift
= extract32(insn
, 22, 2);
2732 bool setflags
= extract32(insn
, 29, 1);
2733 bool sub_op
= extract32(insn
, 30, 1);
2734 bool is_64bit
= extract32(insn
, 31, 1);
2736 TCGv_i64 tcg_rn
= cpu_reg_sp(s
, rn
);
2737 TCGv_i64 tcg_rd
= setflags
? cpu_reg(s
, rd
) : cpu_reg_sp(s
, rd
);
2738 TCGv_i64 tcg_result
;
2747 unallocated_encoding(s
);
2751 tcg_result
= tcg_temp_new_i64();
2754 tcg_gen_subi_i64(tcg_result
, tcg_rn
, imm
);
2756 tcg_gen_addi_i64(tcg_result
, tcg_rn
, imm
);
2759 TCGv_i64 tcg_imm
= tcg_const_i64(imm
);
2761 gen_sub_CC(is_64bit
, tcg_result
, tcg_rn
, tcg_imm
);
2763 gen_add_CC(is_64bit
, tcg_result
, tcg_rn
, tcg_imm
);
2765 tcg_temp_free_i64(tcg_imm
);
2769 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
2771 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
2774 tcg_temp_free_i64(tcg_result
);
2777 /* The input should be a value in the bottom e bits (with higher
2778 * bits zero); returns that value replicated into every element
2779 * of size e in a 64 bit integer.
2781 static uint64_t bitfield_replicate(uint64_t mask
, unsigned int e
)
2791 /* Return a value with the bottom len bits set (where 0 < len <= 64) */
2792 static inline uint64_t bitmask64(unsigned int length
)
2794 assert(length
> 0 && length
<= 64);
2795 return ~0ULL >> (64 - length
);
2798 /* Simplified variant of pseudocode DecodeBitMasks() for the case where we
2799 * only require the wmask. Returns false if the imms/immr/immn are a reserved
2800 * value (ie should cause a guest UNDEF exception), and true if they are
2801 * valid, in which case the decoded bit pattern is written to result.
2803 static bool logic_imm_decode_wmask(uint64_t *result
, unsigned int immn
,
2804 unsigned int imms
, unsigned int immr
)
2807 unsigned e
, levels
, s
, r
;
2810 assert(immn
< 2 && imms
< 64 && immr
< 64);
2812 /* The bit patterns we create here are 64 bit patterns which
2813 * are vectors of identical elements of size e = 2, 4, 8, 16, 32 or
2814 * 64 bits each. Each element contains the same value: a run
2815 * of between 1 and e-1 non-zero bits, rotated within the
2816 * element by between 0 and e-1 bits.
2818 * The element size and run length are encoded into immn (1 bit)
2819 * and imms (6 bits) as follows:
2820 * 64 bit elements: immn = 1, imms = <length of run - 1>
2821 * 32 bit elements: immn = 0, imms = 0 : <length of run - 1>
2822 * 16 bit elements: immn = 0, imms = 10 : <length of run - 1>
2823 * 8 bit elements: immn = 0, imms = 110 : <length of run - 1>
2824 * 4 bit elements: immn = 0, imms = 1110 : <length of run - 1>
2825 * 2 bit elements: immn = 0, imms = 11110 : <length of run - 1>
2826 * Notice that immn = 0, imms = 11111x is the only combination
2827 * not covered by one of the above options; this is reserved.
2828 * Further, <length of run - 1> all-ones is a reserved pattern.
2830 * In all cases the rotation is by immr % e (and immr is 6 bits).
2833 /* First determine the element size */
2834 len
= 31 - clz32((immn
<< 6) | (~imms
& 0x3f));
2836 /* This is the immn == 0, imms == 0x11111x case */
2846 /* <length of run - 1> mustn't be all-ones. */
2850 /* Create the value of one element: s+1 set bits rotated
2851 * by r within the element (which is e bits wide)...
2853 mask
= bitmask64(s
+ 1);
2855 mask
= (mask
>> r
) | (mask
<< (e
- r
));
2856 mask
&= bitmask64(e
);
2858 /* ...then replicate the element over the whole 64 bit value */
2859 mask
= bitfield_replicate(mask
, e
);
2864 /* C3.4.4 Logical (immediate)
2865 * 31 30 29 28 23 22 21 16 15 10 9 5 4 0
2866 * +----+-----+-------------+---+------+------+------+------+
2867 * | sf | opc | 1 0 0 1 0 0 | N | immr | imms | Rn | Rd |
2868 * +----+-----+-------------+---+------+------+------+------+
2870 static void disas_logic_imm(DisasContext
*s
, uint32_t insn
)
2872 unsigned int sf
, opc
, is_n
, immr
, imms
, rn
, rd
;
2873 TCGv_i64 tcg_rd
, tcg_rn
;
2875 bool is_and
= false;
2877 sf
= extract32(insn
, 31, 1);
2878 opc
= extract32(insn
, 29, 2);
2879 is_n
= extract32(insn
, 22, 1);
2880 immr
= extract32(insn
, 16, 6);
2881 imms
= extract32(insn
, 10, 6);
2882 rn
= extract32(insn
, 5, 5);
2883 rd
= extract32(insn
, 0, 5);
2886 unallocated_encoding(s
);
2890 if (opc
== 0x3) { /* ANDS */
2891 tcg_rd
= cpu_reg(s
, rd
);
2893 tcg_rd
= cpu_reg_sp(s
, rd
);
2895 tcg_rn
= cpu_reg(s
, rn
);
2897 if (!logic_imm_decode_wmask(&wmask
, is_n
, imms
, immr
)) {
2898 /* some immediate field values are reserved */
2899 unallocated_encoding(s
);
2904 wmask
&= 0xffffffff;
2908 case 0x3: /* ANDS */
2910 tcg_gen_andi_i64(tcg_rd
, tcg_rn
, wmask
);
2914 tcg_gen_ori_i64(tcg_rd
, tcg_rn
, wmask
);
2917 tcg_gen_xori_i64(tcg_rd
, tcg_rn
, wmask
);
2920 assert(FALSE
); /* must handle all above */
2924 if (!sf
&& !is_and
) {
2925 /* zero extend final result; we know we can skip this for AND
2926 * since the immediate had the high 32 bits clear.
2928 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
2931 if (opc
== 3) { /* ANDS */
2932 gen_logic_CC(sf
, tcg_rd
);
2937 * C3.4.5 Move wide (immediate)
2939 * 31 30 29 28 23 22 21 20 5 4 0
2940 * +--+-----+-------------+-----+----------------+------+
2941 * |sf| opc | 1 0 0 1 0 1 | hw | imm16 | Rd |
2942 * +--+-----+-------------+-----+----------------+------+
2944 * sf: 0 -> 32 bit, 1 -> 64 bit
2945 * opc: 00 -> N, 10 -> Z, 11 -> K
2946 * hw: shift/16 (0,16, and sf only 32, 48)
2948 static void disas_movw_imm(DisasContext
*s
, uint32_t insn
)
2950 int rd
= extract32(insn
, 0, 5);
2951 uint64_t imm
= extract32(insn
, 5, 16);
2952 int sf
= extract32(insn
, 31, 1);
2953 int opc
= extract32(insn
, 29, 2);
2954 int pos
= extract32(insn
, 21, 2) << 4;
2955 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
2958 if (!sf
&& (pos
>= 32)) {
2959 unallocated_encoding(s
);
2973 tcg_gen_movi_i64(tcg_rd
, imm
);
2976 tcg_imm
= tcg_const_i64(imm
);
2977 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_imm
, pos
, 16);
2978 tcg_temp_free_i64(tcg_imm
);
2980 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
2984 unallocated_encoding(s
);
2990 * 31 30 29 28 23 22 21 16 15 10 9 5 4 0
2991 * +----+-----+-------------+---+------+------+------+------+
2992 * | sf | opc | 1 0 0 1 1 0 | N | immr | imms | Rn | Rd |
2993 * +----+-----+-------------+---+------+------+------+------+
2995 static void disas_bitfield(DisasContext
*s
, uint32_t insn
)
2997 unsigned int sf
, n
, opc
, ri
, si
, rn
, rd
, bitsize
, pos
, len
;
2998 TCGv_i64 tcg_rd
, tcg_tmp
;
3000 sf
= extract32(insn
, 31, 1);
3001 opc
= extract32(insn
, 29, 2);
3002 n
= extract32(insn
, 22, 1);
3003 ri
= extract32(insn
, 16, 6);
3004 si
= extract32(insn
, 10, 6);
3005 rn
= extract32(insn
, 5, 5);
3006 rd
= extract32(insn
, 0, 5);
3007 bitsize
= sf
? 64 : 32;
3009 if (sf
!= n
|| ri
>= bitsize
|| si
>= bitsize
|| opc
> 2) {
3010 unallocated_encoding(s
);
3014 tcg_rd
= cpu_reg(s
, rd
);
3016 /* Suppress the zero-extend for !sf. Since RI and SI are constrained
3017 to be smaller than bitsize, we'll never reference data outside the
3018 low 32-bits anyway. */
3019 tcg_tmp
= read_cpu_reg(s
, rn
, 1);
3021 /* Recognize the common aliases. */
3022 if (opc
== 0) { /* SBFM */
3024 if (si
== 7) { /* SXTB */
3025 tcg_gen_ext8s_i64(tcg_rd
, tcg_tmp
);
3027 } else if (si
== 15) { /* SXTH */
3028 tcg_gen_ext16s_i64(tcg_rd
, tcg_tmp
);
3030 } else if (si
== 31) { /* SXTW */
3031 tcg_gen_ext32s_i64(tcg_rd
, tcg_tmp
);
3035 if (si
== 63 || (si
== 31 && ri
<= si
)) { /* ASR */
3037 tcg_gen_ext32s_i64(tcg_tmp
, tcg_tmp
);
3039 tcg_gen_sari_i64(tcg_rd
, tcg_tmp
, ri
);
3042 } else if (opc
== 2) { /* UBFM */
3043 if (ri
== 0) { /* UXTB, UXTH, plus non-canonical AND */
3044 tcg_gen_andi_i64(tcg_rd
, tcg_tmp
, bitmask64(si
+ 1));
3047 if (si
== 63 || (si
== 31 && ri
<= si
)) { /* LSR */
3049 tcg_gen_ext32u_i64(tcg_tmp
, tcg_tmp
);
3051 tcg_gen_shri_i64(tcg_rd
, tcg_tmp
, ri
);
3054 if (si
+ 1 == ri
&& si
!= bitsize
- 1) { /* LSL */
3055 int shift
= bitsize
- 1 - si
;
3056 tcg_gen_shli_i64(tcg_rd
, tcg_tmp
, shift
);
3061 if (opc
!= 1) { /* SBFM or UBFM */
3062 tcg_gen_movi_i64(tcg_rd
, 0);
3065 /* do the bit move operation */
3067 /* Wd<s-r:0> = Wn<s:r> */
3068 tcg_gen_shri_i64(tcg_tmp
, tcg_tmp
, ri
);
3070 len
= (si
- ri
) + 1;
3072 /* Wd<32+s-r,32-r> = Wn<s:0> */
3077 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_tmp
, pos
, len
);
3079 if (opc
== 0) { /* SBFM - sign extend the destination field */
3080 tcg_gen_shli_i64(tcg_rd
, tcg_rd
, 64 - (pos
+ len
));
3081 tcg_gen_sari_i64(tcg_rd
, tcg_rd
, 64 - (pos
+ len
));
3085 if (!sf
) { /* zero extend final result */
3086 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3091 * 31 30 29 28 23 22 21 20 16 15 10 9 5 4 0
3092 * +----+------+-------------+---+----+------+--------+------+------+
3093 * | sf | op21 | 1 0 0 1 1 1 | N | o0 | Rm | imms | Rn | Rd |
3094 * +----+------+-------------+---+----+------+--------+------+------+
3096 static void disas_extract(DisasContext
*s
, uint32_t insn
)
3098 unsigned int sf
, n
, rm
, imm
, rn
, rd
, bitsize
, op21
, op0
;
3100 sf
= extract32(insn
, 31, 1);
3101 n
= extract32(insn
, 22, 1);
3102 rm
= extract32(insn
, 16, 5);
3103 imm
= extract32(insn
, 10, 6);
3104 rn
= extract32(insn
, 5, 5);
3105 rd
= extract32(insn
, 0, 5);
3106 op21
= extract32(insn
, 29, 2);
3107 op0
= extract32(insn
, 21, 1);
3108 bitsize
= sf
? 64 : 32;
3110 if (sf
!= n
|| op21
|| op0
|| imm
>= bitsize
) {
3111 unallocated_encoding(s
);
3113 TCGv_i64 tcg_rd
, tcg_rm
, tcg_rn
;
3115 tcg_rd
= cpu_reg(s
, rd
);
3117 if (unlikely(imm
== 0)) {
3118 /* tcg shl_i32/shl_i64 is undefined for 32/64 bit shifts,
3119 * so an extract from bit 0 is a special case.
3122 tcg_gen_mov_i64(tcg_rd
, cpu_reg(s
, rm
));
3124 tcg_gen_ext32u_i64(tcg_rd
, cpu_reg(s
, rm
));
3126 } else if (rm
== rn
) { /* ROR */
3127 tcg_rm
= cpu_reg(s
, rm
);
3129 tcg_gen_rotri_i64(tcg_rd
, tcg_rm
, imm
);
3131 TCGv_i32 tmp
= tcg_temp_new_i32();
3132 tcg_gen_extrl_i64_i32(tmp
, tcg_rm
);
3133 tcg_gen_rotri_i32(tmp
, tmp
, imm
);
3134 tcg_gen_extu_i32_i64(tcg_rd
, tmp
);
3135 tcg_temp_free_i32(tmp
);
3138 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
3139 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
3140 tcg_gen_shri_i64(tcg_rm
, tcg_rm
, imm
);
3141 tcg_gen_shli_i64(tcg_rn
, tcg_rn
, bitsize
- imm
);
3142 tcg_gen_or_i64(tcg_rd
, tcg_rm
, tcg_rn
);
3144 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3150 /* C3.4 Data processing - immediate */
3151 static void disas_data_proc_imm(DisasContext
*s
, uint32_t insn
)
3153 switch (extract32(insn
, 23, 6)) {
3154 case 0x20: case 0x21: /* PC-rel. addressing */
3155 disas_pc_rel_adr(s
, insn
);
3157 case 0x22: case 0x23: /* Add/subtract (immediate) */
3158 disas_add_sub_imm(s
, insn
);
3160 case 0x24: /* Logical (immediate) */
3161 disas_logic_imm(s
, insn
);
3163 case 0x25: /* Move wide (immediate) */
3164 disas_movw_imm(s
, insn
);
3166 case 0x26: /* Bitfield */
3167 disas_bitfield(s
, insn
);
3169 case 0x27: /* Extract */
3170 disas_extract(s
, insn
);
3173 unallocated_encoding(s
);
3178 /* Shift a TCGv src by TCGv shift_amount, put result in dst.
3179 * Note that it is the caller's responsibility to ensure that the
3180 * shift amount is in range (ie 0..31 or 0..63) and provide the ARM
3181 * mandated semantics for out of range shifts.
3183 static void shift_reg(TCGv_i64 dst
, TCGv_i64 src
, int sf
,
3184 enum a64_shift_type shift_type
, TCGv_i64 shift_amount
)
3186 switch (shift_type
) {
3187 case A64_SHIFT_TYPE_LSL
:
3188 tcg_gen_shl_i64(dst
, src
, shift_amount
);
3190 case A64_SHIFT_TYPE_LSR
:
3191 tcg_gen_shr_i64(dst
, src
, shift_amount
);
3193 case A64_SHIFT_TYPE_ASR
:
3195 tcg_gen_ext32s_i64(dst
, src
);
3197 tcg_gen_sar_i64(dst
, sf
? src
: dst
, shift_amount
);
3199 case A64_SHIFT_TYPE_ROR
:
3201 tcg_gen_rotr_i64(dst
, src
, shift_amount
);
3204 t0
= tcg_temp_new_i32();
3205 t1
= tcg_temp_new_i32();
3206 tcg_gen_extrl_i64_i32(t0
, src
);
3207 tcg_gen_extrl_i64_i32(t1
, shift_amount
);
3208 tcg_gen_rotr_i32(t0
, t0
, t1
);
3209 tcg_gen_extu_i32_i64(dst
, t0
);
3210 tcg_temp_free_i32(t0
);
3211 tcg_temp_free_i32(t1
);
3215 assert(FALSE
); /* all shift types should be handled */
3219 if (!sf
) { /* zero extend final result */
3220 tcg_gen_ext32u_i64(dst
, dst
);
3224 /* Shift a TCGv src by immediate, put result in dst.
3225 * The shift amount must be in range (this should always be true as the
3226 * relevant instructions will UNDEF on bad shift immediates).
3228 static void shift_reg_imm(TCGv_i64 dst
, TCGv_i64 src
, int sf
,
3229 enum a64_shift_type shift_type
, unsigned int shift_i
)
3231 assert(shift_i
< (sf
? 64 : 32));
3234 tcg_gen_mov_i64(dst
, src
);
3236 TCGv_i64 shift_const
;
3238 shift_const
= tcg_const_i64(shift_i
);
3239 shift_reg(dst
, src
, sf
, shift_type
, shift_const
);
3240 tcg_temp_free_i64(shift_const
);
3244 /* C3.5.10 Logical (shifted register)
3245 * 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0
3246 * +----+-----+-----------+-------+---+------+--------+------+------+
3247 * | sf | opc | 0 1 0 1 0 | shift | N | Rm | imm6 | Rn | Rd |
3248 * +----+-----+-----------+-------+---+------+--------+------+------+
3250 static void disas_logic_reg(DisasContext
*s
, uint32_t insn
)
3252 TCGv_i64 tcg_rd
, tcg_rn
, tcg_rm
;
3253 unsigned int sf
, opc
, shift_type
, invert
, rm
, shift_amount
, rn
, rd
;
3255 sf
= extract32(insn
, 31, 1);
3256 opc
= extract32(insn
, 29, 2);
3257 shift_type
= extract32(insn
, 22, 2);
3258 invert
= extract32(insn
, 21, 1);
3259 rm
= extract32(insn
, 16, 5);
3260 shift_amount
= extract32(insn
, 10, 6);
3261 rn
= extract32(insn
, 5, 5);
3262 rd
= extract32(insn
, 0, 5);
3264 if (!sf
&& (shift_amount
& (1 << 5))) {
3265 unallocated_encoding(s
);
3269 tcg_rd
= cpu_reg(s
, rd
);
3271 if (opc
== 1 && shift_amount
== 0 && shift_type
== 0 && rn
== 31) {
3272 /* Unshifted ORR and ORN with WZR/XZR is the standard encoding for
3273 * register-register MOV and MVN, so it is worth special casing.
3275 tcg_rm
= cpu_reg(s
, rm
);
3277 tcg_gen_not_i64(tcg_rd
, tcg_rm
);
3279 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3283 tcg_gen_mov_i64(tcg_rd
, tcg_rm
);
3285 tcg_gen_ext32u_i64(tcg_rd
, tcg_rm
);
3291 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
3294 shift_reg_imm(tcg_rm
, tcg_rm
, sf
, shift_type
, shift_amount
);
3297 tcg_rn
= cpu_reg(s
, rn
);
3299 switch (opc
| (invert
<< 2)) {
3302 tcg_gen_and_i64(tcg_rd
, tcg_rn
, tcg_rm
);
3305 tcg_gen_or_i64(tcg_rd
, tcg_rn
, tcg_rm
);
3308 tcg_gen_xor_i64(tcg_rd
, tcg_rn
, tcg_rm
);
3312 tcg_gen_andc_i64(tcg_rd
, tcg_rn
, tcg_rm
);
3315 tcg_gen_orc_i64(tcg_rd
, tcg_rn
, tcg_rm
);
3318 tcg_gen_eqv_i64(tcg_rd
, tcg_rn
, tcg_rm
);
3326 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3330 gen_logic_CC(sf
, tcg_rd
);
3335 * C3.5.1 Add/subtract (extended register)
3337 * 31|30|29|28 24|23 22|21|20 16|15 13|12 10|9 5|4 0|
3338 * +--+--+--+-----------+-----+--+-------+------+------+----+----+
3339 * |sf|op| S| 0 1 0 1 1 | opt | 1| Rm |option| imm3 | Rn | Rd |
3340 * +--+--+--+-----------+-----+--+-------+------+------+----+----+
3342 * sf: 0 -> 32bit, 1 -> 64bit
3343 * op: 0 -> add , 1 -> sub
3346 * option: extension type (see DecodeRegExtend)
3347 * imm3: optional shift to Rm
3349 * Rd = Rn + LSL(extend(Rm), amount)
3351 static void disas_add_sub_ext_reg(DisasContext
*s
, uint32_t insn
)
3353 int rd
= extract32(insn
, 0, 5);
3354 int rn
= extract32(insn
, 5, 5);
3355 int imm3
= extract32(insn
, 10, 3);
3356 int option
= extract32(insn
, 13, 3);
3357 int rm
= extract32(insn
, 16, 5);
3358 bool setflags
= extract32(insn
, 29, 1);
3359 bool sub_op
= extract32(insn
, 30, 1);
3360 bool sf
= extract32(insn
, 31, 1);
3362 TCGv_i64 tcg_rm
, tcg_rn
; /* temps */
3364 TCGv_i64 tcg_result
;
3367 unallocated_encoding(s
);
3371 /* non-flag setting ops may use SP */
3373 tcg_rd
= cpu_reg_sp(s
, rd
);
3375 tcg_rd
= cpu_reg(s
, rd
);
3377 tcg_rn
= read_cpu_reg_sp(s
, rn
, sf
);
3379 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
3380 ext_and_shift_reg(tcg_rm
, tcg_rm
, option
, imm3
);
3382 tcg_result
= tcg_temp_new_i64();
3386 tcg_gen_sub_i64(tcg_result
, tcg_rn
, tcg_rm
);
3388 tcg_gen_add_i64(tcg_result
, tcg_rn
, tcg_rm
);
3392 gen_sub_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
3394 gen_add_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
3399 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
3401 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
3404 tcg_temp_free_i64(tcg_result
);
3408 * C3.5.2 Add/subtract (shifted register)
3410 * 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0
3411 * +--+--+--+-----------+-----+--+-------+---------+------+------+
3412 * |sf|op| S| 0 1 0 1 1 |shift| 0| Rm | imm6 | Rn | Rd |
3413 * +--+--+--+-----------+-----+--+-------+---------+------+------+
3415 * sf: 0 -> 32bit, 1 -> 64bit
3416 * op: 0 -> add , 1 -> sub
3418 * shift: 00 -> LSL, 01 -> LSR, 10 -> ASR, 11 -> RESERVED
3419 * imm6: Shift amount to apply to Rm before the add/sub
3421 static void disas_add_sub_reg(DisasContext
*s
, uint32_t insn
)
3423 int rd
= extract32(insn
, 0, 5);
3424 int rn
= extract32(insn
, 5, 5);
3425 int imm6
= extract32(insn
, 10, 6);
3426 int rm
= extract32(insn
, 16, 5);
3427 int shift_type
= extract32(insn
, 22, 2);
3428 bool setflags
= extract32(insn
, 29, 1);
3429 bool sub_op
= extract32(insn
, 30, 1);
3430 bool sf
= extract32(insn
, 31, 1);
3432 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
3433 TCGv_i64 tcg_rn
, tcg_rm
;
3434 TCGv_i64 tcg_result
;
3436 if ((shift_type
== 3) || (!sf
&& (imm6
> 31))) {
3437 unallocated_encoding(s
);
3441 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
3442 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
3444 shift_reg_imm(tcg_rm
, tcg_rm
, sf
, shift_type
, imm6
);
3446 tcg_result
= tcg_temp_new_i64();
3450 tcg_gen_sub_i64(tcg_result
, tcg_rn
, tcg_rm
);
3452 tcg_gen_add_i64(tcg_result
, tcg_rn
, tcg_rm
);
3456 gen_sub_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
3458 gen_add_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
3463 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
3465 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
3468 tcg_temp_free_i64(tcg_result
);
3471 /* C3.5.9 Data-processing (3 source)
3473 31 30 29 28 24 23 21 20 16 15 14 10 9 5 4 0
3474 +--+------+-----------+------+------+----+------+------+------+
3475 |sf| op54 | 1 1 0 1 1 | op31 | Rm | o0 | Ra | Rn | Rd |
3476 +--+------+-----------+------+------+----+------+------+------+
3479 static void disas_data_proc_3src(DisasContext
*s
, uint32_t insn
)
3481 int rd
= extract32(insn
, 0, 5);
3482 int rn
= extract32(insn
, 5, 5);
3483 int ra
= extract32(insn
, 10, 5);
3484 int rm
= extract32(insn
, 16, 5);
3485 int op_id
= (extract32(insn
, 29, 3) << 4) |
3486 (extract32(insn
, 21, 3) << 1) |
3487 extract32(insn
, 15, 1);
3488 bool sf
= extract32(insn
, 31, 1);
3489 bool is_sub
= extract32(op_id
, 0, 1);
3490 bool is_high
= extract32(op_id
, 2, 1);
3491 bool is_signed
= false;
3496 /* Note that op_id is sf:op54:op31:o0 so it includes the 32/64 size flag */
3498 case 0x42: /* SMADDL */
3499 case 0x43: /* SMSUBL */
3500 case 0x44: /* SMULH */
3503 case 0x0: /* MADD (32bit) */
3504 case 0x1: /* MSUB (32bit) */
3505 case 0x40: /* MADD (64bit) */
3506 case 0x41: /* MSUB (64bit) */
3507 case 0x4a: /* UMADDL */
3508 case 0x4b: /* UMSUBL */
3509 case 0x4c: /* UMULH */
3512 unallocated_encoding(s
);
3517 TCGv_i64 low_bits
= tcg_temp_new_i64(); /* low bits discarded */
3518 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
3519 TCGv_i64 tcg_rn
= cpu_reg(s
, rn
);
3520 TCGv_i64 tcg_rm
= cpu_reg(s
, rm
);
3523 tcg_gen_muls2_i64(low_bits
, tcg_rd
, tcg_rn
, tcg_rm
);
3525 tcg_gen_mulu2_i64(low_bits
, tcg_rd
, tcg_rn
, tcg_rm
);
3528 tcg_temp_free_i64(low_bits
);
3532 tcg_op1
= tcg_temp_new_i64();
3533 tcg_op2
= tcg_temp_new_i64();
3534 tcg_tmp
= tcg_temp_new_i64();
3537 tcg_gen_mov_i64(tcg_op1
, cpu_reg(s
, rn
));
3538 tcg_gen_mov_i64(tcg_op2
, cpu_reg(s
, rm
));
3541 tcg_gen_ext32s_i64(tcg_op1
, cpu_reg(s
, rn
));
3542 tcg_gen_ext32s_i64(tcg_op2
, cpu_reg(s
, rm
));
3544 tcg_gen_ext32u_i64(tcg_op1
, cpu_reg(s
, rn
));
3545 tcg_gen_ext32u_i64(tcg_op2
, cpu_reg(s
, rm
));
3549 if (ra
== 31 && !is_sub
) {
3550 /* Special-case MADD with rA == XZR; it is the standard MUL alias */
3551 tcg_gen_mul_i64(cpu_reg(s
, rd
), tcg_op1
, tcg_op2
);
3553 tcg_gen_mul_i64(tcg_tmp
, tcg_op1
, tcg_op2
);
3555 tcg_gen_sub_i64(cpu_reg(s
, rd
), cpu_reg(s
, ra
), tcg_tmp
);
3557 tcg_gen_add_i64(cpu_reg(s
, rd
), cpu_reg(s
, ra
), tcg_tmp
);
3562 tcg_gen_ext32u_i64(cpu_reg(s
, rd
), cpu_reg(s
, rd
));
3565 tcg_temp_free_i64(tcg_op1
);
3566 tcg_temp_free_i64(tcg_op2
);
3567 tcg_temp_free_i64(tcg_tmp
);
3570 /* C3.5.3 - Add/subtract (with carry)
3571 * 31 30 29 28 27 26 25 24 23 22 21 20 16 15 10 9 5 4 0
3572 * +--+--+--+------------------------+------+---------+------+-----+
3573 * |sf|op| S| 1 1 0 1 0 0 0 0 | rm | opcode2 | Rn | Rd |
3574 * +--+--+--+------------------------+------+---------+------+-----+
3578 static void disas_adc_sbc(DisasContext
*s
, uint32_t insn
)
3580 unsigned int sf
, op
, setflags
, rm
, rn
, rd
;
3581 TCGv_i64 tcg_y
, tcg_rn
, tcg_rd
;
3583 if (extract32(insn
, 10, 6) != 0) {
3584 unallocated_encoding(s
);
3588 sf
= extract32(insn
, 31, 1);
3589 op
= extract32(insn
, 30, 1);
3590 setflags
= extract32(insn
, 29, 1);
3591 rm
= extract32(insn
, 16, 5);
3592 rn
= extract32(insn
, 5, 5);
3593 rd
= extract32(insn
, 0, 5);
3595 tcg_rd
= cpu_reg(s
, rd
);
3596 tcg_rn
= cpu_reg(s
, rn
);
3599 tcg_y
= new_tmp_a64(s
);
3600 tcg_gen_not_i64(tcg_y
, cpu_reg(s
, rm
));
3602 tcg_y
= cpu_reg(s
, rm
);
3606 gen_adc_CC(sf
, tcg_rd
, tcg_rn
, tcg_y
);
3608 gen_adc(sf
, tcg_rd
, tcg_rn
, tcg_y
);
3612 /* C3.5.4 - C3.5.5 Conditional compare (immediate / register)
3613 * 31 30 29 28 27 26 25 24 23 22 21 20 16 15 12 11 10 9 5 4 3 0
3614 * +--+--+--+------------------------+--------+------+----+--+------+--+-----+
3615 * |sf|op| S| 1 1 0 1 0 0 1 0 |imm5/rm | cond |i/r |o2| Rn |o3|nzcv |
3616 * +--+--+--+------------------------+--------+------+----+--+------+--+-----+
3619 static void disas_cc(DisasContext
*s
, uint32_t insn
)
3621 unsigned int sf
, op
, y
, cond
, rn
, nzcv
, is_imm
;
3622 TCGv_i32 tcg_t0
, tcg_t1
, tcg_t2
;
3623 TCGv_i64 tcg_tmp
, tcg_y
, tcg_rn
;
3626 if (!extract32(insn
, 29, 1)) {
3627 unallocated_encoding(s
);
3630 if (insn
& (1 << 10 | 1 << 4)) {
3631 unallocated_encoding(s
);
3634 sf
= extract32(insn
, 31, 1);
3635 op
= extract32(insn
, 30, 1);
3636 is_imm
= extract32(insn
, 11, 1);
3637 y
= extract32(insn
, 16, 5); /* y = rm (reg) or imm5 (imm) */
3638 cond
= extract32(insn
, 12, 4);
3639 rn
= extract32(insn
, 5, 5);
3640 nzcv
= extract32(insn
, 0, 4);
3642 /* Set T0 = !COND. */
3643 tcg_t0
= tcg_temp_new_i32();
3644 arm_test_cc(&c
, cond
);
3645 tcg_gen_setcondi_i32(tcg_invert_cond(c
.cond
), tcg_t0
, c
.value
, 0);
3648 /* Load the arguments for the new comparison. */
3650 tcg_y
= new_tmp_a64(s
);
3651 tcg_gen_movi_i64(tcg_y
, y
);
3653 tcg_y
= cpu_reg(s
, y
);
3655 tcg_rn
= cpu_reg(s
, rn
);
3657 /* Set the flags for the new comparison. */
3658 tcg_tmp
= tcg_temp_new_i64();
3660 gen_sub_CC(sf
, tcg_tmp
, tcg_rn
, tcg_y
);
3662 gen_add_CC(sf
, tcg_tmp
, tcg_rn
, tcg_y
);
3664 tcg_temp_free_i64(tcg_tmp
);
3666 /* If COND was false, force the flags to #nzcv. Compute two masks
3667 * to help with this: T1 = (COND ? 0 : -1), T2 = (COND ? -1 : 0).
3668 * For tcg hosts that support ANDC, we can make do with just T1.
3669 * In either case, allow the tcg optimizer to delete any unused mask.
3671 tcg_t1
= tcg_temp_new_i32();
3672 tcg_t2
= tcg_temp_new_i32();
3673 tcg_gen_neg_i32(tcg_t1
, tcg_t0
);
3674 tcg_gen_subi_i32(tcg_t2
, tcg_t0
, 1);
3676 if (nzcv
& 8) { /* N */
3677 tcg_gen_or_i32(cpu_NF
, cpu_NF
, tcg_t1
);
3679 if (TCG_TARGET_HAS_andc_i32
) {
3680 tcg_gen_andc_i32(cpu_NF
, cpu_NF
, tcg_t1
);
3682 tcg_gen_and_i32(cpu_NF
, cpu_NF
, tcg_t2
);
3685 if (nzcv
& 4) { /* Z */
3686 if (TCG_TARGET_HAS_andc_i32
) {
3687 tcg_gen_andc_i32(cpu_ZF
, cpu_ZF
, tcg_t1
);
3689 tcg_gen_and_i32(cpu_ZF
, cpu_ZF
, tcg_t2
);
3692 tcg_gen_or_i32(cpu_ZF
, cpu_ZF
, tcg_t0
);
3694 if (nzcv
& 2) { /* C */
3695 tcg_gen_or_i32(cpu_CF
, cpu_CF
, tcg_t0
);
3697 if (TCG_TARGET_HAS_andc_i32
) {
3698 tcg_gen_andc_i32(cpu_CF
, cpu_CF
, tcg_t1
);
3700 tcg_gen_and_i32(cpu_CF
, cpu_CF
, tcg_t2
);
3703 if (nzcv
& 1) { /* V */
3704 tcg_gen_or_i32(cpu_VF
, cpu_VF
, tcg_t1
);
3706 if (TCG_TARGET_HAS_andc_i32
) {
3707 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tcg_t1
);
3709 tcg_gen_and_i32(cpu_VF
, cpu_VF
, tcg_t2
);
3712 tcg_temp_free_i32(tcg_t0
);
3713 tcg_temp_free_i32(tcg_t1
);
3714 tcg_temp_free_i32(tcg_t2
);
3717 /* C3.5.6 Conditional select
3718 * 31 30 29 28 21 20 16 15 12 11 10 9 5 4 0
3719 * +----+----+---+-----------------+------+------+-----+------+------+
3720 * | sf | op | S | 1 1 0 1 0 1 0 0 | Rm | cond | op2 | Rn | Rd |
3721 * +----+----+---+-----------------+------+------+-----+------+------+
3723 static void disas_cond_select(DisasContext
*s
, uint32_t insn
)
3725 unsigned int sf
, else_inv
, rm
, cond
, else_inc
, rn
, rd
;
3726 TCGv_i64 tcg_rd
, zero
;
3729 if (extract32(insn
, 29, 1) || extract32(insn
, 11, 1)) {
3730 /* S == 1 or op2<1> == 1 */
3731 unallocated_encoding(s
);
3734 sf
= extract32(insn
, 31, 1);
3735 else_inv
= extract32(insn
, 30, 1);
3736 rm
= extract32(insn
, 16, 5);
3737 cond
= extract32(insn
, 12, 4);
3738 else_inc
= extract32(insn
, 10, 1);
3739 rn
= extract32(insn
, 5, 5);
3740 rd
= extract32(insn
, 0, 5);
3742 tcg_rd
= cpu_reg(s
, rd
);
3744 a64_test_cc(&c
, cond
);
3745 zero
= tcg_const_i64(0);
3747 if (rn
== 31 && rm
== 31 && (else_inc
^ else_inv
)) {
3749 tcg_gen_setcond_i64(tcg_invert_cond(c
.cond
), tcg_rd
, c
.value
, zero
);
3751 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
3754 TCGv_i64 t_true
= cpu_reg(s
, rn
);
3755 TCGv_i64 t_false
= read_cpu_reg(s
, rm
, 1);
3756 if (else_inv
&& else_inc
) {
3757 tcg_gen_neg_i64(t_false
, t_false
);
3758 } else if (else_inv
) {
3759 tcg_gen_not_i64(t_false
, t_false
);
3760 } else if (else_inc
) {
3761 tcg_gen_addi_i64(t_false
, t_false
, 1);
3763 tcg_gen_movcond_i64(c
.cond
, tcg_rd
, c
.value
, zero
, t_true
, t_false
);
3766 tcg_temp_free_i64(zero
);
3770 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3774 static void handle_clz(DisasContext
*s
, unsigned int sf
,
3775 unsigned int rn
, unsigned int rd
)
3777 TCGv_i64 tcg_rd
, tcg_rn
;
3778 tcg_rd
= cpu_reg(s
, rd
);
3779 tcg_rn
= cpu_reg(s
, rn
);
3782 gen_helper_clz64(tcg_rd
, tcg_rn
);
3784 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
3785 tcg_gen_extrl_i64_i32(tcg_tmp32
, tcg_rn
);
3786 gen_helper_clz(tcg_tmp32
, tcg_tmp32
);
3787 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
3788 tcg_temp_free_i32(tcg_tmp32
);
3792 static void handle_cls(DisasContext
*s
, unsigned int sf
,
3793 unsigned int rn
, unsigned int rd
)
3795 TCGv_i64 tcg_rd
, tcg_rn
;
3796 tcg_rd
= cpu_reg(s
, rd
);
3797 tcg_rn
= cpu_reg(s
, rn
);
3800 gen_helper_cls64(tcg_rd
, tcg_rn
);
3802 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
3803 tcg_gen_extrl_i64_i32(tcg_tmp32
, tcg_rn
);
3804 gen_helper_cls32(tcg_tmp32
, tcg_tmp32
);
3805 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
3806 tcg_temp_free_i32(tcg_tmp32
);
3810 static void handle_rbit(DisasContext
*s
, unsigned int sf
,
3811 unsigned int rn
, unsigned int rd
)
3813 TCGv_i64 tcg_rd
, tcg_rn
;
3814 tcg_rd
= cpu_reg(s
, rd
);
3815 tcg_rn
= cpu_reg(s
, rn
);
3818 gen_helper_rbit64(tcg_rd
, tcg_rn
);
3820 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
3821 tcg_gen_extrl_i64_i32(tcg_tmp32
, tcg_rn
);
3822 gen_helper_rbit(tcg_tmp32
, tcg_tmp32
);
3823 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
3824 tcg_temp_free_i32(tcg_tmp32
);
3828 /* C5.6.149 REV with sf==1, opcode==3 ("REV64") */
3829 static void handle_rev64(DisasContext
*s
, unsigned int sf
,
3830 unsigned int rn
, unsigned int rd
)
3833 unallocated_encoding(s
);
3836 tcg_gen_bswap64_i64(cpu_reg(s
, rd
), cpu_reg(s
, rn
));
3839 /* C5.6.149 REV with sf==0, opcode==2
3840 * C5.6.151 REV32 (sf==1, opcode==2)
3842 static void handle_rev32(DisasContext
*s
, unsigned int sf
,
3843 unsigned int rn
, unsigned int rd
)
3845 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
3848 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
3849 TCGv_i64 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
3851 /* bswap32_i64 requires zero high word */
3852 tcg_gen_ext32u_i64(tcg_tmp
, tcg_rn
);
3853 tcg_gen_bswap32_i64(tcg_rd
, tcg_tmp
);
3854 tcg_gen_shri_i64(tcg_tmp
, tcg_rn
, 32);
3855 tcg_gen_bswap32_i64(tcg_tmp
, tcg_tmp
);
3856 tcg_gen_concat32_i64(tcg_rd
, tcg_rd
, tcg_tmp
);
3858 tcg_temp_free_i64(tcg_tmp
);
3860 tcg_gen_ext32u_i64(tcg_rd
, cpu_reg(s
, rn
));
3861 tcg_gen_bswap32_i64(tcg_rd
, tcg_rd
);
3865 /* C5.6.150 REV16 (opcode==1) */
3866 static void handle_rev16(DisasContext
*s
, unsigned int sf
,
3867 unsigned int rn
, unsigned int rd
)
3869 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
3870 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
3871 TCGv_i64 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
3873 tcg_gen_andi_i64(tcg_tmp
, tcg_rn
, 0xffff);
3874 tcg_gen_bswap16_i64(tcg_rd
, tcg_tmp
);
3876 tcg_gen_shri_i64(tcg_tmp
, tcg_rn
, 16);
3877 tcg_gen_andi_i64(tcg_tmp
, tcg_tmp
, 0xffff);
3878 tcg_gen_bswap16_i64(tcg_tmp
, tcg_tmp
);
3879 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_tmp
, 16, 16);
3882 tcg_gen_shri_i64(tcg_tmp
, tcg_rn
, 32);
3883 tcg_gen_andi_i64(tcg_tmp
, tcg_tmp
, 0xffff);
3884 tcg_gen_bswap16_i64(tcg_tmp
, tcg_tmp
);
3885 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_tmp
, 32, 16);
3887 tcg_gen_shri_i64(tcg_tmp
, tcg_rn
, 48);
3888 tcg_gen_bswap16_i64(tcg_tmp
, tcg_tmp
);
3889 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_tmp
, 48, 16);
3892 tcg_temp_free_i64(tcg_tmp
);
3895 /* C3.5.7 Data-processing (1 source)
3896 * 31 30 29 28 21 20 16 15 10 9 5 4 0
3897 * +----+---+---+-----------------+---------+--------+------+------+
3898 * | sf | 1 | S | 1 1 0 1 0 1 1 0 | opcode2 | opcode | Rn | Rd |
3899 * +----+---+---+-----------------+---------+--------+------+------+
3901 static void disas_data_proc_1src(DisasContext
*s
, uint32_t insn
)
3903 unsigned int sf
, opcode
, rn
, rd
;
3905 if (extract32(insn
, 29, 1) || extract32(insn
, 16, 5)) {
3906 unallocated_encoding(s
);
3910 sf
= extract32(insn
, 31, 1);
3911 opcode
= extract32(insn
, 10, 6);
3912 rn
= extract32(insn
, 5, 5);
3913 rd
= extract32(insn
, 0, 5);
3917 handle_rbit(s
, sf
, rn
, rd
);
3920 handle_rev16(s
, sf
, rn
, rd
);
3923 handle_rev32(s
, sf
, rn
, rd
);
3926 handle_rev64(s
, sf
, rn
, rd
);
3929 handle_clz(s
, sf
, rn
, rd
);
3932 handle_cls(s
, sf
, rn
, rd
);
3937 static void handle_div(DisasContext
*s
, bool is_signed
, unsigned int sf
,
3938 unsigned int rm
, unsigned int rn
, unsigned int rd
)
3940 TCGv_i64 tcg_n
, tcg_m
, tcg_rd
;
3941 tcg_rd
= cpu_reg(s
, rd
);
3943 if (!sf
&& is_signed
) {
3944 tcg_n
= new_tmp_a64(s
);
3945 tcg_m
= new_tmp_a64(s
);
3946 tcg_gen_ext32s_i64(tcg_n
, cpu_reg(s
, rn
));
3947 tcg_gen_ext32s_i64(tcg_m
, cpu_reg(s
, rm
));
3949 tcg_n
= read_cpu_reg(s
, rn
, sf
);
3950 tcg_m
= read_cpu_reg(s
, rm
, sf
);
3954 gen_helper_sdiv64(tcg_rd
, tcg_n
, tcg_m
);
3956 gen_helper_udiv64(tcg_rd
, tcg_n
, tcg_m
);
3959 if (!sf
) { /* zero extend final result */
3960 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3964 /* C5.6.115 LSLV, C5.6.118 LSRV, C5.6.17 ASRV, C5.6.154 RORV */
3965 static void handle_shift_reg(DisasContext
*s
,
3966 enum a64_shift_type shift_type
, unsigned int sf
,
3967 unsigned int rm
, unsigned int rn
, unsigned int rd
)
3969 TCGv_i64 tcg_shift
= tcg_temp_new_i64();
3970 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
3971 TCGv_i64 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
3973 tcg_gen_andi_i64(tcg_shift
, cpu_reg(s
, rm
), sf
? 63 : 31);
3974 shift_reg(tcg_rd
, tcg_rn
, sf
, shift_type
, tcg_shift
);
3975 tcg_temp_free_i64(tcg_shift
);
3978 /* CRC32[BHWX], CRC32C[BHWX] */
3979 static void handle_crc32(DisasContext
*s
,
3980 unsigned int sf
, unsigned int sz
, bool crc32c
,
3981 unsigned int rm
, unsigned int rn
, unsigned int rd
)
3983 TCGv_i64 tcg_acc
, tcg_val
;
3986 if (!arm_dc_feature(s
, ARM_FEATURE_CRC
)
3987 || (sf
== 1 && sz
!= 3)
3988 || (sf
== 0 && sz
== 3)) {
3989 unallocated_encoding(s
);
3994 tcg_val
= cpu_reg(s
, rm
);
4008 g_assert_not_reached();
4010 tcg_val
= new_tmp_a64(s
);
4011 tcg_gen_andi_i64(tcg_val
, cpu_reg(s
, rm
), mask
);
4014 tcg_acc
= cpu_reg(s
, rn
);
4015 tcg_bytes
= tcg_const_i32(1 << sz
);
4018 gen_helper_crc32c_64(cpu_reg(s
, rd
), tcg_acc
, tcg_val
, tcg_bytes
);
4020 gen_helper_crc32_64(cpu_reg(s
, rd
), tcg_acc
, tcg_val
, tcg_bytes
);
4023 tcg_temp_free_i32(tcg_bytes
);
4026 /* C3.5.8 Data-processing (2 source)
4027 * 31 30 29 28 21 20 16 15 10 9 5 4 0
4028 * +----+---+---+-----------------+------+--------+------+------+
4029 * | sf | 0 | S | 1 1 0 1 0 1 1 0 | Rm | opcode | Rn | Rd |
4030 * +----+---+---+-----------------+------+--------+------+------+
4032 static void disas_data_proc_2src(DisasContext
*s
, uint32_t insn
)
4034 unsigned int sf
, rm
, opcode
, rn
, rd
;
4035 sf
= extract32(insn
, 31, 1);
4036 rm
= extract32(insn
, 16, 5);
4037 opcode
= extract32(insn
, 10, 6);
4038 rn
= extract32(insn
, 5, 5);
4039 rd
= extract32(insn
, 0, 5);
4041 if (extract32(insn
, 29, 1)) {
4042 unallocated_encoding(s
);
4048 handle_div(s
, false, sf
, rm
, rn
, rd
);
4051 handle_div(s
, true, sf
, rm
, rn
, rd
);
4054 handle_shift_reg(s
, A64_SHIFT_TYPE_LSL
, sf
, rm
, rn
, rd
);
4057 handle_shift_reg(s
, A64_SHIFT_TYPE_LSR
, sf
, rm
, rn
, rd
);
4060 handle_shift_reg(s
, A64_SHIFT_TYPE_ASR
, sf
, rm
, rn
, rd
);
4063 handle_shift_reg(s
, A64_SHIFT_TYPE_ROR
, sf
, rm
, rn
, rd
);
4072 case 23: /* CRC32 */
4074 int sz
= extract32(opcode
, 0, 2);
4075 bool crc32c
= extract32(opcode
, 2, 1);
4076 handle_crc32(s
, sf
, sz
, crc32c
, rm
, rn
, rd
);
4080 unallocated_encoding(s
);
4085 /* C3.5 Data processing - register */
4086 static void disas_data_proc_reg(DisasContext
*s
, uint32_t insn
)
4088 switch (extract32(insn
, 24, 5)) {
4089 case 0x0a: /* Logical (shifted register) */
4090 disas_logic_reg(s
, insn
);
4092 case 0x0b: /* Add/subtract */
4093 if (insn
& (1 << 21)) { /* (extended register) */
4094 disas_add_sub_ext_reg(s
, insn
);
4096 disas_add_sub_reg(s
, insn
);
4099 case 0x1b: /* Data-processing (3 source) */
4100 disas_data_proc_3src(s
, insn
);
4103 switch (extract32(insn
, 21, 3)) {
4104 case 0x0: /* Add/subtract (with carry) */
4105 disas_adc_sbc(s
, insn
);
4107 case 0x2: /* Conditional compare */
4108 disas_cc(s
, insn
); /* both imm and reg forms */
4110 case 0x4: /* Conditional select */
4111 disas_cond_select(s
, insn
);
4113 case 0x6: /* Data-processing */
4114 if (insn
& (1 << 30)) { /* (1 source) */
4115 disas_data_proc_1src(s
, insn
);
4116 } else { /* (2 source) */
4117 disas_data_proc_2src(s
, insn
);
4121 unallocated_encoding(s
);
4126 unallocated_encoding(s
);
4131 static void handle_fp_compare(DisasContext
*s
, bool is_double
,
4132 unsigned int rn
, unsigned int rm
,
4133 bool cmp_with_zero
, bool signal_all_nans
)
4135 TCGv_i64 tcg_flags
= tcg_temp_new_i64();
4136 TCGv_ptr fpst
= get_fpstatus_ptr();
4139 TCGv_i64 tcg_vn
, tcg_vm
;
4141 tcg_vn
= read_fp_dreg(s
, rn
);
4142 if (cmp_with_zero
) {
4143 tcg_vm
= tcg_const_i64(0);
4145 tcg_vm
= read_fp_dreg(s
, rm
);
4147 if (signal_all_nans
) {
4148 gen_helper_vfp_cmped_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
4150 gen_helper_vfp_cmpd_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
4152 tcg_temp_free_i64(tcg_vn
);
4153 tcg_temp_free_i64(tcg_vm
);
4155 TCGv_i32 tcg_vn
, tcg_vm
;
4157 tcg_vn
= read_fp_sreg(s
, rn
);
4158 if (cmp_with_zero
) {
4159 tcg_vm
= tcg_const_i32(0);
4161 tcg_vm
= read_fp_sreg(s
, rm
);
4163 if (signal_all_nans
) {
4164 gen_helper_vfp_cmpes_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
4166 gen_helper_vfp_cmps_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
4168 tcg_temp_free_i32(tcg_vn
);
4169 tcg_temp_free_i32(tcg_vm
);
4172 tcg_temp_free_ptr(fpst
);
4174 gen_set_nzcv(tcg_flags
);
4176 tcg_temp_free_i64(tcg_flags
);
4179 /* C3.6.22 Floating point compare
4180 * 31 30 29 28 24 23 22 21 20 16 15 14 13 10 9 5 4 0
4181 * +---+---+---+-----------+------+---+------+-----+---------+------+-------+
4182 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | op | 1 0 0 0 | Rn | op2 |
4183 * +---+---+---+-----------+------+---+------+-----+---------+------+-------+
4185 static void disas_fp_compare(DisasContext
*s
, uint32_t insn
)
4187 unsigned int mos
, type
, rm
, op
, rn
, opc
, op2r
;
4189 mos
= extract32(insn
, 29, 3);
4190 type
= extract32(insn
, 22, 2); /* 0 = single, 1 = double */
4191 rm
= extract32(insn
, 16, 5);
4192 op
= extract32(insn
, 14, 2);
4193 rn
= extract32(insn
, 5, 5);
4194 opc
= extract32(insn
, 3, 2);
4195 op2r
= extract32(insn
, 0, 3);
4197 if (mos
|| op
|| op2r
|| type
> 1) {
4198 unallocated_encoding(s
);
4202 if (!fp_access_check(s
)) {
4206 handle_fp_compare(s
, type
, rn
, rm
, opc
& 1, opc
& 2);
4209 /* C3.6.23 Floating point conditional compare
4210 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 3 0
4211 * +---+---+---+-----------+------+---+------+------+-----+------+----+------+
4212 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | cond | 0 1 | Rn | op | nzcv |
4213 * +---+---+---+-----------+------+---+------+------+-----+------+----+------+
4215 static void disas_fp_ccomp(DisasContext
*s
, uint32_t insn
)
4217 unsigned int mos
, type
, rm
, cond
, rn
, op
, nzcv
;
4219 TCGLabel
*label_continue
= NULL
;
4221 mos
= extract32(insn
, 29, 3);
4222 type
= extract32(insn
, 22, 2); /* 0 = single, 1 = double */
4223 rm
= extract32(insn
, 16, 5);
4224 cond
= extract32(insn
, 12, 4);
4225 rn
= extract32(insn
, 5, 5);
4226 op
= extract32(insn
, 4, 1);
4227 nzcv
= extract32(insn
, 0, 4);
4229 if (mos
|| type
> 1) {
4230 unallocated_encoding(s
);
4234 if (!fp_access_check(s
)) {
4238 if (cond
< 0x0e) { /* not always */
4239 TCGLabel
*label_match
= gen_new_label();
4240 label_continue
= gen_new_label();
4241 arm_gen_test_cc(cond
, label_match
);
4243 tcg_flags
= tcg_const_i64(nzcv
<< 28);
4244 gen_set_nzcv(tcg_flags
);
4245 tcg_temp_free_i64(tcg_flags
);
4246 tcg_gen_br(label_continue
);
4247 gen_set_label(label_match
);
4250 handle_fp_compare(s
, type
, rn
, rm
, false, op
);
4253 gen_set_label(label_continue
);
4257 /* C3.6.24 Floating point conditional select
4258 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
4259 * +---+---+---+-----------+------+---+------+------+-----+------+------+
4260 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | cond | 1 1 | Rn | Rd |
4261 * +---+---+---+-----------+------+---+------+------+-----+------+------+
4263 static void disas_fp_csel(DisasContext
*s
, uint32_t insn
)
4265 unsigned int mos
, type
, rm
, cond
, rn
, rd
;
4266 TCGv_i64 t_true
, t_false
, t_zero
;
4269 mos
= extract32(insn
, 29, 3);
4270 type
= extract32(insn
, 22, 2); /* 0 = single, 1 = double */
4271 rm
= extract32(insn
, 16, 5);
4272 cond
= extract32(insn
, 12, 4);
4273 rn
= extract32(insn
, 5, 5);
4274 rd
= extract32(insn
, 0, 5);
4276 if (mos
|| type
> 1) {
4277 unallocated_encoding(s
);
4281 if (!fp_access_check(s
)) {
4285 /* Zero extend sreg inputs to 64 bits now. */
4286 t_true
= tcg_temp_new_i64();
4287 t_false
= tcg_temp_new_i64();
4288 read_vec_element(s
, t_true
, rn
, 0, type
? MO_64
: MO_32
);
4289 read_vec_element(s
, t_false
, rm
, 0, type
? MO_64
: MO_32
);
4291 a64_test_cc(&c
, cond
);
4292 t_zero
= tcg_const_i64(0);
4293 tcg_gen_movcond_i64(c
.cond
, t_true
, c
.value
, t_zero
, t_true
, t_false
);
4294 tcg_temp_free_i64(t_zero
);
4295 tcg_temp_free_i64(t_false
);
4298 /* Note that sregs write back zeros to the high bits,
4299 and we've already done the zero-extension. */
4300 write_fp_dreg(s
, rd
, t_true
);
4301 tcg_temp_free_i64(t_true
);
4304 /* C3.6.25 Floating-point data-processing (1 source) - single precision */
4305 static void handle_fp_1src_single(DisasContext
*s
, int opcode
, int rd
, int rn
)
4311 fpst
= get_fpstatus_ptr();
4312 tcg_op
= read_fp_sreg(s
, rn
);
4313 tcg_res
= tcg_temp_new_i32();
4316 case 0x0: /* FMOV */
4317 tcg_gen_mov_i32(tcg_res
, tcg_op
);
4319 case 0x1: /* FABS */
4320 gen_helper_vfp_abss(tcg_res
, tcg_op
);
4322 case 0x2: /* FNEG */
4323 gen_helper_vfp_negs(tcg_res
, tcg_op
);
4325 case 0x3: /* FSQRT */
4326 gen_helper_vfp_sqrts(tcg_res
, tcg_op
, cpu_env
);
4328 case 0x8: /* FRINTN */
4329 case 0x9: /* FRINTP */
4330 case 0xa: /* FRINTM */
4331 case 0xb: /* FRINTZ */
4332 case 0xc: /* FRINTA */
4334 TCGv_i32 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(opcode
& 7));
4336 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
4337 gen_helper_rints(tcg_res
, tcg_op
, fpst
);
4339 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
4340 tcg_temp_free_i32(tcg_rmode
);
4343 case 0xe: /* FRINTX */
4344 gen_helper_rints_exact(tcg_res
, tcg_op
, fpst
);
4346 case 0xf: /* FRINTI */
4347 gen_helper_rints(tcg_res
, tcg_op
, fpst
);
4353 write_fp_sreg(s
, rd
, tcg_res
);
4355 tcg_temp_free_ptr(fpst
);
4356 tcg_temp_free_i32(tcg_op
);
4357 tcg_temp_free_i32(tcg_res
);
4360 /* C3.6.25 Floating-point data-processing (1 source) - double precision */
4361 static void handle_fp_1src_double(DisasContext
*s
, int opcode
, int rd
, int rn
)
4367 fpst
= get_fpstatus_ptr();
4368 tcg_op
= read_fp_dreg(s
, rn
);
4369 tcg_res
= tcg_temp_new_i64();
4372 case 0x0: /* FMOV */
4373 tcg_gen_mov_i64(tcg_res
, tcg_op
);
4375 case 0x1: /* FABS */
4376 gen_helper_vfp_absd(tcg_res
, tcg_op
);
4378 case 0x2: /* FNEG */
4379 gen_helper_vfp_negd(tcg_res
, tcg_op
);
4381 case 0x3: /* FSQRT */
4382 gen_helper_vfp_sqrtd(tcg_res
, tcg_op
, cpu_env
);
4384 case 0x8: /* FRINTN */
4385 case 0x9: /* FRINTP */
4386 case 0xa: /* FRINTM */
4387 case 0xb: /* FRINTZ */
4388 case 0xc: /* FRINTA */
4390 TCGv_i32 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(opcode
& 7));
4392 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
4393 gen_helper_rintd(tcg_res
, tcg_op
, fpst
);
4395 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
4396 tcg_temp_free_i32(tcg_rmode
);
4399 case 0xe: /* FRINTX */
4400 gen_helper_rintd_exact(tcg_res
, tcg_op
, fpst
);
4402 case 0xf: /* FRINTI */
4403 gen_helper_rintd(tcg_res
, tcg_op
, fpst
);
4409 write_fp_dreg(s
, rd
, tcg_res
);
4411 tcg_temp_free_ptr(fpst
);
4412 tcg_temp_free_i64(tcg_op
);
4413 tcg_temp_free_i64(tcg_res
);
4416 static void handle_fp_fcvt(DisasContext
*s
, int opcode
,
4417 int rd
, int rn
, int dtype
, int ntype
)
4422 TCGv_i32 tcg_rn
= read_fp_sreg(s
, rn
);
4424 /* Single to double */
4425 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
4426 gen_helper_vfp_fcvtds(tcg_rd
, tcg_rn
, cpu_env
);
4427 write_fp_dreg(s
, rd
, tcg_rd
);
4428 tcg_temp_free_i64(tcg_rd
);
4430 /* Single to half */
4431 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
4432 gen_helper_vfp_fcvt_f32_to_f16(tcg_rd
, tcg_rn
, cpu_env
);
4433 /* write_fp_sreg is OK here because top half of tcg_rd is zero */
4434 write_fp_sreg(s
, rd
, tcg_rd
);
4435 tcg_temp_free_i32(tcg_rd
);
4437 tcg_temp_free_i32(tcg_rn
);
4442 TCGv_i64 tcg_rn
= read_fp_dreg(s
, rn
);
4443 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
4445 /* Double to single */
4446 gen_helper_vfp_fcvtsd(tcg_rd
, tcg_rn
, cpu_env
);
4448 /* Double to half */
4449 gen_helper_vfp_fcvt_f64_to_f16(tcg_rd
, tcg_rn
, cpu_env
);
4450 /* write_fp_sreg is OK here because top half of tcg_rd is zero */
4452 write_fp_sreg(s
, rd
, tcg_rd
);
4453 tcg_temp_free_i32(tcg_rd
);
4454 tcg_temp_free_i64(tcg_rn
);
4459 TCGv_i32 tcg_rn
= read_fp_sreg(s
, rn
);
4460 tcg_gen_ext16u_i32(tcg_rn
, tcg_rn
);
4462 /* Half to single */
4463 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
4464 gen_helper_vfp_fcvt_f16_to_f32(tcg_rd
, tcg_rn
, cpu_env
);
4465 write_fp_sreg(s
, rd
, tcg_rd
);
4466 tcg_temp_free_i32(tcg_rd
);
4468 /* Half to double */
4469 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
4470 gen_helper_vfp_fcvt_f16_to_f64(tcg_rd
, tcg_rn
, cpu_env
);
4471 write_fp_dreg(s
, rd
, tcg_rd
);
4472 tcg_temp_free_i64(tcg_rd
);
4474 tcg_temp_free_i32(tcg_rn
);
4482 /* C3.6.25 Floating point data-processing (1 source)
4483 * 31 30 29 28 24 23 22 21 20 15 14 10 9 5 4 0
4484 * +---+---+---+-----------+------+---+--------+-----------+------+------+
4485 * | M | 0 | S | 1 1 1 1 0 | type | 1 | opcode | 1 0 0 0 0 | Rn | Rd |
4486 * +---+---+---+-----------+------+---+--------+-----------+------+------+
4488 static void disas_fp_1src(DisasContext
*s
, uint32_t insn
)
4490 int type
= extract32(insn
, 22, 2);
4491 int opcode
= extract32(insn
, 15, 6);
4492 int rn
= extract32(insn
, 5, 5);
4493 int rd
= extract32(insn
, 0, 5);
4496 case 0x4: case 0x5: case 0x7:
4498 /* FCVT between half, single and double precision */
4499 int dtype
= extract32(opcode
, 0, 2);
4500 if (type
== 2 || dtype
== type
) {
4501 unallocated_encoding(s
);
4504 if (!fp_access_check(s
)) {
4508 handle_fp_fcvt(s
, opcode
, rd
, rn
, dtype
, type
);
4514 /* 32-to-32 and 64-to-64 ops */
4517 if (!fp_access_check(s
)) {
4521 handle_fp_1src_single(s
, opcode
, rd
, rn
);
4524 if (!fp_access_check(s
)) {
4528 handle_fp_1src_double(s
, opcode
, rd
, rn
);
4531 unallocated_encoding(s
);
4535 unallocated_encoding(s
);
4540 /* C3.6.26 Floating-point data-processing (2 source) - single precision */
4541 static void handle_fp_2src_single(DisasContext
*s
, int opcode
,
4542 int rd
, int rn
, int rm
)
4549 tcg_res
= tcg_temp_new_i32();
4550 fpst
= get_fpstatus_ptr();
4551 tcg_op1
= read_fp_sreg(s
, rn
);
4552 tcg_op2
= read_fp_sreg(s
, rm
);
4555 case 0x0: /* FMUL */
4556 gen_helper_vfp_muls(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4558 case 0x1: /* FDIV */
4559 gen_helper_vfp_divs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4561 case 0x2: /* FADD */
4562 gen_helper_vfp_adds(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4564 case 0x3: /* FSUB */
4565 gen_helper_vfp_subs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4567 case 0x4: /* FMAX */
4568 gen_helper_vfp_maxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4570 case 0x5: /* FMIN */
4571 gen_helper_vfp_mins(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4573 case 0x6: /* FMAXNM */
4574 gen_helper_vfp_maxnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4576 case 0x7: /* FMINNM */
4577 gen_helper_vfp_minnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4579 case 0x8: /* FNMUL */
4580 gen_helper_vfp_muls(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4581 gen_helper_vfp_negs(tcg_res
, tcg_res
);
4585 write_fp_sreg(s
, rd
, tcg_res
);
4587 tcg_temp_free_ptr(fpst
);
4588 tcg_temp_free_i32(tcg_op1
);
4589 tcg_temp_free_i32(tcg_op2
);
4590 tcg_temp_free_i32(tcg_res
);
4593 /* C3.6.26 Floating-point data-processing (2 source) - double precision */
4594 static void handle_fp_2src_double(DisasContext
*s
, int opcode
,
4595 int rd
, int rn
, int rm
)
4602 tcg_res
= tcg_temp_new_i64();
4603 fpst
= get_fpstatus_ptr();
4604 tcg_op1
= read_fp_dreg(s
, rn
);
4605 tcg_op2
= read_fp_dreg(s
, rm
);
4608 case 0x0: /* FMUL */
4609 gen_helper_vfp_muld(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4611 case 0x1: /* FDIV */
4612 gen_helper_vfp_divd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4614 case 0x2: /* FADD */
4615 gen_helper_vfp_addd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4617 case 0x3: /* FSUB */
4618 gen_helper_vfp_subd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4620 case 0x4: /* FMAX */
4621 gen_helper_vfp_maxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4623 case 0x5: /* FMIN */
4624 gen_helper_vfp_mind(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4626 case 0x6: /* FMAXNM */
4627 gen_helper_vfp_maxnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4629 case 0x7: /* FMINNM */
4630 gen_helper_vfp_minnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4632 case 0x8: /* FNMUL */
4633 gen_helper_vfp_muld(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4634 gen_helper_vfp_negd(tcg_res
, tcg_res
);
4638 write_fp_dreg(s
, rd
, tcg_res
);
4640 tcg_temp_free_ptr(fpst
);
4641 tcg_temp_free_i64(tcg_op1
);
4642 tcg_temp_free_i64(tcg_op2
);
4643 tcg_temp_free_i64(tcg_res
);
4646 /* C3.6.26 Floating point data-processing (2 source)
4647 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
4648 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
4649 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | opcode | 1 0 | Rn | Rd |
4650 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
4652 static void disas_fp_2src(DisasContext
*s
, uint32_t insn
)
4654 int type
= extract32(insn
, 22, 2);
4655 int rd
= extract32(insn
, 0, 5);
4656 int rn
= extract32(insn
, 5, 5);
4657 int rm
= extract32(insn
, 16, 5);
4658 int opcode
= extract32(insn
, 12, 4);
4661 unallocated_encoding(s
);
4667 if (!fp_access_check(s
)) {
4670 handle_fp_2src_single(s
, opcode
, rd
, rn
, rm
);
4673 if (!fp_access_check(s
)) {
4676 handle_fp_2src_double(s
, opcode
, rd
, rn
, rm
);
4679 unallocated_encoding(s
);
4683 /* C3.6.27 Floating-point data-processing (3 source) - single precision */
4684 static void handle_fp_3src_single(DisasContext
*s
, bool o0
, bool o1
,
4685 int rd
, int rn
, int rm
, int ra
)
4687 TCGv_i32 tcg_op1
, tcg_op2
, tcg_op3
;
4688 TCGv_i32 tcg_res
= tcg_temp_new_i32();
4689 TCGv_ptr fpst
= get_fpstatus_ptr();
4691 tcg_op1
= read_fp_sreg(s
, rn
);
4692 tcg_op2
= read_fp_sreg(s
, rm
);
4693 tcg_op3
= read_fp_sreg(s
, ra
);
4695 /* These are fused multiply-add, and must be done as one
4696 * floating point operation with no rounding between the
4697 * multiplication and addition steps.
4698 * NB that doing the negations here as separate steps is
4699 * correct : an input NaN should come out with its sign bit
4700 * flipped if it is a negated-input.
4703 gen_helper_vfp_negs(tcg_op3
, tcg_op3
);
4707 gen_helper_vfp_negs(tcg_op1
, tcg_op1
);
4710 gen_helper_vfp_muladds(tcg_res
, tcg_op1
, tcg_op2
, tcg_op3
, fpst
);
4712 write_fp_sreg(s
, rd
, tcg_res
);
4714 tcg_temp_free_ptr(fpst
);
4715 tcg_temp_free_i32(tcg_op1
);
4716 tcg_temp_free_i32(tcg_op2
);
4717 tcg_temp_free_i32(tcg_op3
);
4718 tcg_temp_free_i32(tcg_res
);
4721 /* C3.6.27 Floating-point data-processing (3 source) - double precision */
4722 static void handle_fp_3src_double(DisasContext
*s
, bool o0
, bool o1
,
4723 int rd
, int rn
, int rm
, int ra
)
4725 TCGv_i64 tcg_op1
, tcg_op2
, tcg_op3
;
4726 TCGv_i64 tcg_res
= tcg_temp_new_i64();
4727 TCGv_ptr fpst
= get_fpstatus_ptr();
4729 tcg_op1
= read_fp_dreg(s
, rn
);
4730 tcg_op2
= read_fp_dreg(s
, rm
);
4731 tcg_op3
= read_fp_dreg(s
, ra
);
4733 /* These are fused multiply-add, and must be done as one
4734 * floating point operation with no rounding between the
4735 * multiplication and addition steps.
4736 * NB that doing the negations here as separate steps is
4737 * correct : an input NaN should come out with its sign bit
4738 * flipped if it is a negated-input.
4741 gen_helper_vfp_negd(tcg_op3
, tcg_op3
);
4745 gen_helper_vfp_negd(tcg_op1
, tcg_op1
);
4748 gen_helper_vfp_muladdd(tcg_res
, tcg_op1
, tcg_op2
, tcg_op3
, fpst
);
4750 write_fp_dreg(s
, rd
, tcg_res
);
4752 tcg_temp_free_ptr(fpst
);
4753 tcg_temp_free_i64(tcg_op1
);
4754 tcg_temp_free_i64(tcg_op2
);
4755 tcg_temp_free_i64(tcg_op3
);
4756 tcg_temp_free_i64(tcg_res
);
4759 /* C3.6.27 Floating point data-processing (3 source)
4760 * 31 30 29 28 24 23 22 21 20 16 15 14 10 9 5 4 0
4761 * +---+---+---+-----------+------+----+------+----+------+------+------+
4762 * | M | 0 | S | 1 1 1 1 1 | type | o1 | Rm | o0 | Ra | Rn | Rd |
4763 * +---+---+---+-----------+------+----+------+----+------+------+------+
4765 static void disas_fp_3src(DisasContext
*s
, uint32_t insn
)
4767 int type
= extract32(insn
, 22, 2);
4768 int rd
= extract32(insn
, 0, 5);
4769 int rn
= extract32(insn
, 5, 5);
4770 int ra
= extract32(insn
, 10, 5);
4771 int rm
= extract32(insn
, 16, 5);
4772 bool o0
= extract32(insn
, 15, 1);
4773 bool o1
= extract32(insn
, 21, 1);
4777 if (!fp_access_check(s
)) {
4780 handle_fp_3src_single(s
, o0
, o1
, rd
, rn
, rm
, ra
);
4783 if (!fp_access_check(s
)) {
4786 handle_fp_3src_double(s
, o0
, o1
, rd
, rn
, rm
, ra
);
4789 unallocated_encoding(s
);
4793 /* C3.6.28 Floating point immediate
4794 * 31 30 29 28 24 23 22 21 20 13 12 10 9 5 4 0
4795 * +---+---+---+-----------+------+---+------------+-------+------+------+
4796 * | M | 0 | S | 1 1 1 1 0 | type | 1 | imm8 | 1 0 0 | imm5 | Rd |
4797 * +---+---+---+-----------+------+---+------------+-------+------+------+
4799 static void disas_fp_imm(DisasContext
*s
, uint32_t insn
)
4801 int rd
= extract32(insn
, 0, 5);
4802 int imm8
= extract32(insn
, 13, 8);
4803 int is_double
= extract32(insn
, 22, 2);
4807 if (is_double
> 1) {
4808 unallocated_encoding(s
);
4812 if (!fp_access_check(s
)) {
4816 /* The imm8 encodes the sign bit, enough bits to represent
4817 * an exponent in the range 01....1xx to 10....0xx,
4818 * and the most significant 4 bits of the mantissa; see
4819 * VFPExpandImm() in the v8 ARM ARM.
4822 imm
= (extract32(imm8
, 7, 1) ? 0x8000 : 0) |
4823 (extract32(imm8
, 6, 1) ? 0x3fc0 : 0x4000) |
4824 extract32(imm8
, 0, 6);
4827 imm
= (extract32(imm8
, 7, 1) ? 0x8000 : 0) |
4828 (extract32(imm8
, 6, 1) ? 0x3e00 : 0x4000) |
4829 (extract32(imm8
, 0, 6) << 3);
4833 tcg_res
= tcg_const_i64(imm
);
4834 write_fp_dreg(s
, rd
, tcg_res
);
4835 tcg_temp_free_i64(tcg_res
);
4838 /* Handle floating point <=> fixed point conversions. Note that we can
4839 * also deal with fp <=> integer conversions as a special case (scale == 64)
4840 * OPTME: consider handling that special case specially or at least skipping
4841 * the call to scalbn in the helpers for zero shifts.
4843 static void handle_fpfpcvt(DisasContext
*s
, int rd
, int rn
, int opcode
,
4844 bool itof
, int rmode
, int scale
, int sf
, int type
)
4846 bool is_signed
= !(opcode
& 1);
4847 bool is_double
= type
;
4848 TCGv_ptr tcg_fpstatus
;
4851 tcg_fpstatus
= get_fpstatus_ptr();
4853 tcg_shift
= tcg_const_i32(64 - scale
);
4856 TCGv_i64 tcg_int
= cpu_reg(s
, rn
);
4858 TCGv_i64 tcg_extend
= new_tmp_a64(s
);
4861 tcg_gen_ext32s_i64(tcg_extend
, tcg_int
);
4863 tcg_gen_ext32u_i64(tcg_extend
, tcg_int
);
4866 tcg_int
= tcg_extend
;
4870 TCGv_i64 tcg_double
= tcg_temp_new_i64();
4872 gen_helper_vfp_sqtod(tcg_double
, tcg_int
,
4873 tcg_shift
, tcg_fpstatus
);
4875 gen_helper_vfp_uqtod(tcg_double
, tcg_int
,
4876 tcg_shift
, tcg_fpstatus
);
4878 write_fp_dreg(s
, rd
, tcg_double
);
4879 tcg_temp_free_i64(tcg_double
);
4881 TCGv_i32 tcg_single
= tcg_temp_new_i32();
4883 gen_helper_vfp_sqtos(tcg_single
, tcg_int
,
4884 tcg_shift
, tcg_fpstatus
);
4886 gen_helper_vfp_uqtos(tcg_single
, tcg_int
,
4887 tcg_shift
, tcg_fpstatus
);
4889 write_fp_sreg(s
, rd
, tcg_single
);
4890 tcg_temp_free_i32(tcg_single
);
4893 TCGv_i64 tcg_int
= cpu_reg(s
, rd
);
4896 if (extract32(opcode
, 2, 1)) {
4897 /* There are too many rounding modes to all fit into rmode,
4898 * so FCVTA[US] is a special case.
4900 rmode
= FPROUNDING_TIEAWAY
;
4903 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
4905 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
4908 TCGv_i64 tcg_double
= read_fp_dreg(s
, rn
);
4911 gen_helper_vfp_tosld(tcg_int
, tcg_double
,
4912 tcg_shift
, tcg_fpstatus
);
4914 gen_helper_vfp_tosqd(tcg_int
, tcg_double
,
4915 tcg_shift
, tcg_fpstatus
);
4919 gen_helper_vfp_tould(tcg_int
, tcg_double
,
4920 tcg_shift
, tcg_fpstatus
);
4922 gen_helper_vfp_touqd(tcg_int
, tcg_double
,
4923 tcg_shift
, tcg_fpstatus
);
4926 tcg_temp_free_i64(tcg_double
);
4928 TCGv_i32 tcg_single
= read_fp_sreg(s
, rn
);
4931 gen_helper_vfp_tosqs(tcg_int
, tcg_single
,
4932 tcg_shift
, tcg_fpstatus
);
4934 gen_helper_vfp_touqs(tcg_int
, tcg_single
,
4935 tcg_shift
, tcg_fpstatus
);
4938 TCGv_i32 tcg_dest
= tcg_temp_new_i32();
4940 gen_helper_vfp_tosls(tcg_dest
, tcg_single
,
4941 tcg_shift
, tcg_fpstatus
);
4943 gen_helper_vfp_touls(tcg_dest
, tcg_single
,
4944 tcg_shift
, tcg_fpstatus
);
4946 tcg_gen_extu_i32_i64(tcg_int
, tcg_dest
);
4947 tcg_temp_free_i32(tcg_dest
);
4949 tcg_temp_free_i32(tcg_single
);
4952 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
4953 tcg_temp_free_i32(tcg_rmode
);
4956 tcg_gen_ext32u_i64(tcg_int
, tcg_int
);
4960 tcg_temp_free_ptr(tcg_fpstatus
);
4961 tcg_temp_free_i32(tcg_shift
);
4964 /* C3.6.29 Floating point <-> fixed point conversions
4965 * 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 0
4966 * +----+---+---+-----------+------+---+-------+--------+-------+------+------+
4967 * | sf | 0 | S | 1 1 1 1 0 | type | 0 | rmode | opcode | scale | Rn | Rd |
4968 * +----+---+---+-----------+------+---+-------+--------+-------+------+------+
4970 static void disas_fp_fixed_conv(DisasContext
*s
, uint32_t insn
)
4972 int rd
= extract32(insn
, 0, 5);
4973 int rn
= extract32(insn
, 5, 5);
4974 int scale
= extract32(insn
, 10, 6);
4975 int opcode
= extract32(insn
, 16, 3);
4976 int rmode
= extract32(insn
, 19, 2);
4977 int type
= extract32(insn
, 22, 2);
4978 bool sbit
= extract32(insn
, 29, 1);
4979 bool sf
= extract32(insn
, 31, 1);
4982 if (sbit
|| (type
> 1)
4983 || (!sf
&& scale
< 32)) {
4984 unallocated_encoding(s
);
4988 switch ((rmode
<< 3) | opcode
) {
4989 case 0x2: /* SCVTF */
4990 case 0x3: /* UCVTF */
4993 case 0x18: /* FCVTZS */
4994 case 0x19: /* FCVTZU */
4998 unallocated_encoding(s
);
5002 if (!fp_access_check(s
)) {
5006 handle_fpfpcvt(s
, rd
, rn
, opcode
, itof
, FPROUNDING_ZERO
, scale
, sf
, type
);
5009 static void handle_fmov(DisasContext
*s
, int rd
, int rn
, int type
, bool itof
)
5011 /* FMOV: gpr to or from float, double, or top half of quad fp reg,
5012 * without conversion.
5016 TCGv_i64 tcg_rn
= cpu_reg(s
, rn
);
5022 TCGv_i64 tmp
= tcg_temp_new_i64();
5023 tcg_gen_ext32u_i64(tmp
, tcg_rn
);
5024 tcg_gen_st_i64(tmp
, cpu_env
, fp_reg_offset(s
, rd
, MO_64
));
5025 tcg_gen_movi_i64(tmp
, 0);
5026 tcg_gen_st_i64(tmp
, cpu_env
, fp_reg_hi_offset(s
, rd
));
5027 tcg_temp_free_i64(tmp
);
5033 TCGv_i64 tmp
= tcg_const_i64(0);
5034 tcg_gen_st_i64(tcg_rn
, cpu_env
, fp_reg_offset(s
, rd
, MO_64
));
5035 tcg_gen_st_i64(tmp
, cpu_env
, fp_reg_hi_offset(s
, rd
));
5036 tcg_temp_free_i64(tmp
);
5040 /* 64 bit to top half. */
5041 tcg_gen_st_i64(tcg_rn
, cpu_env
, fp_reg_hi_offset(s
, rd
));
5045 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
5050 tcg_gen_ld32u_i64(tcg_rd
, cpu_env
, fp_reg_offset(s
, rn
, MO_32
));
5054 tcg_gen_ld_i64(tcg_rd
, cpu_env
, fp_reg_offset(s
, rn
, MO_64
));
5057 /* 64 bits from top half */
5058 tcg_gen_ld_i64(tcg_rd
, cpu_env
, fp_reg_hi_offset(s
, rn
));
5064 /* C3.6.30 Floating point <-> integer conversions
5065 * 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 0
5066 * +----+---+---+-----------+------+---+-------+-----+-------------+----+----+
5067 * | sf | 0 | S | 1 1 1 1 0 | type | 1 | rmode | opc | 0 0 0 0 0 0 | Rn | Rd |
5068 * +----+---+---+-----------+------+---+-------+-----+-------------+----+----+
5070 static void disas_fp_int_conv(DisasContext
*s
, uint32_t insn
)
5072 int rd
= extract32(insn
, 0, 5);
5073 int rn
= extract32(insn
, 5, 5);
5074 int opcode
= extract32(insn
, 16, 3);
5075 int rmode
= extract32(insn
, 19, 2);
5076 int type
= extract32(insn
, 22, 2);
5077 bool sbit
= extract32(insn
, 29, 1);
5078 bool sf
= extract32(insn
, 31, 1);
5081 unallocated_encoding(s
);
5087 bool itof
= opcode
& 1;
5090 unallocated_encoding(s
);
5094 switch (sf
<< 3 | type
<< 1 | rmode
) {
5095 case 0x0: /* 32 bit */
5096 case 0xa: /* 64 bit */
5097 case 0xd: /* 64 bit to top half of quad */
5100 /* all other sf/type/rmode combinations are invalid */
5101 unallocated_encoding(s
);
5105 if (!fp_access_check(s
)) {
5108 handle_fmov(s
, rd
, rn
, type
, itof
);
5110 /* actual FP conversions */
5111 bool itof
= extract32(opcode
, 1, 1);
5113 if (type
> 1 || (rmode
!= 0 && opcode
> 1)) {
5114 unallocated_encoding(s
);
5118 if (!fp_access_check(s
)) {
5121 handle_fpfpcvt(s
, rd
, rn
, opcode
, itof
, rmode
, 64, sf
, type
);
5125 /* FP-specific subcases of table C3-6 (SIMD and FP data processing)
5126 * 31 30 29 28 25 24 0
5127 * +---+---+---+---------+-----------------------------+
5128 * | | 0 | | 1 1 1 1 | |
5129 * +---+---+---+---------+-----------------------------+
5131 static void disas_data_proc_fp(DisasContext
*s
, uint32_t insn
)
5133 if (extract32(insn
, 24, 1)) {
5134 /* Floating point data-processing (3 source) */
5135 disas_fp_3src(s
, insn
);
5136 } else if (extract32(insn
, 21, 1) == 0) {
5137 /* Floating point to fixed point conversions */
5138 disas_fp_fixed_conv(s
, insn
);
5140 switch (extract32(insn
, 10, 2)) {
5142 /* Floating point conditional compare */
5143 disas_fp_ccomp(s
, insn
);
5146 /* Floating point data-processing (2 source) */
5147 disas_fp_2src(s
, insn
);
5150 /* Floating point conditional select */
5151 disas_fp_csel(s
, insn
);
5154 switch (ctz32(extract32(insn
, 12, 4))) {
5155 case 0: /* [15:12] == xxx1 */
5156 /* Floating point immediate */
5157 disas_fp_imm(s
, insn
);
5159 case 1: /* [15:12] == xx10 */
5160 /* Floating point compare */
5161 disas_fp_compare(s
, insn
);
5163 case 2: /* [15:12] == x100 */
5164 /* Floating point data-processing (1 source) */
5165 disas_fp_1src(s
, insn
);
5167 case 3: /* [15:12] == 1000 */
5168 unallocated_encoding(s
);
5170 default: /* [15:12] == 0000 */
5171 /* Floating point <-> integer conversions */
5172 disas_fp_int_conv(s
, insn
);
5180 static void do_ext64(DisasContext
*s
, TCGv_i64 tcg_left
, TCGv_i64 tcg_right
,
5183 /* Extract 64 bits from the middle of two concatenated 64 bit
5184 * vector register slices left:right. The extracted bits start
5185 * at 'pos' bits into the right (least significant) side.
5186 * We return the result in tcg_right, and guarantee not to
5189 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
5190 assert(pos
> 0 && pos
< 64);
5192 tcg_gen_shri_i64(tcg_right
, tcg_right
, pos
);
5193 tcg_gen_shli_i64(tcg_tmp
, tcg_left
, 64 - pos
);
5194 tcg_gen_or_i64(tcg_right
, tcg_right
, tcg_tmp
);
5196 tcg_temp_free_i64(tcg_tmp
);
5200 * 31 30 29 24 23 22 21 20 16 15 14 11 10 9 5 4 0
5201 * +---+---+-------------+-----+---+------+---+------+---+------+------+
5202 * | 0 | Q | 1 0 1 1 1 0 | op2 | 0 | Rm | 0 | imm4 | 0 | Rn | Rd |
5203 * +---+---+-------------+-----+---+------+---+------+---+------+------+
5205 static void disas_simd_ext(DisasContext
*s
, uint32_t insn
)
5207 int is_q
= extract32(insn
, 30, 1);
5208 int op2
= extract32(insn
, 22, 2);
5209 int imm4
= extract32(insn
, 11, 4);
5210 int rm
= extract32(insn
, 16, 5);
5211 int rn
= extract32(insn
, 5, 5);
5212 int rd
= extract32(insn
, 0, 5);
5213 int pos
= imm4
<< 3;
5214 TCGv_i64 tcg_resl
, tcg_resh
;
5216 if (op2
!= 0 || (!is_q
&& extract32(imm4
, 3, 1))) {
5217 unallocated_encoding(s
);
5221 if (!fp_access_check(s
)) {
5225 tcg_resh
= tcg_temp_new_i64();
5226 tcg_resl
= tcg_temp_new_i64();
5228 /* Vd gets bits starting at pos bits into Vm:Vn. This is
5229 * either extracting 128 bits from a 128:128 concatenation, or
5230 * extracting 64 bits from a 64:64 concatenation.
5233 read_vec_element(s
, tcg_resl
, rn
, 0, MO_64
);
5235 read_vec_element(s
, tcg_resh
, rm
, 0, MO_64
);
5236 do_ext64(s
, tcg_resh
, tcg_resl
, pos
);
5238 tcg_gen_movi_i64(tcg_resh
, 0);
5245 EltPosns eltposns
[] = { {rn
, 0}, {rn
, 1}, {rm
, 0}, {rm
, 1} };
5246 EltPosns
*elt
= eltposns
;
5253 read_vec_element(s
, tcg_resl
, elt
->reg
, elt
->elt
, MO_64
);
5255 read_vec_element(s
, tcg_resh
, elt
->reg
, elt
->elt
, MO_64
);
5258 do_ext64(s
, tcg_resh
, tcg_resl
, pos
);
5259 tcg_hh
= tcg_temp_new_i64();
5260 read_vec_element(s
, tcg_hh
, elt
->reg
, elt
->elt
, MO_64
);
5261 do_ext64(s
, tcg_hh
, tcg_resh
, pos
);
5262 tcg_temp_free_i64(tcg_hh
);
5266 write_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
5267 tcg_temp_free_i64(tcg_resl
);
5268 write_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
5269 tcg_temp_free_i64(tcg_resh
);
5273 * 31 30 29 24 23 22 21 20 16 15 14 13 12 11 10 9 5 4 0
5274 * +---+---+-------------+-----+---+------+---+-----+----+-----+------+------+
5275 * | 0 | Q | 0 0 1 1 1 0 | op2 | 0 | Rm | 0 | len | op | 0 0 | Rn | Rd |
5276 * +---+---+-------------+-----+---+------+---+-----+----+-----+------+------+
5278 static void disas_simd_tb(DisasContext
*s
, uint32_t insn
)
5280 int op2
= extract32(insn
, 22, 2);
5281 int is_q
= extract32(insn
, 30, 1);
5282 int rm
= extract32(insn
, 16, 5);
5283 int rn
= extract32(insn
, 5, 5);
5284 int rd
= extract32(insn
, 0, 5);
5285 int is_tblx
= extract32(insn
, 12, 1);
5286 int len
= extract32(insn
, 13, 2);
5287 TCGv_i64 tcg_resl
, tcg_resh
, tcg_idx
;
5288 TCGv_i32 tcg_regno
, tcg_numregs
;
5291 unallocated_encoding(s
);
5295 if (!fp_access_check(s
)) {
5299 /* This does a table lookup: for every byte element in the input
5300 * we index into a table formed from up to four vector registers,
5301 * and then the output is the result of the lookups. Our helper
5302 * function does the lookup operation for a single 64 bit part of
5305 tcg_resl
= tcg_temp_new_i64();
5306 tcg_resh
= tcg_temp_new_i64();
5309 read_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
5311 tcg_gen_movi_i64(tcg_resl
, 0);
5313 if (is_tblx
&& is_q
) {
5314 read_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
5316 tcg_gen_movi_i64(tcg_resh
, 0);
5319 tcg_idx
= tcg_temp_new_i64();
5320 tcg_regno
= tcg_const_i32(rn
);
5321 tcg_numregs
= tcg_const_i32(len
+ 1);
5322 read_vec_element(s
, tcg_idx
, rm
, 0, MO_64
);
5323 gen_helper_simd_tbl(tcg_resl
, cpu_env
, tcg_resl
, tcg_idx
,
5324 tcg_regno
, tcg_numregs
);
5326 read_vec_element(s
, tcg_idx
, rm
, 1, MO_64
);
5327 gen_helper_simd_tbl(tcg_resh
, cpu_env
, tcg_resh
, tcg_idx
,
5328 tcg_regno
, tcg_numregs
);
5330 tcg_temp_free_i64(tcg_idx
);
5331 tcg_temp_free_i32(tcg_regno
);
5332 tcg_temp_free_i32(tcg_numregs
);
5334 write_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
5335 tcg_temp_free_i64(tcg_resl
);
5336 write_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
5337 tcg_temp_free_i64(tcg_resh
);
5340 /* C3.6.3 ZIP/UZP/TRN
5341 * 31 30 29 24 23 22 21 20 16 15 14 12 11 10 9 5 4 0
5342 * +---+---+-------------+------+---+------+---+------------------+------+
5343 * | 0 | Q | 0 0 1 1 1 0 | size | 0 | Rm | 0 | opc | 1 0 | Rn | Rd |
5344 * +---+---+-------------+------+---+------+---+------------------+------+
5346 static void disas_simd_zip_trn(DisasContext
*s
, uint32_t insn
)
5348 int rd
= extract32(insn
, 0, 5);
5349 int rn
= extract32(insn
, 5, 5);
5350 int rm
= extract32(insn
, 16, 5);
5351 int size
= extract32(insn
, 22, 2);
5352 /* opc field bits [1:0] indicate ZIP/UZP/TRN;
5353 * bit 2 indicates 1 vs 2 variant of the insn.
5355 int opcode
= extract32(insn
, 12, 2);
5356 bool part
= extract32(insn
, 14, 1);
5357 bool is_q
= extract32(insn
, 30, 1);
5358 int esize
= 8 << size
;
5360 int datasize
= is_q
? 128 : 64;
5361 int elements
= datasize
/ esize
;
5362 TCGv_i64 tcg_res
, tcg_resl
, tcg_resh
;
5364 if (opcode
== 0 || (size
== 3 && !is_q
)) {
5365 unallocated_encoding(s
);
5369 if (!fp_access_check(s
)) {
5373 tcg_resl
= tcg_const_i64(0);
5374 tcg_resh
= tcg_const_i64(0);
5375 tcg_res
= tcg_temp_new_i64();
5377 for (i
= 0; i
< elements
; i
++) {
5379 case 1: /* UZP1/2 */
5381 int midpoint
= elements
/ 2;
5383 read_vec_element(s
, tcg_res
, rn
, 2 * i
+ part
, size
);
5385 read_vec_element(s
, tcg_res
, rm
,
5386 2 * (i
- midpoint
) + part
, size
);
5390 case 2: /* TRN1/2 */
5392 read_vec_element(s
, tcg_res
, rm
, (i
& ~1) + part
, size
);
5394 read_vec_element(s
, tcg_res
, rn
, (i
& ~1) + part
, size
);
5397 case 3: /* ZIP1/2 */
5399 int base
= part
* elements
/ 2;
5401 read_vec_element(s
, tcg_res
, rm
, base
+ (i
>> 1), size
);
5403 read_vec_element(s
, tcg_res
, rn
, base
+ (i
>> 1), size
);
5408 g_assert_not_reached();
5413 tcg_gen_shli_i64(tcg_res
, tcg_res
, ofs
);
5414 tcg_gen_or_i64(tcg_resl
, tcg_resl
, tcg_res
);
5416 tcg_gen_shli_i64(tcg_res
, tcg_res
, ofs
- 64);
5417 tcg_gen_or_i64(tcg_resh
, tcg_resh
, tcg_res
);
5421 tcg_temp_free_i64(tcg_res
);
5423 write_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
5424 tcg_temp_free_i64(tcg_resl
);
5425 write_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
5426 tcg_temp_free_i64(tcg_resh
);
5429 static void do_minmaxop(DisasContext
*s
, TCGv_i32 tcg_elt1
, TCGv_i32 tcg_elt2
,
5430 int opc
, bool is_min
, TCGv_ptr fpst
)
5432 /* Helper function for disas_simd_across_lanes: do a single precision
5433 * min/max operation on the specified two inputs,
5434 * and return the result in tcg_elt1.
5438 gen_helper_vfp_minnums(tcg_elt1
, tcg_elt1
, tcg_elt2
, fpst
);
5440 gen_helper_vfp_maxnums(tcg_elt1
, tcg_elt1
, tcg_elt2
, fpst
);
5445 gen_helper_vfp_mins(tcg_elt1
, tcg_elt1
, tcg_elt2
, fpst
);
5447 gen_helper_vfp_maxs(tcg_elt1
, tcg_elt1
, tcg_elt2
, fpst
);
5452 /* C3.6.4 AdvSIMD across lanes
5453 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
5454 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
5455 * | 0 | Q | U | 0 1 1 1 0 | size | 1 1 0 0 0 | opcode | 1 0 | Rn | Rd |
5456 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
5458 static void disas_simd_across_lanes(DisasContext
*s
, uint32_t insn
)
5460 int rd
= extract32(insn
, 0, 5);
5461 int rn
= extract32(insn
, 5, 5);
5462 int size
= extract32(insn
, 22, 2);
5463 int opcode
= extract32(insn
, 12, 5);
5464 bool is_q
= extract32(insn
, 30, 1);
5465 bool is_u
= extract32(insn
, 29, 1);
5467 bool is_min
= false;
5471 TCGv_i64 tcg_res
, tcg_elt
;
5474 case 0x1b: /* ADDV */
5476 unallocated_encoding(s
);
5480 case 0x3: /* SADDLV, UADDLV */
5481 case 0xa: /* SMAXV, UMAXV */
5482 case 0x1a: /* SMINV, UMINV */
5483 if (size
== 3 || (size
== 2 && !is_q
)) {
5484 unallocated_encoding(s
);
5488 case 0xc: /* FMAXNMV, FMINNMV */
5489 case 0xf: /* FMAXV, FMINV */
5490 if (!is_u
|| !is_q
|| extract32(size
, 0, 1)) {
5491 unallocated_encoding(s
);
5494 /* Bit 1 of size field encodes min vs max, and actual size is always
5495 * 32 bits: adjust the size variable so following code can rely on it
5497 is_min
= extract32(size
, 1, 1);
5502 unallocated_encoding(s
);
5506 if (!fp_access_check(s
)) {
5511 elements
= (is_q
? 128 : 64) / esize
;
5513 tcg_res
= tcg_temp_new_i64();
5514 tcg_elt
= tcg_temp_new_i64();
5516 /* These instructions operate across all lanes of a vector
5517 * to produce a single result. We can guarantee that a 64
5518 * bit intermediate is sufficient:
5519 * + for [US]ADDLV the maximum element size is 32 bits, and
5520 * the result type is 64 bits
5521 * + for FMAX*V, FMIN*V, ADDV the intermediate type is the
5522 * same as the element size, which is 32 bits at most
5523 * For the integer operations we can choose to work at 64
5524 * or 32 bits and truncate at the end; for simplicity
5525 * we use 64 bits always. The floating point
5526 * ops do require 32 bit intermediates, though.
5529 read_vec_element(s
, tcg_res
, rn
, 0, size
| (is_u
? 0 : MO_SIGN
));
5531 for (i
= 1; i
< elements
; i
++) {
5532 read_vec_element(s
, tcg_elt
, rn
, i
, size
| (is_u
? 0 : MO_SIGN
));
5535 case 0x03: /* SADDLV / UADDLV */
5536 case 0x1b: /* ADDV */
5537 tcg_gen_add_i64(tcg_res
, tcg_res
, tcg_elt
);
5539 case 0x0a: /* SMAXV / UMAXV */
5540 tcg_gen_movcond_i64(is_u
? TCG_COND_GEU
: TCG_COND_GE
,
5542 tcg_res
, tcg_elt
, tcg_res
, tcg_elt
);
5544 case 0x1a: /* SMINV / UMINV */
5545 tcg_gen_movcond_i64(is_u
? TCG_COND_LEU
: TCG_COND_LE
,
5547 tcg_res
, tcg_elt
, tcg_res
, tcg_elt
);
5551 g_assert_not_reached();
5556 /* Floating point ops which work on 32 bit (single) intermediates.
5557 * Note that correct NaN propagation requires that we do these
5558 * operations in exactly the order specified by the pseudocode.
5560 TCGv_i32 tcg_elt1
= tcg_temp_new_i32();
5561 TCGv_i32 tcg_elt2
= tcg_temp_new_i32();
5562 TCGv_i32 tcg_elt3
= tcg_temp_new_i32();
5563 TCGv_ptr fpst
= get_fpstatus_ptr();
5565 assert(esize
== 32);
5566 assert(elements
== 4);
5568 read_vec_element(s
, tcg_elt
, rn
, 0, MO_32
);
5569 tcg_gen_extrl_i64_i32(tcg_elt1
, tcg_elt
);
5570 read_vec_element(s
, tcg_elt
, rn
, 1, MO_32
);
5571 tcg_gen_extrl_i64_i32(tcg_elt2
, tcg_elt
);
5573 do_minmaxop(s
, tcg_elt1
, tcg_elt2
, opcode
, is_min
, fpst
);
5575 read_vec_element(s
, tcg_elt
, rn
, 2, MO_32
);
5576 tcg_gen_extrl_i64_i32(tcg_elt2
, tcg_elt
);
5577 read_vec_element(s
, tcg_elt
, rn
, 3, MO_32
);
5578 tcg_gen_extrl_i64_i32(tcg_elt3
, tcg_elt
);
5580 do_minmaxop(s
, tcg_elt2
, tcg_elt3
, opcode
, is_min
, fpst
);
5582 do_minmaxop(s
, tcg_elt1
, tcg_elt2
, opcode
, is_min
, fpst
);
5584 tcg_gen_extu_i32_i64(tcg_res
, tcg_elt1
);
5585 tcg_temp_free_i32(tcg_elt1
);
5586 tcg_temp_free_i32(tcg_elt2
);
5587 tcg_temp_free_i32(tcg_elt3
);
5588 tcg_temp_free_ptr(fpst
);
5591 tcg_temp_free_i64(tcg_elt
);
5593 /* Now truncate the result to the width required for the final output */
5594 if (opcode
== 0x03) {
5595 /* SADDLV, UADDLV: result is 2*esize */
5601 tcg_gen_ext8u_i64(tcg_res
, tcg_res
);
5604 tcg_gen_ext16u_i64(tcg_res
, tcg_res
);
5607 tcg_gen_ext32u_i64(tcg_res
, tcg_res
);
5612 g_assert_not_reached();
5615 write_fp_dreg(s
, rd
, tcg_res
);
5616 tcg_temp_free_i64(tcg_res
);
5619 /* C6.3.31 DUP (Element, Vector)
5621 * 31 30 29 21 20 16 15 10 9 5 4 0
5622 * +---+---+-------------------+--------+-------------+------+------+
5623 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 0 1 | Rn | Rd |
5624 * +---+---+-------------------+--------+-------------+------+------+
5626 * size: encoded in imm5 (see ARM ARM LowestSetBit())
5628 static void handle_simd_dupe(DisasContext
*s
, int is_q
, int rd
, int rn
,
5631 int size
= ctz32(imm5
);
5632 int esize
= 8 << size
;
5633 int elements
= (is_q
? 128 : 64) / esize
;
5637 if (size
> 3 || (size
== 3 && !is_q
)) {
5638 unallocated_encoding(s
);
5642 if (!fp_access_check(s
)) {
5646 index
= imm5
>> (size
+ 1);
5648 tmp
= tcg_temp_new_i64();
5649 read_vec_element(s
, tmp
, rn
, index
, size
);
5651 for (i
= 0; i
< elements
; i
++) {
5652 write_vec_element(s
, tmp
, rd
, i
, size
);
5656 clear_vec_high(s
, rd
);
5659 tcg_temp_free_i64(tmp
);
5662 /* C6.3.31 DUP (element, scalar)
5663 * 31 21 20 16 15 10 9 5 4 0
5664 * +-----------------------+--------+-------------+------+------+
5665 * | 0 1 0 1 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 0 1 | Rn | Rd |
5666 * +-----------------------+--------+-------------+------+------+
5668 static void handle_simd_dupes(DisasContext
*s
, int rd
, int rn
,
5671 int size
= ctz32(imm5
);
5676 unallocated_encoding(s
);
5680 if (!fp_access_check(s
)) {
5684 index
= imm5
>> (size
+ 1);
5686 /* This instruction just extracts the specified element and
5687 * zero-extends it into the bottom of the destination register.
5689 tmp
= tcg_temp_new_i64();
5690 read_vec_element(s
, tmp
, rn
, index
, size
);
5691 write_fp_dreg(s
, rd
, tmp
);
5692 tcg_temp_free_i64(tmp
);
5695 /* C6.3.32 DUP (General)
5697 * 31 30 29 21 20 16 15 10 9 5 4 0
5698 * +---+---+-------------------+--------+-------------+------+------+
5699 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 1 1 | Rn | Rd |
5700 * +---+---+-------------------+--------+-------------+------+------+
5702 * size: encoded in imm5 (see ARM ARM LowestSetBit())
5704 static void handle_simd_dupg(DisasContext
*s
, int is_q
, int rd
, int rn
,
5707 int size
= ctz32(imm5
);
5708 int esize
= 8 << size
;
5709 int elements
= (is_q
? 128 : 64)/esize
;
5712 if (size
> 3 || ((size
== 3) && !is_q
)) {
5713 unallocated_encoding(s
);
5717 if (!fp_access_check(s
)) {
5721 for (i
= 0; i
< elements
; i
++) {
5722 write_vec_element(s
, cpu_reg(s
, rn
), rd
, i
, size
);
5725 clear_vec_high(s
, rd
);
5729 /* C6.3.150 INS (Element)
5731 * 31 21 20 16 15 14 11 10 9 5 4 0
5732 * +-----------------------+--------+------------+---+------+------+
5733 * | 0 1 1 0 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
5734 * +-----------------------+--------+------------+---+------+------+
5736 * size: encoded in imm5 (see ARM ARM LowestSetBit())
5737 * index: encoded in imm5<4:size+1>
5739 static void handle_simd_inse(DisasContext
*s
, int rd
, int rn
,
5742 int size
= ctz32(imm5
);
5743 int src_index
, dst_index
;
5747 unallocated_encoding(s
);
5751 if (!fp_access_check(s
)) {
5755 dst_index
= extract32(imm5
, 1+size
, 5);
5756 src_index
= extract32(imm4
, size
, 4);
5758 tmp
= tcg_temp_new_i64();
5760 read_vec_element(s
, tmp
, rn
, src_index
, size
);
5761 write_vec_element(s
, tmp
, rd
, dst_index
, size
);
5763 tcg_temp_free_i64(tmp
);
5767 /* C6.3.151 INS (General)
5769 * 31 21 20 16 15 10 9 5 4 0
5770 * +-----------------------+--------+-------------+------+------+
5771 * | 0 1 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 1 1 1 | Rn | Rd |
5772 * +-----------------------+--------+-------------+------+------+
5774 * size: encoded in imm5 (see ARM ARM LowestSetBit())
5775 * index: encoded in imm5<4:size+1>
5777 static void handle_simd_insg(DisasContext
*s
, int rd
, int rn
, int imm5
)
5779 int size
= ctz32(imm5
);
5783 unallocated_encoding(s
);
5787 if (!fp_access_check(s
)) {
5791 idx
= extract32(imm5
, 1 + size
, 4 - size
);
5792 write_vec_element(s
, cpu_reg(s
, rn
), rd
, idx
, size
);
5796 * C6.3.321 UMOV (General)
5797 * C6.3.237 SMOV (General)
5799 * 31 30 29 21 20 16 15 12 10 9 5 4 0
5800 * +---+---+-------------------+--------+-------------+------+------+
5801 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 1 U 1 1 | Rn | Rd |
5802 * +---+---+-------------------+--------+-------------+------+------+
5804 * U: unsigned when set
5805 * size: encoded in imm5 (see ARM ARM LowestSetBit())
5807 static void handle_simd_umov_smov(DisasContext
*s
, int is_q
, int is_signed
,
5808 int rn
, int rd
, int imm5
)
5810 int size
= ctz32(imm5
);
5814 /* Check for UnallocatedEncodings */
5816 if (size
> 2 || (size
== 2 && !is_q
)) {
5817 unallocated_encoding(s
);
5822 || (size
< 3 && is_q
)
5823 || (size
== 3 && !is_q
)) {
5824 unallocated_encoding(s
);
5829 if (!fp_access_check(s
)) {
5833 element
= extract32(imm5
, 1+size
, 4);
5835 tcg_rd
= cpu_reg(s
, rd
);
5836 read_vec_element(s
, tcg_rd
, rn
, element
, size
| (is_signed
? MO_SIGN
: 0));
5837 if (is_signed
&& !is_q
) {
5838 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
5842 /* C3.6.5 AdvSIMD copy
5843 * 31 30 29 28 21 20 16 15 14 11 10 9 5 4 0
5844 * +---+---+----+-----------------+------+---+------+---+------+------+
5845 * | 0 | Q | op | 0 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
5846 * +---+---+----+-----------------+------+---+------+---+------+------+
5848 static void disas_simd_copy(DisasContext
*s
, uint32_t insn
)
5850 int rd
= extract32(insn
, 0, 5);
5851 int rn
= extract32(insn
, 5, 5);
5852 int imm4
= extract32(insn
, 11, 4);
5853 int op
= extract32(insn
, 29, 1);
5854 int is_q
= extract32(insn
, 30, 1);
5855 int imm5
= extract32(insn
, 16, 5);
5860 handle_simd_inse(s
, rd
, rn
, imm4
, imm5
);
5862 unallocated_encoding(s
);
5867 /* DUP (element - vector) */
5868 handle_simd_dupe(s
, is_q
, rd
, rn
, imm5
);
5872 handle_simd_dupg(s
, is_q
, rd
, rn
, imm5
);
5877 handle_simd_insg(s
, rd
, rn
, imm5
);
5879 unallocated_encoding(s
);
5884 /* UMOV/SMOV (is_q indicates 32/64; imm4 indicates signedness) */
5885 handle_simd_umov_smov(s
, is_q
, (imm4
== 5), rn
, rd
, imm5
);
5888 unallocated_encoding(s
);
5894 /* C3.6.6 AdvSIMD modified immediate
5895 * 31 30 29 28 19 18 16 15 12 11 10 9 5 4 0
5896 * +---+---+----+---------------------+-----+-------+----+---+-------+------+
5897 * | 0 | Q | op | 0 1 1 1 1 0 0 0 0 0 | abc | cmode | o2 | 1 | defgh | Rd |
5898 * +---+---+----+---------------------+-----+-------+----+---+-------+------+
5900 * There are a number of operations that can be carried out here:
5901 * MOVI - move (shifted) imm into register
5902 * MVNI - move inverted (shifted) imm into register
5903 * ORR - bitwise OR of (shifted) imm with register
5904 * BIC - bitwise clear of (shifted) imm with register
5906 static void disas_simd_mod_imm(DisasContext
*s
, uint32_t insn
)
5908 int rd
= extract32(insn
, 0, 5);
5909 int cmode
= extract32(insn
, 12, 4);
5910 int cmode_3_1
= extract32(cmode
, 1, 3);
5911 int cmode_0
= extract32(cmode
, 0, 1);
5912 int o2
= extract32(insn
, 11, 1);
5913 uint64_t abcdefgh
= extract32(insn
, 5, 5) | (extract32(insn
, 16, 3) << 5);
5914 bool is_neg
= extract32(insn
, 29, 1);
5915 bool is_q
= extract32(insn
, 30, 1);
5917 TCGv_i64 tcg_rd
, tcg_imm
;
5920 if (o2
!= 0 || ((cmode
== 0xf) && is_neg
&& !is_q
)) {
5921 unallocated_encoding(s
);
5925 if (!fp_access_check(s
)) {
5929 /* See AdvSIMDExpandImm() in ARM ARM */
5930 switch (cmode_3_1
) {
5931 case 0: /* Replicate(Zeros(24):imm8, 2) */
5932 case 1: /* Replicate(Zeros(16):imm8:Zeros(8), 2) */
5933 case 2: /* Replicate(Zeros(8):imm8:Zeros(16), 2) */
5934 case 3: /* Replicate(imm8:Zeros(24), 2) */
5936 int shift
= cmode_3_1
* 8;
5937 imm
= bitfield_replicate(abcdefgh
<< shift
, 32);
5940 case 4: /* Replicate(Zeros(8):imm8, 4) */
5941 case 5: /* Replicate(imm8:Zeros(8), 4) */
5943 int shift
= (cmode_3_1
& 0x1) * 8;
5944 imm
= bitfield_replicate(abcdefgh
<< shift
, 16);
5949 /* Replicate(Zeros(8):imm8:Ones(16), 2) */
5950 imm
= (abcdefgh
<< 16) | 0xffff;
5952 /* Replicate(Zeros(16):imm8:Ones(8), 2) */
5953 imm
= (abcdefgh
<< 8) | 0xff;
5955 imm
= bitfield_replicate(imm
, 32);
5958 if (!cmode_0
&& !is_neg
) {
5959 imm
= bitfield_replicate(abcdefgh
, 8);
5960 } else if (!cmode_0
&& is_neg
) {
5963 for (i
= 0; i
< 8; i
++) {
5964 if ((abcdefgh
) & (1 << i
)) {
5965 imm
|= 0xffULL
<< (i
* 8);
5968 } else if (cmode_0
) {
5970 imm
= (abcdefgh
& 0x3f) << 48;
5971 if (abcdefgh
& 0x80) {
5972 imm
|= 0x8000000000000000ULL
;
5974 if (abcdefgh
& 0x40) {
5975 imm
|= 0x3fc0000000000000ULL
;
5977 imm
|= 0x4000000000000000ULL
;
5980 imm
= (abcdefgh
& 0x3f) << 19;
5981 if (abcdefgh
& 0x80) {
5984 if (abcdefgh
& 0x40) {
5995 if (cmode_3_1
!= 7 && is_neg
) {
5999 tcg_imm
= tcg_const_i64(imm
);
6000 tcg_rd
= new_tmp_a64(s
);
6002 for (i
= 0; i
< 2; i
++) {
6003 int foffs
= i
? fp_reg_hi_offset(s
, rd
) : fp_reg_offset(s
, rd
, MO_64
);
6005 if (i
== 1 && !is_q
) {
6006 /* non-quad ops clear high half of vector */
6007 tcg_gen_movi_i64(tcg_rd
, 0);
6008 } else if ((cmode
& 0x9) == 0x1 || (cmode
& 0xd) == 0x9) {
6009 tcg_gen_ld_i64(tcg_rd
, cpu_env
, foffs
);
6012 tcg_gen_and_i64(tcg_rd
, tcg_rd
, tcg_imm
);
6015 tcg_gen_or_i64(tcg_rd
, tcg_rd
, tcg_imm
);
6019 tcg_gen_mov_i64(tcg_rd
, tcg_imm
);
6021 tcg_gen_st_i64(tcg_rd
, cpu_env
, foffs
);
6024 tcg_temp_free_i64(tcg_imm
);
6027 /* C3.6.7 AdvSIMD scalar copy
6028 * 31 30 29 28 21 20 16 15 14 11 10 9 5 4 0
6029 * +-----+----+-----------------+------+---+------+---+------+------+
6030 * | 0 1 | op | 1 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
6031 * +-----+----+-----------------+------+---+------+---+------+------+
6033 static void disas_simd_scalar_copy(DisasContext
*s
, uint32_t insn
)
6035 int rd
= extract32(insn
, 0, 5);
6036 int rn
= extract32(insn
, 5, 5);
6037 int imm4
= extract32(insn
, 11, 4);
6038 int imm5
= extract32(insn
, 16, 5);
6039 int op
= extract32(insn
, 29, 1);
6041 if (op
!= 0 || imm4
!= 0) {
6042 unallocated_encoding(s
);
6046 /* DUP (element, scalar) */
6047 handle_simd_dupes(s
, rd
, rn
, imm5
);
6050 /* C3.6.8 AdvSIMD scalar pairwise
6051 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
6052 * +-----+---+-----------+------+-----------+--------+-----+------+------+
6053 * | 0 1 | U | 1 1 1 1 0 | size | 1 1 0 0 0 | opcode | 1 0 | Rn | Rd |
6054 * +-----+---+-----------+------+-----------+--------+-----+------+------+
6056 static void disas_simd_scalar_pairwise(DisasContext
*s
, uint32_t insn
)
6058 int u
= extract32(insn
, 29, 1);
6059 int size
= extract32(insn
, 22, 2);
6060 int opcode
= extract32(insn
, 12, 5);
6061 int rn
= extract32(insn
, 5, 5);
6062 int rd
= extract32(insn
, 0, 5);
6065 /* For some ops (the FP ones), size[1] is part of the encoding.
6066 * For ADDP strictly it is not but size[1] is always 1 for valid
6069 opcode
|= (extract32(size
, 1, 1) << 5);
6072 case 0x3b: /* ADDP */
6073 if (u
|| size
!= 3) {
6074 unallocated_encoding(s
);
6077 if (!fp_access_check(s
)) {
6081 TCGV_UNUSED_PTR(fpst
);
6083 case 0xc: /* FMAXNMP */
6084 case 0xd: /* FADDP */
6085 case 0xf: /* FMAXP */
6086 case 0x2c: /* FMINNMP */
6087 case 0x2f: /* FMINP */
6088 /* FP op, size[0] is 32 or 64 bit */
6090 unallocated_encoding(s
);
6093 if (!fp_access_check(s
)) {
6097 size
= extract32(size
, 0, 1) ? 3 : 2;
6098 fpst
= get_fpstatus_ptr();
6101 unallocated_encoding(s
);
6106 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
6107 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
6108 TCGv_i64 tcg_res
= tcg_temp_new_i64();
6110 read_vec_element(s
, tcg_op1
, rn
, 0, MO_64
);
6111 read_vec_element(s
, tcg_op2
, rn
, 1, MO_64
);
6114 case 0x3b: /* ADDP */
6115 tcg_gen_add_i64(tcg_res
, tcg_op1
, tcg_op2
);
6117 case 0xc: /* FMAXNMP */
6118 gen_helper_vfp_maxnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6120 case 0xd: /* FADDP */
6121 gen_helper_vfp_addd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6123 case 0xf: /* FMAXP */
6124 gen_helper_vfp_maxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6126 case 0x2c: /* FMINNMP */
6127 gen_helper_vfp_minnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6129 case 0x2f: /* FMINP */
6130 gen_helper_vfp_mind(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6133 g_assert_not_reached();
6136 write_fp_dreg(s
, rd
, tcg_res
);
6138 tcg_temp_free_i64(tcg_op1
);
6139 tcg_temp_free_i64(tcg_op2
);
6140 tcg_temp_free_i64(tcg_res
);
6142 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
6143 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
6144 TCGv_i32 tcg_res
= tcg_temp_new_i32();
6146 read_vec_element_i32(s
, tcg_op1
, rn
, 0, MO_32
);
6147 read_vec_element_i32(s
, tcg_op2
, rn
, 1, MO_32
);
6150 case 0xc: /* FMAXNMP */
6151 gen_helper_vfp_maxnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6153 case 0xd: /* FADDP */
6154 gen_helper_vfp_adds(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6156 case 0xf: /* FMAXP */
6157 gen_helper_vfp_maxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6159 case 0x2c: /* FMINNMP */
6160 gen_helper_vfp_minnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6162 case 0x2f: /* FMINP */
6163 gen_helper_vfp_mins(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6166 g_assert_not_reached();
6169 write_fp_sreg(s
, rd
, tcg_res
);
6171 tcg_temp_free_i32(tcg_op1
);
6172 tcg_temp_free_i32(tcg_op2
);
6173 tcg_temp_free_i32(tcg_res
);
6176 if (!TCGV_IS_UNUSED_PTR(fpst
)) {
6177 tcg_temp_free_ptr(fpst
);
6182 * Common SSHR[RA]/USHR[RA] - Shift right (optional rounding/accumulate)
6184 * This code is handles the common shifting code and is used by both
6185 * the vector and scalar code.
6187 static void handle_shri_with_rndacc(TCGv_i64 tcg_res
, TCGv_i64 tcg_src
,
6188 TCGv_i64 tcg_rnd
, bool accumulate
,
6189 bool is_u
, int size
, int shift
)
6191 bool extended_result
= false;
6192 bool round
= !TCGV_IS_UNUSED_I64(tcg_rnd
);
6194 TCGv_i64 tcg_src_hi
;
6196 if (round
&& size
== 3) {
6197 extended_result
= true;
6198 ext_lshift
= 64 - shift
;
6199 tcg_src_hi
= tcg_temp_new_i64();
6200 } else if (shift
== 64) {
6201 if (!accumulate
&& is_u
) {
6202 /* result is zero */
6203 tcg_gen_movi_i64(tcg_res
, 0);
6208 /* Deal with the rounding step */
6210 if (extended_result
) {
6211 TCGv_i64 tcg_zero
= tcg_const_i64(0);
6213 /* take care of sign extending tcg_res */
6214 tcg_gen_sari_i64(tcg_src_hi
, tcg_src
, 63);
6215 tcg_gen_add2_i64(tcg_src
, tcg_src_hi
,
6216 tcg_src
, tcg_src_hi
,
6219 tcg_gen_add2_i64(tcg_src
, tcg_src_hi
,
6223 tcg_temp_free_i64(tcg_zero
);
6225 tcg_gen_add_i64(tcg_src
, tcg_src
, tcg_rnd
);
6229 /* Now do the shift right */
6230 if (round
&& extended_result
) {
6231 /* extended case, >64 bit precision required */
6232 if (ext_lshift
== 0) {
6233 /* special case, only high bits matter */
6234 tcg_gen_mov_i64(tcg_src
, tcg_src_hi
);
6236 tcg_gen_shri_i64(tcg_src
, tcg_src
, shift
);
6237 tcg_gen_shli_i64(tcg_src_hi
, tcg_src_hi
, ext_lshift
);
6238 tcg_gen_or_i64(tcg_src
, tcg_src
, tcg_src_hi
);
6243 /* essentially shifting in 64 zeros */
6244 tcg_gen_movi_i64(tcg_src
, 0);
6246 tcg_gen_shri_i64(tcg_src
, tcg_src
, shift
);
6250 /* effectively extending the sign-bit */
6251 tcg_gen_sari_i64(tcg_src
, tcg_src
, 63);
6253 tcg_gen_sari_i64(tcg_src
, tcg_src
, shift
);
6259 tcg_gen_add_i64(tcg_res
, tcg_res
, tcg_src
);
6261 tcg_gen_mov_i64(tcg_res
, tcg_src
);
6264 if (extended_result
) {
6265 tcg_temp_free_i64(tcg_src_hi
);
6269 /* Common SHL/SLI - Shift left with an optional insert */
6270 static void handle_shli_with_ins(TCGv_i64 tcg_res
, TCGv_i64 tcg_src
,
6271 bool insert
, int shift
)
6273 if (insert
) { /* SLI */
6274 tcg_gen_deposit_i64(tcg_res
, tcg_res
, tcg_src
, shift
, 64 - shift
);
6276 tcg_gen_shli_i64(tcg_res
, tcg_src
, shift
);
6280 /* SRI: shift right with insert */
6281 static void handle_shri_with_ins(TCGv_i64 tcg_res
, TCGv_i64 tcg_src
,
6282 int size
, int shift
)
6284 int esize
= 8 << size
;
6286 /* shift count same as element size is valid but does nothing;
6287 * special case to avoid potential shift by 64.
6289 if (shift
!= esize
) {
6290 tcg_gen_shri_i64(tcg_src
, tcg_src
, shift
);
6291 tcg_gen_deposit_i64(tcg_res
, tcg_res
, tcg_src
, 0, esize
- shift
);
6295 /* SSHR[RA]/USHR[RA] - Scalar shift right (optional rounding/accumulate) */
6296 static void handle_scalar_simd_shri(DisasContext
*s
,
6297 bool is_u
, int immh
, int immb
,
6298 int opcode
, int rn
, int rd
)
6301 int immhb
= immh
<< 3 | immb
;
6302 int shift
= 2 * (8 << size
) - immhb
;
6303 bool accumulate
= false;
6305 bool insert
= false;
6310 if (!extract32(immh
, 3, 1)) {
6311 unallocated_encoding(s
);
6315 if (!fp_access_check(s
)) {
6320 case 0x02: /* SSRA / USRA (accumulate) */
6323 case 0x04: /* SRSHR / URSHR (rounding) */
6326 case 0x06: /* SRSRA / URSRA (accum + rounding) */
6327 accumulate
= round
= true;
6329 case 0x08: /* SRI */
6335 uint64_t round_const
= 1ULL << (shift
- 1);
6336 tcg_round
= tcg_const_i64(round_const
);
6338 TCGV_UNUSED_I64(tcg_round
);
6341 tcg_rn
= read_fp_dreg(s
, rn
);
6342 tcg_rd
= (accumulate
|| insert
) ? read_fp_dreg(s
, rd
) : tcg_temp_new_i64();
6345 handle_shri_with_ins(tcg_rd
, tcg_rn
, size
, shift
);
6347 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
6348 accumulate
, is_u
, size
, shift
);
6351 write_fp_dreg(s
, rd
, tcg_rd
);
6353 tcg_temp_free_i64(tcg_rn
);
6354 tcg_temp_free_i64(tcg_rd
);
6356 tcg_temp_free_i64(tcg_round
);
6360 /* SHL/SLI - Scalar shift left */
6361 static void handle_scalar_simd_shli(DisasContext
*s
, bool insert
,
6362 int immh
, int immb
, int opcode
,
6365 int size
= 32 - clz32(immh
) - 1;
6366 int immhb
= immh
<< 3 | immb
;
6367 int shift
= immhb
- (8 << size
);
6368 TCGv_i64 tcg_rn
= new_tmp_a64(s
);
6369 TCGv_i64 tcg_rd
= new_tmp_a64(s
);
6371 if (!extract32(immh
, 3, 1)) {
6372 unallocated_encoding(s
);
6376 if (!fp_access_check(s
)) {
6380 tcg_rn
= read_fp_dreg(s
, rn
);
6381 tcg_rd
= insert
? read_fp_dreg(s
, rd
) : tcg_temp_new_i64();
6383 handle_shli_with_ins(tcg_rd
, tcg_rn
, insert
, shift
);
6385 write_fp_dreg(s
, rd
, tcg_rd
);
6387 tcg_temp_free_i64(tcg_rn
);
6388 tcg_temp_free_i64(tcg_rd
);
6391 /* SQSHRN/SQSHRUN - Saturating (signed/unsigned) shift right with
6392 * (signed/unsigned) narrowing */
6393 static void handle_vec_simd_sqshrn(DisasContext
*s
, bool is_scalar
, bool is_q
,
6394 bool is_u_shift
, bool is_u_narrow
,
6395 int immh
, int immb
, int opcode
,
6398 int immhb
= immh
<< 3 | immb
;
6399 int size
= 32 - clz32(immh
) - 1;
6400 int esize
= 8 << size
;
6401 int shift
= (2 * esize
) - immhb
;
6402 int elements
= is_scalar
? 1 : (64 / esize
);
6403 bool round
= extract32(opcode
, 0, 1);
6404 TCGMemOp ldop
= (size
+ 1) | (is_u_shift
? 0 : MO_SIGN
);
6405 TCGv_i64 tcg_rn
, tcg_rd
, tcg_round
;
6406 TCGv_i32 tcg_rd_narrowed
;
6409 static NeonGenNarrowEnvFn
* const signed_narrow_fns
[4][2] = {
6410 { gen_helper_neon_narrow_sat_s8
,
6411 gen_helper_neon_unarrow_sat8
},
6412 { gen_helper_neon_narrow_sat_s16
,
6413 gen_helper_neon_unarrow_sat16
},
6414 { gen_helper_neon_narrow_sat_s32
,
6415 gen_helper_neon_unarrow_sat32
},
6418 static NeonGenNarrowEnvFn
* const unsigned_narrow_fns
[4] = {
6419 gen_helper_neon_narrow_sat_u8
,
6420 gen_helper_neon_narrow_sat_u16
,
6421 gen_helper_neon_narrow_sat_u32
,
6424 NeonGenNarrowEnvFn
*narrowfn
;
6430 if (extract32(immh
, 3, 1)) {
6431 unallocated_encoding(s
);
6435 if (!fp_access_check(s
)) {
6440 narrowfn
= unsigned_narrow_fns
[size
];
6442 narrowfn
= signed_narrow_fns
[size
][is_u_narrow
? 1 : 0];
6445 tcg_rn
= tcg_temp_new_i64();
6446 tcg_rd
= tcg_temp_new_i64();
6447 tcg_rd_narrowed
= tcg_temp_new_i32();
6448 tcg_final
= tcg_const_i64(0);
6451 uint64_t round_const
= 1ULL << (shift
- 1);
6452 tcg_round
= tcg_const_i64(round_const
);
6454 TCGV_UNUSED_I64(tcg_round
);
6457 for (i
= 0; i
< elements
; i
++) {
6458 read_vec_element(s
, tcg_rn
, rn
, i
, ldop
);
6459 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
6460 false, is_u_shift
, size
+1, shift
);
6461 narrowfn(tcg_rd_narrowed
, cpu_env
, tcg_rd
);
6462 tcg_gen_extu_i32_i64(tcg_rd
, tcg_rd_narrowed
);
6463 tcg_gen_deposit_i64(tcg_final
, tcg_final
, tcg_rd
, esize
* i
, esize
);
6467 clear_vec_high(s
, rd
);
6468 write_vec_element(s
, tcg_final
, rd
, 0, MO_64
);
6470 write_vec_element(s
, tcg_final
, rd
, 1, MO_64
);
6474 tcg_temp_free_i64(tcg_round
);
6476 tcg_temp_free_i64(tcg_rn
);
6477 tcg_temp_free_i64(tcg_rd
);
6478 tcg_temp_free_i32(tcg_rd_narrowed
);
6479 tcg_temp_free_i64(tcg_final
);
6483 /* SQSHLU, UQSHL, SQSHL: saturating left shifts */
6484 static void handle_simd_qshl(DisasContext
*s
, bool scalar
, bool is_q
,
6485 bool src_unsigned
, bool dst_unsigned
,
6486 int immh
, int immb
, int rn
, int rd
)
6488 int immhb
= immh
<< 3 | immb
;
6489 int size
= 32 - clz32(immh
) - 1;
6490 int shift
= immhb
- (8 << size
);
6494 assert(!(scalar
&& is_q
));
6497 if (!is_q
&& extract32(immh
, 3, 1)) {
6498 unallocated_encoding(s
);
6502 /* Since we use the variable-shift helpers we must
6503 * replicate the shift count into each element of
6504 * the tcg_shift value.
6508 shift
|= shift
<< 8;
6511 shift
|= shift
<< 16;
6517 g_assert_not_reached();
6521 if (!fp_access_check(s
)) {
6526 TCGv_i64 tcg_shift
= tcg_const_i64(shift
);
6527 static NeonGenTwo64OpEnvFn
* const fns
[2][2] = {
6528 { gen_helper_neon_qshl_s64
, gen_helper_neon_qshlu_s64
},
6529 { NULL
, gen_helper_neon_qshl_u64
},
6531 NeonGenTwo64OpEnvFn
*genfn
= fns
[src_unsigned
][dst_unsigned
];
6532 int maxpass
= is_q
? 2 : 1;
6534 for (pass
= 0; pass
< maxpass
; pass
++) {
6535 TCGv_i64 tcg_op
= tcg_temp_new_i64();
6537 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
6538 genfn(tcg_op
, cpu_env
, tcg_op
, tcg_shift
);
6539 write_vec_element(s
, tcg_op
, rd
, pass
, MO_64
);
6541 tcg_temp_free_i64(tcg_op
);
6543 tcg_temp_free_i64(tcg_shift
);
6546 clear_vec_high(s
, rd
);
6549 TCGv_i32 tcg_shift
= tcg_const_i32(shift
);
6550 static NeonGenTwoOpEnvFn
* const fns
[2][2][3] = {
6552 { gen_helper_neon_qshl_s8
,
6553 gen_helper_neon_qshl_s16
,
6554 gen_helper_neon_qshl_s32
},
6555 { gen_helper_neon_qshlu_s8
,
6556 gen_helper_neon_qshlu_s16
,
6557 gen_helper_neon_qshlu_s32
}
6559 { NULL
, NULL
, NULL
},
6560 { gen_helper_neon_qshl_u8
,
6561 gen_helper_neon_qshl_u16
,
6562 gen_helper_neon_qshl_u32
}
6565 NeonGenTwoOpEnvFn
*genfn
= fns
[src_unsigned
][dst_unsigned
][size
];
6566 TCGMemOp memop
= scalar
? size
: MO_32
;
6567 int maxpass
= scalar
? 1 : is_q
? 4 : 2;
6569 for (pass
= 0; pass
< maxpass
; pass
++) {
6570 TCGv_i32 tcg_op
= tcg_temp_new_i32();
6572 read_vec_element_i32(s
, tcg_op
, rn
, pass
, memop
);
6573 genfn(tcg_op
, cpu_env
, tcg_op
, tcg_shift
);
6577 tcg_gen_ext8u_i32(tcg_op
, tcg_op
);
6580 tcg_gen_ext16u_i32(tcg_op
, tcg_op
);
6585 g_assert_not_reached();
6587 write_fp_sreg(s
, rd
, tcg_op
);
6589 write_vec_element_i32(s
, tcg_op
, rd
, pass
, MO_32
);
6592 tcg_temp_free_i32(tcg_op
);
6594 tcg_temp_free_i32(tcg_shift
);
6596 if (!is_q
&& !scalar
) {
6597 clear_vec_high(s
, rd
);
6602 /* Common vector code for handling integer to FP conversion */
6603 static void handle_simd_intfp_conv(DisasContext
*s
, int rd
, int rn
,
6604 int elements
, int is_signed
,
6605 int fracbits
, int size
)
6607 bool is_double
= size
== 3 ? true : false;
6608 TCGv_ptr tcg_fpst
= get_fpstatus_ptr();
6609 TCGv_i32 tcg_shift
= tcg_const_i32(fracbits
);
6610 TCGv_i64 tcg_int
= tcg_temp_new_i64();
6611 TCGMemOp mop
= size
| (is_signed
? MO_SIGN
: 0);
6614 for (pass
= 0; pass
< elements
; pass
++) {
6615 read_vec_element(s
, tcg_int
, rn
, pass
, mop
);
6618 TCGv_i64 tcg_double
= tcg_temp_new_i64();
6620 gen_helper_vfp_sqtod(tcg_double
, tcg_int
,
6621 tcg_shift
, tcg_fpst
);
6623 gen_helper_vfp_uqtod(tcg_double
, tcg_int
,
6624 tcg_shift
, tcg_fpst
);
6626 if (elements
== 1) {
6627 write_fp_dreg(s
, rd
, tcg_double
);
6629 write_vec_element(s
, tcg_double
, rd
, pass
, MO_64
);
6631 tcg_temp_free_i64(tcg_double
);
6633 TCGv_i32 tcg_single
= tcg_temp_new_i32();
6635 gen_helper_vfp_sqtos(tcg_single
, tcg_int
,
6636 tcg_shift
, tcg_fpst
);
6638 gen_helper_vfp_uqtos(tcg_single
, tcg_int
,
6639 tcg_shift
, tcg_fpst
);
6641 if (elements
== 1) {
6642 write_fp_sreg(s
, rd
, tcg_single
);
6644 write_vec_element_i32(s
, tcg_single
, rd
, pass
, MO_32
);
6646 tcg_temp_free_i32(tcg_single
);
6650 if (!is_double
&& elements
== 2) {
6651 clear_vec_high(s
, rd
);
6654 tcg_temp_free_i64(tcg_int
);
6655 tcg_temp_free_ptr(tcg_fpst
);
6656 tcg_temp_free_i32(tcg_shift
);
6659 /* UCVTF/SCVTF - Integer to FP conversion */
6660 static void handle_simd_shift_intfp_conv(DisasContext
*s
, bool is_scalar
,
6661 bool is_q
, bool is_u
,
6662 int immh
, int immb
, int opcode
,
6665 bool is_double
= extract32(immh
, 3, 1);
6666 int size
= is_double
? MO_64
: MO_32
;
6668 int immhb
= immh
<< 3 | immb
;
6669 int fracbits
= (is_double
? 128 : 64) - immhb
;
6671 if (!extract32(immh
, 2, 2)) {
6672 unallocated_encoding(s
);
6679 elements
= is_double
? 2 : is_q
? 4 : 2;
6680 if (is_double
&& !is_q
) {
6681 unallocated_encoding(s
);
6686 if (!fp_access_check(s
)) {
6690 /* immh == 0 would be a failure of the decode logic */
6693 handle_simd_intfp_conv(s
, rd
, rn
, elements
, !is_u
, fracbits
, size
);
6696 /* FCVTZS, FVCVTZU - FP to fixedpoint conversion */
6697 static void handle_simd_shift_fpint_conv(DisasContext
*s
, bool is_scalar
,
6698 bool is_q
, bool is_u
,
6699 int immh
, int immb
, int rn
, int rd
)
6701 bool is_double
= extract32(immh
, 3, 1);
6702 int immhb
= immh
<< 3 | immb
;
6703 int fracbits
= (is_double
? 128 : 64) - immhb
;
6705 TCGv_ptr tcg_fpstatus
;
6706 TCGv_i32 tcg_rmode
, tcg_shift
;
6708 if (!extract32(immh
, 2, 2)) {
6709 unallocated_encoding(s
);
6713 if (!is_scalar
&& !is_q
&& is_double
) {
6714 unallocated_encoding(s
);
6718 if (!fp_access_check(s
)) {
6722 assert(!(is_scalar
&& is_q
));
6724 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(FPROUNDING_ZERO
));
6725 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
6726 tcg_fpstatus
= get_fpstatus_ptr();
6727 tcg_shift
= tcg_const_i32(fracbits
);
6730 int maxpass
= is_scalar
? 1 : 2;
6732 for (pass
= 0; pass
< maxpass
; pass
++) {
6733 TCGv_i64 tcg_op
= tcg_temp_new_i64();
6735 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
6737 gen_helper_vfp_touqd(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
6739 gen_helper_vfp_tosqd(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
6741 write_vec_element(s
, tcg_op
, rd
, pass
, MO_64
);
6742 tcg_temp_free_i64(tcg_op
);
6745 clear_vec_high(s
, rd
);
6748 int maxpass
= is_scalar
? 1 : is_q
? 4 : 2;
6749 for (pass
= 0; pass
< maxpass
; pass
++) {
6750 TCGv_i32 tcg_op
= tcg_temp_new_i32();
6752 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_32
);
6754 gen_helper_vfp_touls(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
6756 gen_helper_vfp_tosls(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
6759 write_fp_sreg(s
, rd
, tcg_op
);
6761 write_vec_element_i32(s
, tcg_op
, rd
, pass
, MO_32
);
6763 tcg_temp_free_i32(tcg_op
);
6765 if (!is_q
&& !is_scalar
) {
6766 clear_vec_high(s
, rd
);
6770 tcg_temp_free_ptr(tcg_fpstatus
);
6771 tcg_temp_free_i32(tcg_shift
);
6772 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
6773 tcg_temp_free_i32(tcg_rmode
);
6776 /* C3.6.9 AdvSIMD scalar shift by immediate
6777 * 31 30 29 28 23 22 19 18 16 15 11 10 9 5 4 0
6778 * +-----+---+-------------+------+------+--------+---+------+------+
6779 * | 0 1 | U | 1 1 1 1 1 0 | immh | immb | opcode | 1 | Rn | Rd |
6780 * +-----+---+-------------+------+------+--------+---+------+------+
6782 * This is the scalar version so it works on a fixed sized registers
6784 static void disas_simd_scalar_shift_imm(DisasContext
*s
, uint32_t insn
)
6786 int rd
= extract32(insn
, 0, 5);
6787 int rn
= extract32(insn
, 5, 5);
6788 int opcode
= extract32(insn
, 11, 5);
6789 int immb
= extract32(insn
, 16, 3);
6790 int immh
= extract32(insn
, 19, 4);
6791 bool is_u
= extract32(insn
, 29, 1);
6794 unallocated_encoding(s
);
6799 case 0x08: /* SRI */
6801 unallocated_encoding(s
);
6805 case 0x00: /* SSHR / USHR */
6806 case 0x02: /* SSRA / USRA */
6807 case 0x04: /* SRSHR / URSHR */
6808 case 0x06: /* SRSRA / URSRA */
6809 handle_scalar_simd_shri(s
, is_u
, immh
, immb
, opcode
, rn
, rd
);
6811 case 0x0a: /* SHL / SLI */
6812 handle_scalar_simd_shli(s
, is_u
, immh
, immb
, opcode
, rn
, rd
);
6814 case 0x1c: /* SCVTF, UCVTF */
6815 handle_simd_shift_intfp_conv(s
, true, false, is_u
, immh
, immb
,
6818 case 0x10: /* SQSHRUN, SQSHRUN2 */
6819 case 0x11: /* SQRSHRUN, SQRSHRUN2 */
6821 unallocated_encoding(s
);
6824 handle_vec_simd_sqshrn(s
, true, false, false, true,
6825 immh
, immb
, opcode
, rn
, rd
);
6827 case 0x12: /* SQSHRN, SQSHRN2, UQSHRN */
6828 case 0x13: /* SQRSHRN, SQRSHRN2, UQRSHRN, UQRSHRN2 */
6829 handle_vec_simd_sqshrn(s
, true, false, is_u
, is_u
,
6830 immh
, immb
, opcode
, rn
, rd
);
6832 case 0xc: /* SQSHLU */
6834 unallocated_encoding(s
);
6837 handle_simd_qshl(s
, true, false, false, true, immh
, immb
, rn
, rd
);
6839 case 0xe: /* SQSHL, UQSHL */
6840 handle_simd_qshl(s
, true, false, is_u
, is_u
, immh
, immb
, rn
, rd
);
6842 case 0x1f: /* FCVTZS, FCVTZU */
6843 handle_simd_shift_fpint_conv(s
, true, false, is_u
, immh
, immb
, rn
, rd
);
6846 unallocated_encoding(s
);
6851 /* C3.6.10 AdvSIMD scalar three different
6852 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
6853 * +-----+---+-----------+------+---+------+--------+-----+------+------+
6854 * | 0 1 | U | 1 1 1 1 0 | size | 1 | Rm | opcode | 0 0 | Rn | Rd |
6855 * +-----+---+-----------+------+---+------+--------+-----+------+------+
6857 static void disas_simd_scalar_three_reg_diff(DisasContext
*s
, uint32_t insn
)
6859 bool is_u
= extract32(insn
, 29, 1);
6860 int size
= extract32(insn
, 22, 2);
6861 int opcode
= extract32(insn
, 12, 4);
6862 int rm
= extract32(insn
, 16, 5);
6863 int rn
= extract32(insn
, 5, 5);
6864 int rd
= extract32(insn
, 0, 5);
6867 unallocated_encoding(s
);
6872 case 0x9: /* SQDMLAL, SQDMLAL2 */
6873 case 0xb: /* SQDMLSL, SQDMLSL2 */
6874 case 0xd: /* SQDMULL, SQDMULL2 */
6875 if (size
== 0 || size
== 3) {
6876 unallocated_encoding(s
);
6881 unallocated_encoding(s
);
6885 if (!fp_access_check(s
)) {
6890 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
6891 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
6892 TCGv_i64 tcg_res
= tcg_temp_new_i64();
6894 read_vec_element(s
, tcg_op1
, rn
, 0, MO_32
| MO_SIGN
);
6895 read_vec_element(s
, tcg_op2
, rm
, 0, MO_32
| MO_SIGN
);
6897 tcg_gen_mul_i64(tcg_res
, tcg_op1
, tcg_op2
);
6898 gen_helper_neon_addl_saturate_s64(tcg_res
, cpu_env
, tcg_res
, tcg_res
);
6901 case 0xd: /* SQDMULL, SQDMULL2 */
6903 case 0xb: /* SQDMLSL, SQDMLSL2 */
6904 tcg_gen_neg_i64(tcg_res
, tcg_res
);
6906 case 0x9: /* SQDMLAL, SQDMLAL2 */
6907 read_vec_element(s
, tcg_op1
, rd
, 0, MO_64
);
6908 gen_helper_neon_addl_saturate_s64(tcg_res
, cpu_env
,
6912 g_assert_not_reached();
6915 write_fp_dreg(s
, rd
, tcg_res
);
6917 tcg_temp_free_i64(tcg_op1
);
6918 tcg_temp_free_i64(tcg_op2
);
6919 tcg_temp_free_i64(tcg_res
);
6921 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
6922 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
6923 TCGv_i64 tcg_res
= tcg_temp_new_i64();
6925 read_vec_element_i32(s
, tcg_op1
, rn
, 0, MO_16
);
6926 read_vec_element_i32(s
, tcg_op2
, rm
, 0, MO_16
);
6928 gen_helper_neon_mull_s16(tcg_res
, tcg_op1
, tcg_op2
);
6929 gen_helper_neon_addl_saturate_s32(tcg_res
, cpu_env
, tcg_res
, tcg_res
);
6932 case 0xd: /* SQDMULL, SQDMULL2 */
6934 case 0xb: /* SQDMLSL, SQDMLSL2 */
6935 gen_helper_neon_negl_u32(tcg_res
, tcg_res
);
6937 case 0x9: /* SQDMLAL, SQDMLAL2 */
6939 TCGv_i64 tcg_op3
= tcg_temp_new_i64();
6940 read_vec_element(s
, tcg_op3
, rd
, 0, MO_32
);
6941 gen_helper_neon_addl_saturate_s32(tcg_res
, cpu_env
,
6943 tcg_temp_free_i64(tcg_op3
);
6947 g_assert_not_reached();
6950 tcg_gen_ext32u_i64(tcg_res
, tcg_res
);
6951 write_fp_dreg(s
, rd
, tcg_res
);
6953 tcg_temp_free_i32(tcg_op1
);
6954 tcg_temp_free_i32(tcg_op2
);
6955 tcg_temp_free_i64(tcg_res
);
6959 static void handle_3same_64(DisasContext
*s
, int opcode
, bool u
,
6960 TCGv_i64 tcg_rd
, TCGv_i64 tcg_rn
, TCGv_i64 tcg_rm
)
6962 /* Handle 64x64->64 opcodes which are shared between the scalar
6963 * and vector 3-same groups. We cover every opcode where size == 3
6964 * is valid in either the three-reg-same (integer, not pairwise)
6965 * or scalar-three-reg-same groups. (Some opcodes are not yet
6971 case 0x1: /* SQADD */
6973 gen_helper_neon_qadd_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
6975 gen_helper_neon_qadd_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
6978 case 0x5: /* SQSUB */
6980 gen_helper_neon_qsub_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
6982 gen_helper_neon_qsub_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
6985 case 0x6: /* CMGT, CMHI */
6986 /* 64 bit integer comparison, result = test ? (2^64 - 1) : 0.
6987 * We implement this using setcond (test) and then negating.
6989 cond
= u
? TCG_COND_GTU
: TCG_COND_GT
;
6991 tcg_gen_setcond_i64(cond
, tcg_rd
, tcg_rn
, tcg_rm
);
6992 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
6994 case 0x7: /* CMGE, CMHS */
6995 cond
= u
? TCG_COND_GEU
: TCG_COND_GE
;
6997 case 0x11: /* CMTST, CMEQ */
7002 /* CMTST : test is "if (X & Y != 0)". */
7003 tcg_gen_and_i64(tcg_rd
, tcg_rn
, tcg_rm
);
7004 tcg_gen_setcondi_i64(TCG_COND_NE
, tcg_rd
, tcg_rd
, 0);
7005 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
7007 case 0x8: /* SSHL, USHL */
7009 gen_helper_neon_shl_u64(tcg_rd
, tcg_rn
, tcg_rm
);
7011 gen_helper_neon_shl_s64(tcg_rd
, tcg_rn
, tcg_rm
);
7014 case 0x9: /* SQSHL, UQSHL */
7016 gen_helper_neon_qshl_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
7018 gen_helper_neon_qshl_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
7021 case 0xa: /* SRSHL, URSHL */
7023 gen_helper_neon_rshl_u64(tcg_rd
, tcg_rn
, tcg_rm
);
7025 gen_helper_neon_rshl_s64(tcg_rd
, tcg_rn
, tcg_rm
);
7028 case 0xb: /* SQRSHL, UQRSHL */
7030 gen_helper_neon_qrshl_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
7032 gen_helper_neon_qrshl_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
7035 case 0x10: /* ADD, SUB */
7037 tcg_gen_sub_i64(tcg_rd
, tcg_rn
, tcg_rm
);
7039 tcg_gen_add_i64(tcg_rd
, tcg_rn
, tcg_rm
);
7043 g_assert_not_reached();
7047 /* Handle the 3-same-operands float operations; shared by the scalar
7048 * and vector encodings. The caller must filter out any encodings
7049 * not allocated for the encoding it is dealing with.
7051 static void handle_3same_float(DisasContext
*s
, int size
, int elements
,
7052 int fpopcode
, int rd
, int rn
, int rm
)
7055 TCGv_ptr fpst
= get_fpstatus_ptr();
7057 for (pass
= 0; pass
< elements
; pass
++) {
7060 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
7061 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
7062 TCGv_i64 tcg_res
= tcg_temp_new_i64();
7064 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
7065 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
7068 case 0x39: /* FMLS */
7069 /* As usual for ARM, separate negation for fused multiply-add */
7070 gen_helper_vfp_negd(tcg_op1
, tcg_op1
);
7072 case 0x19: /* FMLA */
7073 read_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
7074 gen_helper_vfp_muladdd(tcg_res
, tcg_op1
, tcg_op2
,
7077 case 0x18: /* FMAXNM */
7078 gen_helper_vfp_maxnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7080 case 0x1a: /* FADD */
7081 gen_helper_vfp_addd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7083 case 0x1b: /* FMULX */
7084 gen_helper_vfp_mulxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7086 case 0x1c: /* FCMEQ */
7087 gen_helper_neon_ceq_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7089 case 0x1e: /* FMAX */
7090 gen_helper_vfp_maxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7092 case 0x1f: /* FRECPS */
7093 gen_helper_recpsf_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7095 case 0x38: /* FMINNM */
7096 gen_helper_vfp_minnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7098 case 0x3a: /* FSUB */
7099 gen_helper_vfp_subd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7101 case 0x3e: /* FMIN */
7102 gen_helper_vfp_mind(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7104 case 0x3f: /* FRSQRTS */
7105 gen_helper_rsqrtsf_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7107 case 0x5b: /* FMUL */
7108 gen_helper_vfp_muld(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7110 case 0x5c: /* FCMGE */
7111 gen_helper_neon_cge_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7113 case 0x5d: /* FACGE */
7114 gen_helper_neon_acge_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7116 case 0x5f: /* FDIV */
7117 gen_helper_vfp_divd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7119 case 0x7a: /* FABD */
7120 gen_helper_vfp_subd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7121 gen_helper_vfp_absd(tcg_res
, tcg_res
);
7123 case 0x7c: /* FCMGT */
7124 gen_helper_neon_cgt_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7126 case 0x7d: /* FACGT */
7127 gen_helper_neon_acgt_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7130 g_assert_not_reached();
7133 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
7135 tcg_temp_free_i64(tcg_res
);
7136 tcg_temp_free_i64(tcg_op1
);
7137 tcg_temp_free_i64(tcg_op2
);
7140 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
7141 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
7142 TCGv_i32 tcg_res
= tcg_temp_new_i32();
7144 read_vec_element_i32(s
, tcg_op1
, rn
, pass
, MO_32
);
7145 read_vec_element_i32(s
, tcg_op2
, rm
, pass
, MO_32
);
7148 case 0x39: /* FMLS */
7149 /* As usual for ARM, separate negation for fused multiply-add */
7150 gen_helper_vfp_negs(tcg_op1
, tcg_op1
);
7152 case 0x19: /* FMLA */
7153 read_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
7154 gen_helper_vfp_muladds(tcg_res
, tcg_op1
, tcg_op2
,
7157 case 0x1a: /* FADD */
7158 gen_helper_vfp_adds(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7160 case 0x1b: /* FMULX */
7161 gen_helper_vfp_mulxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7163 case 0x1c: /* FCMEQ */
7164 gen_helper_neon_ceq_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7166 case 0x1e: /* FMAX */
7167 gen_helper_vfp_maxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7169 case 0x1f: /* FRECPS */
7170 gen_helper_recpsf_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7172 case 0x18: /* FMAXNM */
7173 gen_helper_vfp_maxnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7175 case 0x38: /* FMINNM */
7176 gen_helper_vfp_minnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7178 case 0x3a: /* FSUB */
7179 gen_helper_vfp_subs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7181 case 0x3e: /* FMIN */
7182 gen_helper_vfp_mins(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7184 case 0x3f: /* FRSQRTS */
7185 gen_helper_rsqrtsf_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7187 case 0x5b: /* FMUL */
7188 gen_helper_vfp_muls(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7190 case 0x5c: /* FCMGE */
7191 gen_helper_neon_cge_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7193 case 0x5d: /* FACGE */
7194 gen_helper_neon_acge_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7196 case 0x5f: /* FDIV */
7197 gen_helper_vfp_divs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7199 case 0x7a: /* FABD */
7200 gen_helper_vfp_subs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7201 gen_helper_vfp_abss(tcg_res
, tcg_res
);
7203 case 0x7c: /* FCMGT */
7204 gen_helper_neon_cgt_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7206 case 0x7d: /* FACGT */
7207 gen_helper_neon_acgt_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7210 g_assert_not_reached();
7213 if (elements
== 1) {
7214 /* scalar single so clear high part */
7215 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
7217 tcg_gen_extu_i32_i64(tcg_tmp
, tcg_res
);
7218 write_vec_element(s
, tcg_tmp
, rd
, pass
, MO_64
);
7219 tcg_temp_free_i64(tcg_tmp
);
7221 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
7224 tcg_temp_free_i32(tcg_res
);
7225 tcg_temp_free_i32(tcg_op1
);
7226 tcg_temp_free_i32(tcg_op2
);
7230 tcg_temp_free_ptr(fpst
);
7232 if ((elements
<< size
) < 4) {
7233 /* scalar, or non-quad vector op */
7234 clear_vec_high(s
, rd
);
7238 /* C3.6.11 AdvSIMD scalar three same
7239 * 31 30 29 28 24 23 22 21 20 16 15 11 10 9 5 4 0
7240 * +-----+---+-----------+------+---+------+--------+---+------+------+
7241 * | 0 1 | U | 1 1 1 1 0 | size | 1 | Rm | opcode | 1 | Rn | Rd |
7242 * +-----+---+-----------+------+---+------+--------+---+------+------+
7244 static void disas_simd_scalar_three_reg_same(DisasContext
*s
, uint32_t insn
)
7246 int rd
= extract32(insn
, 0, 5);
7247 int rn
= extract32(insn
, 5, 5);
7248 int opcode
= extract32(insn
, 11, 5);
7249 int rm
= extract32(insn
, 16, 5);
7250 int size
= extract32(insn
, 22, 2);
7251 bool u
= extract32(insn
, 29, 1);
7254 if (opcode
>= 0x18) {
7255 /* Floating point: U, size[1] and opcode indicate operation */
7256 int fpopcode
= opcode
| (extract32(size
, 1, 1) << 5) | (u
<< 6);
7258 case 0x1b: /* FMULX */
7259 case 0x1f: /* FRECPS */
7260 case 0x3f: /* FRSQRTS */
7261 case 0x5d: /* FACGE */
7262 case 0x7d: /* FACGT */
7263 case 0x1c: /* FCMEQ */
7264 case 0x5c: /* FCMGE */
7265 case 0x7c: /* FCMGT */
7266 case 0x7a: /* FABD */
7269 unallocated_encoding(s
);
7273 if (!fp_access_check(s
)) {
7277 handle_3same_float(s
, extract32(size
, 0, 1), 1, fpopcode
, rd
, rn
, rm
);
7282 case 0x1: /* SQADD, UQADD */
7283 case 0x5: /* SQSUB, UQSUB */
7284 case 0x9: /* SQSHL, UQSHL */
7285 case 0xb: /* SQRSHL, UQRSHL */
7287 case 0x8: /* SSHL, USHL */
7288 case 0xa: /* SRSHL, URSHL */
7289 case 0x6: /* CMGT, CMHI */
7290 case 0x7: /* CMGE, CMHS */
7291 case 0x11: /* CMTST, CMEQ */
7292 case 0x10: /* ADD, SUB (vector) */
7294 unallocated_encoding(s
);
7298 case 0x16: /* SQDMULH, SQRDMULH (vector) */
7299 if (size
!= 1 && size
!= 2) {
7300 unallocated_encoding(s
);
7305 unallocated_encoding(s
);
7309 if (!fp_access_check(s
)) {
7313 tcg_rd
= tcg_temp_new_i64();
7316 TCGv_i64 tcg_rn
= read_fp_dreg(s
, rn
);
7317 TCGv_i64 tcg_rm
= read_fp_dreg(s
, rm
);
7319 handle_3same_64(s
, opcode
, u
, tcg_rd
, tcg_rn
, tcg_rm
);
7320 tcg_temp_free_i64(tcg_rn
);
7321 tcg_temp_free_i64(tcg_rm
);
7323 /* Do a single operation on the lowest element in the vector.
7324 * We use the standard Neon helpers and rely on 0 OP 0 == 0 with
7325 * no side effects for all these operations.
7326 * OPTME: special-purpose helpers would avoid doing some
7327 * unnecessary work in the helper for the 8 and 16 bit cases.
7329 NeonGenTwoOpEnvFn
*genenvfn
;
7330 TCGv_i32 tcg_rn
= tcg_temp_new_i32();
7331 TCGv_i32 tcg_rm
= tcg_temp_new_i32();
7332 TCGv_i32 tcg_rd32
= tcg_temp_new_i32();
7334 read_vec_element_i32(s
, tcg_rn
, rn
, 0, size
);
7335 read_vec_element_i32(s
, tcg_rm
, rm
, 0, size
);
7338 case 0x1: /* SQADD, UQADD */
7340 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
7341 { gen_helper_neon_qadd_s8
, gen_helper_neon_qadd_u8
},
7342 { gen_helper_neon_qadd_s16
, gen_helper_neon_qadd_u16
},
7343 { gen_helper_neon_qadd_s32
, gen_helper_neon_qadd_u32
},
7345 genenvfn
= fns
[size
][u
];
7348 case 0x5: /* SQSUB, UQSUB */
7350 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
7351 { gen_helper_neon_qsub_s8
, gen_helper_neon_qsub_u8
},
7352 { gen_helper_neon_qsub_s16
, gen_helper_neon_qsub_u16
},
7353 { gen_helper_neon_qsub_s32
, gen_helper_neon_qsub_u32
},
7355 genenvfn
= fns
[size
][u
];
7358 case 0x9: /* SQSHL, UQSHL */
7360 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
7361 { gen_helper_neon_qshl_s8
, gen_helper_neon_qshl_u8
},
7362 { gen_helper_neon_qshl_s16
, gen_helper_neon_qshl_u16
},
7363 { gen_helper_neon_qshl_s32
, gen_helper_neon_qshl_u32
},
7365 genenvfn
= fns
[size
][u
];
7368 case 0xb: /* SQRSHL, UQRSHL */
7370 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
7371 { gen_helper_neon_qrshl_s8
, gen_helper_neon_qrshl_u8
},
7372 { gen_helper_neon_qrshl_s16
, gen_helper_neon_qrshl_u16
},
7373 { gen_helper_neon_qrshl_s32
, gen_helper_neon_qrshl_u32
},
7375 genenvfn
= fns
[size
][u
];
7378 case 0x16: /* SQDMULH, SQRDMULH */
7380 static NeonGenTwoOpEnvFn
* const fns
[2][2] = {
7381 { gen_helper_neon_qdmulh_s16
, gen_helper_neon_qrdmulh_s16
},
7382 { gen_helper_neon_qdmulh_s32
, gen_helper_neon_qrdmulh_s32
},
7384 assert(size
== 1 || size
== 2);
7385 genenvfn
= fns
[size
- 1][u
];
7389 g_assert_not_reached();
7392 genenvfn(tcg_rd32
, cpu_env
, tcg_rn
, tcg_rm
);
7393 tcg_gen_extu_i32_i64(tcg_rd
, tcg_rd32
);
7394 tcg_temp_free_i32(tcg_rd32
);
7395 tcg_temp_free_i32(tcg_rn
);
7396 tcg_temp_free_i32(tcg_rm
);
7399 write_fp_dreg(s
, rd
, tcg_rd
);
7401 tcg_temp_free_i64(tcg_rd
);
7404 static void handle_2misc_64(DisasContext
*s
, int opcode
, bool u
,
7405 TCGv_i64 tcg_rd
, TCGv_i64 tcg_rn
,
7406 TCGv_i32 tcg_rmode
, TCGv_ptr tcg_fpstatus
)
7408 /* Handle 64->64 opcodes which are shared between the scalar and
7409 * vector 2-reg-misc groups. We cover every integer opcode where size == 3
7410 * is valid in either group and also the double-precision fp ops.
7411 * The caller only need provide tcg_rmode and tcg_fpstatus if the op
7417 case 0x4: /* CLS, CLZ */
7419 gen_helper_clz64(tcg_rd
, tcg_rn
);
7421 gen_helper_cls64(tcg_rd
, tcg_rn
);
7425 /* This opcode is shared with CNT and RBIT but we have earlier
7426 * enforced that size == 3 if and only if this is the NOT insn.
7428 tcg_gen_not_i64(tcg_rd
, tcg_rn
);
7430 case 0x7: /* SQABS, SQNEG */
7432 gen_helper_neon_qneg_s64(tcg_rd
, cpu_env
, tcg_rn
);
7434 gen_helper_neon_qabs_s64(tcg_rd
, cpu_env
, tcg_rn
);
7437 case 0xa: /* CMLT */
7438 /* 64 bit integer comparison against zero, result is
7439 * test ? (2^64 - 1) : 0. We implement via setcond(!test) and
7444 tcg_gen_setcondi_i64(cond
, tcg_rd
, tcg_rn
, 0);
7445 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
7447 case 0x8: /* CMGT, CMGE */
7448 cond
= u
? TCG_COND_GE
: TCG_COND_GT
;
7450 case 0x9: /* CMEQ, CMLE */
7451 cond
= u
? TCG_COND_LE
: TCG_COND_EQ
;
7453 case 0xb: /* ABS, NEG */
7455 tcg_gen_neg_i64(tcg_rd
, tcg_rn
);
7457 TCGv_i64 tcg_zero
= tcg_const_i64(0);
7458 tcg_gen_neg_i64(tcg_rd
, tcg_rn
);
7459 tcg_gen_movcond_i64(TCG_COND_GT
, tcg_rd
, tcg_rn
, tcg_zero
,
7461 tcg_temp_free_i64(tcg_zero
);
7464 case 0x2f: /* FABS */
7465 gen_helper_vfp_absd(tcg_rd
, tcg_rn
);
7467 case 0x6f: /* FNEG */
7468 gen_helper_vfp_negd(tcg_rd
, tcg_rn
);
7470 case 0x7f: /* FSQRT */
7471 gen_helper_vfp_sqrtd(tcg_rd
, tcg_rn
, cpu_env
);
7473 case 0x1a: /* FCVTNS */
7474 case 0x1b: /* FCVTMS */
7475 case 0x1c: /* FCVTAS */
7476 case 0x3a: /* FCVTPS */
7477 case 0x3b: /* FCVTZS */
7479 TCGv_i32 tcg_shift
= tcg_const_i32(0);
7480 gen_helper_vfp_tosqd(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
7481 tcg_temp_free_i32(tcg_shift
);
7484 case 0x5a: /* FCVTNU */
7485 case 0x5b: /* FCVTMU */
7486 case 0x5c: /* FCVTAU */
7487 case 0x7a: /* FCVTPU */
7488 case 0x7b: /* FCVTZU */
7490 TCGv_i32 tcg_shift
= tcg_const_i32(0);
7491 gen_helper_vfp_touqd(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
7492 tcg_temp_free_i32(tcg_shift
);
7495 case 0x18: /* FRINTN */
7496 case 0x19: /* FRINTM */
7497 case 0x38: /* FRINTP */
7498 case 0x39: /* FRINTZ */
7499 case 0x58: /* FRINTA */
7500 case 0x79: /* FRINTI */
7501 gen_helper_rintd(tcg_rd
, tcg_rn
, tcg_fpstatus
);
7503 case 0x59: /* FRINTX */
7504 gen_helper_rintd_exact(tcg_rd
, tcg_rn
, tcg_fpstatus
);
7507 g_assert_not_reached();
7511 static void handle_2misc_fcmp_zero(DisasContext
*s
, int opcode
,
7512 bool is_scalar
, bool is_u
, bool is_q
,
7513 int size
, int rn
, int rd
)
7515 bool is_double
= (size
== 3);
7518 if (!fp_access_check(s
)) {
7522 fpst
= get_fpstatus_ptr();
7525 TCGv_i64 tcg_op
= tcg_temp_new_i64();
7526 TCGv_i64 tcg_zero
= tcg_const_i64(0);
7527 TCGv_i64 tcg_res
= tcg_temp_new_i64();
7528 NeonGenTwoDoubleOPFn
*genfn
;
7533 case 0x2e: /* FCMLT (zero) */
7536 case 0x2c: /* FCMGT (zero) */
7537 genfn
= gen_helper_neon_cgt_f64
;
7539 case 0x2d: /* FCMEQ (zero) */
7540 genfn
= gen_helper_neon_ceq_f64
;
7542 case 0x6d: /* FCMLE (zero) */
7545 case 0x6c: /* FCMGE (zero) */
7546 genfn
= gen_helper_neon_cge_f64
;
7549 g_assert_not_reached();
7552 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
7553 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
7555 genfn(tcg_res
, tcg_zero
, tcg_op
, fpst
);
7557 genfn(tcg_res
, tcg_op
, tcg_zero
, fpst
);
7559 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
7562 clear_vec_high(s
, rd
);
7565 tcg_temp_free_i64(tcg_res
);
7566 tcg_temp_free_i64(tcg_zero
);
7567 tcg_temp_free_i64(tcg_op
);
7569 TCGv_i32 tcg_op
= tcg_temp_new_i32();
7570 TCGv_i32 tcg_zero
= tcg_const_i32(0);
7571 TCGv_i32 tcg_res
= tcg_temp_new_i32();
7572 NeonGenTwoSingleOPFn
*genfn
;
7574 int pass
, maxpasses
;
7577 case 0x2e: /* FCMLT (zero) */
7580 case 0x2c: /* FCMGT (zero) */
7581 genfn
= gen_helper_neon_cgt_f32
;
7583 case 0x2d: /* FCMEQ (zero) */
7584 genfn
= gen_helper_neon_ceq_f32
;
7586 case 0x6d: /* FCMLE (zero) */
7589 case 0x6c: /* FCMGE (zero) */
7590 genfn
= gen_helper_neon_cge_f32
;
7593 g_assert_not_reached();
7599 maxpasses
= is_q
? 4 : 2;
7602 for (pass
= 0; pass
< maxpasses
; pass
++) {
7603 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_32
);
7605 genfn(tcg_res
, tcg_zero
, tcg_op
, fpst
);
7607 genfn(tcg_res
, tcg_op
, tcg_zero
, fpst
);
7610 write_fp_sreg(s
, rd
, tcg_res
);
7612 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
7615 tcg_temp_free_i32(tcg_res
);
7616 tcg_temp_free_i32(tcg_zero
);
7617 tcg_temp_free_i32(tcg_op
);
7618 if (!is_q
&& !is_scalar
) {
7619 clear_vec_high(s
, rd
);
7623 tcg_temp_free_ptr(fpst
);
7626 static void handle_2misc_reciprocal(DisasContext
*s
, int opcode
,
7627 bool is_scalar
, bool is_u
, bool is_q
,
7628 int size
, int rn
, int rd
)
7630 bool is_double
= (size
== 3);
7631 TCGv_ptr fpst
= get_fpstatus_ptr();
7634 TCGv_i64 tcg_op
= tcg_temp_new_i64();
7635 TCGv_i64 tcg_res
= tcg_temp_new_i64();
7638 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
7639 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
7641 case 0x3d: /* FRECPE */
7642 gen_helper_recpe_f64(tcg_res
, tcg_op
, fpst
);
7644 case 0x3f: /* FRECPX */
7645 gen_helper_frecpx_f64(tcg_res
, tcg_op
, fpst
);
7647 case 0x7d: /* FRSQRTE */
7648 gen_helper_rsqrte_f64(tcg_res
, tcg_op
, fpst
);
7651 g_assert_not_reached();
7653 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
7656 clear_vec_high(s
, rd
);
7659 tcg_temp_free_i64(tcg_res
);
7660 tcg_temp_free_i64(tcg_op
);
7662 TCGv_i32 tcg_op
= tcg_temp_new_i32();
7663 TCGv_i32 tcg_res
= tcg_temp_new_i32();
7664 int pass
, maxpasses
;
7669 maxpasses
= is_q
? 4 : 2;
7672 for (pass
= 0; pass
< maxpasses
; pass
++) {
7673 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_32
);
7676 case 0x3c: /* URECPE */
7677 gen_helper_recpe_u32(tcg_res
, tcg_op
, fpst
);
7679 case 0x3d: /* FRECPE */
7680 gen_helper_recpe_f32(tcg_res
, tcg_op
, fpst
);
7682 case 0x3f: /* FRECPX */
7683 gen_helper_frecpx_f32(tcg_res
, tcg_op
, fpst
);
7685 case 0x7d: /* FRSQRTE */
7686 gen_helper_rsqrte_f32(tcg_res
, tcg_op
, fpst
);
7689 g_assert_not_reached();
7693 write_fp_sreg(s
, rd
, tcg_res
);
7695 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
7698 tcg_temp_free_i32(tcg_res
);
7699 tcg_temp_free_i32(tcg_op
);
7700 if (!is_q
&& !is_scalar
) {
7701 clear_vec_high(s
, rd
);
7704 tcg_temp_free_ptr(fpst
);
7707 static void handle_2misc_narrow(DisasContext
*s
, bool scalar
,
7708 int opcode
, bool u
, bool is_q
,
7709 int size
, int rn
, int rd
)
7711 /* Handle 2-reg-misc ops which are narrowing (so each 2*size element
7712 * in the source becomes a size element in the destination).
7715 TCGv_i32 tcg_res
[2];
7716 int destelt
= is_q
? 2 : 0;
7717 int passes
= scalar
? 1 : 2;
7720 tcg_res
[1] = tcg_const_i32(0);
7723 for (pass
= 0; pass
< passes
; pass
++) {
7724 TCGv_i64 tcg_op
= tcg_temp_new_i64();
7725 NeonGenNarrowFn
*genfn
= NULL
;
7726 NeonGenNarrowEnvFn
*genenvfn
= NULL
;
7729 read_vec_element(s
, tcg_op
, rn
, pass
, size
+ 1);
7731 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
7733 tcg_res
[pass
] = tcg_temp_new_i32();
7736 case 0x12: /* XTN, SQXTUN */
7738 static NeonGenNarrowFn
* const xtnfns
[3] = {
7739 gen_helper_neon_narrow_u8
,
7740 gen_helper_neon_narrow_u16
,
7741 tcg_gen_extrl_i64_i32
,
7743 static NeonGenNarrowEnvFn
* const sqxtunfns
[3] = {
7744 gen_helper_neon_unarrow_sat8
,
7745 gen_helper_neon_unarrow_sat16
,
7746 gen_helper_neon_unarrow_sat32
,
7749 genenvfn
= sqxtunfns
[size
];
7751 genfn
= xtnfns
[size
];
7755 case 0x14: /* SQXTN, UQXTN */
7757 static NeonGenNarrowEnvFn
* const fns
[3][2] = {
7758 { gen_helper_neon_narrow_sat_s8
,
7759 gen_helper_neon_narrow_sat_u8
},
7760 { gen_helper_neon_narrow_sat_s16
,
7761 gen_helper_neon_narrow_sat_u16
},
7762 { gen_helper_neon_narrow_sat_s32
,
7763 gen_helper_neon_narrow_sat_u32
},
7765 genenvfn
= fns
[size
][u
];
7768 case 0x16: /* FCVTN, FCVTN2 */
7769 /* 32 bit to 16 bit or 64 bit to 32 bit float conversion */
7771 gen_helper_vfp_fcvtsd(tcg_res
[pass
], tcg_op
, cpu_env
);
7773 TCGv_i32 tcg_lo
= tcg_temp_new_i32();
7774 TCGv_i32 tcg_hi
= tcg_temp_new_i32();
7775 tcg_gen_extr_i64_i32(tcg_lo
, tcg_hi
, tcg_op
);
7776 gen_helper_vfp_fcvt_f32_to_f16(tcg_lo
, tcg_lo
, cpu_env
);
7777 gen_helper_vfp_fcvt_f32_to_f16(tcg_hi
, tcg_hi
, cpu_env
);
7778 tcg_gen_deposit_i32(tcg_res
[pass
], tcg_lo
, tcg_hi
, 16, 16);
7779 tcg_temp_free_i32(tcg_lo
);
7780 tcg_temp_free_i32(tcg_hi
);
7783 case 0x56: /* FCVTXN, FCVTXN2 */
7784 /* 64 bit to 32 bit float conversion
7785 * with von Neumann rounding (round to odd)
7788 gen_helper_fcvtx_f64_to_f32(tcg_res
[pass
], tcg_op
, cpu_env
);
7791 g_assert_not_reached();
7795 genfn(tcg_res
[pass
], tcg_op
);
7796 } else if (genenvfn
) {
7797 genenvfn(tcg_res
[pass
], cpu_env
, tcg_op
);
7800 tcg_temp_free_i64(tcg_op
);
7803 for (pass
= 0; pass
< 2; pass
++) {
7804 write_vec_element_i32(s
, tcg_res
[pass
], rd
, destelt
+ pass
, MO_32
);
7805 tcg_temp_free_i32(tcg_res
[pass
]);
7808 clear_vec_high(s
, rd
);
7812 /* Remaining saturating accumulating ops */
7813 static void handle_2misc_satacc(DisasContext
*s
, bool is_scalar
, bool is_u
,
7814 bool is_q
, int size
, int rn
, int rd
)
7816 bool is_double
= (size
== 3);
7819 TCGv_i64 tcg_rn
= tcg_temp_new_i64();
7820 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
7823 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
7824 read_vec_element(s
, tcg_rn
, rn
, pass
, MO_64
);
7825 read_vec_element(s
, tcg_rd
, rd
, pass
, MO_64
);
7827 if (is_u
) { /* USQADD */
7828 gen_helper_neon_uqadd_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
7829 } else { /* SUQADD */
7830 gen_helper_neon_sqadd_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
7832 write_vec_element(s
, tcg_rd
, rd
, pass
, MO_64
);
7835 clear_vec_high(s
, rd
);
7838 tcg_temp_free_i64(tcg_rd
);
7839 tcg_temp_free_i64(tcg_rn
);
7841 TCGv_i32 tcg_rn
= tcg_temp_new_i32();
7842 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
7843 int pass
, maxpasses
;
7848 maxpasses
= is_q
? 4 : 2;
7851 for (pass
= 0; pass
< maxpasses
; pass
++) {
7853 read_vec_element_i32(s
, tcg_rn
, rn
, pass
, size
);
7854 read_vec_element_i32(s
, tcg_rd
, rd
, pass
, size
);
7856 read_vec_element_i32(s
, tcg_rn
, rn
, pass
, MO_32
);
7857 read_vec_element_i32(s
, tcg_rd
, rd
, pass
, MO_32
);
7860 if (is_u
) { /* USQADD */
7863 gen_helper_neon_uqadd_s8(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
7866 gen_helper_neon_uqadd_s16(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
7869 gen_helper_neon_uqadd_s32(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
7872 g_assert_not_reached();
7874 } else { /* SUQADD */
7877 gen_helper_neon_sqadd_u8(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
7880 gen_helper_neon_sqadd_u16(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
7883 gen_helper_neon_sqadd_u32(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
7886 g_assert_not_reached();
7891 TCGv_i64 tcg_zero
= tcg_const_i64(0);
7892 write_vec_element(s
, tcg_zero
, rd
, 0, MO_64
);
7893 tcg_temp_free_i64(tcg_zero
);
7895 write_vec_element_i32(s
, tcg_rd
, rd
, pass
, MO_32
);
7899 clear_vec_high(s
, rd
);
7902 tcg_temp_free_i32(tcg_rd
);
7903 tcg_temp_free_i32(tcg_rn
);
7907 /* C3.6.12 AdvSIMD scalar two reg misc
7908 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
7909 * +-----+---+-----------+------+-----------+--------+-----+------+------+
7910 * | 0 1 | U | 1 1 1 1 0 | size | 1 0 0 0 0 | opcode | 1 0 | Rn | Rd |
7911 * +-----+---+-----------+------+-----------+--------+-----+------+------+
7913 static void disas_simd_scalar_two_reg_misc(DisasContext
*s
, uint32_t insn
)
7915 int rd
= extract32(insn
, 0, 5);
7916 int rn
= extract32(insn
, 5, 5);
7917 int opcode
= extract32(insn
, 12, 5);
7918 int size
= extract32(insn
, 22, 2);
7919 bool u
= extract32(insn
, 29, 1);
7920 bool is_fcvt
= false;
7923 TCGv_ptr tcg_fpstatus
;
7926 case 0x3: /* USQADD / SUQADD*/
7927 if (!fp_access_check(s
)) {
7930 handle_2misc_satacc(s
, true, u
, false, size
, rn
, rd
);
7932 case 0x7: /* SQABS / SQNEG */
7934 case 0xa: /* CMLT */
7936 unallocated_encoding(s
);
7940 case 0x8: /* CMGT, CMGE */
7941 case 0x9: /* CMEQ, CMLE */
7942 case 0xb: /* ABS, NEG */
7944 unallocated_encoding(s
);
7948 case 0x12: /* SQXTUN */
7950 unallocated_encoding(s
);
7954 case 0x14: /* SQXTN, UQXTN */
7956 unallocated_encoding(s
);
7959 if (!fp_access_check(s
)) {
7962 handle_2misc_narrow(s
, true, opcode
, u
, false, size
, rn
, rd
);
7967 /* Floating point: U, size[1] and opcode indicate operation;
7968 * size[0] indicates single or double precision.
7970 opcode
|= (extract32(size
, 1, 1) << 5) | (u
<< 6);
7971 size
= extract32(size
, 0, 1) ? 3 : 2;
7973 case 0x2c: /* FCMGT (zero) */
7974 case 0x2d: /* FCMEQ (zero) */
7975 case 0x2e: /* FCMLT (zero) */
7976 case 0x6c: /* FCMGE (zero) */
7977 case 0x6d: /* FCMLE (zero) */
7978 handle_2misc_fcmp_zero(s
, opcode
, true, u
, true, size
, rn
, rd
);
7980 case 0x1d: /* SCVTF */
7981 case 0x5d: /* UCVTF */
7983 bool is_signed
= (opcode
== 0x1d);
7984 if (!fp_access_check(s
)) {
7987 handle_simd_intfp_conv(s
, rd
, rn
, 1, is_signed
, 0, size
);
7990 case 0x3d: /* FRECPE */
7991 case 0x3f: /* FRECPX */
7992 case 0x7d: /* FRSQRTE */
7993 if (!fp_access_check(s
)) {
7996 handle_2misc_reciprocal(s
, opcode
, true, u
, true, size
, rn
, rd
);
7998 case 0x1a: /* FCVTNS */
7999 case 0x1b: /* FCVTMS */
8000 case 0x3a: /* FCVTPS */
8001 case 0x3b: /* FCVTZS */
8002 case 0x5a: /* FCVTNU */
8003 case 0x5b: /* FCVTMU */
8004 case 0x7a: /* FCVTPU */
8005 case 0x7b: /* FCVTZU */
8007 rmode
= extract32(opcode
, 5, 1) | (extract32(opcode
, 0, 1) << 1);
8009 case 0x1c: /* FCVTAS */
8010 case 0x5c: /* FCVTAU */
8011 /* TIEAWAY doesn't fit in the usual rounding mode encoding */
8013 rmode
= FPROUNDING_TIEAWAY
;
8015 case 0x56: /* FCVTXN, FCVTXN2 */
8017 unallocated_encoding(s
);
8020 if (!fp_access_check(s
)) {
8023 handle_2misc_narrow(s
, true, opcode
, u
, false, size
- 1, rn
, rd
);
8026 unallocated_encoding(s
);
8031 unallocated_encoding(s
);
8035 if (!fp_access_check(s
)) {
8040 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
8041 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
8042 tcg_fpstatus
= get_fpstatus_ptr();
8044 TCGV_UNUSED_I32(tcg_rmode
);
8045 TCGV_UNUSED_PTR(tcg_fpstatus
);
8049 TCGv_i64 tcg_rn
= read_fp_dreg(s
, rn
);
8050 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
8052 handle_2misc_64(s
, opcode
, u
, tcg_rd
, tcg_rn
, tcg_rmode
, tcg_fpstatus
);
8053 write_fp_dreg(s
, rd
, tcg_rd
);
8054 tcg_temp_free_i64(tcg_rd
);
8055 tcg_temp_free_i64(tcg_rn
);
8057 TCGv_i32 tcg_rn
= tcg_temp_new_i32();
8058 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
8060 read_vec_element_i32(s
, tcg_rn
, rn
, 0, size
);
8063 case 0x7: /* SQABS, SQNEG */
8065 NeonGenOneOpEnvFn
*genfn
;
8066 static NeonGenOneOpEnvFn
* const fns
[3][2] = {
8067 { gen_helper_neon_qabs_s8
, gen_helper_neon_qneg_s8
},
8068 { gen_helper_neon_qabs_s16
, gen_helper_neon_qneg_s16
},
8069 { gen_helper_neon_qabs_s32
, gen_helper_neon_qneg_s32
},
8071 genfn
= fns
[size
][u
];
8072 genfn(tcg_rd
, cpu_env
, tcg_rn
);
8075 case 0x1a: /* FCVTNS */
8076 case 0x1b: /* FCVTMS */
8077 case 0x1c: /* FCVTAS */
8078 case 0x3a: /* FCVTPS */
8079 case 0x3b: /* FCVTZS */
8081 TCGv_i32 tcg_shift
= tcg_const_i32(0);
8082 gen_helper_vfp_tosls(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
8083 tcg_temp_free_i32(tcg_shift
);
8086 case 0x5a: /* FCVTNU */
8087 case 0x5b: /* FCVTMU */
8088 case 0x5c: /* FCVTAU */
8089 case 0x7a: /* FCVTPU */
8090 case 0x7b: /* FCVTZU */
8092 TCGv_i32 tcg_shift
= tcg_const_i32(0);
8093 gen_helper_vfp_touls(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
8094 tcg_temp_free_i32(tcg_shift
);
8098 g_assert_not_reached();
8101 write_fp_sreg(s
, rd
, tcg_rd
);
8102 tcg_temp_free_i32(tcg_rd
);
8103 tcg_temp_free_i32(tcg_rn
);
8107 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
8108 tcg_temp_free_i32(tcg_rmode
);
8109 tcg_temp_free_ptr(tcg_fpstatus
);
8113 /* SSHR[RA]/USHR[RA] - Vector shift right (optional rounding/accumulate) */
8114 static void handle_vec_simd_shri(DisasContext
*s
, bool is_q
, bool is_u
,
8115 int immh
, int immb
, int opcode
, int rn
, int rd
)
8117 int size
= 32 - clz32(immh
) - 1;
8118 int immhb
= immh
<< 3 | immb
;
8119 int shift
= 2 * (8 << size
) - immhb
;
8120 bool accumulate
= false;
8122 bool insert
= false;
8123 int dsize
= is_q
? 128 : 64;
8124 int esize
= 8 << size
;
8125 int elements
= dsize
/esize
;
8126 TCGMemOp memop
= size
| (is_u
? 0 : MO_SIGN
);
8127 TCGv_i64 tcg_rn
= new_tmp_a64(s
);
8128 TCGv_i64 tcg_rd
= new_tmp_a64(s
);
8132 if (extract32(immh
, 3, 1) && !is_q
) {
8133 unallocated_encoding(s
);
8137 if (size
> 3 && !is_q
) {
8138 unallocated_encoding(s
);
8142 if (!fp_access_check(s
)) {
8147 case 0x02: /* SSRA / USRA (accumulate) */
8150 case 0x04: /* SRSHR / URSHR (rounding) */
8153 case 0x06: /* SRSRA / URSRA (accum + rounding) */
8154 accumulate
= round
= true;
8156 case 0x08: /* SRI */
8162 uint64_t round_const
= 1ULL << (shift
- 1);
8163 tcg_round
= tcg_const_i64(round_const
);
8165 TCGV_UNUSED_I64(tcg_round
);
8168 for (i
= 0; i
< elements
; i
++) {
8169 read_vec_element(s
, tcg_rn
, rn
, i
, memop
);
8170 if (accumulate
|| insert
) {
8171 read_vec_element(s
, tcg_rd
, rd
, i
, memop
);
8175 handle_shri_with_ins(tcg_rd
, tcg_rn
, size
, shift
);
8177 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
8178 accumulate
, is_u
, size
, shift
);
8181 write_vec_element(s
, tcg_rd
, rd
, i
, size
);
8185 clear_vec_high(s
, rd
);
8189 tcg_temp_free_i64(tcg_round
);
8193 /* SHL/SLI - Vector shift left */
8194 static void handle_vec_simd_shli(DisasContext
*s
, bool is_q
, bool insert
,
8195 int immh
, int immb
, int opcode
, int rn
, int rd
)
8197 int size
= 32 - clz32(immh
) - 1;
8198 int immhb
= immh
<< 3 | immb
;
8199 int shift
= immhb
- (8 << size
);
8200 int dsize
= is_q
? 128 : 64;
8201 int esize
= 8 << size
;
8202 int elements
= dsize
/esize
;
8203 TCGv_i64 tcg_rn
= new_tmp_a64(s
);
8204 TCGv_i64 tcg_rd
= new_tmp_a64(s
);
8207 if (extract32(immh
, 3, 1) && !is_q
) {
8208 unallocated_encoding(s
);
8212 if (size
> 3 && !is_q
) {
8213 unallocated_encoding(s
);
8217 if (!fp_access_check(s
)) {
8221 for (i
= 0; i
< elements
; i
++) {
8222 read_vec_element(s
, tcg_rn
, rn
, i
, size
);
8224 read_vec_element(s
, tcg_rd
, rd
, i
, size
);
8227 handle_shli_with_ins(tcg_rd
, tcg_rn
, insert
, shift
);
8229 write_vec_element(s
, tcg_rd
, rd
, i
, size
);
8233 clear_vec_high(s
, rd
);
8237 /* USHLL/SHLL - Vector shift left with widening */
8238 static void handle_vec_simd_wshli(DisasContext
*s
, bool is_q
, bool is_u
,
8239 int immh
, int immb
, int opcode
, int rn
, int rd
)
8241 int size
= 32 - clz32(immh
) - 1;
8242 int immhb
= immh
<< 3 | immb
;
8243 int shift
= immhb
- (8 << size
);
8245 int esize
= 8 << size
;
8246 int elements
= dsize
/esize
;
8247 TCGv_i64 tcg_rn
= new_tmp_a64(s
);
8248 TCGv_i64 tcg_rd
= new_tmp_a64(s
);
8252 unallocated_encoding(s
);
8256 if (!fp_access_check(s
)) {
8260 /* For the LL variants the store is larger than the load,
8261 * so if rd == rn we would overwrite parts of our input.
8262 * So load everything right now and use shifts in the main loop.
8264 read_vec_element(s
, tcg_rn
, rn
, is_q
? 1 : 0, MO_64
);
8266 for (i
= 0; i
< elements
; i
++) {
8267 tcg_gen_shri_i64(tcg_rd
, tcg_rn
, i
* esize
);
8268 ext_and_shift_reg(tcg_rd
, tcg_rd
, size
| (!is_u
<< 2), 0);
8269 tcg_gen_shli_i64(tcg_rd
, tcg_rd
, shift
);
8270 write_vec_element(s
, tcg_rd
, rd
, i
, size
+ 1);
8274 /* SHRN/RSHRN - Shift right with narrowing (and potential rounding) */
8275 static void handle_vec_simd_shrn(DisasContext
*s
, bool is_q
,
8276 int immh
, int immb
, int opcode
, int rn
, int rd
)
8278 int immhb
= immh
<< 3 | immb
;
8279 int size
= 32 - clz32(immh
) - 1;
8281 int esize
= 8 << size
;
8282 int elements
= dsize
/esize
;
8283 int shift
= (2 * esize
) - immhb
;
8284 bool round
= extract32(opcode
, 0, 1);
8285 TCGv_i64 tcg_rn
, tcg_rd
, tcg_final
;
8289 if (extract32(immh
, 3, 1)) {
8290 unallocated_encoding(s
);
8294 if (!fp_access_check(s
)) {
8298 tcg_rn
= tcg_temp_new_i64();
8299 tcg_rd
= tcg_temp_new_i64();
8300 tcg_final
= tcg_temp_new_i64();
8301 read_vec_element(s
, tcg_final
, rd
, is_q
? 1 : 0, MO_64
);
8304 uint64_t round_const
= 1ULL << (shift
- 1);
8305 tcg_round
= tcg_const_i64(round_const
);
8307 TCGV_UNUSED_I64(tcg_round
);
8310 for (i
= 0; i
< elements
; i
++) {
8311 read_vec_element(s
, tcg_rn
, rn
, i
, size
+1);
8312 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
8313 false, true, size
+1, shift
);
8315 tcg_gen_deposit_i64(tcg_final
, tcg_final
, tcg_rd
, esize
* i
, esize
);
8319 clear_vec_high(s
, rd
);
8320 write_vec_element(s
, tcg_final
, rd
, 0, MO_64
);
8322 write_vec_element(s
, tcg_final
, rd
, 1, MO_64
);
8326 tcg_temp_free_i64(tcg_round
);
8328 tcg_temp_free_i64(tcg_rn
);
8329 tcg_temp_free_i64(tcg_rd
);
8330 tcg_temp_free_i64(tcg_final
);
8335 /* C3.6.14 AdvSIMD shift by immediate
8336 * 31 30 29 28 23 22 19 18 16 15 11 10 9 5 4 0
8337 * +---+---+---+-------------+------+------+--------+---+------+------+
8338 * | 0 | Q | U | 0 1 1 1 1 0 | immh | immb | opcode | 1 | Rn | Rd |
8339 * +---+---+---+-------------+------+------+--------+---+------+------+
8341 static void disas_simd_shift_imm(DisasContext
*s
, uint32_t insn
)
8343 int rd
= extract32(insn
, 0, 5);
8344 int rn
= extract32(insn
, 5, 5);
8345 int opcode
= extract32(insn
, 11, 5);
8346 int immb
= extract32(insn
, 16, 3);
8347 int immh
= extract32(insn
, 19, 4);
8348 bool is_u
= extract32(insn
, 29, 1);
8349 bool is_q
= extract32(insn
, 30, 1);
8352 case 0x08: /* SRI */
8354 unallocated_encoding(s
);
8358 case 0x00: /* SSHR / USHR */
8359 case 0x02: /* SSRA / USRA (accumulate) */
8360 case 0x04: /* SRSHR / URSHR (rounding) */
8361 case 0x06: /* SRSRA / URSRA (accum + rounding) */
8362 handle_vec_simd_shri(s
, is_q
, is_u
, immh
, immb
, opcode
, rn
, rd
);
8364 case 0x0a: /* SHL / SLI */
8365 handle_vec_simd_shli(s
, is_q
, is_u
, immh
, immb
, opcode
, rn
, rd
);
8367 case 0x10: /* SHRN */
8368 case 0x11: /* RSHRN / SQRSHRUN */
8370 handle_vec_simd_sqshrn(s
, false, is_q
, false, true, immh
, immb
,
8373 handle_vec_simd_shrn(s
, is_q
, immh
, immb
, opcode
, rn
, rd
);
8376 case 0x12: /* SQSHRN / UQSHRN */
8377 case 0x13: /* SQRSHRN / UQRSHRN */
8378 handle_vec_simd_sqshrn(s
, false, is_q
, is_u
, is_u
, immh
, immb
,
8381 case 0x14: /* SSHLL / USHLL */
8382 handle_vec_simd_wshli(s
, is_q
, is_u
, immh
, immb
, opcode
, rn
, rd
);
8384 case 0x1c: /* SCVTF / UCVTF */
8385 handle_simd_shift_intfp_conv(s
, false, is_q
, is_u
, immh
, immb
,
8388 case 0xc: /* SQSHLU */
8390 unallocated_encoding(s
);
8393 handle_simd_qshl(s
, false, is_q
, false, true, immh
, immb
, rn
, rd
);
8395 case 0xe: /* SQSHL, UQSHL */
8396 handle_simd_qshl(s
, false, is_q
, is_u
, is_u
, immh
, immb
, rn
, rd
);
8398 case 0x1f: /* FCVTZS/ FCVTZU */
8399 handle_simd_shift_fpint_conv(s
, false, is_q
, is_u
, immh
, immb
, rn
, rd
);
8402 unallocated_encoding(s
);
8407 /* Generate code to do a "long" addition or subtraction, ie one done in
8408 * TCGv_i64 on vector lanes twice the width specified by size.
8410 static void gen_neon_addl(int size
, bool is_sub
, TCGv_i64 tcg_res
,
8411 TCGv_i64 tcg_op1
, TCGv_i64 tcg_op2
)
8413 static NeonGenTwo64OpFn
* const fns
[3][2] = {
8414 { gen_helper_neon_addl_u16
, gen_helper_neon_subl_u16
},
8415 { gen_helper_neon_addl_u32
, gen_helper_neon_subl_u32
},
8416 { tcg_gen_add_i64
, tcg_gen_sub_i64
},
8418 NeonGenTwo64OpFn
*genfn
;
8421 genfn
= fns
[size
][is_sub
];
8422 genfn(tcg_res
, tcg_op1
, tcg_op2
);
8425 static void handle_3rd_widening(DisasContext
*s
, int is_q
, int is_u
, int size
,
8426 int opcode
, int rd
, int rn
, int rm
)
8428 /* 3-reg-different widening insns: 64 x 64 -> 128 */
8429 TCGv_i64 tcg_res
[2];
8432 tcg_res
[0] = tcg_temp_new_i64();
8433 tcg_res
[1] = tcg_temp_new_i64();
8435 /* Does this op do an adding accumulate, a subtracting accumulate,
8436 * or no accumulate at all?
8454 read_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
8455 read_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
8458 /* size == 2 means two 32x32->64 operations; this is worth special
8459 * casing because we can generally handle it inline.
8462 for (pass
= 0; pass
< 2; pass
++) {
8463 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
8464 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
8465 TCGv_i64 tcg_passres
;
8466 TCGMemOp memop
= MO_32
| (is_u
? 0 : MO_SIGN
);
8468 int elt
= pass
+ is_q
* 2;
8470 read_vec_element(s
, tcg_op1
, rn
, elt
, memop
);
8471 read_vec_element(s
, tcg_op2
, rm
, elt
, memop
);
8474 tcg_passres
= tcg_res
[pass
];
8476 tcg_passres
= tcg_temp_new_i64();
8480 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
8481 tcg_gen_add_i64(tcg_passres
, tcg_op1
, tcg_op2
);
8483 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
8484 tcg_gen_sub_i64(tcg_passres
, tcg_op1
, tcg_op2
);
8486 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
8487 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
8489 TCGv_i64 tcg_tmp1
= tcg_temp_new_i64();
8490 TCGv_i64 tcg_tmp2
= tcg_temp_new_i64();
8492 tcg_gen_sub_i64(tcg_tmp1
, tcg_op1
, tcg_op2
);
8493 tcg_gen_sub_i64(tcg_tmp2
, tcg_op2
, tcg_op1
);
8494 tcg_gen_movcond_i64(is_u
? TCG_COND_GEU
: TCG_COND_GE
,
8496 tcg_op1
, tcg_op2
, tcg_tmp1
, tcg_tmp2
);
8497 tcg_temp_free_i64(tcg_tmp1
);
8498 tcg_temp_free_i64(tcg_tmp2
);
8501 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
8502 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
8503 case 12: /* UMULL, UMULL2, SMULL, SMULL2 */
8504 tcg_gen_mul_i64(tcg_passres
, tcg_op1
, tcg_op2
);
8506 case 9: /* SQDMLAL, SQDMLAL2 */
8507 case 11: /* SQDMLSL, SQDMLSL2 */
8508 case 13: /* SQDMULL, SQDMULL2 */
8509 tcg_gen_mul_i64(tcg_passres
, tcg_op1
, tcg_op2
);
8510 gen_helper_neon_addl_saturate_s64(tcg_passres
, cpu_env
,
8511 tcg_passres
, tcg_passres
);
8514 g_assert_not_reached();
8517 if (opcode
== 9 || opcode
== 11) {
8518 /* saturating accumulate ops */
8520 tcg_gen_neg_i64(tcg_passres
, tcg_passres
);
8522 gen_helper_neon_addl_saturate_s64(tcg_res
[pass
], cpu_env
,
8523 tcg_res
[pass
], tcg_passres
);
8524 } else if (accop
> 0) {
8525 tcg_gen_add_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
8526 } else if (accop
< 0) {
8527 tcg_gen_sub_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
8531 tcg_temp_free_i64(tcg_passres
);
8534 tcg_temp_free_i64(tcg_op1
);
8535 tcg_temp_free_i64(tcg_op2
);
8538 /* size 0 or 1, generally helper functions */
8539 for (pass
= 0; pass
< 2; pass
++) {
8540 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
8541 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
8542 TCGv_i64 tcg_passres
;
8543 int elt
= pass
+ is_q
* 2;
8545 read_vec_element_i32(s
, tcg_op1
, rn
, elt
, MO_32
);
8546 read_vec_element_i32(s
, tcg_op2
, rm
, elt
, MO_32
);
8549 tcg_passres
= tcg_res
[pass
];
8551 tcg_passres
= tcg_temp_new_i64();
8555 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
8556 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
8558 TCGv_i64 tcg_op2_64
= tcg_temp_new_i64();
8559 static NeonGenWidenFn
* const widenfns
[2][2] = {
8560 { gen_helper_neon_widen_s8
, gen_helper_neon_widen_u8
},
8561 { gen_helper_neon_widen_s16
, gen_helper_neon_widen_u16
},
8563 NeonGenWidenFn
*widenfn
= widenfns
[size
][is_u
];
8565 widenfn(tcg_op2_64
, tcg_op2
);
8566 widenfn(tcg_passres
, tcg_op1
);
8567 gen_neon_addl(size
, (opcode
== 2), tcg_passres
,
8568 tcg_passres
, tcg_op2_64
);
8569 tcg_temp_free_i64(tcg_op2_64
);
8572 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
8573 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
8576 gen_helper_neon_abdl_u16(tcg_passres
, tcg_op1
, tcg_op2
);
8578 gen_helper_neon_abdl_s16(tcg_passres
, tcg_op1
, tcg_op2
);
8582 gen_helper_neon_abdl_u32(tcg_passres
, tcg_op1
, tcg_op2
);
8584 gen_helper_neon_abdl_s32(tcg_passres
, tcg_op1
, tcg_op2
);
8588 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
8589 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
8590 case 12: /* UMULL, UMULL2, SMULL, SMULL2 */
8593 gen_helper_neon_mull_u8(tcg_passres
, tcg_op1
, tcg_op2
);
8595 gen_helper_neon_mull_s8(tcg_passres
, tcg_op1
, tcg_op2
);
8599 gen_helper_neon_mull_u16(tcg_passres
, tcg_op1
, tcg_op2
);
8601 gen_helper_neon_mull_s16(tcg_passres
, tcg_op1
, tcg_op2
);
8605 case 9: /* SQDMLAL, SQDMLAL2 */
8606 case 11: /* SQDMLSL, SQDMLSL2 */
8607 case 13: /* SQDMULL, SQDMULL2 */
8609 gen_helper_neon_mull_s16(tcg_passres
, tcg_op1
, tcg_op2
);
8610 gen_helper_neon_addl_saturate_s32(tcg_passres
, cpu_env
,
8611 tcg_passres
, tcg_passres
);
8613 case 14: /* PMULL */
8615 gen_helper_neon_mull_p8(tcg_passres
, tcg_op1
, tcg_op2
);
8618 g_assert_not_reached();
8620 tcg_temp_free_i32(tcg_op1
);
8621 tcg_temp_free_i32(tcg_op2
);
8624 if (opcode
== 9 || opcode
== 11) {
8625 /* saturating accumulate ops */
8627 gen_helper_neon_negl_u32(tcg_passres
, tcg_passres
);
8629 gen_helper_neon_addl_saturate_s32(tcg_res
[pass
], cpu_env
,
8633 gen_neon_addl(size
, (accop
< 0), tcg_res
[pass
],
8634 tcg_res
[pass
], tcg_passres
);
8636 tcg_temp_free_i64(tcg_passres
);
8641 write_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
8642 write_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
8643 tcg_temp_free_i64(tcg_res
[0]);
8644 tcg_temp_free_i64(tcg_res
[1]);
8647 static void handle_3rd_wide(DisasContext
*s
, int is_q
, int is_u
, int size
,
8648 int opcode
, int rd
, int rn
, int rm
)
8650 TCGv_i64 tcg_res
[2];
8651 int part
= is_q
? 2 : 0;
8654 for (pass
= 0; pass
< 2; pass
++) {
8655 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
8656 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
8657 TCGv_i64 tcg_op2_wide
= tcg_temp_new_i64();
8658 static NeonGenWidenFn
* const widenfns
[3][2] = {
8659 { gen_helper_neon_widen_s8
, gen_helper_neon_widen_u8
},
8660 { gen_helper_neon_widen_s16
, gen_helper_neon_widen_u16
},
8661 { tcg_gen_ext_i32_i64
, tcg_gen_extu_i32_i64
},
8663 NeonGenWidenFn
*widenfn
= widenfns
[size
][is_u
];
8665 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
8666 read_vec_element_i32(s
, tcg_op2
, rm
, part
+ pass
, MO_32
);
8667 widenfn(tcg_op2_wide
, tcg_op2
);
8668 tcg_temp_free_i32(tcg_op2
);
8669 tcg_res
[pass
] = tcg_temp_new_i64();
8670 gen_neon_addl(size
, (opcode
== 3),
8671 tcg_res
[pass
], tcg_op1
, tcg_op2_wide
);
8672 tcg_temp_free_i64(tcg_op1
);
8673 tcg_temp_free_i64(tcg_op2_wide
);
8676 for (pass
= 0; pass
< 2; pass
++) {
8677 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
8678 tcg_temp_free_i64(tcg_res
[pass
]);
8682 static void do_narrow_round_high_u32(TCGv_i32 res
, TCGv_i64 in
)
8684 tcg_gen_addi_i64(in
, in
, 1U << 31);
8685 tcg_gen_extrh_i64_i32(res
, in
);
8688 static void handle_3rd_narrowing(DisasContext
*s
, int is_q
, int is_u
, int size
,
8689 int opcode
, int rd
, int rn
, int rm
)
8691 TCGv_i32 tcg_res
[2];
8692 int part
= is_q
? 2 : 0;
8695 for (pass
= 0; pass
< 2; pass
++) {
8696 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
8697 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
8698 TCGv_i64 tcg_wideres
= tcg_temp_new_i64();
8699 static NeonGenNarrowFn
* const narrowfns
[3][2] = {
8700 { gen_helper_neon_narrow_high_u8
,
8701 gen_helper_neon_narrow_round_high_u8
},
8702 { gen_helper_neon_narrow_high_u16
,
8703 gen_helper_neon_narrow_round_high_u16
},
8704 { tcg_gen_extrh_i64_i32
, do_narrow_round_high_u32
},
8706 NeonGenNarrowFn
*gennarrow
= narrowfns
[size
][is_u
];
8708 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
8709 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
8711 gen_neon_addl(size
, (opcode
== 6), tcg_wideres
, tcg_op1
, tcg_op2
);
8713 tcg_temp_free_i64(tcg_op1
);
8714 tcg_temp_free_i64(tcg_op2
);
8716 tcg_res
[pass
] = tcg_temp_new_i32();
8717 gennarrow(tcg_res
[pass
], tcg_wideres
);
8718 tcg_temp_free_i64(tcg_wideres
);
8721 for (pass
= 0; pass
< 2; pass
++) {
8722 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
+ part
, MO_32
);
8723 tcg_temp_free_i32(tcg_res
[pass
]);
8726 clear_vec_high(s
, rd
);
8730 static void handle_pmull_64(DisasContext
*s
, int is_q
, int rd
, int rn
, int rm
)
8732 /* PMULL of 64 x 64 -> 128 is an odd special case because it
8733 * is the only three-reg-diff instruction which produces a
8734 * 128-bit wide result from a single operation. However since
8735 * it's possible to calculate the two halves more or less
8736 * separately we just use two helper calls.
8738 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
8739 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
8740 TCGv_i64 tcg_res
= tcg_temp_new_i64();
8742 read_vec_element(s
, tcg_op1
, rn
, is_q
, MO_64
);
8743 read_vec_element(s
, tcg_op2
, rm
, is_q
, MO_64
);
8744 gen_helper_neon_pmull_64_lo(tcg_res
, tcg_op1
, tcg_op2
);
8745 write_vec_element(s
, tcg_res
, rd
, 0, MO_64
);
8746 gen_helper_neon_pmull_64_hi(tcg_res
, tcg_op1
, tcg_op2
);
8747 write_vec_element(s
, tcg_res
, rd
, 1, MO_64
);
8749 tcg_temp_free_i64(tcg_op1
);
8750 tcg_temp_free_i64(tcg_op2
);
8751 tcg_temp_free_i64(tcg_res
);
8754 /* C3.6.15 AdvSIMD three different
8755 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
8756 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
8757 * | 0 | Q | U | 0 1 1 1 0 | size | 1 | Rm | opcode | 0 0 | Rn | Rd |
8758 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
8760 static void disas_simd_three_reg_diff(DisasContext
*s
, uint32_t insn
)
8762 /* Instructions in this group fall into three basic classes
8763 * (in each case with the operation working on each element in
8764 * the input vectors):
8765 * (1) widening 64 x 64 -> 128 (with possibly Vd as an extra
8767 * (2) wide 64 x 128 -> 128
8768 * (3) narrowing 128 x 128 -> 64
8769 * Here we do initial decode, catch unallocated cases and
8770 * dispatch to separate functions for each class.
8772 int is_q
= extract32(insn
, 30, 1);
8773 int is_u
= extract32(insn
, 29, 1);
8774 int size
= extract32(insn
, 22, 2);
8775 int opcode
= extract32(insn
, 12, 4);
8776 int rm
= extract32(insn
, 16, 5);
8777 int rn
= extract32(insn
, 5, 5);
8778 int rd
= extract32(insn
, 0, 5);
8781 case 1: /* SADDW, SADDW2, UADDW, UADDW2 */
8782 case 3: /* SSUBW, SSUBW2, USUBW, USUBW2 */
8783 /* 64 x 128 -> 128 */
8785 unallocated_encoding(s
);
8788 if (!fp_access_check(s
)) {
8791 handle_3rd_wide(s
, is_q
, is_u
, size
, opcode
, rd
, rn
, rm
);
8793 case 4: /* ADDHN, ADDHN2, RADDHN, RADDHN2 */
8794 case 6: /* SUBHN, SUBHN2, RSUBHN, RSUBHN2 */
8795 /* 128 x 128 -> 64 */
8797 unallocated_encoding(s
);
8800 if (!fp_access_check(s
)) {
8803 handle_3rd_narrowing(s
, is_q
, is_u
, size
, opcode
, rd
, rn
, rm
);
8805 case 14: /* PMULL, PMULL2 */
8806 if (is_u
|| size
== 1 || size
== 2) {
8807 unallocated_encoding(s
);
8811 if (!arm_dc_feature(s
, ARM_FEATURE_V8_PMULL
)) {
8812 unallocated_encoding(s
);
8815 if (!fp_access_check(s
)) {
8818 handle_pmull_64(s
, is_q
, rd
, rn
, rm
);
8822 case 9: /* SQDMLAL, SQDMLAL2 */
8823 case 11: /* SQDMLSL, SQDMLSL2 */
8824 case 13: /* SQDMULL, SQDMULL2 */
8825 if (is_u
|| size
== 0) {
8826 unallocated_encoding(s
);
8830 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
8831 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
8832 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
8833 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
8834 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
8835 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
8836 case 12: /* SMULL, SMULL2, UMULL, UMULL2 */
8837 /* 64 x 64 -> 128 */
8839 unallocated_encoding(s
);
8843 if (!fp_access_check(s
)) {
8847 handle_3rd_widening(s
, is_q
, is_u
, size
, opcode
, rd
, rn
, rm
);
8850 /* opcode 15 not allocated */
8851 unallocated_encoding(s
);
8856 /* Logic op (opcode == 3) subgroup of C3.6.16. */
8857 static void disas_simd_3same_logic(DisasContext
*s
, uint32_t insn
)
8859 int rd
= extract32(insn
, 0, 5);
8860 int rn
= extract32(insn
, 5, 5);
8861 int rm
= extract32(insn
, 16, 5);
8862 int size
= extract32(insn
, 22, 2);
8863 bool is_u
= extract32(insn
, 29, 1);
8864 bool is_q
= extract32(insn
, 30, 1);
8865 TCGv_i64 tcg_op1
, tcg_op2
, tcg_res
[2];
8868 if (!fp_access_check(s
)) {
8872 tcg_op1
= tcg_temp_new_i64();
8873 tcg_op2
= tcg_temp_new_i64();
8874 tcg_res
[0] = tcg_temp_new_i64();
8875 tcg_res
[1] = tcg_temp_new_i64();
8877 for (pass
= 0; pass
< (is_q
? 2 : 1); pass
++) {
8878 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
8879 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
8884 tcg_gen_and_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
8887 tcg_gen_andc_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
8890 tcg_gen_or_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
8893 tcg_gen_orc_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
8898 /* B* ops need res loaded to operate on */
8899 read_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
8904 tcg_gen_xor_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
8906 case 1: /* BSL bitwise select */
8907 tcg_gen_xor_i64(tcg_op1
, tcg_op1
, tcg_op2
);
8908 tcg_gen_and_i64(tcg_op1
, tcg_op1
, tcg_res
[pass
]);
8909 tcg_gen_xor_i64(tcg_res
[pass
], tcg_op2
, tcg_op1
);
8911 case 2: /* BIT, bitwise insert if true */
8912 tcg_gen_xor_i64(tcg_op1
, tcg_op1
, tcg_res
[pass
]);
8913 tcg_gen_and_i64(tcg_op1
, tcg_op1
, tcg_op2
);
8914 tcg_gen_xor_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_op1
);
8916 case 3: /* BIF, bitwise insert if false */
8917 tcg_gen_xor_i64(tcg_op1
, tcg_op1
, tcg_res
[pass
]);
8918 tcg_gen_andc_i64(tcg_op1
, tcg_op1
, tcg_op2
);
8919 tcg_gen_xor_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_op1
);
8925 write_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
8927 tcg_gen_movi_i64(tcg_res
[1], 0);
8929 write_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
8931 tcg_temp_free_i64(tcg_op1
);
8932 tcg_temp_free_i64(tcg_op2
);
8933 tcg_temp_free_i64(tcg_res
[0]);
8934 tcg_temp_free_i64(tcg_res
[1]);
8937 /* Helper functions for 32 bit comparisons */
8938 static void gen_max_s32(TCGv_i32 res
, TCGv_i32 op1
, TCGv_i32 op2
)
8940 tcg_gen_movcond_i32(TCG_COND_GE
, res
, op1
, op2
, op1
, op2
);
8943 static void gen_max_u32(TCGv_i32 res
, TCGv_i32 op1
, TCGv_i32 op2
)
8945 tcg_gen_movcond_i32(TCG_COND_GEU
, res
, op1
, op2
, op1
, op2
);
8948 static void gen_min_s32(TCGv_i32 res
, TCGv_i32 op1
, TCGv_i32 op2
)
8950 tcg_gen_movcond_i32(TCG_COND_LE
, res
, op1
, op2
, op1
, op2
);
8953 static void gen_min_u32(TCGv_i32 res
, TCGv_i32 op1
, TCGv_i32 op2
)
8955 tcg_gen_movcond_i32(TCG_COND_LEU
, res
, op1
, op2
, op1
, op2
);
8958 /* Pairwise op subgroup of C3.6.16.
8960 * This is called directly or via the handle_3same_float for float pairwise
8961 * operations where the opcode and size are calculated differently.
8963 static void handle_simd_3same_pair(DisasContext
*s
, int is_q
, int u
, int opcode
,
8964 int size
, int rn
, int rm
, int rd
)
8969 /* Floating point operations need fpst */
8970 if (opcode
>= 0x58) {
8971 fpst
= get_fpstatus_ptr();
8973 TCGV_UNUSED_PTR(fpst
);
8976 if (!fp_access_check(s
)) {
8980 /* These operations work on the concatenated rm:rn, with each pair of
8981 * adjacent elements being operated on to produce an element in the result.
8984 TCGv_i64 tcg_res
[2];
8986 for (pass
= 0; pass
< 2; pass
++) {
8987 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
8988 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
8989 int passreg
= (pass
== 0) ? rn
: rm
;
8991 read_vec_element(s
, tcg_op1
, passreg
, 0, MO_64
);
8992 read_vec_element(s
, tcg_op2
, passreg
, 1, MO_64
);
8993 tcg_res
[pass
] = tcg_temp_new_i64();
8996 case 0x17: /* ADDP */
8997 tcg_gen_add_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
8999 case 0x58: /* FMAXNMP */
9000 gen_helper_vfp_maxnumd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
9002 case 0x5a: /* FADDP */
9003 gen_helper_vfp_addd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
9005 case 0x5e: /* FMAXP */
9006 gen_helper_vfp_maxd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
9008 case 0x78: /* FMINNMP */
9009 gen_helper_vfp_minnumd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
9011 case 0x7e: /* FMINP */
9012 gen_helper_vfp_mind(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
9015 g_assert_not_reached();
9018 tcg_temp_free_i64(tcg_op1
);
9019 tcg_temp_free_i64(tcg_op2
);
9022 for (pass
= 0; pass
< 2; pass
++) {
9023 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
9024 tcg_temp_free_i64(tcg_res
[pass
]);
9027 int maxpass
= is_q
? 4 : 2;
9028 TCGv_i32 tcg_res
[4];
9030 for (pass
= 0; pass
< maxpass
; pass
++) {
9031 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
9032 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
9033 NeonGenTwoOpFn
*genfn
= NULL
;
9034 int passreg
= pass
< (maxpass
/ 2) ? rn
: rm
;
9035 int passelt
= (is_q
&& (pass
& 1)) ? 2 : 0;
9037 read_vec_element_i32(s
, tcg_op1
, passreg
, passelt
, MO_32
);
9038 read_vec_element_i32(s
, tcg_op2
, passreg
, passelt
+ 1, MO_32
);
9039 tcg_res
[pass
] = tcg_temp_new_i32();
9042 case 0x17: /* ADDP */
9044 static NeonGenTwoOpFn
* const fns
[3] = {
9045 gen_helper_neon_padd_u8
,
9046 gen_helper_neon_padd_u16
,
9052 case 0x14: /* SMAXP, UMAXP */
9054 static NeonGenTwoOpFn
* const fns
[3][2] = {
9055 { gen_helper_neon_pmax_s8
, gen_helper_neon_pmax_u8
},
9056 { gen_helper_neon_pmax_s16
, gen_helper_neon_pmax_u16
},
9057 { gen_max_s32
, gen_max_u32
},
9059 genfn
= fns
[size
][u
];
9062 case 0x15: /* SMINP, UMINP */
9064 static NeonGenTwoOpFn
* const fns
[3][2] = {
9065 { gen_helper_neon_pmin_s8
, gen_helper_neon_pmin_u8
},
9066 { gen_helper_neon_pmin_s16
, gen_helper_neon_pmin_u16
},
9067 { gen_min_s32
, gen_min_u32
},
9069 genfn
= fns
[size
][u
];
9072 /* The FP operations are all on single floats (32 bit) */
9073 case 0x58: /* FMAXNMP */
9074 gen_helper_vfp_maxnums(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
9076 case 0x5a: /* FADDP */
9077 gen_helper_vfp_adds(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
9079 case 0x5e: /* FMAXP */
9080 gen_helper_vfp_maxs(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
9082 case 0x78: /* FMINNMP */
9083 gen_helper_vfp_minnums(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
9085 case 0x7e: /* FMINP */
9086 gen_helper_vfp_mins(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
9089 g_assert_not_reached();
9092 /* FP ops called directly, otherwise call now */
9094 genfn(tcg_res
[pass
], tcg_op1
, tcg_op2
);
9097 tcg_temp_free_i32(tcg_op1
);
9098 tcg_temp_free_i32(tcg_op2
);
9101 for (pass
= 0; pass
< maxpass
; pass
++) {
9102 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
, MO_32
);
9103 tcg_temp_free_i32(tcg_res
[pass
]);
9106 clear_vec_high(s
, rd
);
9110 if (!TCGV_IS_UNUSED_PTR(fpst
)) {
9111 tcg_temp_free_ptr(fpst
);
9115 /* Floating point op subgroup of C3.6.16. */
9116 static void disas_simd_3same_float(DisasContext
*s
, uint32_t insn
)
9118 /* For floating point ops, the U, size[1] and opcode bits
9119 * together indicate the operation. size[0] indicates single
9122 int fpopcode
= extract32(insn
, 11, 5)
9123 | (extract32(insn
, 23, 1) << 5)
9124 | (extract32(insn
, 29, 1) << 6);
9125 int is_q
= extract32(insn
, 30, 1);
9126 int size
= extract32(insn
, 22, 1);
9127 int rm
= extract32(insn
, 16, 5);
9128 int rn
= extract32(insn
, 5, 5);
9129 int rd
= extract32(insn
, 0, 5);
9131 int datasize
= is_q
? 128 : 64;
9132 int esize
= 32 << size
;
9133 int elements
= datasize
/ esize
;
9135 if (size
== 1 && !is_q
) {
9136 unallocated_encoding(s
);
9141 case 0x58: /* FMAXNMP */
9142 case 0x5a: /* FADDP */
9143 case 0x5e: /* FMAXP */
9144 case 0x78: /* FMINNMP */
9145 case 0x7e: /* FMINP */
9146 if (size
&& !is_q
) {
9147 unallocated_encoding(s
);
9150 handle_simd_3same_pair(s
, is_q
, 0, fpopcode
, size
? MO_64
: MO_32
,
9153 case 0x1b: /* FMULX */
9154 case 0x1f: /* FRECPS */
9155 case 0x3f: /* FRSQRTS */
9156 case 0x5d: /* FACGE */
9157 case 0x7d: /* FACGT */
9158 case 0x19: /* FMLA */
9159 case 0x39: /* FMLS */
9160 case 0x18: /* FMAXNM */
9161 case 0x1a: /* FADD */
9162 case 0x1c: /* FCMEQ */
9163 case 0x1e: /* FMAX */
9164 case 0x38: /* FMINNM */
9165 case 0x3a: /* FSUB */
9166 case 0x3e: /* FMIN */
9167 case 0x5b: /* FMUL */
9168 case 0x5c: /* FCMGE */
9169 case 0x5f: /* FDIV */
9170 case 0x7a: /* FABD */
9171 case 0x7c: /* FCMGT */
9172 if (!fp_access_check(s
)) {
9176 handle_3same_float(s
, size
, elements
, fpopcode
, rd
, rn
, rm
);
9179 unallocated_encoding(s
);
9184 /* Integer op subgroup of C3.6.16. */
9185 static void disas_simd_3same_int(DisasContext
*s
, uint32_t insn
)
9187 int is_q
= extract32(insn
, 30, 1);
9188 int u
= extract32(insn
, 29, 1);
9189 int size
= extract32(insn
, 22, 2);
9190 int opcode
= extract32(insn
, 11, 5);
9191 int rm
= extract32(insn
, 16, 5);
9192 int rn
= extract32(insn
, 5, 5);
9193 int rd
= extract32(insn
, 0, 5);
9197 case 0x13: /* MUL, PMUL */
9198 if (u
&& size
!= 0) {
9199 unallocated_encoding(s
);
9203 case 0x0: /* SHADD, UHADD */
9204 case 0x2: /* SRHADD, URHADD */
9205 case 0x4: /* SHSUB, UHSUB */
9206 case 0xc: /* SMAX, UMAX */
9207 case 0xd: /* SMIN, UMIN */
9208 case 0xe: /* SABD, UABD */
9209 case 0xf: /* SABA, UABA */
9210 case 0x12: /* MLA, MLS */
9212 unallocated_encoding(s
);
9216 case 0x16: /* SQDMULH, SQRDMULH */
9217 if (size
== 0 || size
== 3) {
9218 unallocated_encoding(s
);
9223 if (size
== 3 && !is_q
) {
9224 unallocated_encoding(s
);
9230 if (!fp_access_check(s
)) {
9236 for (pass
= 0; pass
< 2; pass
++) {
9237 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
9238 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
9239 TCGv_i64 tcg_res
= tcg_temp_new_i64();
9241 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
9242 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
9244 handle_3same_64(s
, opcode
, u
, tcg_res
, tcg_op1
, tcg_op2
);
9246 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
9248 tcg_temp_free_i64(tcg_res
);
9249 tcg_temp_free_i64(tcg_op1
);
9250 tcg_temp_free_i64(tcg_op2
);
9253 for (pass
= 0; pass
< (is_q
? 4 : 2); pass
++) {
9254 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
9255 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
9256 TCGv_i32 tcg_res
= tcg_temp_new_i32();
9257 NeonGenTwoOpFn
*genfn
= NULL
;
9258 NeonGenTwoOpEnvFn
*genenvfn
= NULL
;
9260 read_vec_element_i32(s
, tcg_op1
, rn
, pass
, MO_32
);
9261 read_vec_element_i32(s
, tcg_op2
, rm
, pass
, MO_32
);
9264 case 0x0: /* SHADD, UHADD */
9266 static NeonGenTwoOpFn
* const fns
[3][2] = {
9267 { gen_helper_neon_hadd_s8
, gen_helper_neon_hadd_u8
},
9268 { gen_helper_neon_hadd_s16
, gen_helper_neon_hadd_u16
},
9269 { gen_helper_neon_hadd_s32
, gen_helper_neon_hadd_u32
},
9271 genfn
= fns
[size
][u
];
9274 case 0x1: /* SQADD, UQADD */
9276 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9277 { gen_helper_neon_qadd_s8
, gen_helper_neon_qadd_u8
},
9278 { gen_helper_neon_qadd_s16
, gen_helper_neon_qadd_u16
},
9279 { gen_helper_neon_qadd_s32
, gen_helper_neon_qadd_u32
},
9281 genenvfn
= fns
[size
][u
];
9284 case 0x2: /* SRHADD, URHADD */
9286 static NeonGenTwoOpFn
* const fns
[3][2] = {
9287 { gen_helper_neon_rhadd_s8
, gen_helper_neon_rhadd_u8
},
9288 { gen_helper_neon_rhadd_s16
, gen_helper_neon_rhadd_u16
},
9289 { gen_helper_neon_rhadd_s32
, gen_helper_neon_rhadd_u32
},
9291 genfn
= fns
[size
][u
];
9294 case 0x4: /* SHSUB, UHSUB */
9296 static NeonGenTwoOpFn
* const fns
[3][2] = {
9297 { gen_helper_neon_hsub_s8
, gen_helper_neon_hsub_u8
},
9298 { gen_helper_neon_hsub_s16
, gen_helper_neon_hsub_u16
},
9299 { gen_helper_neon_hsub_s32
, gen_helper_neon_hsub_u32
},
9301 genfn
= fns
[size
][u
];
9304 case 0x5: /* SQSUB, UQSUB */
9306 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9307 { gen_helper_neon_qsub_s8
, gen_helper_neon_qsub_u8
},
9308 { gen_helper_neon_qsub_s16
, gen_helper_neon_qsub_u16
},
9309 { gen_helper_neon_qsub_s32
, gen_helper_neon_qsub_u32
},
9311 genenvfn
= fns
[size
][u
];
9314 case 0x6: /* CMGT, CMHI */
9316 static NeonGenTwoOpFn
* const fns
[3][2] = {
9317 { gen_helper_neon_cgt_s8
, gen_helper_neon_cgt_u8
},
9318 { gen_helper_neon_cgt_s16
, gen_helper_neon_cgt_u16
},
9319 { gen_helper_neon_cgt_s32
, gen_helper_neon_cgt_u32
},
9321 genfn
= fns
[size
][u
];
9324 case 0x7: /* CMGE, CMHS */
9326 static NeonGenTwoOpFn
* const fns
[3][2] = {
9327 { gen_helper_neon_cge_s8
, gen_helper_neon_cge_u8
},
9328 { gen_helper_neon_cge_s16
, gen_helper_neon_cge_u16
},
9329 { gen_helper_neon_cge_s32
, gen_helper_neon_cge_u32
},
9331 genfn
= fns
[size
][u
];
9334 case 0x8: /* SSHL, USHL */
9336 static NeonGenTwoOpFn
* const fns
[3][2] = {
9337 { gen_helper_neon_shl_s8
, gen_helper_neon_shl_u8
},
9338 { gen_helper_neon_shl_s16
, gen_helper_neon_shl_u16
},
9339 { gen_helper_neon_shl_s32
, gen_helper_neon_shl_u32
},
9341 genfn
= fns
[size
][u
];
9344 case 0x9: /* SQSHL, UQSHL */
9346 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9347 { gen_helper_neon_qshl_s8
, gen_helper_neon_qshl_u8
},
9348 { gen_helper_neon_qshl_s16
, gen_helper_neon_qshl_u16
},
9349 { gen_helper_neon_qshl_s32
, gen_helper_neon_qshl_u32
},
9351 genenvfn
= fns
[size
][u
];
9354 case 0xa: /* SRSHL, URSHL */
9356 static NeonGenTwoOpFn
* const fns
[3][2] = {
9357 { gen_helper_neon_rshl_s8
, gen_helper_neon_rshl_u8
},
9358 { gen_helper_neon_rshl_s16
, gen_helper_neon_rshl_u16
},
9359 { gen_helper_neon_rshl_s32
, gen_helper_neon_rshl_u32
},
9361 genfn
= fns
[size
][u
];
9364 case 0xb: /* SQRSHL, UQRSHL */
9366 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9367 { gen_helper_neon_qrshl_s8
, gen_helper_neon_qrshl_u8
},
9368 { gen_helper_neon_qrshl_s16
, gen_helper_neon_qrshl_u16
},
9369 { gen_helper_neon_qrshl_s32
, gen_helper_neon_qrshl_u32
},
9371 genenvfn
= fns
[size
][u
];
9374 case 0xc: /* SMAX, UMAX */
9376 static NeonGenTwoOpFn
* const fns
[3][2] = {
9377 { gen_helper_neon_max_s8
, gen_helper_neon_max_u8
},
9378 { gen_helper_neon_max_s16
, gen_helper_neon_max_u16
},
9379 { gen_max_s32
, gen_max_u32
},
9381 genfn
= fns
[size
][u
];
9385 case 0xd: /* SMIN, UMIN */
9387 static NeonGenTwoOpFn
* const fns
[3][2] = {
9388 { gen_helper_neon_min_s8
, gen_helper_neon_min_u8
},
9389 { gen_helper_neon_min_s16
, gen_helper_neon_min_u16
},
9390 { gen_min_s32
, gen_min_u32
},
9392 genfn
= fns
[size
][u
];
9395 case 0xe: /* SABD, UABD */
9396 case 0xf: /* SABA, UABA */
9398 static NeonGenTwoOpFn
* const fns
[3][2] = {
9399 { gen_helper_neon_abd_s8
, gen_helper_neon_abd_u8
},
9400 { gen_helper_neon_abd_s16
, gen_helper_neon_abd_u16
},
9401 { gen_helper_neon_abd_s32
, gen_helper_neon_abd_u32
},
9403 genfn
= fns
[size
][u
];
9406 case 0x10: /* ADD, SUB */
9408 static NeonGenTwoOpFn
* const fns
[3][2] = {
9409 { gen_helper_neon_add_u8
, gen_helper_neon_sub_u8
},
9410 { gen_helper_neon_add_u16
, gen_helper_neon_sub_u16
},
9411 { tcg_gen_add_i32
, tcg_gen_sub_i32
},
9413 genfn
= fns
[size
][u
];
9416 case 0x11: /* CMTST, CMEQ */
9418 static NeonGenTwoOpFn
* const fns
[3][2] = {
9419 { gen_helper_neon_tst_u8
, gen_helper_neon_ceq_u8
},
9420 { gen_helper_neon_tst_u16
, gen_helper_neon_ceq_u16
},
9421 { gen_helper_neon_tst_u32
, gen_helper_neon_ceq_u32
},
9423 genfn
= fns
[size
][u
];
9426 case 0x13: /* MUL, PMUL */
9430 genfn
= gen_helper_neon_mul_p8
;
9433 /* fall through : MUL */
9434 case 0x12: /* MLA, MLS */
9436 static NeonGenTwoOpFn
* const fns
[3] = {
9437 gen_helper_neon_mul_u8
,
9438 gen_helper_neon_mul_u16
,
9444 case 0x16: /* SQDMULH, SQRDMULH */
9446 static NeonGenTwoOpEnvFn
* const fns
[2][2] = {
9447 { gen_helper_neon_qdmulh_s16
, gen_helper_neon_qrdmulh_s16
},
9448 { gen_helper_neon_qdmulh_s32
, gen_helper_neon_qrdmulh_s32
},
9450 assert(size
== 1 || size
== 2);
9451 genenvfn
= fns
[size
- 1][u
];
9455 g_assert_not_reached();
9459 genenvfn(tcg_res
, cpu_env
, tcg_op1
, tcg_op2
);
9461 genfn(tcg_res
, tcg_op1
, tcg_op2
);
9464 if (opcode
== 0xf || opcode
== 0x12) {
9465 /* SABA, UABA, MLA, MLS: accumulating ops */
9466 static NeonGenTwoOpFn
* const fns
[3][2] = {
9467 { gen_helper_neon_add_u8
, gen_helper_neon_sub_u8
},
9468 { gen_helper_neon_add_u16
, gen_helper_neon_sub_u16
},
9469 { tcg_gen_add_i32
, tcg_gen_sub_i32
},
9471 bool is_sub
= (opcode
== 0x12 && u
); /* MLS */
9473 genfn
= fns
[size
][is_sub
];
9474 read_vec_element_i32(s
, tcg_op1
, rd
, pass
, MO_32
);
9475 genfn(tcg_res
, tcg_op1
, tcg_res
);
9478 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
9480 tcg_temp_free_i32(tcg_res
);
9481 tcg_temp_free_i32(tcg_op1
);
9482 tcg_temp_free_i32(tcg_op2
);
9487 clear_vec_high(s
, rd
);
9491 /* C3.6.16 AdvSIMD three same
9492 * 31 30 29 28 24 23 22 21 20 16 15 11 10 9 5 4 0
9493 * +---+---+---+-----------+------+---+------+--------+---+------+------+
9494 * | 0 | Q | U | 0 1 1 1 0 | size | 1 | Rm | opcode | 1 | Rn | Rd |
9495 * +---+---+---+-----------+------+---+------+--------+---+------+------+
9497 static void disas_simd_three_reg_same(DisasContext
*s
, uint32_t insn
)
9499 int opcode
= extract32(insn
, 11, 5);
9502 case 0x3: /* logic ops */
9503 disas_simd_3same_logic(s
, insn
);
9505 case 0x17: /* ADDP */
9506 case 0x14: /* SMAXP, UMAXP */
9507 case 0x15: /* SMINP, UMINP */
9509 /* Pairwise operations */
9510 int is_q
= extract32(insn
, 30, 1);
9511 int u
= extract32(insn
, 29, 1);
9512 int size
= extract32(insn
, 22, 2);
9513 int rm
= extract32(insn
, 16, 5);
9514 int rn
= extract32(insn
, 5, 5);
9515 int rd
= extract32(insn
, 0, 5);
9516 if (opcode
== 0x17) {
9517 if (u
|| (size
== 3 && !is_q
)) {
9518 unallocated_encoding(s
);
9523 unallocated_encoding(s
);
9527 handle_simd_3same_pair(s
, is_q
, u
, opcode
, size
, rn
, rm
, rd
);
9531 /* floating point ops, sz[1] and U are part of opcode */
9532 disas_simd_3same_float(s
, insn
);
9535 disas_simd_3same_int(s
, insn
);
9540 static void handle_2misc_widening(DisasContext
*s
, int opcode
, bool is_q
,
9541 int size
, int rn
, int rd
)
9543 /* Handle 2-reg-misc ops which are widening (so each size element
9544 * in the source becomes a 2*size element in the destination.
9545 * The only instruction like this is FCVTL.
9550 /* 32 -> 64 bit fp conversion */
9551 TCGv_i64 tcg_res
[2];
9552 int srcelt
= is_q
? 2 : 0;
9554 for (pass
= 0; pass
< 2; pass
++) {
9555 TCGv_i32 tcg_op
= tcg_temp_new_i32();
9556 tcg_res
[pass
] = tcg_temp_new_i64();
9558 read_vec_element_i32(s
, tcg_op
, rn
, srcelt
+ pass
, MO_32
);
9559 gen_helper_vfp_fcvtds(tcg_res
[pass
], tcg_op
, cpu_env
);
9560 tcg_temp_free_i32(tcg_op
);
9562 for (pass
= 0; pass
< 2; pass
++) {
9563 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
9564 tcg_temp_free_i64(tcg_res
[pass
]);
9567 /* 16 -> 32 bit fp conversion */
9568 int srcelt
= is_q
? 4 : 0;
9569 TCGv_i32 tcg_res
[4];
9571 for (pass
= 0; pass
< 4; pass
++) {
9572 tcg_res
[pass
] = tcg_temp_new_i32();
9574 read_vec_element_i32(s
, tcg_res
[pass
], rn
, srcelt
+ pass
, MO_16
);
9575 gen_helper_vfp_fcvt_f16_to_f32(tcg_res
[pass
], tcg_res
[pass
],
9578 for (pass
= 0; pass
< 4; pass
++) {
9579 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
, MO_32
);
9580 tcg_temp_free_i32(tcg_res
[pass
]);
9585 static void handle_rev(DisasContext
*s
, int opcode
, bool u
,
9586 bool is_q
, int size
, int rn
, int rd
)
9588 int op
= (opcode
<< 1) | u
;
9589 int opsz
= op
+ size
;
9590 int grp_size
= 3 - opsz
;
9591 int dsize
= is_q
? 128 : 64;
9595 unallocated_encoding(s
);
9599 if (!fp_access_check(s
)) {
9604 /* Special case bytes, use bswap op on each group of elements */
9605 int groups
= dsize
/ (8 << grp_size
);
9607 for (i
= 0; i
< groups
; i
++) {
9608 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
9610 read_vec_element(s
, tcg_tmp
, rn
, i
, grp_size
);
9613 tcg_gen_bswap16_i64(tcg_tmp
, tcg_tmp
);
9616 tcg_gen_bswap32_i64(tcg_tmp
, tcg_tmp
);
9619 tcg_gen_bswap64_i64(tcg_tmp
, tcg_tmp
);
9622 g_assert_not_reached();
9624 write_vec_element(s
, tcg_tmp
, rd
, i
, grp_size
);
9625 tcg_temp_free_i64(tcg_tmp
);
9628 clear_vec_high(s
, rd
);
9631 int revmask
= (1 << grp_size
) - 1;
9632 int esize
= 8 << size
;
9633 int elements
= dsize
/ esize
;
9634 TCGv_i64 tcg_rn
= tcg_temp_new_i64();
9635 TCGv_i64 tcg_rd
= tcg_const_i64(0);
9636 TCGv_i64 tcg_rd_hi
= tcg_const_i64(0);
9638 for (i
= 0; i
< elements
; i
++) {
9639 int e_rev
= (i
& 0xf) ^ revmask
;
9640 int off
= e_rev
* esize
;
9641 read_vec_element(s
, tcg_rn
, rn
, i
, size
);
9643 tcg_gen_deposit_i64(tcg_rd_hi
, tcg_rd_hi
,
9644 tcg_rn
, off
- 64, esize
);
9646 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_rn
, off
, esize
);
9649 write_vec_element(s
, tcg_rd
, rd
, 0, MO_64
);
9650 write_vec_element(s
, tcg_rd_hi
, rd
, 1, MO_64
);
9652 tcg_temp_free_i64(tcg_rd_hi
);
9653 tcg_temp_free_i64(tcg_rd
);
9654 tcg_temp_free_i64(tcg_rn
);
9658 static void handle_2misc_pairwise(DisasContext
*s
, int opcode
, bool u
,
9659 bool is_q
, int size
, int rn
, int rd
)
9661 /* Implement the pairwise operations from 2-misc:
9662 * SADDLP, UADDLP, SADALP, UADALP.
9663 * These all add pairs of elements in the input to produce a
9664 * double-width result element in the output (possibly accumulating).
9666 bool accum
= (opcode
== 0x6);
9667 int maxpass
= is_q
? 2 : 1;
9669 TCGv_i64 tcg_res
[2];
9672 /* 32 + 32 -> 64 op */
9673 TCGMemOp memop
= size
+ (u
? 0 : MO_SIGN
);
9675 for (pass
= 0; pass
< maxpass
; pass
++) {
9676 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
9677 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
9679 tcg_res
[pass
] = tcg_temp_new_i64();
9681 read_vec_element(s
, tcg_op1
, rn
, pass
* 2, memop
);
9682 read_vec_element(s
, tcg_op2
, rn
, pass
* 2 + 1, memop
);
9683 tcg_gen_add_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
9685 read_vec_element(s
, tcg_op1
, rd
, pass
, MO_64
);
9686 tcg_gen_add_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_op1
);
9689 tcg_temp_free_i64(tcg_op1
);
9690 tcg_temp_free_i64(tcg_op2
);
9693 for (pass
= 0; pass
< maxpass
; pass
++) {
9694 TCGv_i64 tcg_op
= tcg_temp_new_i64();
9695 NeonGenOneOpFn
*genfn
;
9696 static NeonGenOneOpFn
* const fns
[2][2] = {
9697 { gen_helper_neon_addlp_s8
, gen_helper_neon_addlp_u8
},
9698 { gen_helper_neon_addlp_s16
, gen_helper_neon_addlp_u16
},
9701 genfn
= fns
[size
][u
];
9703 tcg_res
[pass
] = tcg_temp_new_i64();
9705 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
9706 genfn(tcg_res
[pass
], tcg_op
);
9709 read_vec_element(s
, tcg_op
, rd
, pass
, MO_64
);
9711 gen_helper_neon_addl_u16(tcg_res
[pass
],
9712 tcg_res
[pass
], tcg_op
);
9714 gen_helper_neon_addl_u32(tcg_res
[pass
],
9715 tcg_res
[pass
], tcg_op
);
9718 tcg_temp_free_i64(tcg_op
);
9722 tcg_res
[1] = tcg_const_i64(0);
9724 for (pass
= 0; pass
< 2; pass
++) {
9725 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
9726 tcg_temp_free_i64(tcg_res
[pass
]);
9730 static void handle_shll(DisasContext
*s
, bool is_q
, int size
, int rn
, int rd
)
9732 /* Implement SHLL and SHLL2 */
9734 int part
= is_q
? 2 : 0;
9735 TCGv_i64 tcg_res
[2];
9737 for (pass
= 0; pass
< 2; pass
++) {
9738 static NeonGenWidenFn
* const widenfns
[3] = {
9739 gen_helper_neon_widen_u8
,
9740 gen_helper_neon_widen_u16
,
9741 tcg_gen_extu_i32_i64
,
9743 NeonGenWidenFn
*widenfn
= widenfns
[size
];
9744 TCGv_i32 tcg_op
= tcg_temp_new_i32();
9746 read_vec_element_i32(s
, tcg_op
, rn
, part
+ pass
, MO_32
);
9747 tcg_res
[pass
] = tcg_temp_new_i64();
9748 widenfn(tcg_res
[pass
], tcg_op
);
9749 tcg_gen_shli_i64(tcg_res
[pass
], tcg_res
[pass
], 8 << size
);
9751 tcg_temp_free_i32(tcg_op
);
9754 for (pass
= 0; pass
< 2; pass
++) {
9755 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
9756 tcg_temp_free_i64(tcg_res
[pass
]);
9760 /* C3.6.17 AdvSIMD two reg misc
9761 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
9762 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
9763 * | 0 | Q | U | 0 1 1 1 0 | size | 1 0 0 0 0 | opcode | 1 0 | Rn | Rd |
9764 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
9766 static void disas_simd_two_reg_misc(DisasContext
*s
, uint32_t insn
)
9768 int size
= extract32(insn
, 22, 2);
9769 int opcode
= extract32(insn
, 12, 5);
9770 bool u
= extract32(insn
, 29, 1);
9771 bool is_q
= extract32(insn
, 30, 1);
9772 int rn
= extract32(insn
, 5, 5);
9773 int rd
= extract32(insn
, 0, 5);
9774 bool need_fpstatus
= false;
9775 bool need_rmode
= false;
9778 TCGv_ptr tcg_fpstatus
;
9781 case 0x0: /* REV64, REV32 */
9782 case 0x1: /* REV16 */
9783 handle_rev(s
, opcode
, u
, is_q
, size
, rn
, rd
);
9785 case 0x5: /* CNT, NOT, RBIT */
9786 if (u
&& size
== 0) {
9787 /* NOT: adjust size so we can use the 64-bits-at-a-time loop. */
9790 } else if (u
&& size
== 1) {
9793 } else if (!u
&& size
== 0) {
9797 unallocated_encoding(s
);
9799 case 0x12: /* XTN, XTN2, SQXTUN, SQXTUN2 */
9800 case 0x14: /* SQXTN, SQXTN2, UQXTN, UQXTN2 */
9802 unallocated_encoding(s
);
9805 if (!fp_access_check(s
)) {
9809 handle_2misc_narrow(s
, false, opcode
, u
, is_q
, size
, rn
, rd
);
9811 case 0x4: /* CLS, CLZ */
9813 unallocated_encoding(s
);
9817 case 0x2: /* SADDLP, UADDLP */
9818 case 0x6: /* SADALP, UADALP */
9820 unallocated_encoding(s
);
9823 if (!fp_access_check(s
)) {
9826 handle_2misc_pairwise(s
, opcode
, u
, is_q
, size
, rn
, rd
);
9828 case 0x13: /* SHLL, SHLL2 */
9829 if (u
== 0 || size
== 3) {
9830 unallocated_encoding(s
);
9833 if (!fp_access_check(s
)) {
9836 handle_shll(s
, is_q
, size
, rn
, rd
);
9838 case 0xa: /* CMLT */
9840 unallocated_encoding(s
);
9844 case 0x8: /* CMGT, CMGE */
9845 case 0x9: /* CMEQ, CMLE */
9846 case 0xb: /* ABS, NEG */
9847 if (size
== 3 && !is_q
) {
9848 unallocated_encoding(s
);
9852 case 0x3: /* SUQADD, USQADD */
9853 if (size
== 3 && !is_q
) {
9854 unallocated_encoding(s
);
9857 if (!fp_access_check(s
)) {
9860 handle_2misc_satacc(s
, false, u
, is_q
, size
, rn
, rd
);
9862 case 0x7: /* SQABS, SQNEG */
9863 if (size
== 3 && !is_q
) {
9864 unallocated_encoding(s
);
9872 /* Floating point: U, size[1] and opcode indicate operation;
9873 * size[0] indicates single or double precision.
9875 int is_double
= extract32(size
, 0, 1);
9876 opcode
|= (extract32(size
, 1, 1) << 5) | (u
<< 6);
9877 size
= is_double
? 3 : 2;
9879 case 0x2f: /* FABS */
9880 case 0x6f: /* FNEG */
9881 if (size
== 3 && !is_q
) {
9882 unallocated_encoding(s
);
9886 case 0x1d: /* SCVTF */
9887 case 0x5d: /* UCVTF */
9889 bool is_signed
= (opcode
== 0x1d) ? true : false;
9890 int elements
= is_double
? 2 : is_q
? 4 : 2;
9891 if (is_double
&& !is_q
) {
9892 unallocated_encoding(s
);
9895 if (!fp_access_check(s
)) {
9898 handle_simd_intfp_conv(s
, rd
, rn
, elements
, is_signed
, 0, size
);
9901 case 0x2c: /* FCMGT (zero) */
9902 case 0x2d: /* FCMEQ (zero) */
9903 case 0x2e: /* FCMLT (zero) */
9904 case 0x6c: /* FCMGE (zero) */
9905 case 0x6d: /* FCMLE (zero) */
9906 if (size
== 3 && !is_q
) {
9907 unallocated_encoding(s
);
9910 handle_2misc_fcmp_zero(s
, opcode
, false, u
, is_q
, size
, rn
, rd
);
9912 case 0x7f: /* FSQRT */
9913 if (size
== 3 && !is_q
) {
9914 unallocated_encoding(s
);
9918 case 0x1a: /* FCVTNS */
9919 case 0x1b: /* FCVTMS */
9920 case 0x3a: /* FCVTPS */
9921 case 0x3b: /* FCVTZS */
9922 case 0x5a: /* FCVTNU */
9923 case 0x5b: /* FCVTMU */
9924 case 0x7a: /* FCVTPU */
9925 case 0x7b: /* FCVTZU */
9926 need_fpstatus
= true;
9928 rmode
= extract32(opcode
, 5, 1) | (extract32(opcode
, 0, 1) << 1);
9929 if (size
== 3 && !is_q
) {
9930 unallocated_encoding(s
);
9934 case 0x5c: /* FCVTAU */
9935 case 0x1c: /* FCVTAS */
9936 need_fpstatus
= true;
9938 rmode
= FPROUNDING_TIEAWAY
;
9939 if (size
== 3 && !is_q
) {
9940 unallocated_encoding(s
);
9944 case 0x3c: /* URECPE */
9946 unallocated_encoding(s
);
9950 case 0x3d: /* FRECPE */
9951 case 0x7d: /* FRSQRTE */
9952 if (size
== 3 && !is_q
) {
9953 unallocated_encoding(s
);
9956 if (!fp_access_check(s
)) {
9959 handle_2misc_reciprocal(s
, opcode
, false, u
, is_q
, size
, rn
, rd
);
9961 case 0x56: /* FCVTXN, FCVTXN2 */
9963 unallocated_encoding(s
);
9967 case 0x16: /* FCVTN, FCVTN2 */
9968 /* handle_2misc_narrow does a 2*size -> size operation, but these
9969 * instructions encode the source size rather than dest size.
9971 if (!fp_access_check(s
)) {
9974 handle_2misc_narrow(s
, false, opcode
, 0, is_q
, size
- 1, rn
, rd
);
9976 case 0x17: /* FCVTL, FCVTL2 */
9977 if (!fp_access_check(s
)) {
9980 handle_2misc_widening(s
, opcode
, is_q
, size
, rn
, rd
);
9982 case 0x18: /* FRINTN */
9983 case 0x19: /* FRINTM */
9984 case 0x38: /* FRINTP */
9985 case 0x39: /* FRINTZ */
9987 rmode
= extract32(opcode
, 5, 1) | (extract32(opcode
, 0, 1) << 1);
9989 case 0x59: /* FRINTX */
9990 case 0x79: /* FRINTI */
9991 need_fpstatus
= true;
9992 if (size
== 3 && !is_q
) {
9993 unallocated_encoding(s
);
9997 case 0x58: /* FRINTA */
9999 rmode
= FPROUNDING_TIEAWAY
;
10000 need_fpstatus
= true;
10001 if (size
== 3 && !is_q
) {
10002 unallocated_encoding(s
);
10006 case 0x7c: /* URSQRTE */
10008 unallocated_encoding(s
);
10011 need_fpstatus
= true;
10014 unallocated_encoding(s
);
10020 unallocated_encoding(s
);
10024 if (!fp_access_check(s
)) {
10028 if (need_fpstatus
) {
10029 tcg_fpstatus
= get_fpstatus_ptr();
10031 TCGV_UNUSED_PTR(tcg_fpstatus
);
10034 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
10035 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
10037 TCGV_UNUSED_I32(tcg_rmode
);
10041 /* All 64-bit element operations can be shared with scalar 2misc */
10044 for (pass
= 0; pass
< (is_q
? 2 : 1); pass
++) {
10045 TCGv_i64 tcg_op
= tcg_temp_new_i64();
10046 TCGv_i64 tcg_res
= tcg_temp_new_i64();
10048 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
10050 handle_2misc_64(s
, opcode
, u
, tcg_res
, tcg_op
,
10051 tcg_rmode
, tcg_fpstatus
);
10053 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
10055 tcg_temp_free_i64(tcg_res
);
10056 tcg_temp_free_i64(tcg_op
);
10061 for (pass
= 0; pass
< (is_q
? 4 : 2); pass
++) {
10062 TCGv_i32 tcg_op
= tcg_temp_new_i32();
10063 TCGv_i32 tcg_res
= tcg_temp_new_i32();
10066 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_32
);
10069 /* Special cases for 32 bit elements */
10071 case 0xa: /* CMLT */
10072 /* 32 bit integer comparison against zero, result is
10073 * test ? (2^32 - 1) : 0. We implement via setcond(test)
10076 cond
= TCG_COND_LT
;
10078 tcg_gen_setcondi_i32(cond
, tcg_res
, tcg_op
, 0);
10079 tcg_gen_neg_i32(tcg_res
, tcg_res
);
10081 case 0x8: /* CMGT, CMGE */
10082 cond
= u
? TCG_COND_GE
: TCG_COND_GT
;
10084 case 0x9: /* CMEQ, CMLE */
10085 cond
= u
? TCG_COND_LE
: TCG_COND_EQ
;
10087 case 0x4: /* CLS */
10089 gen_helper_clz32(tcg_res
, tcg_op
);
10091 gen_helper_cls32(tcg_res
, tcg_op
);
10094 case 0x7: /* SQABS, SQNEG */
10096 gen_helper_neon_qneg_s32(tcg_res
, cpu_env
, tcg_op
);
10098 gen_helper_neon_qabs_s32(tcg_res
, cpu_env
, tcg_op
);
10101 case 0xb: /* ABS, NEG */
10103 tcg_gen_neg_i32(tcg_res
, tcg_op
);
10105 TCGv_i32 tcg_zero
= tcg_const_i32(0);
10106 tcg_gen_neg_i32(tcg_res
, tcg_op
);
10107 tcg_gen_movcond_i32(TCG_COND_GT
, tcg_res
, tcg_op
,
10108 tcg_zero
, tcg_op
, tcg_res
);
10109 tcg_temp_free_i32(tcg_zero
);
10112 case 0x2f: /* FABS */
10113 gen_helper_vfp_abss(tcg_res
, tcg_op
);
10115 case 0x6f: /* FNEG */
10116 gen_helper_vfp_negs(tcg_res
, tcg_op
);
10118 case 0x7f: /* FSQRT */
10119 gen_helper_vfp_sqrts(tcg_res
, tcg_op
, cpu_env
);
10121 case 0x1a: /* FCVTNS */
10122 case 0x1b: /* FCVTMS */
10123 case 0x1c: /* FCVTAS */
10124 case 0x3a: /* FCVTPS */
10125 case 0x3b: /* FCVTZS */
10127 TCGv_i32 tcg_shift
= tcg_const_i32(0);
10128 gen_helper_vfp_tosls(tcg_res
, tcg_op
,
10129 tcg_shift
, tcg_fpstatus
);
10130 tcg_temp_free_i32(tcg_shift
);
10133 case 0x5a: /* FCVTNU */
10134 case 0x5b: /* FCVTMU */
10135 case 0x5c: /* FCVTAU */
10136 case 0x7a: /* FCVTPU */
10137 case 0x7b: /* FCVTZU */
10139 TCGv_i32 tcg_shift
= tcg_const_i32(0);
10140 gen_helper_vfp_touls(tcg_res
, tcg_op
,
10141 tcg_shift
, tcg_fpstatus
);
10142 tcg_temp_free_i32(tcg_shift
);
10145 case 0x18: /* FRINTN */
10146 case 0x19: /* FRINTM */
10147 case 0x38: /* FRINTP */
10148 case 0x39: /* FRINTZ */
10149 case 0x58: /* FRINTA */
10150 case 0x79: /* FRINTI */
10151 gen_helper_rints(tcg_res
, tcg_op
, tcg_fpstatus
);
10153 case 0x59: /* FRINTX */
10154 gen_helper_rints_exact(tcg_res
, tcg_op
, tcg_fpstatus
);
10156 case 0x7c: /* URSQRTE */
10157 gen_helper_rsqrte_u32(tcg_res
, tcg_op
, tcg_fpstatus
);
10160 g_assert_not_reached();
10163 /* Use helpers for 8 and 16 bit elements */
10165 case 0x5: /* CNT, RBIT */
10166 /* For these two insns size is part of the opcode specifier
10167 * (handled earlier); they always operate on byte elements.
10170 gen_helper_neon_rbit_u8(tcg_res
, tcg_op
);
10172 gen_helper_neon_cnt_u8(tcg_res
, tcg_op
);
10175 case 0x7: /* SQABS, SQNEG */
10177 NeonGenOneOpEnvFn
*genfn
;
10178 static NeonGenOneOpEnvFn
* const fns
[2][2] = {
10179 { gen_helper_neon_qabs_s8
, gen_helper_neon_qneg_s8
},
10180 { gen_helper_neon_qabs_s16
, gen_helper_neon_qneg_s16
},
10182 genfn
= fns
[size
][u
];
10183 genfn(tcg_res
, cpu_env
, tcg_op
);
10186 case 0x8: /* CMGT, CMGE */
10187 case 0x9: /* CMEQ, CMLE */
10188 case 0xa: /* CMLT */
10190 static NeonGenTwoOpFn
* const fns
[3][2] = {
10191 { gen_helper_neon_cgt_s8
, gen_helper_neon_cgt_s16
},
10192 { gen_helper_neon_cge_s8
, gen_helper_neon_cge_s16
},
10193 { gen_helper_neon_ceq_u8
, gen_helper_neon_ceq_u16
},
10195 NeonGenTwoOpFn
*genfn
;
10198 TCGv_i32 tcg_zero
= tcg_const_i32(0);
10200 /* comp = index into [CMGT, CMGE, CMEQ, CMLE, CMLT] */
10201 comp
= (opcode
- 0x8) * 2 + u
;
10202 /* ...but LE, LT are implemented as reverse GE, GT */
10203 reverse
= (comp
> 2);
10207 genfn
= fns
[comp
][size
];
10209 genfn(tcg_res
, tcg_zero
, tcg_op
);
10211 genfn(tcg_res
, tcg_op
, tcg_zero
);
10213 tcg_temp_free_i32(tcg_zero
);
10216 case 0xb: /* ABS, NEG */
10218 TCGv_i32 tcg_zero
= tcg_const_i32(0);
10220 gen_helper_neon_sub_u16(tcg_res
, tcg_zero
, tcg_op
);
10222 gen_helper_neon_sub_u8(tcg_res
, tcg_zero
, tcg_op
);
10224 tcg_temp_free_i32(tcg_zero
);
10227 gen_helper_neon_abs_s16(tcg_res
, tcg_op
);
10229 gen_helper_neon_abs_s8(tcg_res
, tcg_op
);
10233 case 0x4: /* CLS, CLZ */
10236 gen_helper_neon_clz_u8(tcg_res
, tcg_op
);
10238 gen_helper_neon_clz_u16(tcg_res
, tcg_op
);
10242 gen_helper_neon_cls_s8(tcg_res
, tcg_op
);
10244 gen_helper_neon_cls_s16(tcg_res
, tcg_op
);
10249 g_assert_not_reached();
10253 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
10255 tcg_temp_free_i32(tcg_res
);
10256 tcg_temp_free_i32(tcg_op
);
10260 clear_vec_high(s
, rd
);
10264 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
10265 tcg_temp_free_i32(tcg_rmode
);
10267 if (need_fpstatus
) {
10268 tcg_temp_free_ptr(tcg_fpstatus
);
10272 /* C3.6.13 AdvSIMD scalar x indexed element
10273 * 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 9 5 4 0
10274 * +-----+---+-----------+------+---+---+------+-----+---+---+------+------+
10275 * | 0 1 | U | 1 1 1 1 1 | size | L | M | Rm | opc | H | 0 | Rn | Rd |
10276 * +-----+---+-----------+------+---+---+------+-----+---+---+------+------+
10277 * C3.6.18 AdvSIMD vector x indexed element
10278 * 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 9 5 4 0
10279 * +---+---+---+-----------+------+---+---+------+-----+---+---+------+------+
10280 * | 0 | Q | U | 0 1 1 1 1 | size | L | M | Rm | opc | H | 0 | Rn | Rd |
10281 * +---+---+---+-----------+------+---+---+------+-----+---+---+------+------+
10283 static void disas_simd_indexed(DisasContext
*s
, uint32_t insn
)
10285 /* This encoding has two kinds of instruction:
10286 * normal, where we perform elt x idxelt => elt for each
10287 * element in the vector
10288 * long, where we perform elt x idxelt and generate a result of
10289 * double the width of the input element
10290 * The long ops have a 'part' specifier (ie come in INSN, INSN2 pairs).
10292 bool is_scalar
= extract32(insn
, 28, 1);
10293 bool is_q
= extract32(insn
, 30, 1);
10294 bool u
= extract32(insn
, 29, 1);
10295 int size
= extract32(insn
, 22, 2);
10296 int l
= extract32(insn
, 21, 1);
10297 int m
= extract32(insn
, 20, 1);
10298 /* Note that the Rm field here is only 4 bits, not 5 as it usually is */
10299 int rm
= extract32(insn
, 16, 4);
10300 int opcode
= extract32(insn
, 12, 4);
10301 int h
= extract32(insn
, 11, 1);
10302 int rn
= extract32(insn
, 5, 5);
10303 int rd
= extract32(insn
, 0, 5);
10304 bool is_long
= false;
10305 bool is_fp
= false;
10310 case 0x0: /* MLA */
10311 case 0x4: /* MLS */
10312 if (!u
|| is_scalar
) {
10313 unallocated_encoding(s
);
10317 case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
10318 case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
10319 case 0xa: /* SMULL, SMULL2, UMULL, UMULL2 */
10321 unallocated_encoding(s
);
10326 case 0x3: /* SQDMLAL, SQDMLAL2 */
10327 case 0x7: /* SQDMLSL, SQDMLSL2 */
10328 case 0xb: /* SQDMULL, SQDMULL2 */
10331 case 0xc: /* SQDMULH */
10332 case 0xd: /* SQRDMULH */
10334 unallocated_encoding(s
);
10338 case 0x8: /* MUL */
10339 if (u
|| is_scalar
) {
10340 unallocated_encoding(s
);
10344 case 0x1: /* FMLA */
10345 case 0x5: /* FMLS */
10347 unallocated_encoding(s
);
10351 case 0x9: /* FMUL, FMULX */
10352 if (!extract32(size
, 1, 1)) {
10353 unallocated_encoding(s
);
10359 unallocated_encoding(s
);
10364 /* low bit of size indicates single/double */
10365 size
= extract32(size
, 0, 1) ? 3 : 2;
10367 index
= h
<< 1 | l
;
10370 unallocated_encoding(s
);
10379 index
= h
<< 2 | l
<< 1 | m
;
10382 index
= h
<< 1 | l
;
10386 unallocated_encoding(s
);
10391 if (!fp_access_check(s
)) {
10396 fpst
= get_fpstatus_ptr();
10398 TCGV_UNUSED_PTR(fpst
);
10402 TCGv_i64 tcg_idx
= tcg_temp_new_i64();
10405 assert(is_fp
&& is_q
&& !is_long
);
10407 read_vec_element(s
, tcg_idx
, rm
, index
, MO_64
);
10409 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
10410 TCGv_i64 tcg_op
= tcg_temp_new_i64();
10411 TCGv_i64 tcg_res
= tcg_temp_new_i64();
10413 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
10416 case 0x5: /* FMLS */
10417 /* As usual for ARM, separate negation for fused multiply-add */
10418 gen_helper_vfp_negd(tcg_op
, tcg_op
);
10420 case 0x1: /* FMLA */
10421 read_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
10422 gen_helper_vfp_muladdd(tcg_res
, tcg_op
, tcg_idx
, tcg_res
, fpst
);
10424 case 0x9: /* FMUL, FMULX */
10426 gen_helper_vfp_mulxd(tcg_res
, tcg_op
, tcg_idx
, fpst
);
10428 gen_helper_vfp_muld(tcg_res
, tcg_op
, tcg_idx
, fpst
);
10432 g_assert_not_reached();
10435 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
10436 tcg_temp_free_i64(tcg_op
);
10437 tcg_temp_free_i64(tcg_res
);
10441 clear_vec_high(s
, rd
);
10444 tcg_temp_free_i64(tcg_idx
);
10445 } else if (!is_long
) {
10446 /* 32 bit floating point, or 16 or 32 bit integer.
10447 * For the 16 bit scalar case we use the usual Neon helpers and
10448 * rely on the fact that 0 op 0 == 0 with no side effects.
10450 TCGv_i32 tcg_idx
= tcg_temp_new_i32();
10451 int pass
, maxpasses
;
10456 maxpasses
= is_q
? 4 : 2;
10459 read_vec_element_i32(s
, tcg_idx
, rm
, index
, size
);
10461 if (size
== 1 && !is_scalar
) {
10462 /* The simplest way to handle the 16x16 indexed ops is to duplicate
10463 * the index into both halves of the 32 bit tcg_idx and then use
10464 * the usual Neon helpers.
10466 tcg_gen_deposit_i32(tcg_idx
, tcg_idx
, tcg_idx
, 16, 16);
10469 for (pass
= 0; pass
< maxpasses
; pass
++) {
10470 TCGv_i32 tcg_op
= tcg_temp_new_i32();
10471 TCGv_i32 tcg_res
= tcg_temp_new_i32();
10473 read_vec_element_i32(s
, tcg_op
, rn
, pass
, is_scalar
? size
: MO_32
);
10476 case 0x0: /* MLA */
10477 case 0x4: /* MLS */
10478 case 0x8: /* MUL */
10480 static NeonGenTwoOpFn
* const fns
[2][2] = {
10481 { gen_helper_neon_add_u16
, gen_helper_neon_sub_u16
},
10482 { tcg_gen_add_i32
, tcg_gen_sub_i32
},
10484 NeonGenTwoOpFn
*genfn
;
10485 bool is_sub
= opcode
== 0x4;
10488 gen_helper_neon_mul_u16(tcg_res
, tcg_op
, tcg_idx
);
10490 tcg_gen_mul_i32(tcg_res
, tcg_op
, tcg_idx
);
10492 if (opcode
== 0x8) {
10495 read_vec_element_i32(s
, tcg_op
, rd
, pass
, MO_32
);
10496 genfn
= fns
[size
- 1][is_sub
];
10497 genfn(tcg_res
, tcg_op
, tcg_res
);
10500 case 0x5: /* FMLS */
10501 /* As usual for ARM, separate negation for fused multiply-add */
10502 gen_helper_vfp_negs(tcg_op
, tcg_op
);
10504 case 0x1: /* FMLA */
10505 read_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
10506 gen_helper_vfp_muladds(tcg_res
, tcg_op
, tcg_idx
, tcg_res
, fpst
);
10508 case 0x9: /* FMUL, FMULX */
10510 gen_helper_vfp_mulxs(tcg_res
, tcg_op
, tcg_idx
, fpst
);
10512 gen_helper_vfp_muls(tcg_res
, tcg_op
, tcg_idx
, fpst
);
10515 case 0xc: /* SQDMULH */
10517 gen_helper_neon_qdmulh_s16(tcg_res
, cpu_env
,
10520 gen_helper_neon_qdmulh_s32(tcg_res
, cpu_env
,
10524 case 0xd: /* SQRDMULH */
10526 gen_helper_neon_qrdmulh_s16(tcg_res
, cpu_env
,
10529 gen_helper_neon_qrdmulh_s32(tcg_res
, cpu_env
,
10534 g_assert_not_reached();
10538 write_fp_sreg(s
, rd
, tcg_res
);
10540 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
10543 tcg_temp_free_i32(tcg_op
);
10544 tcg_temp_free_i32(tcg_res
);
10547 tcg_temp_free_i32(tcg_idx
);
10550 clear_vec_high(s
, rd
);
10553 /* long ops: 16x16->32 or 32x32->64 */
10554 TCGv_i64 tcg_res
[2];
10556 bool satop
= extract32(opcode
, 0, 1);
10557 TCGMemOp memop
= MO_32
;
10564 TCGv_i64 tcg_idx
= tcg_temp_new_i64();
10566 read_vec_element(s
, tcg_idx
, rm
, index
, memop
);
10568 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
10569 TCGv_i64 tcg_op
= tcg_temp_new_i64();
10570 TCGv_i64 tcg_passres
;
10576 passelt
= pass
+ (is_q
* 2);
10579 read_vec_element(s
, tcg_op
, rn
, passelt
, memop
);
10581 tcg_res
[pass
] = tcg_temp_new_i64();
10583 if (opcode
== 0xa || opcode
== 0xb) {
10584 /* Non-accumulating ops */
10585 tcg_passres
= tcg_res
[pass
];
10587 tcg_passres
= tcg_temp_new_i64();
10590 tcg_gen_mul_i64(tcg_passres
, tcg_op
, tcg_idx
);
10591 tcg_temp_free_i64(tcg_op
);
10594 /* saturating, doubling */
10595 gen_helper_neon_addl_saturate_s64(tcg_passres
, cpu_env
,
10596 tcg_passres
, tcg_passres
);
10599 if (opcode
== 0xa || opcode
== 0xb) {
10603 /* Accumulating op: handle accumulate step */
10604 read_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
10607 case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
10608 tcg_gen_add_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
10610 case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
10611 tcg_gen_sub_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
10613 case 0x7: /* SQDMLSL, SQDMLSL2 */
10614 tcg_gen_neg_i64(tcg_passres
, tcg_passres
);
10616 case 0x3: /* SQDMLAL, SQDMLAL2 */
10617 gen_helper_neon_addl_saturate_s64(tcg_res
[pass
], cpu_env
,
10622 g_assert_not_reached();
10624 tcg_temp_free_i64(tcg_passres
);
10626 tcg_temp_free_i64(tcg_idx
);
10629 clear_vec_high(s
, rd
);
10632 TCGv_i32 tcg_idx
= tcg_temp_new_i32();
10635 read_vec_element_i32(s
, tcg_idx
, rm
, index
, size
);
10638 /* The simplest way to handle the 16x16 indexed ops is to
10639 * duplicate the index into both halves of the 32 bit tcg_idx
10640 * and then use the usual Neon helpers.
10642 tcg_gen_deposit_i32(tcg_idx
, tcg_idx
, tcg_idx
, 16, 16);
10645 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
10646 TCGv_i32 tcg_op
= tcg_temp_new_i32();
10647 TCGv_i64 tcg_passres
;
10650 read_vec_element_i32(s
, tcg_op
, rn
, pass
, size
);
10652 read_vec_element_i32(s
, tcg_op
, rn
,
10653 pass
+ (is_q
* 2), MO_32
);
10656 tcg_res
[pass
] = tcg_temp_new_i64();
10658 if (opcode
== 0xa || opcode
== 0xb) {
10659 /* Non-accumulating ops */
10660 tcg_passres
= tcg_res
[pass
];
10662 tcg_passres
= tcg_temp_new_i64();
10665 if (memop
& MO_SIGN
) {
10666 gen_helper_neon_mull_s16(tcg_passres
, tcg_op
, tcg_idx
);
10668 gen_helper_neon_mull_u16(tcg_passres
, tcg_op
, tcg_idx
);
10671 gen_helper_neon_addl_saturate_s32(tcg_passres
, cpu_env
,
10672 tcg_passres
, tcg_passres
);
10674 tcg_temp_free_i32(tcg_op
);
10676 if (opcode
== 0xa || opcode
== 0xb) {
10680 /* Accumulating op: handle accumulate step */
10681 read_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
10684 case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
10685 gen_helper_neon_addl_u32(tcg_res
[pass
], tcg_res
[pass
],
10688 case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
10689 gen_helper_neon_subl_u32(tcg_res
[pass
], tcg_res
[pass
],
10692 case 0x7: /* SQDMLSL, SQDMLSL2 */
10693 gen_helper_neon_negl_u32(tcg_passres
, tcg_passres
);
10695 case 0x3: /* SQDMLAL, SQDMLAL2 */
10696 gen_helper_neon_addl_saturate_s32(tcg_res
[pass
], cpu_env
,
10701 g_assert_not_reached();
10703 tcg_temp_free_i64(tcg_passres
);
10705 tcg_temp_free_i32(tcg_idx
);
10708 tcg_gen_ext32u_i64(tcg_res
[0], tcg_res
[0]);
10713 tcg_res
[1] = tcg_const_i64(0);
10716 for (pass
= 0; pass
< 2; pass
++) {
10717 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
10718 tcg_temp_free_i64(tcg_res
[pass
]);
10722 if (!TCGV_IS_UNUSED_PTR(fpst
)) {
10723 tcg_temp_free_ptr(fpst
);
10727 /* C3.6.19 Crypto AES
10728 * 31 24 23 22 21 17 16 12 11 10 9 5 4 0
10729 * +-----------------+------+-----------+--------+-----+------+------+
10730 * | 0 1 0 0 1 1 1 0 | size | 1 0 1 0 0 | opcode | 1 0 | Rn | Rd |
10731 * +-----------------+------+-----------+--------+-----+------+------+
10733 static void disas_crypto_aes(DisasContext
*s
, uint32_t insn
)
10735 int size
= extract32(insn
, 22, 2);
10736 int opcode
= extract32(insn
, 12, 5);
10737 int rn
= extract32(insn
, 5, 5);
10738 int rd
= extract32(insn
, 0, 5);
10740 TCGv_i32 tcg_rd_regno
, tcg_rn_regno
, tcg_decrypt
;
10741 CryptoThreeOpEnvFn
*genfn
;
10743 if (!arm_dc_feature(s
, ARM_FEATURE_V8_AES
)
10745 unallocated_encoding(s
);
10750 case 0x4: /* AESE */
10752 genfn
= gen_helper_crypto_aese
;
10754 case 0x6: /* AESMC */
10756 genfn
= gen_helper_crypto_aesmc
;
10758 case 0x5: /* AESD */
10760 genfn
= gen_helper_crypto_aese
;
10762 case 0x7: /* AESIMC */
10764 genfn
= gen_helper_crypto_aesmc
;
10767 unallocated_encoding(s
);
10771 /* Note that we convert the Vx register indexes into the
10772 * index within the vfp.regs[] array, so we can share the
10773 * helper with the AArch32 instructions.
10775 tcg_rd_regno
= tcg_const_i32(rd
<< 1);
10776 tcg_rn_regno
= tcg_const_i32(rn
<< 1);
10777 tcg_decrypt
= tcg_const_i32(decrypt
);
10779 genfn(cpu_env
, tcg_rd_regno
, tcg_rn_regno
, tcg_decrypt
);
10781 tcg_temp_free_i32(tcg_rd_regno
);
10782 tcg_temp_free_i32(tcg_rn_regno
);
10783 tcg_temp_free_i32(tcg_decrypt
);
10786 /* C3.6.20 Crypto three-reg SHA
10787 * 31 24 23 22 21 20 16 15 14 12 11 10 9 5 4 0
10788 * +-----------------+------+---+------+---+--------+-----+------+------+
10789 * | 0 1 0 1 1 1 1 0 | size | 0 | Rm | 0 | opcode | 0 0 | Rn | Rd |
10790 * +-----------------+------+---+------+---+--------+-----+------+------+
10792 static void disas_crypto_three_reg_sha(DisasContext
*s
, uint32_t insn
)
10794 int size
= extract32(insn
, 22, 2);
10795 int opcode
= extract32(insn
, 12, 3);
10796 int rm
= extract32(insn
, 16, 5);
10797 int rn
= extract32(insn
, 5, 5);
10798 int rd
= extract32(insn
, 0, 5);
10799 CryptoThreeOpEnvFn
*genfn
;
10800 TCGv_i32 tcg_rd_regno
, tcg_rn_regno
, tcg_rm_regno
;
10801 int feature
= ARM_FEATURE_V8_SHA256
;
10804 unallocated_encoding(s
);
10809 case 0: /* SHA1C */
10810 case 1: /* SHA1P */
10811 case 2: /* SHA1M */
10812 case 3: /* SHA1SU0 */
10814 feature
= ARM_FEATURE_V8_SHA1
;
10816 case 4: /* SHA256H */
10817 genfn
= gen_helper_crypto_sha256h
;
10819 case 5: /* SHA256H2 */
10820 genfn
= gen_helper_crypto_sha256h2
;
10822 case 6: /* SHA256SU1 */
10823 genfn
= gen_helper_crypto_sha256su1
;
10826 unallocated_encoding(s
);
10830 if (!arm_dc_feature(s
, feature
)) {
10831 unallocated_encoding(s
);
10835 tcg_rd_regno
= tcg_const_i32(rd
<< 1);
10836 tcg_rn_regno
= tcg_const_i32(rn
<< 1);
10837 tcg_rm_regno
= tcg_const_i32(rm
<< 1);
10840 genfn(cpu_env
, tcg_rd_regno
, tcg_rn_regno
, tcg_rm_regno
);
10842 TCGv_i32 tcg_opcode
= tcg_const_i32(opcode
);
10844 gen_helper_crypto_sha1_3reg(cpu_env
, tcg_rd_regno
,
10845 tcg_rn_regno
, tcg_rm_regno
, tcg_opcode
);
10846 tcg_temp_free_i32(tcg_opcode
);
10849 tcg_temp_free_i32(tcg_rd_regno
);
10850 tcg_temp_free_i32(tcg_rn_regno
);
10851 tcg_temp_free_i32(tcg_rm_regno
);
10854 /* C3.6.21 Crypto two-reg SHA
10855 * 31 24 23 22 21 17 16 12 11 10 9 5 4 0
10856 * +-----------------+------+-----------+--------+-----+------+------+
10857 * | 0 1 0 1 1 1 1 0 | size | 1 0 1 0 0 | opcode | 1 0 | Rn | Rd |
10858 * +-----------------+------+-----------+--------+-----+------+------+
10860 static void disas_crypto_two_reg_sha(DisasContext
*s
, uint32_t insn
)
10862 int size
= extract32(insn
, 22, 2);
10863 int opcode
= extract32(insn
, 12, 5);
10864 int rn
= extract32(insn
, 5, 5);
10865 int rd
= extract32(insn
, 0, 5);
10866 CryptoTwoOpEnvFn
*genfn
;
10868 TCGv_i32 tcg_rd_regno
, tcg_rn_regno
;
10871 unallocated_encoding(s
);
10876 case 0: /* SHA1H */
10877 feature
= ARM_FEATURE_V8_SHA1
;
10878 genfn
= gen_helper_crypto_sha1h
;
10880 case 1: /* SHA1SU1 */
10881 feature
= ARM_FEATURE_V8_SHA1
;
10882 genfn
= gen_helper_crypto_sha1su1
;
10884 case 2: /* SHA256SU0 */
10885 feature
= ARM_FEATURE_V8_SHA256
;
10886 genfn
= gen_helper_crypto_sha256su0
;
10889 unallocated_encoding(s
);
10893 if (!arm_dc_feature(s
, feature
)) {
10894 unallocated_encoding(s
);
10898 tcg_rd_regno
= tcg_const_i32(rd
<< 1);
10899 tcg_rn_regno
= tcg_const_i32(rn
<< 1);
10901 genfn(cpu_env
, tcg_rd_regno
, tcg_rn_regno
);
10903 tcg_temp_free_i32(tcg_rd_regno
);
10904 tcg_temp_free_i32(tcg_rn_regno
);
10907 /* C3.6 Data processing - SIMD, inc Crypto
10909 * As the decode gets a little complex we are using a table based
10910 * approach for this part of the decode.
10912 static const AArch64DecodeTable data_proc_simd
[] = {
10913 /* pattern , mask , fn */
10914 { 0x0e200400, 0x9f200400, disas_simd_three_reg_same
},
10915 { 0x0e200000, 0x9f200c00, disas_simd_three_reg_diff
},
10916 { 0x0e200800, 0x9f3e0c00, disas_simd_two_reg_misc
},
10917 { 0x0e300800, 0x9f3e0c00, disas_simd_across_lanes
},
10918 { 0x0e000400, 0x9fe08400, disas_simd_copy
},
10919 { 0x0f000000, 0x9f000400, disas_simd_indexed
}, /* vector indexed */
10920 /* simd_mod_imm decode is a subset of simd_shift_imm, so must precede it */
10921 { 0x0f000400, 0x9ff80400, disas_simd_mod_imm
},
10922 { 0x0f000400, 0x9f800400, disas_simd_shift_imm
},
10923 { 0x0e000000, 0xbf208c00, disas_simd_tb
},
10924 { 0x0e000800, 0xbf208c00, disas_simd_zip_trn
},
10925 { 0x2e000000, 0xbf208400, disas_simd_ext
},
10926 { 0x5e200400, 0xdf200400, disas_simd_scalar_three_reg_same
},
10927 { 0x5e200000, 0xdf200c00, disas_simd_scalar_three_reg_diff
},
10928 { 0x5e200800, 0xdf3e0c00, disas_simd_scalar_two_reg_misc
},
10929 { 0x5e300800, 0xdf3e0c00, disas_simd_scalar_pairwise
},
10930 { 0x5e000400, 0xdfe08400, disas_simd_scalar_copy
},
10931 { 0x5f000000, 0xdf000400, disas_simd_indexed
}, /* scalar indexed */
10932 { 0x5f000400, 0xdf800400, disas_simd_scalar_shift_imm
},
10933 { 0x4e280800, 0xff3e0c00, disas_crypto_aes
},
10934 { 0x5e000000, 0xff208c00, disas_crypto_three_reg_sha
},
10935 { 0x5e280800, 0xff3e0c00, disas_crypto_two_reg_sha
},
10936 { 0x00000000, 0x00000000, NULL
}
10939 static void disas_data_proc_simd(DisasContext
*s
, uint32_t insn
)
10941 /* Note that this is called with all non-FP cases from
10942 * table C3-6 so it must UNDEF for entries not specifically
10943 * allocated to instructions in that table.
10945 AArch64DecodeFn
*fn
= lookup_disas_fn(&data_proc_simd
[0], insn
);
10949 unallocated_encoding(s
);
10953 /* C3.6 Data processing - SIMD and floating point */
10954 static void disas_data_proc_simd_fp(DisasContext
*s
, uint32_t insn
)
10956 if (extract32(insn
, 28, 1) == 1 && extract32(insn
, 30, 1) == 0) {
10957 disas_data_proc_fp(s
, insn
);
10959 /* SIMD, including crypto */
10960 disas_data_proc_simd(s
, insn
);
10964 /* C3.1 A64 instruction index by encoding */
10965 static void disas_a64_insn(CPUARMState
*env
, DisasContext
*s
)
10969 insn
= arm_ldl_code(env
, s
->pc
, s
->bswap_code
);
10973 s
->fp_access_checked
= false;
10975 switch (extract32(insn
, 25, 4)) {
10976 case 0x0: case 0x1: case 0x2: case 0x3: /* UNALLOCATED */
10977 unallocated_encoding(s
);
10979 case 0x8: case 0x9: /* Data processing - immediate */
10980 disas_data_proc_imm(s
, insn
);
10982 case 0xa: case 0xb: /* Branch, exception generation and system insns */
10983 disas_b_exc_sys(s
, insn
);
10988 case 0xe: /* Loads and stores */
10989 disas_ldst(s
, insn
);
10992 case 0xd: /* Data processing - register */
10993 disas_data_proc_reg(s
, insn
);
10996 case 0xf: /* Data processing - SIMD and floating point */
10997 disas_data_proc_simd_fp(s
, insn
);
11000 assert(FALSE
); /* all 15 cases should be handled above */
11004 /* if we allocated any temporaries, free them here */
11008 void gen_intermediate_code_a64(ARMCPU
*cpu
, TranslationBlock
*tb
)
11010 CPUState
*cs
= CPU(cpu
);
11011 CPUARMState
*env
= &cpu
->env
;
11012 DisasContext dc1
, *dc
= &dc1
;
11013 target_ulong pc_start
;
11014 target_ulong next_page_start
;
11022 dc
->is_jmp
= DISAS_NEXT
;
11024 dc
->singlestep_enabled
= cs
->singlestep_enabled
;
11028 /* If we are coming from secure EL0 in a system with a 32-bit EL3, then
11029 * there is no secure EL1, so we route exceptions to EL3.
11031 dc
->secure_routed_to_el3
= arm_feature(env
, ARM_FEATURE_EL3
) &&
11032 !arm_el_is_aa64(env
, 3);
11034 dc
->bswap_code
= 0;
11035 dc
->condexec_mask
= 0;
11036 dc
->condexec_cond
= 0;
11037 dc
->mmu_idx
= ARM_TBFLAG_MMUIDX(tb
->flags
);
11038 dc
->current_el
= arm_mmu_idx_to_el(dc
->mmu_idx
);
11039 #if !defined(CONFIG_USER_ONLY)
11040 dc
->user
= (dc
->current_el
== 0);
11042 dc
->fp_excp_el
= ARM_TBFLAG_FPEXC_EL(tb
->flags
);
11044 dc
->vec_stride
= 0;
11045 dc
->cp_regs
= cpu
->cp_regs
;
11046 dc
->features
= env
->features
;
11048 /* Single step state. The code-generation logic here is:
11050 * generate code with no special handling for single-stepping (except
11051 * that anything that can make us go to SS_ACTIVE == 1 must end the TB;
11052 * this happens anyway because those changes are all system register or
11054 * SS_ACTIVE == 1, PSTATE.SS == 1: (active-not-pending)
11055 * emit code for one insn
11056 * emit code to clear PSTATE.SS
11057 * emit code to generate software step exception for completed step
11058 * end TB (as usual for having generated an exception)
11059 * SS_ACTIVE == 1, PSTATE.SS == 0: (active-pending)
11060 * emit code to generate a software step exception
11063 dc
->ss_active
= ARM_TBFLAG_SS_ACTIVE(tb
->flags
);
11064 dc
->pstate_ss
= ARM_TBFLAG_PSTATE_SS(tb
->flags
);
11065 dc
->is_ldex
= false;
11066 dc
->ss_same_el
= (arm_debug_target_el(env
) == dc
->current_el
);
11068 init_tmp_a64_array(dc
);
11070 next_page_start
= (pc_start
& TARGET_PAGE_MASK
) + TARGET_PAGE_SIZE
;
11072 max_insns
= tb
->cflags
& CF_COUNT_MASK
;
11073 if (max_insns
== 0) {
11074 max_insns
= CF_COUNT_MASK
;
11076 if (max_insns
> TCG_MAX_INSNS
) {
11077 max_insns
= TCG_MAX_INSNS
;
11082 tcg_clear_temp_count();
11085 tcg_gen_insn_start(dc
->pc
, 0);
11088 if (unlikely(!QTAILQ_EMPTY(&cs
->breakpoints
))) {
11090 QTAILQ_FOREACH(bp
, &cs
->breakpoints
, entry
) {
11091 if (bp
->pc
== dc
->pc
) {
11092 if (bp
->flags
& BP_CPU
) {
11093 gen_a64_set_pc_im(dc
->pc
);
11094 gen_helper_check_breakpoints(cpu_env
);
11095 /* End the TB early; it likely won't be executed */
11096 dc
->is_jmp
= DISAS_UPDATE
;
11098 gen_exception_internal_insn(dc
, 0, EXCP_DEBUG
);
11099 /* The address covered by the breakpoint must be
11100 included in [tb->pc, tb->pc + tb->size) in order
11101 to for it to be properly cleared -- thus we
11102 increment the PC here so that the logic setting
11103 tb->size below does the right thing. */
11105 goto done_generating
;
11112 if (num_insns
== max_insns
&& (tb
->cflags
& CF_LAST_IO
)) {
11116 if (dc
->ss_active
&& !dc
->pstate_ss
) {
11117 /* Singlestep state is Active-pending.
11118 * If we're in this state at the start of a TB then either
11119 * a) we just took an exception to an EL which is being debugged
11120 * and this is the first insn in the exception handler
11121 * b) debug exceptions were masked and we just unmasked them
11122 * without changing EL (eg by clearing PSTATE.D)
11123 * In either case we're going to take a swstep exception in the
11124 * "did not step an insn" case, and so the syndrome ISV and EX
11125 * bits should be zero.
11127 assert(num_insns
== 1);
11128 gen_exception(EXCP_UDEF
, syn_swstep(dc
->ss_same_el
, 0, 0),
11129 default_exception_el(dc
));
11130 dc
->is_jmp
= DISAS_EXC
;
11134 disas_a64_insn(env
, dc
);
11136 if (tcg_check_temp_count()) {
11137 fprintf(stderr
, "TCG temporary leak before "TARGET_FMT_lx
"\n",
11141 /* Translation stops when a conditional branch is encountered.
11142 * Otherwise the subsequent code could get translated several times.
11143 * Also stop translation when a page boundary is reached. This
11144 * ensures prefetch aborts occur at the right place.
11146 } while (!dc
->is_jmp
&& !tcg_op_buf_full() &&
11147 !cs
->singlestep_enabled
&&
11150 dc
->pc
< next_page_start
&&
11151 num_insns
< max_insns
);
11153 if (tb
->cflags
& CF_LAST_IO
) {
11157 if (unlikely(cs
->singlestep_enabled
|| dc
->ss_active
)
11158 && dc
->is_jmp
!= DISAS_EXC
) {
11159 /* Note that this means single stepping WFI doesn't halt the CPU.
11160 * For conditional branch insns this is harmless unreachable code as
11161 * gen_goto_tb() has already handled emitting the debug exception
11162 * (and thus a tb-jump is not possible when singlestepping).
11164 assert(dc
->is_jmp
!= DISAS_TB_JUMP
);
11165 if (dc
->is_jmp
!= DISAS_JUMP
) {
11166 gen_a64_set_pc_im(dc
->pc
);
11168 if (cs
->singlestep_enabled
) {
11169 gen_exception_internal(EXCP_DEBUG
);
11171 gen_step_complete_exception(dc
);
11174 switch (dc
->is_jmp
) {
11176 gen_goto_tb(dc
, 1, dc
->pc
);
11180 gen_a64_set_pc_im(dc
->pc
);
11183 /* indicate that the hash table must be used to find the next TB */
11184 tcg_gen_exit_tb(0);
11186 case DISAS_TB_JUMP
:
11191 gen_a64_set_pc_im(dc
->pc
);
11192 gen_helper_wfe(cpu_env
);
11195 gen_a64_set_pc_im(dc
->pc
);
11196 gen_helper_yield(cpu_env
);
11199 /* This is a special case because we don't want to just halt the CPU
11200 * if trying to debug across a WFI.
11202 gen_a64_set_pc_im(dc
->pc
);
11203 gen_helper_wfi(cpu_env
);
11204 /* The helper doesn't necessarily throw an exception, but we
11205 * must go back to the main loop to check for interrupts anyway.
11207 tcg_gen_exit_tb(0);
11213 gen_tb_end(tb
, num_insns
);
11216 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM
)) {
11217 qemu_log("----------------\n");
11218 qemu_log("IN: %s\n", lookup_symbol(pc_start
));
11219 log_target_disas(cs
, pc_start
, dc
->pc
- pc_start
,
11220 4 | (dc
->bswap_code
<< 1));
11224 tb
->size
= dc
->pc
- pc_start
;
11225 tb
->icount
= num_insns
;