target-xtensa/helper.c

   1 /*
   2  * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are met:
   7  *     * Redistributions of source code must retain the above copyright
   8  *       notice, this list of conditions and the following disclaimer.
   9  *     * Redistributions in binary form must reproduce the above copyright
  10  *       notice, this list of conditions and the following disclaimer in the
  11  *       documentation and/or other materials provided with the distribution.
  12  *     * Neither the name of the Open Source and Linux Lab nor the
  13  *       names of its contributors may be used to endorse or promote products
  14  *       derived from this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  17  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  19  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
  20  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  21  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  22  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  23  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  24  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  25  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  26  */
  27
  28 #include "cpu.h"
  29 #include "exec/exec-all.h"
  30 #include "exec/gdbstub.h"
  31 #include "qemu/host-utils.h"
  32 #if !defined(CONFIG_USER_ONLY)
  33 #include "hw/loader.h"
  34 #endif
  35
  36 static struct XtensaConfigList *xtensa_cores;
  37
  38 static void xtensa_core_class_init(ObjectClass *oc, void *data)
  39 {
  40     CPUClass *cc = CPU_CLASS(oc);
  41     XtensaCPUClass *xcc = XTENSA_CPU_CLASS(oc);
  42     const XtensaConfig *config = data;
  43
  44     xcc->config = config;
  45
  46     /* Use num_core_regs to see only non-privileged registers in an unmodified
  47      * gdb. Use num_regs to see all registers. gdb modification is required
  48      * for that: reset bit 0 in the 'flags' field of the registers definitions
  49      * in the gdb/xtensa-config.c inside gdb source tree or inside gdb overlay.
  50      */
  51     cc->gdb_num_core_regs = config->gdb_regmap.num_regs;
  52 }
  53
  54 void xtensa_register_core(XtensaConfigList *node)
  55 {
  56     TypeInfo type = {
  57         .parent = TYPE_XTENSA_CPU,
  58         .class_init = xtensa_core_class_init,
  59         .class_data = (void *)node->config,
  60     };
  61
  62     node->next = xtensa_cores;
  63     xtensa_cores = node;
  64     type.name = g_strdup_printf("%s-" TYPE_XTENSA_CPU, node->config->name);
  65     type_register(&type);
  66     g_free((gpointer)type.name);
  67 }
  68
  69 static uint32_t check_hw_breakpoints(CPUXtensaState *env)
  70 {
  71     unsigned i;
  72
  73     for (i = 0; i < env->config->ndbreak; ++i) {
  74         if (env->cpu_watchpoint[i] &&
  75                 env->cpu_watchpoint[i]->flags & BP_WATCHPOINT_HIT) {
  76             return DEBUGCAUSE_DB | (i << DEBUGCAUSE_DBNUM_SHIFT);
  77         }
  78     }
  79     return 0;
  80 }
  81
  82 void xtensa_breakpoint_handler(CPUState *cs)
  83 {
  84     XtensaCPU *cpu = XTENSA_CPU(cs);
  85     CPUXtensaState *env = &cpu->env;
  86
  87     if (cs->watchpoint_hit) {
  88         if (cs->watchpoint_hit->flags & BP_CPU) {
  89             uint32_t cause;
  90
  91             cs->watchpoint_hit = NULL;
  92             cause = check_hw_breakpoints(env);
  93             if (cause) {
  94                 debug_exception_env(env, cause);
  95             }
  96             cpu_resume_from_signal(cs, NULL);
  97         }
  98     }
  99 }
 100
 101 XtensaCPU *cpu_xtensa_init(const char *cpu_model)
 102 {
 103     ObjectClass *oc;
 104     XtensaCPU *cpu;
 105     CPUXtensaState *env;
 106
 107     oc = cpu_class_by_name(TYPE_XTENSA_CPU, cpu_model);
 108     if (oc == NULL) {
 109         return NULL;
 110     }
 111
 112     cpu = XTENSA_CPU(object_new(object_class_get_name(oc)));
 113     env = &cpu->env;
 114
 115     xtensa_irq_init(env);
 116
 117     object_property_set_bool(OBJECT(cpu), true, "realized", NULL);
 118
 119     return cpu;
 120 }
 121
 122
 123 void xtensa_cpu_list(FILE *f, fprintf_function cpu_fprintf)
 124 {
 125     XtensaConfigList *core = xtensa_cores;
 126     cpu_fprintf(f, "Available CPUs:\n");
 127     for (; core; core = core->next) {
 128         cpu_fprintf(f, "  %s\n", core->config->name);
 129     }
 130 }
 131
 132 hwaddr xtensa_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
 133 {
 134     XtensaCPU *cpu = XTENSA_CPU(cs);
 135     uint32_t paddr;
 136     uint32_t page_size;
 137     unsigned access;
 138
 139     if (xtensa_get_physical_addr(&cpu->env, false, addr, 0, 0,
 140                 &paddr, &page_size, &access) == 0) {
 141         return paddr;
 142     }
 143     if (xtensa_get_physical_addr(&cpu->env, false, addr, 2, 0,
 144                 &paddr, &page_size, &access) == 0) {
 145         return paddr;
 146     }
 147     return ~0;
 148 }
 149
 150 static uint32_t relocated_vector(CPUXtensaState *env, uint32_t vector)
 151 {
 152     if (xtensa_option_enabled(env->config,
 153                 XTENSA_OPTION_RELOCATABLE_VECTOR)) {
 154         return vector - env->config->vecbase + env->sregs[VECBASE];
 155     } else {
 156         return vector;
 157     }
 158 }
 159
 160 /*!
 161  * Handle penging IRQ.
 162  * For the high priority interrupt jump to the corresponding interrupt vector.
 163  * For the level-1 interrupt convert it to either user, kernel or double
 164  * exception with the 'level-1 interrupt' exception cause.
 165  */
 166 static void handle_interrupt(CPUXtensaState *env)
 167 {
 168     int level = env->pending_irq_level;
 169
 170     if (level > xtensa_get_cintlevel(env) &&
 171             level <= env->config->nlevel &&
 172             (env->config->level_mask[level] &
 173              env->sregs[INTSET] &
 174              env->sregs[INTENABLE])) {
 175         CPUState *cs = CPU(xtensa_env_get_cpu(env));
 176
 177         if (level > 1) {
 178             env->sregs[EPC1 + level - 1] = env->pc;
 179             env->sregs[EPS2 + level - 2] = env->sregs[PS];
 180             env->sregs[PS] =
 181                 (env->sregs[PS] & ~PS_INTLEVEL) | level | PS_EXCM;
 182             env->pc = relocated_vector(env,
 183                     env->config->interrupt_vector[level]);
 184         } else {
 185             env->sregs[EXCCAUSE] = LEVEL1_INTERRUPT_CAUSE;
 186
 187             if (env->sregs[PS] & PS_EXCM) {
 188                 if (env->config->ndepc) {
 189                     env->sregs[DEPC] = env->pc;
 190                 } else {
 191                     env->sregs[EPC1] = env->pc;
 192                 }
 193                 cs->exception_index = EXC_DOUBLE;
 194             } else {
 195                 env->sregs[EPC1] = env->pc;
 196                 cs->exception_index =
 197                     (env->sregs[PS] & PS_UM) ? EXC_USER : EXC_KERNEL;
 198             }
 199             env->sregs[PS] |= PS_EXCM;
 200         }
 201         env->exception_taken = 1;
 202     }
 203 }
 204
 205 void xtensa_cpu_do_interrupt(CPUState *cs)
 206 {
 207     XtensaCPU *cpu = XTENSA_CPU(cs);
 208     CPUXtensaState *env = &cpu->env;
 209
 210     if (cs->exception_index == EXC_IRQ) {
 211         qemu_log_mask(CPU_LOG_INT,
 212                 "%s(EXC_IRQ) level = %d, cintlevel = %d, "
 213                 "pc = %08x, a0 = %08x, ps = %08x, "
 214                 "intset = %08x, intenable = %08x, "
 215                 "ccount = %08x\n",
 216                 __func__, env->pending_irq_level, xtensa_get_cintlevel(env),
 217                 env->pc, env->regs[0], env->sregs[PS],
 218                 env->sregs[INTSET], env->sregs[INTENABLE],
 219                 env->sregs[CCOUNT]);
 220         handle_interrupt(env);
 221     }
 222
 223     switch (cs->exception_index) {
 224     case EXC_WINDOW_OVERFLOW4:
 225     case EXC_WINDOW_UNDERFLOW4:
 226     case EXC_WINDOW_OVERFLOW8:
 227     case EXC_WINDOW_UNDERFLOW8:
 228     case EXC_WINDOW_OVERFLOW12:
 229     case EXC_WINDOW_UNDERFLOW12:
 230     case EXC_KERNEL:
 231     case EXC_USER:
 232     case EXC_DOUBLE:
 233     case EXC_DEBUG:
 234         qemu_log_mask(CPU_LOG_INT, "%s(%d) "
 235                 "pc = %08x, a0 = %08x, ps = %08x, ccount = %08x\n",
 236                 __func__, cs->exception_index,
 237                 env->pc, env->regs[0], env->sregs[PS], env->sregs[CCOUNT]);
 238         if (env->config->exception_vector[cs->exception_index]) {
 239             env->pc = relocated_vector(env,
 240                     env->config->exception_vector[cs->exception_index]);
 241             env->exception_taken = 1;
 242         } else {
 243             qemu_log("%s(pc = %08x) bad exception_index: %d\n",
 244                     __func__, env->pc, cs->exception_index);
 245         }
 246         break;
 247
 248     case EXC_IRQ:
 249         break;
 250
 251     default:
 252         qemu_log("%s(pc = %08x) unknown exception_index: %d\n",
 253                 __func__, env->pc, cs->exception_index);
 254         break;
 255     }
 256     check_interrupts(env);
 257 }
 258
 259 static void reset_tlb_mmu_all_ways(CPUXtensaState *env,
 260         const xtensa_tlb *tlb, xtensa_tlb_entry entry[][MAX_TLB_WAY_SIZE])
 261 {
 262     unsigned wi, ei;
 263
 264     for (wi = 0; wi < tlb->nways; ++wi) {
 265         for (ei = 0; ei < tlb->way_size[wi]; ++ei) {
 266             entry[wi][ei].asid = 0;
 267             entry[wi][ei].variable = true;
 268         }
 269     }
 270 }
 271
 272 static void reset_tlb_mmu_ways56(CPUXtensaState *env,
 273         const xtensa_tlb *tlb, xtensa_tlb_entry entry[][MAX_TLB_WAY_SIZE])
 274 {
 275     if (!tlb->varway56) {
 276         static const xtensa_tlb_entry way5[] = {
 277             {
 278                 .vaddr = 0xd0000000,
 279                 .paddr = 0,
 280                 .asid = 1,
 281                 .attr = 7,
 282                 .variable = false,
 283             }, {
 284                 .vaddr = 0xd8000000,
 285                 .paddr = 0,
 286                 .asid = 1,
 287                 .attr = 3,
 288                 .variable = false,
 289             }
 290         };
 291         static const xtensa_tlb_entry way6[] = {
 292             {
 293                 .vaddr = 0xe0000000,
 294                 .paddr = 0xf0000000,
 295                 .asid = 1,
 296                 .attr = 7,
 297                 .variable = false,
 298             }, {
 299                 .vaddr = 0xf0000000,
 300                 .paddr = 0xf0000000,
 301                 .asid = 1,
 302                 .attr = 3,
 303                 .variable = false,
 304             }
 305         };
 306         memcpy(entry[5], way5, sizeof(way5));
 307         memcpy(entry[6], way6, sizeof(way6));
 308     } else {
 309         uint32_t ei;
 310         for (ei = 0; ei < 8; ++ei) {
 311             entry[6][ei].vaddr = ei << 29;
 312             entry[6][ei].paddr = ei << 29;
 313             entry[6][ei].asid = 1;
 314             entry[6][ei].attr = 3;
 315         }
 316     }
 317 }
 318
 319 static void reset_tlb_region_way0(CPUXtensaState *env,
 320         xtensa_tlb_entry entry[][MAX_TLB_WAY_SIZE])
 321 {
 322     unsigned ei;
 323
 324     for (ei = 0; ei < 8; ++ei) {
 325         entry[0][ei].vaddr = ei << 29;
 326         entry[0][ei].paddr = ei << 29;
 327         entry[0][ei].asid = 1;
 328         entry[0][ei].attr = 2;
 329         entry[0][ei].variable = true;
 330     }
 331 }
 332
 333 void reset_mmu(CPUXtensaState *env)
 334 {
 335     if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
 336         env->sregs[RASID] = 0x04030201;
 337         env->sregs[ITLBCFG] = 0;
 338         env->sregs[DTLBCFG] = 0;
 339         env->autorefill_idx = 0;
 340         reset_tlb_mmu_all_ways(env, &env->config->itlb, env->itlb);
 341         reset_tlb_mmu_all_ways(env, &env->config->dtlb, env->dtlb);
 342         reset_tlb_mmu_ways56(env, &env->config->itlb, env->itlb);
 343         reset_tlb_mmu_ways56(env, &env->config->dtlb, env->dtlb);
 344     } else {
 345         reset_tlb_region_way0(env, env->itlb);
 346         reset_tlb_region_way0(env, env->dtlb);
 347     }
 348 }
 349
 350 static unsigned get_ring(const CPUXtensaState *env, uint8_t asid)
 351 {
 352     unsigned i;
 353     for (i = 0; i < 4; ++i) {
 354         if (((env->sregs[RASID] >> i * 8) & 0xff) == asid) {
 355             return i;
 356         }
 357     }
 358     return 0xff;
 359 }
 360
 361 /*!
 362  * Lookup xtensa TLB for the given virtual address.
 363  * See ISA, 4.6.2.2
 364  *
 365  * \param pwi: [out] way index
 366  * \param pei: [out] entry index
 367  * \param pring: [out] access ring
 368  * \return 0 if ok, exception cause code otherwise
 369  */
 370 int xtensa_tlb_lookup(const CPUXtensaState *env, uint32_t addr, bool dtlb,
 371         uint32_t *pwi, uint32_t *pei, uint8_t *pring)
 372 {
 373     const xtensa_tlb *tlb = dtlb ?
 374         &env->config->dtlb : &env->config->itlb;
 375     const xtensa_tlb_entry (*entry)[MAX_TLB_WAY_SIZE] = dtlb ?
 376         env->dtlb : env->itlb;
 377
 378     int nhits = 0;
 379     unsigned wi;
 380
 381     for (wi = 0; wi < tlb->nways; ++wi) {
 382         uint32_t vpn;
 383         uint32_t ei;
 384         split_tlb_entry_spec_way(env, addr, dtlb, &vpn, wi, &ei);
 385         if (entry[wi][ei].vaddr == vpn && entry[wi][ei].asid) {
 386             unsigned ring = get_ring(env, entry[wi][ei].asid);
 387             if (ring < 4) {
 388                 if (++nhits > 1) {
 389                     return dtlb ?
 390                         LOAD_STORE_TLB_MULTI_HIT_CAUSE :
 391                         INST_TLB_MULTI_HIT_CAUSE;
 392                 }
 393                 *pwi = wi;
 394                 *pei = ei;
 395                 *pring = ring;
 396             }
 397         }
 398     }
 399     return nhits ? 0 :
 400         (dtlb ? LOAD_STORE_TLB_MISS_CAUSE : INST_TLB_MISS_CAUSE);
 401 }
 402
 403 /*!
 404  * Convert MMU ATTR to PAGE_{READ,WRITE,EXEC} mask.
 405  * See ISA, 4.6.5.10
 406  */
 407 static unsigned mmu_attr_to_access(uint32_t attr)
 408 {
 409     unsigned access = 0;
 410
 411     if (attr < 12) {
 412         access |= PAGE_READ;
 413         if (attr & 0x1) {
 414             access |= PAGE_EXEC;
 415         }
 416         if (attr & 0x2) {
 417             access |= PAGE_WRITE;
 418         }
 419
 420         switch (attr & 0xc) {
 421         case 0:
 422             access |= PAGE_CACHE_BYPASS;
 423             break;
 424
 425         case 4:
 426             access |= PAGE_CACHE_WB;
 427             break;
 428
 429         case 8:
 430             access |= PAGE_CACHE_WT;
 431             break;
 432         }
 433     } else if (attr == 13) {
 434         access |= PAGE_READ | PAGE_WRITE | PAGE_CACHE_ISOLATE;
 435     }
 436     return access;
 437 }
 438
 439 /*!
 440  * Convert region protection ATTR to PAGE_{READ,WRITE,EXEC} mask.
 441  * See ISA, 4.6.3.3
 442  */
 443 static unsigned region_attr_to_access(uint32_t attr)
 444 {
 445     static const unsigned access[16] = {
 446          [0] = PAGE_READ | PAGE_WRITE             | PAGE_CACHE_WT,
 447          [1] = PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_WT,
 448          [2] = PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_BYPASS,
 449          [3] =                          PAGE_EXEC | PAGE_CACHE_WB,
 450          [4] = PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_WB,
 451          [5] = PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_WB,
 452         [14] = PAGE_READ | PAGE_WRITE             | PAGE_CACHE_ISOLATE,
 453     };
 454
 455     return access[attr & 0xf];
 456 }
 457
 458 /*!
 459  * Convert cacheattr to PAGE_{READ,WRITE,EXEC} mask.
 460  * See ISA, A.2.14 The Cache Attribute Register
 461  */
 462 static unsigned cacheattr_attr_to_access(uint32_t attr)
 463 {
 464     static const unsigned access[16] = {
 465          [0] = PAGE_READ | PAGE_WRITE             | PAGE_CACHE_WT,
 466          [1] = PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_WT,
 467          [2] = PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_BYPASS,
 468          [3] =                          PAGE_EXEC | PAGE_CACHE_WB,
 469          [4] = PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_WB,
 470         [14] = PAGE_READ | PAGE_WRITE             | PAGE_CACHE_ISOLATE,
 471     };
 472
 473     return access[attr & 0xf];
 474 }
 475
 476 static bool is_access_granted(unsigned access, int is_write)
 477 {
 478     switch (is_write) {
 479     case 0:
 480         return access & PAGE_READ;
 481
 482     case 1:
 483         return access & PAGE_WRITE;
 484
 485     case 2:
 486         return access & PAGE_EXEC;
 487
 488     default:
 489         return 0;
 490     }
 491 }
 492
 493 static int get_pte(CPUXtensaState *env, uint32_t vaddr, uint32_t *pte);
 494
 495 static int get_physical_addr_mmu(CPUXtensaState *env, bool update_tlb,
 496         uint32_t vaddr, int is_write, int mmu_idx,
 497         uint32_t *paddr, uint32_t *page_size, unsigned *access,
 498         bool may_lookup_pt)
 499 {
 500     bool dtlb = is_write != 2;
 501     uint32_t wi;
 502     uint32_t ei;
 503     uint8_t ring;
 504     uint32_t vpn;
 505     uint32_t pte;
 506     const xtensa_tlb_entry *entry = NULL;
 507     xtensa_tlb_entry tmp_entry;
 508     int ret = xtensa_tlb_lookup(env, vaddr, dtlb, &wi, &ei, &ring);
 509
 510     if ((ret == INST_TLB_MISS_CAUSE || ret == LOAD_STORE_TLB_MISS_CAUSE) &&
 511             may_lookup_pt && get_pte(env, vaddr, &pte) == 0) {
 512         ring = (pte >> 4) & 0x3;
 513         wi = 0;
 514         split_tlb_entry_spec_way(env, vaddr, dtlb, &vpn, wi, &ei);
 515
 516         if (update_tlb) {
 517             wi = ++env->autorefill_idx & 0x3;
 518             xtensa_tlb_set_entry(env, dtlb, wi, ei, vpn, pte);
 519             env->sregs[EXCVADDR] = vaddr;
 520             qemu_log("%s: autorefill(%08x): %08x -> %08x\n",
 521                     __func__, vaddr, vpn, pte);
 522         } else {
 523             xtensa_tlb_set_entry_mmu(env, &tmp_entry, dtlb, wi, ei, vpn, pte);
 524             entry = &tmp_entry;
 525         }
 526         ret = 0;
 527     }
 528     if (ret != 0) {
 529         return ret;
 530     }
 531
 532     if (entry == NULL) {
 533         entry = xtensa_tlb_get_entry(env, dtlb, wi, ei);
 534     }
 535
 536     if (ring < mmu_idx) {
 537         return dtlb ?
 538             LOAD_STORE_PRIVILEGE_CAUSE :
 539             INST_FETCH_PRIVILEGE_CAUSE;
 540     }
 541
 542     *access = mmu_attr_to_access(entry->attr) &
 543         ~(dtlb ? PAGE_EXEC : PAGE_READ | PAGE_WRITE);
 544     if (!is_access_granted(*access, is_write)) {
 545         return dtlb ?
 546             (is_write ?
 547              STORE_PROHIBITED_CAUSE :
 548              LOAD_PROHIBITED_CAUSE) :
 549             INST_FETCH_PROHIBITED_CAUSE;
 550     }
 551
 552     *paddr = entry->paddr | (vaddr & ~xtensa_tlb_get_addr_mask(env, dtlb, wi));
 553     *page_size = ~xtensa_tlb_get_addr_mask(env, dtlb, wi) + 1;
 554
 555     return 0;
 556 }
 557
 558 static int get_pte(CPUXtensaState *env, uint32_t vaddr, uint32_t *pte)
 559 {
 560     CPUState *cs = CPU(xtensa_env_get_cpu(env));
 561     uint32_t paddr;
 562     uint32_t page_size;
 563     unsigned access;
 564     uint32_t pt_vaddr =
 565         (env->sregs[PTEVADDR] | (vaddr >> 10)) & 0xfffffffc;
 566     int ret = get_physical_addr_mmu(env, false, pt_vaddr, 0, 0,
 567             &paddr, &page_size, &access, false);
 568
 569     qemu_log("%s: trying autorefill(%08x) -> %08x\n", __func__,
 570             vaddr, ret ? ~0 : paddr);
 571
 572     if (ret == 0) {
 573         *pte = ldl_phys(cs->as, paddr);
 574     }
 575     return ret;
 576 }
 577
 578 static int get_physical_addr_region(CPUXtensaState *env,
 579         uint32_t vaddr, int is_write, int mmu_idx,
 580         uint32_t *paddr, uint32_t *page_size, unsigned *access)
 581 {
 582     bool dtlb = is_write != 2;
 583     uint32_t wi = 0;
 584     uint32_t ei = (vaddr >> 29) & 0x7;
 585     const xtensa_tlb_entry *entry =
 586         xtensa_tlb_get_entry(env, dtlb, wi, ei);
 587
 588     *access = region_attr_to_access(entry->attr);
 589     if (!is_access_granted(*access, is_write)) {
 590         return dtlb ?
 591             (is_write ?
 592              STORE_PROHIBITED_CAUSE :
 593              LOAD_PROHIBITED_CAUSE) :
 594             INST_FETCH_PROHIBITED_CAUSE;
 595     }
 596
 597     *paddr = entry->paddr | (vaddr & ~REGION_PAGE_MASK);
 598     *page_size = ~REGION_PAGE_MASK + 1;
 599
 600     return 0;
 601 }
 602
 603 /*!
 604  * Convert virtual address to physical addr.
 605  * MMU may issue pagewalk and change xtensa autorefill TLB way entry.
 606  *
 607  * \return 0 if ok, exception cause code otherwise
 608  */
 609 int xtensa_get_physical_addr(CPUXtensaState *env, bool update_tlb,
 610         uint32_t vaddr, int is_write, int mmu_idx,
 611         uint32_t *paddr, uint32_t *page_size, unsigned *access)
 612 {
 613     if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
 614         return get_physical_addr_mmu(env, update_tlb,
 615                 vaddr, is_write, mmu_idx, paddr, page_size, access, true);
 616     } else if (xtensa_option_bits_enabled(env->config,
 617                 XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_PROTECTION) |
 618                 XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_TRANSLATION))) {
 619         return get_physical_addr_region(env, vaddr, is_write, mmu_idx,
 620                 paddr, page_size, access);
 621     } else {
 622         *paddr = vaddr;
 623         *page_size = TARGET_PAGE_SIZE;
 624         *access = cacheattr_attr_to_access(
 625                 env->sregs[CACHEATTR] >> ((vaddr & 0xe0000000) >> 27));
 626         return 0;
 627     }
 628 }
 629
 630 static void dump_tlb(FILE *f, fprintf_function cpu_fprintf,
 631         CPUXtensaState *env, bool dtlb)
 632 {
 633     unsigned wi, ei;
 634     const xtensa_tlb *conf =
 635         dtlb ? &env->config->dtlb : &env->config->itlb;
 636     unsigned (*attr_to_access)(uint32_t) =
 637         xtensa_option_enabled(env->config, XTENSA_OPTION_MMU) ?
 638         mmu_attr_to_access : region_attr_to_access;
 639
 640     for (wi = 0; wi < conf->nways; ++wi) {
 641         uint32_t sz = ~xtensa_tlb_get_addr_mask(env, dtlb, wi) + 1;
 642         const char *sz_text;
 643         bool print_header = true;
 644
 645         if (sz >= 0x100000) {
 646             sz >>= 20;
 647             sz_text = "MB";
 648         } else {
 649             sz >>= 10;
 650             sz_text = "KB";
 651         }
 652
 653         for (ei = 0; ei < conf->way_size[wi]; ++ei) {
 654             const xtensa_tlb_entry *entry =
 655                 xtensa_tlb_get_entry(env, dtlb, wi, ei);
 656
 657             if (entry->asid) {
 658                 static const char * const cache_text[8] = {
 659                     [PAGE_CACHE_BYPASS >> PAGE_CACHE_SHIFT] = "Bypass",
 660                     [PAGE_CACHE_WT >> PAGE_CACHE_SHIFT] = "WT",
 661                     [PAGE_CACHE_WB >> PAGE_CACHE_SHIFT] = "WB",
 662                     [PAGE_CACHE_ISOLATE >> PAGE_CACHE_SHIFT] = "Isolate",
 663                 };
 664                 unsigned access = attr_to_access(entry->attr);
 665                 unsigned cache_idx = (access & PAGE_CACHE_MASK) >>
 666                     PAGE_CACHE_SHIFT;
 667
 668                 if (print_header) {
 669                     print_header = false;
 670                     cpu_fprintf(f, "Way %u (%d %s)\n", wi, sz, sz_text);
 671                     cpu_fprintf(f,
 672                             "\tVaddr       Paddr       ASID  Attr RWX Cache\n"
 673                             "\t----------  ----------  ----  ---- --- -------\n");
 674                 }
 675                 cpu_fprintf(f,
 676                         "\t0x%08x  0x%08x  0x%02x  0x%02x %c%c%c %-7s\n",
 677                         entry->vaddr,
 678                         entry->paddr,
 679                         entry->asid,
 680                         entry->attr,
 681                         (access & PAGE_READ) ? 'R' : '-',
 682                         (access & PAGE_WRITE) ? 'W' : '-',
 683                         (access & PAGE_EXEC) ? 'X' : '-',
 684                         cache_text[cache_idx] ? cache_text[cache_idx] :
 685                             "Invalid");
 686             }
 687         }
 688     }
 689 }
 690
 691 void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUXtensaState *env)
 692 {
 693     if (xtensa_option_bits_enabled(env->config,
 694                 XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_PROTECTION) |
 695                 XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_TRANSLATION) |
 696                 XTENSA_OPTION_BIT(XTENSA_OPTION_MMU))) {
 697
 698         cpu_fprintf(f, "ITLB:\n");
 699         dump_tlb(f, cpu_fprintf, env, false);
 700         cpu_fprintf(f, "\nDTLB:\n");
 701         dump_tlb(f, cpu_fprintf, env, true);
 702     } else {
 703         cpu_fprintf(f, "No TLB for this CPU core\n");
 704     }
 705 }