4 * Copyright (c) 2003 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
24 #include "qemu/osdep.h"
25 #include "qapi/error.h"
28 #include "ui/console.h"
29 #include "hw/i386/pc.h"
30 #include "hw/pci/pci.h"
32 #include "ui/pixel_ops.h"
33 #include "qemu/timer.h"
34 #include "hw/xen/xen.h"
38 //#define DEBUG_VGA_MEM
39 //#define DEBUG_VGA_REG
41 //#define DEBUG_BOCHS_VBE
43 /* 16 state changes per vertical frame @60 Hz */
44 #define VGA_TEXT_CURSOR_PERIOD_MS (1000 * 2 * 16 / 60)
47 * Video Graphics Array (VGA)
49 * Chipset docs for original IBM VGA:
50 * http://www.mcamafia.de/pdf/ibm_vgaxga_trm2.pdf
53 * http://www.osdever.net/FreeVGA/home.htm
55 * Standard VGA features and Bochs VBE extensions are implemented.
58 /* force some bits to zero */
59 const uint8_t sr_mask
[8] = {
70 const uint8_t gr_mask
[16] = {
89 #define cbswap_32(__x) \
91 (((uint32_t)(__x) & (uint32_t)0x000000ffUL) << 24) | \
92 (((uint32_t)(__x) & (uint32_t)0x0000ff00UL) << 8) | \
93 (((uint32_t)(__x) & (uint32_t)0x00ff0000UL) >> 8) | \
94 (((uint32_t)(__x) & (uint32_t)0xff000000UL) >> 24) ))
96 #ifdef HOST_WORDS_BIGENDIAN
97 #define PAT(x) cbswap_32(x)
102 #ifdef HOST_WORDS_BIGENDIAN
108 #ifdef HOST_WORDS_BIGENDIAN
109 #define GET_PLANE(data, p) (((data) >> (24 - (p) * 8)) & 0xff)
111 #define GET_PLANE(data, p) (((data) >> ((p) * 8)) & 0xff)
114 static const uint32_t mask16
[16] = {
135 #ifdef HOST_WORDS_BIGENDIAN
138 #define PAT(x) cbswap_32(x)
141 static uint32_t expand4
[256];
142 static uint16_t expand2
[256];
143 static uint8_t expand4to8
[16];
145 static void vbe_update_vgaregs(VGACommonState
*s
);
147 static inline bool vbe_enabled(VGACommonState
*s
)
149 return s
->vbe_regs
[VBE_DISPI_INDEX_ENABLE
] & VBE_DISPI_ENABLED
;
152 static inline uint8_t sr(VGACommonState
*s
, int idx
)
154 return vbe_enabled(s
) ? s
->sr_vbe
[idx
] : s
->sr
[idx
];
157 static void vga_update_memory_access(VGACommonState
*s
)
159 hwaddr base
, offset
, size
;
161 if (s
->legacy_address_space
== NULL
) {
165 if (s
->has_chain4_alias
) {
166 memory_region_del_subregion(s
->legacy_address_space
, &s
->chain4_alias
);
167 object_unparent(OBJECT(&s
->chain4_alias
));
168 s
->has_chain4_alias
= false;
169 s
->plane_updated
= 0xf;
171 if ((sr(s
, VGA_SEQ_PLANE_WRITE
) & VGA_SR02_ALL_PLANES
) ==
172 VGA_SR02_ALL_PLANES
&& sr(s
, VGA_SEQ_MEMORY_MODE
) & VGA_SR04_CHN_4M
) {
174 switch ((s
->gr
[VGA_GFX_MISC
] >> 2) & 3) {
182 offset
= s
->bank_offset
;
194 assert(offset
+ size
<= s
->vram_size
);
195 memory_region_init_alias(&s
->chain4_alias
, memory_region_owner(&s
->vram
),
196 "vga.chain4", &s
->vram
, offset
, size
);
197 memory_region_add_subregion_overlap(s
->legacy_address_space
, base
,
198 &s
->chain4_alias
, 2);
199 s
->has_chain4_alias
= true;
203 static void vga_dumb_update_retrace_info(VGACommonState
*s
)
208 static void vga_precise_update_retrace_info(VGACommonState
*s
)
211 int hretr_start_char
;
212 int hretr_skew_chars
;
216 int vretr_start_line
;
225 const int clk_hz
[] = {25175000, 28322000, 25175000, 25175000};
226 int64_t chars_per_sec
;
227 struct vga_precise_retrace
*r
= &s
->retrace_info
.precise
;
229 htotal_chars
= s
->cr
[VGA_CRTC_H_TOTAL
] + 5;
230 hretr_start_char
= s
->cr
[VGA_CRTC_H_SYNC_START
];
231 hretr_skew_chars
= (s
->cr
[VGA_CRTC_H_SYNC_END
] >> 5) & 3;
232 hretr_end_char
= s
->cr
[VGA_CRTC_H_SYNC_END
] & 0x1f;
234 vtotal_lines
= (s
->cr
[VGA_CRTC_V_TOTAL
] |
235 (((s
->cr
[VGA_CRTC_OVERFLOW
] & 1) |
236 ((s
->cr
[VGA_CRTC_OVERFLOW
] >> 4) & 2)) << 8)) + 2;
237 vretr_start_line
= s
->cr
[VGA_CRTC_V_SYNC_START
] |
238 ((((s
->cr
[VGA_CRTC_OVERFLOW
] >> 2) & 1) |
239 ((s
->cr
[VGA_CRTC_OVERFLOW
] >> 6) & 2)) << 8);
240 vretr_end_line
= s
->cr
[VGA_CRTC_V_SYNC_END
] & 0xf;
242 clocking_mode
= (sr(s
, VGA_SEQ_CLOCK_MODE
) >> 3) & 1;
243 clock_sel
= (s
->msr
>> 2) & 3;
244 dots
= (s
->msr
& 1) ? 8 : 9;
246 chars_per_sec
= clk_hz
[clock_sel
] / dots
;
248 htotal_chars
<<= clocking_mode
;
250 r
->total_chars
= vtotal_lines
* htotal_chars
;
252 r
->ticks_per_char
= NANOSECONDS_PER_SECOND
/ (r
->total_chars
* r
->freq
);
254 r
->ticks_per_char
= NANOSECONDS_PER_SECOND
/ chars_per_sec
;
257 r
->vstart
= vretr_start_line
;
258 r
->vend
= r
->vstart
+ vretr_end_line
+ 1;
260 r
->hstart
= hretr_start_char
+ hretr_skew_chars
;
261 r
->hend
= r
->hstart
+ hretr_end_char
+ 1;
262 r
->htotal
= htotal_chars
;
265 div2
= (s
->cr
[VGA_CRTC_MODE
] >> 2) & 1;
266 sldiv2
= (s
->cr
[VGA_CRTC_MODE
] >> 3) & 1;
276 "div2 = %d sldiv2 = %d\n"
277 "clocking_mode = %d\n"
278 "clock_sel = %d %d\n"
280 "ticks/char = %" PRId64
"\n"
282 (double) NANOSECONDS_PER_SECOND
/ (r
->ticks_per_char
* r
->total_chars
),
300 static uint8_t vga_precise_retrace(VGACommonState
*s
)
302 struct vga_precise_retrace
*r
= &s
->retrace_info
.precise
;
303 uint8_t val
= s
->st01
& ~(ST01_V_RETRACE
| ST01_DISP_ENABLE
);
305 if (r
->total_chars
) {
306 int cur_line
, cur_line_char
, cur_char
;
309 cur_tick
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
);
311 cur_char
= (cur_tick
/ r
->ticks_per_char
) % r
->total_chars
;
312 cur_line
= cur_char
/ r
->htotal
;
314 if (cur_line
>= r
->vstart
&& cur_line
<= r
->vend
) {
315 val
|= ST01_V_RETRACE
| ST01_DISP_ENABLE
;
317 cur_line_char
= cur_char
% r
->htotal
;
318 if (cur_line_char
>= r
->hstart
&& cur_line_char
<= r
->hend
) {
319 val
|= ST01_DISP_ENABLE
;
325 return s
->st01
^ (ST01_V_RETRACE
| ST01_DISP_ENABLE
);
329 static uint8_t vga_dumb_retrace(VGACommonState
*s
)
331 return s
->st01
^ (ST01_V_RETRACE
| ST01_DISP_ENABLE
);
334 int vga_ioport_invalid(VGACommonState
*s
, uint32_t addr
)
336 if (s
->msr
& VGA_MIS_COLOR
) {
338 return (addr
>= 0x3b0 && addr
<= 0x3bf);
341 return (addr
>= 0x3d0 && addr
<= 0x3df);
345 uint32_t vga_ioport_read(void *opaque
, uint32_t addr
)
347 VGACommonState
*s
= opaque
;
350 if (vga_ioport_invalid(s
, addr
)) {
355 if (s
->ar_flip_flop
== 0) {
362 index
= s
->ar_index
& 0x1f;
363 if (index
< VGA_ATT_C
) {
376 val
= s
->sr
[s
->sr_index
];
378 printf("vga: read SR%x = 0x%02x\n", s
->sr_index
, val
);
385 val
= s
->dac_write_index
;
388 val
= s
->palette
[s
->dac_read_index
* 3 + s
->dac_sub_index
];
389 if (++s
->dac_sub_index
== 3) {
390 s
->dac_sub_index
= 0;
404 val
= s
->gr
[s
->gr_index
];
406 printf("vga: read GR%x = 0x%02x\n", s
->gr_index
, val
);
415 val
= s
->cr
[s
->cr_index
];
417 printf("vga: read CR%x = 0x%02x\n", s
->cr_index
, val
);
422 /* just toggle to fool polling */
423 val
= s
->st01
= s
->retrace(s
);
431 #if defined(DEBUG_VGA)
432 printf("VGA: read addr=0x%04x data=0x%02x\n", addr
, val
);
437 void vga_ioport_write(void *opaque
, uint32_t addr
, uint32_t val
)
439 VGACommonState
*s
= opaque
;
442 /* check port range access depending on color/monochrome mode */
443 if (vga_ioport_invalid(s
, addr
)) {
447 printf("VGA: write addr=0x%04x data=0x%02x\n", addr
, val
);
452 if (s
->ar_flip_flop
== 0) {
456 index
= s
->ar_index
& 0x1f;
458 case VGA_ATC_PALETTE0
... VGA_ATC_PALETTEF
:
459 s
->ar
[index
] = val
& 0x3f;
462 s
->ar
[index
] = val
& ~0x10;
464 case VGA_ATC_OVERSCAN
:
467 case VGA_ATC_PLANE_ENABLE
:
468 s
->ar
[index
] = val
& ~0xc0;
471 s
->ar
[index
] = val
& ~0xf0;
473 case VGA_ATC_COLOR_PAGE
:
474 s
->ar
[index
] = val
& ~0xf0;
480 s
->ar_flip_flop
^= 1;
483 s
->msr
= val
& ~0x10;
484 s
->update_retrace_info(s
);
487 s
->sr_index
= val
& 7;
491 printf("vga: write SR%x = 0x%02x\n", s
->sr_index
, val
);
493 s
->sr
[s
->sr_index
] = val
& sr_mask
[s
->sr_index
];
494 if (s
->sr_index
== VGA_SEQ_CLOCK_MODE
) {
495 s
->update_retrace_info(s
);
497 vga_update_memory_access(s
);
500 s
->dac_read_index
= val
;
501 s
->dac_sub_index
= 0;
505 s
->dac_write_index
= val
;
506 s
->dac_sub_index
= 0;
510 s
->dac_cache
[s
->dac_sub_index
] = val
;
511 if (++s
->dac_sub_index
== 3) {
512 memcpy(&s
->palette
[s
->dac_write_index
* 3], s
->dac_cache
, 3);
513 s
->dac_sub_index
= 0;
514 s
->dac_write_index
++;
518 s
->gr_index
= val
& 0x0f;
522 printf("vga: write GR%x = 0x%02x\n", s
->gr_index
, val
);
524 s
->gr
[s
->gr_index
] = val
& gr_mask
[s
->gr_index
];
525 vbe_update_vgaregs(s
);
526 vga_update_memory_access(s
);
535 printf("vga: write CR%x = 0x%02x\n", s
->cr_index
, val
);
537 /* handle CR0-7 protection */
538 if ((s
->cr
[VGA_CRTC_V_SYNC_END
] & VGA_CR11_LOCK_CR0_CR7
) &&
539 s
->cr_index
<= VGA_CRTC_OVERFLOW
) {
540 /* can always write bit 4 of CR7 */
541 if (s
->cr_index
== VGA_CRTC_OVERFLOW
) {
542 s
->cr
[VGA_CRTC_OVERFLOW
] = (s
->cr
[VGA_CRTC_OVERFLOW
] & ~0x10) |
544 vbe_update_vgaregs(s
);
548 s
->cr
[s
->cr_index
] = val
;
549 vbe_update_vgaregs(s
);
551 switch(s
->cr_index
) {
552 case VGA_CRTC_H_TOTAL
:
553 case VGA_CRTC_H_SYNC_START
:
554 case VGA_CRTC_H_SYNC_END
:
555 case VGA_CRTC_V_TOTAL
:
556 case VGA_CRTC_OVERFLOW
:
557 case VGA_CRTC_V_SYNC_END
:
559 s
->update_retrace_info(s
);
571 * Sanity check vbe register writes.
573 * As we don't have a way to signal errors to the guest in the bochs
574 * dispi interface we'll go adjust the registers to the closest valid
577 static void vbe_fixup_regs(VGACommonState
*s
)
579 uint16_t *r
= s
->vbe_regs
;
580 uint32_t bits
, linelength
, maxy
, offset
;
582 if (!vbe_enabled(s
)) {
583 /* vbe is turned off -- nothing to do */
588 switch (r
[VBE_DISPI_INDEX_BPP
]) {
594 bits
= r
[VBE_DISPI_INDEX_BPP
];
600 bits
= r
[VBE_DISPI_INDEX_BPP
] = 8;
605 r
[VBE_DISPI_INDEX_XRES
] &= ~7u;
606 if (r
[VBE_DISPI_INDEX_XRES
] == 0) {
607 r
[VBE_DISPI_INDEX_XRES
] = 8;
609 if (r
[VBE_DISPI_INDEX_XRES
] > VBE_DISPI_MAX_XRES
) {
610 r
[VBE_DISPI_INDEX_XRES
] = VBE_DISPI_MAX_XRES
;
612 r
[VBE_DISPI_INDEX_VIRT_WIDTH
] &= ~7u;
613 if (r
[VBE_DISPI_INDEX_VIRT_WIDTH
] > VBE_DISPI_MAX_XRES
) {
614 r
[VBE_DISPI_INDEX_VIRT_WIDTH
] = VBE_DISPI_MAX_XRES
;
616 if (r
[VBE_DISPI_INDEX_VIRT_WIDTH
] < r
[VBE_DISPI_INDEX_XRES
]) {
617 r
[VBE_DISPI_INDEX_VIRT_WIDTH
] = r
[VBE_DISPI_INDEX_XRES
];
621 linelength
= r
[VBE_DISPI_INDEX_VIRT_WIDTH
] * bits
/ 8;
622 maxy
= s
->vbe_size
/ linelength
;
623 if (r
[VBE_DISPI_INDEX_YRES
] == 0) {
624 r
[VBE_DISPI_INDEX_YRES
] = 1;
626 if (r
[VBE_DISPI_INDEX_YRES
] > VBE_DISPI_MAX_YRES
) {
627 r
[VBE_DISPI_INDEX_YRES
] = VBE_DISPI_MAX_YRES
;
629 if (r
[VBE_DISPI_INDEX_YRES
] > maxy
) {
630 r
[VBE_DISPI_INDEX_YRES
] = maxy
;
634 if (r
[VBE_DISPI_INDEX_X_OFFSET
] > VBE_DISPI_MAX_XRES
) {
635 r
[VBE_DISPI_INDEX_X_OFFSET
] = VBE_DISPI_MAX_XRES
;
637 if (r
[VBE_DISPI_INDEX_Y_OFFSET
] > VBE_DISPI_MAX_YRES
) {
638 r
[VBE_DISPI_INDEX_Y_OFFSET
] = VBE_DISPI_MAX_YRES
;
640 offset
= r
[VBE_DISPI_INDEX_X_OFFSET
] * bits
/ 8;
641 offset
+= r
[VBE_DISPI_INDEX_Y_OFFSET
] * linelength
;
642 if (offset
+ r
[VBE_DISPI_INDEX_YRES
] * linelength
> s
->vbe_size
) {
643 r
[VBE_DISPI_INDEX_Y_OFFSET
] = 0;
644 offset
= r
[VBE_DISPI_INDEX_X_OFFSET
] * bits
/ 8;
645 if (offset
+ r
[VBE_DISPI_INDEX_YRES
] * linelength
> s
->vbe_size
) {
646 r
[VBE_DISPI_INDEX_X_OFFSET
] = 0;
651 /* update vga state */
652 r
[VBE_DISPI_INDEX_VIRT_HEIGHT
] = maxy
;
653 s
->vbe_line_offset
= linelength
;
654 s
->vbe_start_addr
= offset
/ 4;
657 /* we initialize the VGA graphic mode */
658 static void vbe_update_vgaregs(VGACommonState
*s
)
660 int h
, shift_control
;
662 if (!vbe_enabled(s
)) {
663 /* vbe is turned off -- nothing to do */
667 /* graphic mode + memory map 1 */
668 s
->gr
[VGA_GFX_MISC
] = (s
->gr
[VGA_GFX_MISC
] & ~0x0c) | 0x04 |
669 VGA_GR06_GRAPHICS_MODE
;
670 s
->cr
[VGA_CRTC_MODE
] |= 3; /* no CGA modes */
671 s
->cr
[VGA_CRTC_OFFSET
] = s
->vbe_line_offset
>> 3;
673 s
->cr
[VGA_CRTC_H_DISP
] =
674 (s
->vbe_regs
[VBE_DISPI_INDEX_XRES
] >> 3) - 1;
675 /* height (only meaningful if < 1024) */
676 h
= s
->vbe_regs
[VBE_DISPI_INDEX_YRES
] - 1;
677 s
->cr
[VGA_CRTC_V_DISP_END
] = h
;
678 s
->cr
[VGA_CRTC_OVERFLOW
] = (s
->cr
[VGA_CRTC_OVERFLOW
] & ~0x42) |
679 ((h
>> 7) & 0x02) | ((h
>> 3) & 0x40);
680 /* line compare to 1023 */
681 s
->cr
[VGA_CRTC_LINE_COMPARE
] = 0xff;
682 s
->cr
[VGA_CRTC_OVERFLOW
] |= 0x10;
683 s
->cr
[VGA_CRTC_MAX_SCAN
] |= 0x40;
685 if (s
->vbe_regs
[VBE_DISPI_INDEX_BPP
] == 4) {
687 s
->sr_vbe
[VGA_SEQ_CLOCK_MODE
] &= ~8; /* no double line */
690 /* set chain 4 mode */
691 s
->sr_vbe
[VGA_SEQ_MEMORY_MODE
] |= VGA_SR04_CHN_4M
;
692 /* activate all planes */
693 s
->sr_vbe
[VGA_SEQ_PLANE_WRITE
] |= VGA_SR02_ALL_PLANES
;
695 s
->gr
[VGA_GFX_MODE
] = (s
->gr
[VGA_GFX_MODE
] & ~0x60) |
696 (shift_control
<< 5);
697 s
->cr
[VGA_CRTC_MAX_SCAN
] &= ~0x9f; /* no double scan */
700 static uint32_t vbe_ioport_read_index(void *opaque
, uint32_t addr
)
702 VGACommonState
*s
= opaque
;
708 uint32_t vbe_ioport_read_data(void *opaque
, uint32_t addr
)
710 VGACommonState
*s
= opaque
;
713 if (s
->vbe_index
< VBE_DISPI_INDEX_NB
) {
714 if (s
->vbe_regs
[VBE_DISPI_INDEX_ENABLE
] & VBE_DISPI_GETCAPS
) {
715 switch(s
->vbe_index
) {
716 /* XXX: do not hardcode ? */
717 case VBE_DISPI_INDEX_XRES
:
718 val
= VBE_DISPI_MAX_XRES
;
720 case VBE_DISPI_INDEX_YRES
:
721 val
= VBE_DISPI_MAX_YRES
;
723 case VBE_DISPI_INDEX_BPP
:
724 val
= VBE_DISPI_MAX_BPP
;
727 val
= s
->vbe_regs
[s
->vbe_index
];
731 val
= s
->vbe_regs
[s
->vbe_index
];
733 } else if (s
->vbe_index
== VBE_DISPI_INDEX_VIDEO_MEMORY_64K
) {
734 val
= s
->vbe_size
/ (64 * 1024);
738 #ifdef DEBUG_BOCHS_VBE
739 printf("VBE: read index=0x%x val=0x%x\n", s
->vbe_index
, val
);
744 void vbe_ioport_write_index(void *opaque
, uint32_t addr
, uint32_t val
)
746 VGACommonState
*s
= opaque
;
750 void vbe_ioport_write_data(void *opaque
, uint32_t addr
, uint32_t val
)
752 VGACommonState
*s
= opaque
;
754 if (s
->vbe_index
<= VBE_DISPI_INDEX_NB
) {
755 #ifdef DEBUG_BOCHS_VBE
756 printf("VBE: write index=0x%x val=0x%x\n", s
->vbe_index
, val
);
758 switch(s
->vbe_index
) {
759 case VBE_DISPI_INDEX_ID
:
760 if (val
== VBE_DISPI_ID0
||
761 val
== VBE_DISPI_ID1
||
762 val
== VBE_DISPI_ID2
||
763 val
== VBE_DISPI_ID3
||
764 val
== VBE_DISPI_ID4
) {
765 s
->vbe_regs
[s
->vbe_index
] = val
;
768 case VBE_DISPI_INDEX_XRES
:
769 case VBE_DISPI_INDEX_YRES
:
770 case VBE_DISPI_INDEX_BPP
:
771 case VBE_DISPI_INDEX_VIRT_WIDTH
:
772 case VBE_DISPI_INDEX_X_OFFSET
:
773 case VBE_DISPI_INDEX_Y_OFFSET
:
774 s
->vbe_regs
[s
->vbe_index
] = val
;
776 vbe_update_vgaregs(s
);
778 case VBE_DISPI_INDEX_BANK
:
779 val
&= s
->vbe_bank_mask
;
780 s
->vbe_regs
[s
->vbe_index
] = val
;
781 s
->bank_offset
= (val
<< 16);
782 vga_update_memory_access(s
);
784 case VBE_DISPI_INDEX_ENABLE
:
785 if ((val
& VBE_DISPI_ENABLED
) &&
786 !(s
->vbe_regs
[VBE_DISPI_INDEX_ENABLE
] & VBE_DISPI_ENABLED
)) {
788 s
->vbe_regs
[VBE_DISPI_INDEX_VIRT_WIDTH
] = 0;
789 s
->vbe_regs
[VBE_DISPI_INDEX_X_OFFSET
] = 0;
790 s
->vbe_regs
[VBE_DISPI_INDEX_Y_OFFSET
] = 0;
791 s
->vbe_regs
[VBE_DISPI_INDEX_ENABLE
] |= VBE_DISPI_ENABLED
;
793 vbe_update_vgaregs(s
);
795 /* clear the screen */
796 if (!(val
& VBE_DISPI_NOCLEARMEM
)) {
797 memset(s
->vram_ptr
, 0,
798 s
->vbe_regs
[VBE_DISPI_INDEX_YRES
] * s
->vbe_line_offset
);
803 s
->dac_8bit
= (val
& VBE_DISPI_8BIT_DAC
) > 0;
804 s
->vbe_regs
[s
->vbe_index
] = val
;
805 vga_update_memory_access(s
);
813 /* called for accesses between 0xa0000 and 0xc0000 */
814 uint32_t vga_mem_readb(VGACommonState
*s
, hwaddr addr
)
816 int memory_map_mode
, plane
;
819 /* convert to VGA memory offset */
820 memory_map_mode
= (s
->gr
[VGA_GFX_MISC
] >> 2) & 3;
822 switch(memory_map_mode
) {
828 addr
+= s
->bank_offset
;
843 if (sr(s
, VGA_SEQ_MEMORY_MODE
) & VGA_SR04_CHN_4M
) {
844 /* chain 4 mode : simplest access */
845 assert(addr
< s
->vram_size
);
846 ret
= s
->vram_ptr
[addr
];
847 } else if (s
->gr
[VGA_GFX_MODE
] & 0x10) {
848 /* odd/even mode (aka text mode mapping) */
849 plane
= (s
->gr
[VGA_GFX_PLANE_READ
] & 2) | (addr
& 1);
850 addr
= ((addr
& ~1) << 1) | plane
;
851 if (addr
>= s
->vram_size
) {
854 ret
= s
->vram_ptr
[addr
];
856 /* standard VGA latched access */
857 if (addr
* sizeof(uint32_t) >= s
->vram_size
) {
860 s
->latch
= ((uint32_t *)s
->vram_ptr
)[addr
];
862 if (!(s
->gr
[VGA_GFX_MODE
] & 0x08)) {
864 plane
= s
->gr
[VGA_GFX_PLANE_READ
];
865 ret
= GET_PLANE(s
->latch
, plane
);
868 ret
= (s
->latch
^ mask16
[s
->gr
[VGA_GFX_COMPARE_VALUE
]]) &
869 mask16
[s
->gr
[VGA_GFX_COMPARE_MASK
]];
878 /* called for accesses between 0xa0000 and 0xc0000 */
879 void vga_mem_writeb(VGACommonState
*s
, hwaddr addr
, uint32_t val
)
881 int memory_map_mode
, plane
, write_mode
, b
, func_select
, mask
;
882 uint32_t write_mask
, bit_mask
, set_mask
;
885 printf("vga: [0x" TARGET_FMT_plx
"] = 0x%02x\n", addr
, val
);
887 /* convert to VGA memory offset */
888 memory_map_mode
= (s
->gr
[VGA_GFX_MISC
] >> 2) & 3;
890 switch(memory_map_mode
) {
896 addr
+= s
->bank_offset
;
911 if (sr(s
, VGA_SEQ_MEMORY_MODE
) & VGA_SR04_CHN_4M
) {
912 /* chain 4 mode : simplest access */
915 if (sr(s
, VGA_SEQ_PLANE_WRITE
) & mask
) {
916 assert(addr
< s
->vram_size
);
917 s
->vram_ptr
[addr
] = val
;
919 printf("vga: chain4: [0x" TARGET_FMT_plx
"]\n", addr
);
921 s
->plane_updated
|= mask
; /* only used to detect font change */
922 memory_region_set_dirty(&s
->vram
, addr
, 1);
924 } else if (s
->gr
[VGA_GFX_MODE
] & 0x10) {
925 /* odd/even mode (aka text mode mapping) */
926 plane
= (s
->gr
[VGA_GFX_PLANE_READ
] & 2) | (addr
& 1);
928 if (sr(s
, VGA_SEQ_PLANE_WRITE
) & mask
) {
929 addr
= ((addr
& ~1) << 1) | plane
;
930 if (addr
>= s
->vram_size
) {
933 s
->vram_ptr
[addr
] = val
;
935 printf("vga: odd/even: [0x" TARGET_FMT_plx
"]\n", addr
);
937 s
->plane_updated
|= mask
; /* only used to detect font change */
938 memory_region_set_dirty(&s
->vram
, addr
, 1);
941 /* standard VGA latched access */
942 write_mode
= s
->gr
[VGA_GFX_MODE
] & 3;
947 b
= s
->gr
[VGA_GFX_DATA_ROTATE
] & 7;
948 val
= ((val
>> b
) | (val
<< (8 - b
))) & 0xff;
952 /* apply set/reset mask */
953 set_mask
= mask16
[s
->gr
[VGA_GFX_SR_ENABLE
]];
954 val
= (val
& ~set_mask
) |
955 (mask16
[s
->gr
[VGA_GFX_SR_VALUE
]] & set_mask
);
956 bit_mask
= s
->gr
[VGA_GFX_BIT_MASK
];
962 val
= mask16
[val
& 0x0f];
963 bit_mask
= s
->gr
[VGA_GFX_BIT_MASK
];
967 b
= s
->gr
[VGA_GFX_DATA_ROTATE
] & 7;
968 val
= (val
>> b
) | (val
<< (8 - b
));
970 bit_mask
= s
->gr
[VGA_GFX_BIT_MASK
] & val
;
971 val
= mask16
[s
->gr
[VGA_GFX_SR_VALUE
]];
975 /* apply logical operation */
976 func_select
= s
->gr
[VGA_GFX_DATA_ROTATE
] >> 3;
977 switch(func_select
) {
997 bit_mask
|= bit_mask
<< 8;
998 bit_mask
|= bit_mask
<< 16;
999 val
= (val
& bit_mask
) | (s
->latch
& ~bit_mask
);
1002 /* mask data according to sr[2] */
1003 mask
= sr(s
, VGA_SEQ_PLANE_WRITE
);
1004 s
->plane_updated
|= mask
; /* only used to detect font change */
1005 write_mask
= mask16
[mask
];
1006 if (addr
* sizeof(uint32_t) >= s
->vram_size
) {
1009 ((uint32_t *)s
->vram_ptr
)[addr
] =
1010 (((uint32_t *)s
->vram_ptr
)[addr
] & ~write_mask
) |
1012 #ifdef DEBUG_VGA_MEM
1013 printf("vga: latch: [0x" TARGET_FMT_plx
"] mask=0x%08x val=0x%08x\n",
1014 addr
* 4, write_mask
, val
);
1016 memory_region_set_dirty(&s
->vram
, addr
<< 2, sizeof(uint32_t));
1020 typedef void vga_draw_line_func(VGACommonState
*s1
, uint8_t *d
,
1021 const uint8_t *s
, int width
);
1023 #include "vga-helpers.h"
1025 /* return true if the palette was modified */
1026 static int update_palette16(VGACommonState
*s
)
1029 uint32_t v
, col
, *palette
;
1032 palette
= s
->last_palette
;
1033 for(i
= 0; i
< 16; i
++) {
1035 if (s
->ar
[VGA_ATC_MODE
] & 0x80) {
1036 v
= ((s
->ar
[VGA_ATC_COLOR_PAGE
] & 0xf) << 4) | (v
& 0xf);
1038 v
= ((s
->ar
[VGA_ATC_COLOR_PAGE
] & 0xc) << 4) | (v
& 0x3f);
1041 col
= rgb_to_pixel32(c6_to_8(s
->palette
[v
]),
1042 c6_to_8(s
->palette
[v
+ 1]),
1043 c6_to_8(s
->palette
[v
+ 2]));
1044 if (col
!= palette
[i
]) {
1052 /* return true if the palette was modified */
1053 static int update_palette256(VGACommonState
*s
)
1056 uint32_t v
, col
, *palette
;
1059 palette
= s
->last_palette
;
1061 for(i
= 0; i
< 256; i
++) {
1063 col
= rgb_to_pixel32(s
->palette
[v
],
1067 col
= rgb_to_pixel32(c6_to_8(s
->palette
[v
]),
1068 c6_to_8(s
->palette
[v
+ 1]),
1069 c6_to_8(s
->palette
[v
+ 2]));
1071 if (col
!= palette
[i
]) {
1080 static void vga_get_offsets(VGACommonState
*s
,
1081 uint32_t *pline_offset
,
1082 uint32_t *pstart_addr
,
1083 uint32_t *pline_compare
)
1085 uint32_t start_addr
, line_offset
, line_compare
;
1087 if (vbe_enabled(s
)) {
1088 line_offset
= s
->vbe_line_offset
;
1089 start_addr
= s
->vbe_start_addr
;
1090 line_compare
= 65535;
1092 /* compute line_offset in bytes */
1093 line_offset
= s
->cr
[VGA_CRTC_OFFSET
];
1096 /* starting address */
1097 start_addr
= s
->cr
[VGA_CRTC_START_LO
] |
1098 (s
->cr
[VGA_CRTC_START_HI
] << 8);
1101 line_compare
= s
->cr
[VGA_CRTC_LINE_COMPARE
] |
1102 ((s
->cr
[VGA_CRTC_OVERFLOW
] & 0x10) << 4) |
1103 ((s
->cr
[VGA_CRTC_MAX_SCAN
] & 0x40) << 3);
1105 *pline_offset
= line_offset
;
1106 *pstart_addr
= start_addr
;
1107 *pline_compare
= line_compare
;
1110 /* update start_addr and line_offset. Return TRUE if modified */
1111 static int update_basic_params(VGACommonState
*s
)
1114 uint32_t start_addr
, line_offset
, line_compare
;
1118 s
->get_offsets(s
, &line_offset
, &start_addr
, &line_compare
);
1120 if (line_offset
!= s
->line_offset
||
1121 start_addr
!= s
->start_addr
||
1122 line_compare
!= s
->line_compare
) {
1123 s
->line_offset
= line_offset
;
1124 s
->start_addr
= start_addr
;
1125 s
->line_compare
= line_compare
;
1132 static const uint8_t cursor_glyph
[32 * 4] = {
1133 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1134 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1135 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1136 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1137 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1138 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1139 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1140 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1141 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1142 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1143 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1144 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1145 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1146 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1147 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1148 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1151 static void vga_get_text_resolution(VGACommonState
*s
, int *pwidth
, int *pheight
,
1152 int *pcwidth
, int *pcheight
)
1154 int width
, cwidth
, height
, cheight
;
1156 /* total width & height */
1157 cheight
= (s
->cr
[VGA_CRTC_MAX_SCAN
] & 0x1f) + 1;
1159 if (!(sr(s
, VGA_SEQ_CLOCK_MODE
) & VGA_SR01_CHAR_CLK_8DOTS
)) {
1162 if (sr(s
, VGA_SEQ_CLOCK_MODE
) & 0x08) {
1163 cwidth
= 16; /* NOTE: no 18 pixel wide */
1165 width
= (s
->cr
[VGA_CRTC_H_DISP
] + 1);
1166 if (s
->cr
[VGA_CRTC_V_TOTAL
] == 100) {
1167 /* ugly hack for CGA 160x100x16 - explain me the logic */
1170 height
= s
->cr
[VGA_CRTC_V_DISP_END
] |
1171 ((s
->cr
[VGA_CRTC_OVERFLOW
] & 0x02) << 7) |
1172 ((s
->cr
[VGA_CRTC_OVERFLOW
] & 0x40) << 3);
1173 height
= (height
+ 1) / cheight
;
1179 *pcheight
= cheight
;
1190 static void vga_draw_text(VGACommonState
*s
, int full_update
)
1192 DisplaySurface
*surface
= qemu_console_surface(s
->con
);
1193 int cx
, cy
, cheight
, cw
, ch
, cattr
, height
, width
, ch_attr
;
1194 int cx_min
, cx_max
, linesize
, x_incr
, line
, line1
;
1195 uint32_t offset
, fgcol
, bgcol
, v
, cursor_offset
;
1196 uint8_t *d1
, *d
, *src
, *dest
, *cursor_ptr
;
1197 const uint8_t *font_ptr
, *font_base
[2];
1198 int dup9
, line_offset
;
1200 uint32_t *ch_attr_ptr
;
1201 int64_t now
= qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL
);
1203 /* compute font data address (in plane 2) */
1204 v
= sr(s
, VGA_SEQ_CHARACTER_MAP
);
1205 offset
= (((v
>> 4) & 1) | ((v
<< 1) & 6)) * 8192 * 4 + 2;
1206 if (offset
!= s
->font_offsets
[0]) {
1207 s
->font_offsets
[0] = offset
;
1210 font_base
[0] = s
->vram_ptr
+ offset
;
1212 offset
= (((v
>> 5) & 1) | ((v
>> 1) & 6)) * 8192 * 4 + 2;
1213 font_base
[1] = s
->vram_ptr
+ offset
;
1214 if (offset
!= s
->font_offsets
[1]) {
1215 s
->font_offsets
[1] = offset
;
1218 if (s
->plane_updated
& (1 << 2) || s
->has_chain4_alias
) {
1219 /* if the plane 2 was modified since the last display, it
1220 indicates the font may have been modified */
1221 s
->plane_updated
= 0;
1224 full_update
|= update_basic_params(s
);
1226 line_offset
= s
->line_offset
;
1228 vga_get_text_resolution(s
, &width
, &height
, &cw
, &cheight
);
1229 if ((height
* width
) <= 1) {
1230 /* better than nothing: exit if transient size is too small */
1233 if ((height
* width
) > CH_ATTR_SIZE
) {
1234 /* better than nothing: exit if transient size is too big */
1238 if (width
!= s
->last_width
|| height
!= s
->last_height
||
1239 cw
!= s
->last_cw
|| cheight
!= s
->last_ch
|| s
->last_depth
) {
1240 s
->last_scr_width
= width
* cw
;
1241 s
->last_scr_height
= height
* cheight
;
1242 qemu_console_resize(s
->con
, s
->last_scr_width
, s
->last_scr_height
);
1243 surface
= qemu_console_surface(s
->con
);
1244 dpy_text_resize(s
->con
, width
, height
);
1246 s
->last_width
= width
;
1247 s
->last_height
= height
;
1248 s
->last_ch
= cheight
;
1252 full_update
|= update_palette16(s
);
1253 palette
= s
->last_palette
;
1254 x_incr
= cw
* surface_bytes_per_pixel(surface
);
1257 s
->full_update_text
= 1;
1259 if (s
->full_update_gfx
) {
1260 s
->full_update_gfx
= 0;
1264 cursor_offset
= ((s
->cr
[VGA_CRTC_CURSOR_HI
] << 8) |
1265 s
->cr
[VGA_CRTC_CURSOR_LO
]) - s
->start_addr
;
1266 if (cursor_offset
!= s
->cursor_offset
||
1267 s
->cr
[VGA_CRTC_CURSOR_START
] != s
->cursor_start
||
1268 s
->cr
[VGA_CRTC_CURSOR_END
] != s
->cursor_end
) {
1269 /* if the cursor position changed, we update the old and new
1271 if (s
->cursor_offset
< CH_ATTR_SIZE
)
1272 s
->last_ch_attr
[s
->cursor_offset
] = -1;
1273 if (cursor_offset
< CH_ATTR_SIZE
)
1274 s
->last_ch_attr
[cursor_offset
] = -1;
1275 s
->cursor_offset
= cursor_offset
;
1276 s
->cursor_start
= s
->cr
[VGA_CRTC_CURSOR_START
];
1277 s
->cursor_end
= s
->cr
[VGA_CRTC_CURSOR_END
];
1279 cursor_ptr
= s
->vram_ptr
+ (s
->start_addr
+ cursor_offset
) * 4;
1280 if (now
>= s
->cursor_blink_time
) {
1281 s
->cursor_blink_time
= now
+ VGA_TEXT_CURSOR_PERIOD_MS
/ 2;
1282 s
->cursor_visible_phase
= !s
->cursor_visible_phase
;
1285 dest
= surface_data(surface
);
1286 linesize
= surface_stride(surface
);
1287 ch_attr_ptr
= s
->last_ch_attr
;
1289 offset
= s
->start_addr
* 4;
1290 for(cy
= 0; cy
< height
; cy
++) {
1292 src
= s
->vram_ptr
+ offset
;
1295 for(cx
= 0; cx
< width
; cx
++) {
1296 ch_attr
= *(uint16_t *)src
;
1297 if (full_update
|| ch_attr
!= *ch_attr_ptr
|| src
== cursor_ptr
) {
1302 *ch_attr_ptr
= ch_attr
;
1303 #ifdef HOST_WORDS_BIGENDIAN
1305 cattr
= ch_attr
& 0xff;
1307 ch
= ch_attr
& 0xff;
1308 cattr
= ch_attr
>> 8;
1310 font_ptr
= font_base
[(cattr
>> 3) & 1];
1311 font_ptr
+= 32 * 4 * ch
;
1312 bgcol
= palette
[cattr
>> 4];
1313 fgcol
= palette
[cattr
& 0x0f];
1315 vga_draw_glyph16(d1
, linesize
,
1316 font_ptr
, cheight
, fgcol
, bgcol
);
1317 } else if (cw
!= 9) {
1318 vga_draw_glyph8(d1
, linesize
,
1319 font_ptr
, cheight
, fgcol
, bgcol
);
1322 if (ch
>= 0xb0 && ch
<= 0xdf &&
1323 (s
->ar
[VGA_ATC_MODE
] & 0x04)) {
1326 vga_draw_glyph9(d1
, linesize
,
1327 font_ptr
, cheight
, fgcol
, bgcol
, dup9
);
1329 if (src
== cursor_ptr
&&
1330 !(s
->cr
[VGA_CRTC_CURSOR_START
] & 0x20) &&
1331 s
->cursor_visible_phase
) {
1332 int line_start
, line_last
, h
;
1333 /* draw the cursor */
1334 line_start
= s
->cr
[VGA_CRTC_CURSOR_START
] & 0x1f;
1335 line_last
= s
->cr
[VGA_CRTC_CURSOR_END
] & 0x1f;
1336 /* XXX: check that */
1337 if (line_last
> cheight
- 1)
1338 line_last
= cheight
- 1;
1339 if (line_last
>= line_start
&& line_start
< cheight
) {
1340 h
= line_last
- line_start
+ 1;
1341 d
= d1
+ linesize
* line_start
;
1343 vga_draw_glyph16(d
, linesize
,
1344 cursor_glyph
, h
, fgcol
, bgcol
);
1345 } else if (cw
!= 9) {
1346 vga_draw_glyph8(d
, linesize
,
1347 cursor_glyph
, h
, fgcol
, bgcol
);
1349 vga_draw_glyph9(d
, linesize
,
1350 cursor_glyph
, h
, fgcol
, bgcol
, 1);
1360 dpy_gfx_update(s
->con
, cx_min
* cw
, cy
* cheight
,
1361 (cx_max
- cx_min
+ 1) * cw
, cheight
);
1363 dest
+= linesize
* cheight
;
1364 line1
= line
+ cheight
;
1365 offset
+= line_offset
;
1366 if (line
< s
->line_compare
&& line1
>= s
->line_compare
) {
1391 static vga_draw_line_func
* const vga_draw_line_table
[VGA_DRAW_LINE_NB
] = {
1408 static int vga_get_bpp(VGACommonState
*s
)
1412 if (vbe_enabled(s
)) {
1413 ret
= s
->vbe_regs
[VBE_DISPI_INDEX_BPP
];
1420 static void vga_get_resolution(VGACommonState
*s
, int *pwidth
, int *pheight
)
1424 if (vbe_enabled(s
)) {
1425 width
= s
->vbe_regs
[VBE_DISPI_INDEX_XRES
];
1426 height
= s
->vbe_regs
[VBE_DISPI_INDEX_YRES
];
1428 width
= (s
->cr
[VGA_CRTC_H_DISP
] + 1) * 8;
1429 height
= s
->cr
[VGA_CRTC_V_DISP_END
] |
1430 ((s
->cr
[VGA_CRTC_OVERFLOW
] & 0x02) << 7) |
1431 ((s
->cr
[VGA_CRTC_OVERFLOW
] & 0x40) << 3);
1432 height
= (height
+ 1);
1438 void vga_invalidate_scanlines(VGACommonState
*s
, int y1
, int y2
)
1441 if (y1
>= VGA_MAX_HEIGHT
)
1443 if (y2
>= VGA_MAX_HEIGHT
)
1444 y2
= VGA_MAX_HEIGHT
;
1445 for(y
= y1
; y
< y2
; y
++) {
1446 s
->invalidated_y_table
[y
>> 5] |= 1 << (y
& 0x1f);
1450 void vga_sync_dirty_bitmap(VGACommonState
*s
)
1452 memory_region_sync_dirty_bitmap(&s
->vram
);
1455 void vga_dirty_log_start(VGACommonState
*s
)
1457 memory_region_set_log(&s
->vram
, true, DIRTY_MEMORY_VGA
);
1460 void vga_dirty_log_stop(VGACommonState
*s
)
1462 memory_region_set_log(&s
->vram
, false, DIRTY_MEMORY_VGA
);
1468 static void vga_draw_graphic(VGACommonState
*s
, int full_update
)
1470 DisplaySurface
*surface
= qemu_console_surface(s
->con
);
1471 int y1
, y
, update
, linesize
, y_start
, double_scan
, mask
, depth
;
1472 int width
, height
, shift_control
, line_offset
, bwidth
, bits
;
1473 ram_addr_t page0
, page1
, page_min
, page_max
;
1474 int disp_width
, multi_scan
, multi_run
;
1476 uint32_t v
, addr1
, addr
;
1477 vga_draw_line_func
*vga_draw_line
= NULL
;
1479 pixman_format_code_t format
;
1480 #ifdef HOST_WORDS_BIGENDIAN
1481 bool byteswap
= !s
->big_endian_fb
;
1483 bool byteswap
= s
->big_endian_fb
;
1486 full_update
|= update_basic_params(s
);
1489 vga_sync_dirty_bitmap(s
);
1491 s
->get_resolution(s
, &width
, &height
);
1494 shift_control
= (s
->gr
[VGA_GFX_MODE
] >> 5) & 3;
1495 double_scan
= (s
->cr
[VGA_CRTC_MAX_SCAN
] >> 7);
1496 if (shift_control
!= 1) {
1497 multi_scan
= (((s
->cr
[VGA_CRTC_MAX_SCAN
] & 0x1f) + 1) << double_scan
)
1500 /* in CGA modes, multi_scan is ignored */
1501 /* XXX: is it correct ? */
1502 multi_scan
= double_scan
;
1504 multi_run
= multi_scan
;
1505 if (shift_control
!= s
->shift_control
||
1506 double_scan
!= s
->double_scan
) {
1508 s
->shift_control
= shift_control
;
1509 s
->double_scan
= double_scan
;
1512 if (shift_control
== 0) {
1513 if (sr(s
, VGA_SEQ_CLOCK_MODE
) & 8) {
1516 } else if (shift_control
== 1) {
1517 if (sr(s
, VGA_SEQ_CLOCK_MODE
) & 8) {
1522 depth
= s
->get_bpp(s
);
1525 * Check whether we can share the surface with the backend
1526 * or whether we need a shadow surface. We share native
1527 * endian surfaces for 15bpp and above and byteswapped
1528 * surfaces for 24bpp and above.
1530 format
= qemu_default_pixman_format(depth
, !byteswap
);
1532 share_surface
= dpy_gfx_check_format(s
->con
, format
)
1533 && !s
->force_shadow
;
1535 share_surface
= false;
1537 if (s
->line_offset
!= s
->last_line_offset
||
1538 disp_width
!= s
->last_width
||
1539 height
!= s
->last_height
||
1540 s
->last_depth
!= depth
||
1541 s
->last_byteswap
!= byteswap
||
1542 share_surface
!= is_buffer_shared(surface
)) {
1543 if (share_surface
) {
1544 surface
= qemu_create_displaysurface_from(disp_width
,
1545 height
, format
, s
->line_offset
,
1546 s
->vram_ptr
+ (s
->start_addr
* 4));
1547 dpy_gfx_replace_surface(s
->con
, surface
);
1549 printf("VGA: Using shared surface for depth=%d swap=%d\n",
1553 qemu_console_resize(s
->con
, disp_width
, height
);
1554 surface
= qemu_console_surface(s
->con
);
1556 printf("VGA: Using shadow surface for depth=%d swap=%d\n",
1560 s
->last_scr_width
= disp_width
;
1561 s
->last_scr_height
= height
;
1562 s
->last_width
= disp_width
;
1563 s
->last_height
= height
;
1564 s
->last_line_offset
= s
->line_offset
;
1565 s
->last_depth
= depth
;
1566 s
->last_byteswap
= byteswap
;
1568 } else if (is_buffer_shared(surface
) &&
1569 (full_update
|| surface_data(surface
) != s
->vram_ptr
1570 + (s
->start_addr
* 4))) {
1571 pixman_format_code_t format
=
1572 qemu_default_pixman_format(depth
, !byteswap
);
1573 surface
= qemu_create_displaysurface_from(disp_width
,
1574 height
, format
, s
->line_offset
,
1575 s
->vram_ptr
+ (s
->start_addr
* 4));
1576 dpy_gfx_replace_surface(s
->con
, surface
);
1579 if (shift_control
== 0) {
1580 full_update
|= update_palette16(s
);
1581 if (sr(s
, VGA_SEQ_CLOCK_MODE
) & 8) {
1582 v
= VGA_DRAW_LINE4D2
;
1587 } else if (shift_control
== 1) {
1588 full_update
|= update_palette16(s
);
1589 if (sr(s
, VGA_SEQ_CLOCK_MODE
) & 8) {
1590 v
= VGA_DRAW_LINE2D2
;
1596 switch(s
->get_bpp(s
)) {
1599 full_update
|= update_palette256(s
);
1600 v
= VGA_DRAW_LINE8D2
;
1604 full_update
|= update_palette256(s
);
1609 v
= s
->big_endian_fb
? VGA_DRAW_LINE15_BE
: VGA_DRAW_LINE15_LE
;
1613 v
= s
->big_endian_fb
? VGA_DRAW_LINE16_BE
: VGA_DRAW_LINE16_LE
;
1617 v
= s
->big_endian_fb
? VGA_DRAW_LINE24_BE
: VGA_DRAW_LINE24_LE
;
1621 v
= s
->big_endian_fb
? VGA_DRAW_LINE32_BE
: VGA_DRAW_LINE32_LE
;
1626 vga_draw_line
= vga_draw_line_table
[v
];
1628 if (!is_buffer_shared(surface
) && s
->cursor_invalidate
) {
1629 s
->cursor_invalidate(s
);
1632 line_offset
= s
->line_offset
;
1634 printf("w=%d h=%d v=%d line_offset=%d cr[0x09]=0x%02x cr[0x17]=0x%02x linecmp=%d sr[0x01]=0x%02x\n",
1635 width
, height
, v
, line_offset
, s
->cr
[9], s
->cr
[VGA_CRTC_MODE
],
1636 s
->line_compare
, sr(s
, VGA_SEQ_CLOCK_MODE
));
1638 addr1
= (s
->start_addr
* 4);
1639 bwidth
= (width
* bits
+ 7) / 8;
1643 d
= surface_data(surface
);
1644 linesize
= surface_stride(surface
);
1646 for(y
= 0; y
< height
; y
++) {
1648 if (!(s
->cr
[VGA_CRTC_MODE
] & 1)) {
1650 /* CGA compatibility handling */
1651 shift
= 14 + ((s
->cr
[VGA_CRTC_MODE
] >> 6) & 1);
1652 addr
= (addr
& ~(1 << shift
)) | ((y1
& 1) << shift
);
1654 if (!(s
->cr
[VGA_CRTC_MODE
] & 2)) {
1655 addr
= (addr
& ~0x8000) | ((y1
& 2) << 14);
1657 update
= full_update
;
1659 page1
= addr
+ bwidth
- 1;
1660 update
|= memory_region_get_dirty(&s
->vram
, page0
, page1
- page0
,
1662 /* explicit invalidation for the hardware cursor */
1663 update
|= (s
->invalidated_y_table
[y
>> 5] >> (y
& 0x1f)) & 1;
1667 if (page0
< page_min
)
1669 if (page1
> page_max
)
1671 if (!(is_buffer_shared(surface
))) {
1672 vga_draw_line(s
, d
, s
->vram_ptr
+ addr
, width
);
1673 if (s
->cursor_draw_line
)
1674 s
->cursor_draw_line(s
, d
, y
);
1678 /* flush to display */
1679 dpy_gfx_update(s
->con
, 0, y_start
,
1680 disp_width
, y
- y_start
);
1685 mask
= (s
->cr
[VGA_CRTC_MODE
] & 3) ^ 3;
1686 if ((y1
& mask
) == mask
)
1687 addr1
+= line_offset
;
1689 multi_run
= multi_scan
;
1693 /* line compare acts on the displayed lines */
1694 if (y
== s
->line_compare
)
1699 /* flush to display */
1700 dpy_gfx_update(s
->con
, 0, y_start
,
1701 disp_width
, y
- y_start
);
1703 /* reset modified pages */
1704 if (page_max
>= page_min
) {
1705 memory_region_reset_dirty(&s
->vram
,
1707 page_max
- page_min
,
1710 memset(s
->invalidated_y_table
, 0, ((height
+ 31) >> 5) * 4);
1713 static void vga_draw_blank(VGACommonState
*s
, int full_update
)
1715 DisplaySurface
*surface
= qemu_console_surface(s
->con
);
1721 if (s
->last_scr_width
<= 0 || s
->last_scr_height
<= 0)
1724 w
= s
->last_scr_width
* surface_bytes_per_pixel(surface
);
1725 d
= surface_data(surface
);
1726 for(i
= 0; i
< s
->last_scr_height
; i
++) {
1728 d
+= surface_stride(surface
);
1730 dpy_gfx_update(s
->con
, 0, 0,
1731 s
->last_scr_width
, s
->last_scr_height
);
1734 #define GMODE_TEXT 0
1735 #define GMODE_GRAPH 1
1736 #define GMODE_BLANK 2
1738 static void vga_update_display(void *opaque
)
1740 VGACommonState
*s
= opaque
;
1741 DisplaySurface
*surface
= qemu_console_surface(s
->con
);
1742 int full_update
, graphic_mode
;
1744 qemu_flush_coalesced_mmio_buffer();
1746 if (surface_bits_per_pixel(surface
) == 0) {
1750 if (!(s
->ar_index
& 0x20)) {
1751 graphic_mode
= GMODE_BLANK
;
1753 graphic_mode
= s
->gr
[VGA_GFX_MISC
] & VGA_GR06_GRAPHICS_MODE
;
1755 if (graphic_mode
!= s
->graphic_mode
) {
1756 s
->graphic_mode
= graphic_mode
;
1757 s
->cursor_blink_time
= qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL
);
1760 switch(graphic_mode
) {
1762 vga_draw_text(s
, full_update
);
1765 vga_draw_graphic(s
, full_update
);
1769 vga_draw_blank(s
, full_update
);
1775 /* force a full display refresh */
1776 static void vga_invalidate_display(void *opaque
)
1778 VGACommonState
*s
= opaque
;
1781 s
->last_height
= -1;
1784 void vga_common_reset(VGACommonState
*s
)
1787 memset(s
->sr
, '\0', sizeof(s
->sr
));
1788 memset(s
->sr_vbe
, '\0', sizeof(s
->sr_vbe
));
1790 memset(s
->gr
, '\0', sizeof(s
->gr
));
1792 memset(s
->ar
, '\0', sizeof(s
->ar
));
1793 s
->ar_flip_flop
= 0;
1795 memset(s
->cr
, '\0', sizeof(s
->cr
));
1801 s
->dac_sub_index
= 0;
1802 s
->dac_read_index
= 0;
1803 s
->dac_write_index
= 0;
1804 memset(s
->dac_cache
, '\0', sizeof(s
->dac_cache
));
1806 memset(s
->palette
, '\0', sizeof(s
->palette
));
1809 memset(s
->vbe_regs
, '\0', sizeof(s
->vbe_regs
));
1810 s
->vbe_regs
[VBE_DISPI_INDEX_ID
] = VBE_DISPI_ID5
;
1811 s
->vbe_start_addr
= 0;
1812 s
->vbe_line_offset
= 0;
1813 s
->vbe_bank_mask
= (s
->vram_size
>> 16) - 1;
1814 memset(s
->font_offsets
, '\0', sizeof(s
->font_offsets
));
1815 s
->graphic_mode
= -1; /* force full update */
1816 s
->shift_control
= 0;
1819 s
->line_compare
= 0;
1821 s
->plane_updated
= 0;
1826 s
->last_scr_width
= 0;
1827 s
->last_scr_height
= 0;
1828 s
->cursor_start
= 0;
1830 s
->cursor_offset
= 0;
1831 s
->big_endian_fb
= s
->default_endian_fb
;
1832 memset(s
->invalidated_y_table
, '\0', sizeof(s
->invalidated_y_table
));
1833 memset(s
->last_palette
, '\0', sizeof(s
->last_palette
));
1834 memset(s
->last_ch_attr
, '\0', sizeof(s
->last_ch_attr
));
1835 switch (vga_retrace_method
) {
1836 case VGA_RETRACE_DUMB
:
1838 case VGA_RETRACE_PRECISE
:
1839 memset(&s
->retrace_info
, 0, sizeof (s
->retrace_info
));
1842 vga_update_memory_access(s
);
1845 static void vga_reset(void *opaque
)
1847 VGACommonState
*s
= opaque
;
1848 vga_common_reset(s
);
1851 #define TEXTMODE_X(x) ((x) % width)
1852 #define TEXTMODE_Y(x) ((x) / width)
1853 #define VMEM2CHTYPE(v) ((v & 0xff0007ff) | \
1854 ((v & 0x00000800) << 10) | ((v & 0x00007000) >> 1))
1855 /* relay text rendering to the display driver
1856 * instead of doing a full vga_update_display() */
1857 static void vga_update_text(void *opaque
, console_ch_t
*chardata
)
1859 VGACommonState
*s
= opaque
;
1860 int graphic_mode
, i
, cursor_offset
, cursor_visible
;
1861 int cw
, cheight
, width
, height
, size
, c_min
, c_max
;
1863 console_ch_t
*dst
, val
;
1864 char msg_buffer
[80];
1865 int full_update
= 0;
1867 qemu_flush_coalesced_mmio_buffer();
1869 if (!(s
->ar_index
& 0x20)) {
1870 graphic_mode
= GMODE_BLANK
;
1872 graphic_mode
= s
->gr
[VGA_GFX_MISC
] & VGA_GR06_GRAPHICS_MODE
;
1874 if (graphic_mode
!= s
->graphic_mode
) {
1875 s
->graphic_mode
= graphic_mode
;
1878 if (s
->last_width
== -1) {
1883 switch (graphic_mode
) {
1885 /* TODO: update palette */
1886 full_update
|= update_basic_params(s
);
1888 /* total width & height */
1889 cheight
= (s
->cr
[VGA_CRTC_MAX_SCAN
] & 0x1f) + 1;
1891 if (!(sr(s
, VGA_SEQ_CLOCK_MODE
) & VGA_SR01_CHAR_CLK_8DOTS
)) {
1894 if (sr(s
, VGA_SEQ_CLOCK_MODE
) & 0x08) {
1895 cw
= 16; /* NOTE: no 18 pixel wide */
1897 width
= (s
->cr
[VGA_CRTC_H_DISP
] + 1);
1898 if (s
->cr
[VGA_CRTC_V_TOTAL
] == 100) {
1899 /* ugly hack for CGA 160x100x16 - explain me the logic */
1902 height
= s
->cr
[VGA_CRTC_V_DISP_END
] |
1903 ((s
->cr
[VGA_CRTC_OVERFLOW
] & 0x02) << 7) |
1904 ((s
->cr
[VGA_CRTC_OVERFLOW
] & 0x40) << 3);
1905 height
= (height
+ 1) / cheight
;
1908 size
= (height
* width
);
1909 if (size
> CH_ATTR_SIZE
) {
1913 snprintf(msg_buffer
, sizeof(msg_buffer
), "%i x %i Text mode",
1918 if (width
!= s
->last_width
|| height
!= s
->last_height
||
1919 cw
!= s
->last_cw
|| cheight
!= s
->last_ch
) {
1920 s
->last_scr_width
= width
* cw
;
1921 s
->last_scr_height
= height
* cheight
;
1922 qemu_console_resize(s
->con
, s
->last_scr_width
, s
->last_scr_height
);
1923 dpy_text_resize(s
->con
, width
, height
);
1925 s
->last_width
= width
;
1926 s
->last_height
= height
;
1927 s
->last_ch
= cheight
;
1933 s
->full_update_gfx
= 1;
1935 if (s
->full_update_text
) {
1936 s
->full_update_text
= 0;
1940 /* Update "hardware" cursor */
1941 cursor_offset
= ((s
->cr
[VGA_CRTC_CURSOR_HI
] << 8) |
1942 s
->cr
[VGA_CRTC_CURSOR_LO
]) - s
->start_addr
;
1943 if (cursor_offset
!= s
->cursor_offset
||
1944 s
->cr
[VGA_CRTC_CURSOR_START
] != s
->cursor_start
||
1945 s
->cr
[VGA_CRTC_CURSOR_END
] != s
->cursor_end
|| full_update
) {
1946 cursor_visible
= !(s
->cr
[VGA_CRTC_CURSOR_START
] & 0x20);
1947 if (cursor_visible
&& cursor_offset
< size
&& cursor_offset
>= 0)
1948 dpy_text_cursor(s
->con
,
1949 TEXTMODE_X(cursor_offset
),
1950 TEXTMODE_Y(cursor_offset
));
1952 dpy_text_cursor(s
->con
, -1, -1);
1953 s
->cursor_offset
= cursor_offset
;
1954 s
->cursor_start
= s
->cr
[VGA_CRTC_CURSOR_START
];
1955 s
->cursor_end
= s
->cr
[VGA_CRTC_CURSOR_END
];
1958 src
= (uint32_t *) s
->vram_ptr
+ s
->start_addr
;
1962 for (i
= 0; i
< size
; src
++, dst
++, i
++)
1963 console_write_ch(dst
, VMEM2CHTYPE(le32_to_cpu(*src
)));
1965 dpy_text_update(s
->con
, 0, 0, width
, height
);
1969 for (i
= 0; i
< size
; src
++, dst
++, i
++) {
1970 console_write_ch(&val
, VMEM2CHTYPE(le32_to_cpu(*src
)));
1978 for (; i
< size
; src
++, dst
++, i
++) {
1979 console_write_ch(&val
, VMEM2CHTYPE(le32_to_cpu(*src
)));
1986 if (c_min
<= c_max
) {
1987 i
= TEXTMODE_Y(c_min
);
1988 dpy_text_update(s
->con
, 0, i
, width
, TEXTMODE_Y(c_max
) - i
+ 1);
1997 s
->get_resolution(s
, &width
, &height
);
1998 snprintf(msg_buffer
, sizeof(msg_buffer
), "%i x %i Graphic mode",
2006 snprintf(msg_buffer
, sizeof(msg_buffer
), "VGA Blank mode");
2010 /* Display a message */
2012 s
->last_height
= height
= 3;
2013 dpy_text_cursor(s
->con
, -1, -1);
2014 dpy_text_resize(s
->con
, s
->last_width
, height
);
2016 for (dst
= chardata
, i
= 0; i
< s
->last_width
* height
; i
++)
2017 console_write_ch(dst
++, ' ');
2019 size
= strlen(msg_buffer
);
2020 width
= (s
->last_width
- size
) / 2;
2021 dst
= chardata
+ s
->last_width
+ width
;
2022 for (i
= 0; i
< size
; i
++)
2023 console_write_ch(dst
++, ATTR2CHTYPE(msg_buffer
[i
], QEMU_COLOR_BLUE
,
2024 QEMU_COLOR_BLACK
, 1));
2026 dpy_text_update(s
->con
, 0, 0, s
->last_width
, height
);
2029 static uint64_t vga_mem_read(void *opaque
, hwaddr addr
,
2032 VGACommonState
*s
= opaque
;
2034 return vga_mem_readb(s
, addr
);
2037 static void vga_mem_write(void *opaque
, hwaddr addr
,
2038 uint64_t data
, unsigned size
)
2040 VGACommonState
*s
= opaque
;
2042 vga_mem_writeb(s
, addr
, data
);
2045 const MemoryRegionOps vga_mem_ops
= {
2046 .read
= vga_mem_read
,
2047 .write
= vga_mem_write
,
2048 .endianness
= DEVICE_LITTLE_ENDIAN
,
2050 .min_access_size
= 1,
2051 .max_access_size
= 1,
2055 static int vga_common_post_load(void *opaque
, int version_id
)
2057 VGACommonState
*s
= opaque
;
2060 s
->graphic_mode
= -1;
2061 vbe_update_vgaregs(s
);
2065 static bool vga_endian_state_needed(void *opaque
)
2067 VGACommonState
*s
= opaque
;
2070 * Only send the endian state if it's different from the
2071 * default one, thus ensuring backward compatibility for
2072 * migration of the common case
2074 return s
->default_endian_fb
!= s
->big_endian_fb
;
2077 static const VMStateDescription vmstate_vga_endian
= {
2078 .name
= "vga.endian",
2080 .minimum_version_id
= 1,
2081 .needed
= vga_endian_state_needed
,
2082 .fields
= (VMStateField
[]) {
2083 VMSTATE_BOOL(big_endian_fb
, VGACommonState
),
2084 VMSTATE_END_OF_LIST()
2088 const VMStateDescription vmstate_vga_common
= {
2091 .minimum_version_id
= 2,
2092 .post_load
= vga_common_post_load
,
2093 .fields
= (VMStateField
[]) {
2094 VMSTATE_UINT32(latch
, VGACommonState
),
2095 VMSTATE_UINT8(sr_index
, VGACommonState
),
2096 VMSTATE_PARTIAL_BUFFER(sr
, VGACommonState
, 8),
2097 VMSTATE_UINT8(gr_index
, VGACommonState
),
2098 VMSTATE_PARTIAL_BUFFER(gr
, VGACommonState
, 16),
2099 VMSTATE_UINT8(ar_index
, VGACommonState
),
2100 VMSTATE_BUFFER(ar
, VGACommonState
),
2101 VMSTATE_INT32(ar_flip_flop
, VGACommonState
),
2102 VMSTATE_UINT8(cr_index
, VGACommonState
),
2103 VMSTATE_BUFFER(cr
, VGACommonState
),
2104 VMSTATE_UINT8(msr
, VGACommonState
),
2105 VMSTATE_UINT8(fcr
, VGACommonState
),
2106 VMSTATE_UINT8(st00
, VGACommonState
),
2107 VMSTATE_UINT8(st01
, VGACommonState
),
2109 VMSTATE_UINT8(dac_state
, VGACommonState
),
2110 VMSTATE_UINT8(dac_sub_index
, VGACommonState
),
2111 VMSTATE_UINT8(dac_read_index
, VGACommonState
),
2112 VMSTATE_UINT8(dac_write_index
, VGACommonState
),
2113 VMSTATE_BUFFER(dac_cache
, VGACommonState
),
2114 VMSTATE_BUFFER(palette
, VGACommonState
),
2116 VMSTATE_INT32(bank_offset
, VGACommonState
),
2117 VMSTATE_UINT8_EQUAL(is_vbe_vmstate
, VGACommonState
),
2118 VMSTATE_UINT16(vbe_index
, VGACommonState
),
2119 VMSTATE_UINT16_ARRAY(vbe_regs
, VGACommonState
, VBE_DISPI_INDEX_NB
),
2120 VMSTATE_UINT32(vbe_start_addr
, VGACommonState
),
2121 VMSTATE_UINT32(vbe_line_offset
, VGACommonState
),
2122 VMSTATE_UINT32(vbe_bank_mask
, VGACommonState
),
2123 VMSTATE_END_OF_LIST()
2125 .subsections
= (const VMStateDescription
*[]) {
2126 &vmstate_vga_endian
,
2131 static const GraphicHwOps vga_ops
= {
2132 .invalidate
= vga_invalidate_display
,
2133 .gfx_update
= vga_update_display
,
2134 .text_update
= vga_update_text
,
2137 static inline uint32_t uint_clamp(uint32_t val
, uint32_t vmin
, uint32_t vmax
)
2148 void vga_common_init(VGACommonState
*s
, Object
*obj
, bool global_vmstate
)
2152 for(i
= 0;i
< 256; i
++) {
2154 for(j
= 0; j
< 8; j
++) {
2155 v
|= ((i
>> j
) & 1) << (j
* 4);
2160 for(j
= 0; j
< 4; j
++) {
2161 v
|= ((i
>> (2 * j
)) & 3) << (j
* 4);
2165 for(i
= 0; i
< 16; i
++) {
2167 for(j
= 0; j
< 4; j
++) {
2170 v
|= b
<< (2 * j
+ 1);
2175 s
->vram_size_mb
= uint_clamp(s
->vram_size_mb
, 1, 512);
2176 s
->vram_size_mb
= pow2ceil(s
->vram_size_mb
);
2177 s
->vram_size
= s
->vram_size_mb
<< 20;
2180 s
->vbe_size
= s
->vram_size
;
2183 s
->is_vbe_vmstate
= 1;
2184 memory_region_init_ram(&s
->vram
, obj
, "vga.vram", s
->vram_size
,
2186 vmstate_register_ram(&s
->vram
, global_vmstate
? NULL
: DEVICE(obj
));
2187 xen_register_framebuffer(&s
->vram
);
2188 s
->vram_ptr
= memory_region_get_ram_ptr(&s
->vram
);
2189 s
->get_bpp
= vga_get_bpp
;
2190 s
->get_offsets
= vga_get_offsets
;
2191 s
->get_resolution
= vga_get_resolution
;
2192 s
->hw_ops
= &vga_ops
;
2193 switch (vga_retrace_method
) {
2194 case VGA_RETRACE_DUMB
:
2195 s
->retrace
= vga_dumb_retrace
;
2196 s
->update_retrace_info
= vga_dumb_update_retrace_info
;
2199 case VGA_RETRACE_PRECISE
:
2200 s
->retrace
= vga_precise_retrace
;
2201 s
->update_retrace_info
= vga_precise_update_retrace_info
;
2206 * Set default fb endian based on target, could probably be turned
2207 * into a device attribute set by the machine/platform to remove
2208 * all target endian dependencies from this file.
2210 #ifdef TARGET_WORDS_BIGENDIAN
2211 s
->default_endian_fb
= true;
2213 s
->default_endian_fb
= false;
2215 vga_dirty_log_start(s
);
2218 static const MemoryRegionPortio vga_portio_list
[] = {
2219 { 0x04, 2, 1, .read
= vga_ioport_read
, .write
= vga_ioport_write
}, /* 3b4 */
2220 { 0x0a, 1, 1, .read
= vga_ioport_read
, .write
= vga_ioport_write
}, /* 3ba */
2221 { 0x10, 16, 1, .read
= vga_ioport_read
, .write
= vga_ioport_write
}, /* 3c0 */
2222 { 0x24, 2, 1, .read
= vga_ioport_read
, .write
= vga_ioport_write
}, /* 3d4 */
2223 { 0x2a, 1, 1, .read
= vga_ioport_read
, .write
= vga_ioport_write
}, /* 3da */
2224 PORTIO_END_OF_LIST(),
2227 static const MemoryRegionPortio vbe_portio_list
[] = {
2228 { 0, 1, 2, .read
= vbe_ioport_read_index
, .write
= vbe_ioport_write_index
},
2230 { 1, 1, 2, .read
= vbe_ioport_read_data
, .write
= vbe_ioport_write_data
},
2232 { 2, 1, 2, .read
= vbe_ioport_read_data
, .write
= vbe_ioport_write_data
},
2233 PORTIO_END_OF_LIST(),
2236 /* Used by both ISA and PCI */
2237 MemoryRegion
*vga_init_io(VGACommonState
*s
, Object
*obj
,
2238 const MemoryRegionPortio
**vga_ports
,
2239 const MemoryRegionPortio
**vbe_ports
)
2241 MemoryRegion
*vga_mem
;
2243 *vga_ports
= vga_portio_list
;
2244 *vbe_ports
= vbe_portio_list
;
2246 vga_mem
= g_malloc(sizeof(*vga_mem
));
2247 memory_region_init_io(vga_mem
, obj
, &vga_mem_ops
, s
,
2248 "vga-lowmem", 0x20000);
2249 memory_region_set_flush_coalesced(vga_mem
);
2254 void vga_init(VGACommonState
*s
, Object
*obj
, MemoryRegion
*address_space
,
2255 MemoryRegion
*address_space_io
, bool init_vga_ports
)
2257 MemoryRegion
*vga_io_memory
;
2258 const MemoryRegionPortio
*vga_ports
, *vbe_ports
;
2260 qemu_register_reset(vga_reset
, s
);
2264 s
->legacy_address_space
= address_space
;
2266 vga_io_memory
= vga_init_io(s
, obj
, &vga_ports
, &vbe_ports
);
2267 memory_region_add_subregion_overlap(address_space
,
2271 memory_region_set_coalescing(vga_io_memory
);
2272 if (init_vga_ports
) {
2273 portio_list_init(&s
->vga_port_list
, obj
, vga_ports
, s
, "vga");
2274 portio_list_set_flush_coalesced(&s
->vga_port_list
);
2275 portio_list_add(&s
->vga_port_list
, address_space_io
, 0x3b0);
2278 portio_list_init(&s
->vbe_port_list
, obj
, vbe_ports
, s
, "vbe");
2279 portio_list_add(&s
->vbe_port_list
, address_space_io
, 0x1ce);
2283 void vga_init_vbe(VGACommonState
*s
, Object
*obj
, MemoryRegion
*system_memory
)
2285 /* With pc-0.12 and below we map both the PCI BAR and the fixed VBE region,
2286 * so use an alias to avoid double-mapping the same region.
2288 memory_region_init_alias(&s
->vram_vbe
, obj
, "vram.vbe",
2289 &s
->vram
, 0, memory_region_size(&s
->vram
));
2290 /* XXX: use optimized standard vga accesses */
2291 memory_region_add_subregion(system_memory
,
2292 VBE_DISPI_LFB_PHYSICAL_ADDRESS
,