target/ppc/helper_regs.c

   1 /*
   2  *  PowerPC emulation special registers manipulation helpers for qemu.
   3  *
   4  *  Copyright (c) 2003-2007 Jocelyn Mayer
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2.1 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "qemu/osdep.h"
  21 #include "cpu.h"
  22 #include "qemu/main-loop.h"
  23 #include "exec/exec-all.h"
  24 #include "sysemu/kvm.h"
  25 #include "helper_regs.h"
  26 #include "power8-pmu.h"
  27 #include "cpu-models.h"
  28 #include "spr_common.h"
  29
  30 /* Swap temporary saved registers with GPRs */
  31 void hreg_swap_gpr_tgpr(CPUPPCState *env)
  32 {
  33     target_ulong tmp;
  34
  35     tmp = env->gpr[0];
  36     env->gpr[0] = env->tgpr[0];
  37     env->tgpr[0] = tmp;
  38     tmp = env->gpr[1];
  39     env->gpr[1] = env->tgpr[1];
  40     env->tgpr[1] = tmp;
  41     tmp = env->gpr[2];
  42     env->gpr[2] = env->tgpr[2];
  43     env->tgpr[2] = tmp;
  44     tmp = env->gpr[3];
  45     env->gpr[3] = env->tgpr[3];
  46     env->tgpr[3] = tmp;
  47 }
  48
  49 static uint32_t hreg_compute_hflags_value(CPUPPCState *env)
  50 {
  51     target_ulong msr = env->msr;
  52     uint32_t ppc_flags = env->flags;
  53     uint32_t hflags = 0;
  54     uint32_t msr_mask;
  55
  56     /* Some bits come straight across from MSR. */
  57     QEMU_BUILD_BUG_ON(MSR_LE != HFLAGS_LE);
  58     QEMU_BUILD_BUG_ON(MSR_PR != HFLAGS_PR);
  59     QEMU_BUILD_BUG_ON(MSR_DR != HFLAGS_DR);
  60     QEMU_BUILD_BUG_ON(MSR_FP != HFLAGS_FP);
  61     msr_mask = ((1 << MSR_LE) | (1 << MSR_PR) |
  62                 (1 << MSR_DR) | (1 << MSR_FP));
  63
  64     if (ppc_flags & POWERPC_FLAG_DE) {
  65         target_ulong dbcr0 = env->spr[SPR_BOOKE_DBCR0];
  66         if (dbcr0 & DBCR0_ICMP) {
  67             hflags |= 1 << HFLAGS_SE;
  68         }
  69         if (dbcr0 & DBCR0_BRT) {
  70             hflags |= 1 << HFLAGS_BE;
  71         }
  72     } else {
  73         if (ppc_flags & POWERPC_FLAG_BE) {
  74             QEMU_BUILD_BUG_ON(MSR_BE != HFLAGS_BE);
  75             msr_mask |= 1 << MSR_BE;
  76         }
  77         if (ppc_flags & POWERPC_FLAG_SE) {
  78             QEMU_BUILD_BUG_ON(MSR_SE != HFLAGS_SE);
  79             msr_mask |= 1 << MSR_SE;
  80         }
  81     }
  82
  83     if (msr_is_64bit(env, msr)) {
  84         hflags |= 1 << HFLAGS_64;
  85     }
  86     if ((ppc_flags & POWERPC_FLAG_SPE) && (msr & (1 << MSR_SPE))) {
  87         hflags |= 1 << HFLAGS_SPE;
  88     }
  89     if (ppc_flags & POWERPC_FLAG_VRE) {
  90         QEMU_BUILD_BUG_ON(MSR_VR != HFLAGS_VR);
  91         msr_mask |= 1 << MSR_VR;
  92     }
  93     if (ppc_flags & POWERPC_FLAG_VSX) {
  94         QEMU_BUILD_BUG_ON(MSR_VSX != HFLAGS_VSX);
  95         msr_mask |= 1 << MSR_VSX;
  96     }
  97     if ((ppc_flags & POWERPC_FLAG_TM) && (msr & (1ull << MSR_TM))) {
  98         hflags |= 1 << HFLAGS_TM;
  99     }
 100     if (env->spr[SPR_LPCR] & LPCR_GTSE) {
 101         hflags |= 1 << HFLAGS_GTSE;
 102     }
 103     if (env->spr[SPR_LPCR] & LPCR_HR) {
 104         hflags |= 1 << HFLAGS_HR;
 105     }
 106     if (env->spr[SPR_POWER_MMCR0] & MMCR0_PMCC0) {
 107         hflags |= 1 << HFLAGS_PMCC0;
 108     }
 109     if (env->spr[SPR_POWER_MMCR0] & MMCR0_PMCC1) {
 110         hflags |= 1 << HFLAGS_PMCC1;
 111     }
 112
 113 #ifndef CONFIG_USER_ONLY
 114     if (!env->has_hv_mode || (msr & (1ull << MSR_HV))) {
 115         hflags |= 1 << HFLAGS_HV;
 116     }
 117
 118 #if defined(TARGET_PPC64)
 119     if (env->pmc_ins_cnt) {
 120         hflags |= 1 << HFLAGS_INSN_CNT;
 121     }
 122 #endif
 123
 124     /*
 125      * This is our encoding for server processors. The architecture
 126      * specifies that there is no such thing as userspace with
 127      * translation off, however it appears that MacOS does it and some
 128      * 32-bit CPUs support it. Weird...
 129      *
 130      *   0 = Guest User space virtual mode
 131      *   1 = Guest Kernel space virtual mode
 132      *   2 = Guest User space real mode
 133      *   3 = Guest Kernel space real mode
 134      *   4 = HV User space virtual mode
 135      *   5 = HV Kernel space virtual mode
 136      *   6 = HV User space real mode
 137      *   7 = HV Kernel space real mode
 138      *
 139      * For BookE, we need 8 MMU modes as follow:
 140      *
 141      *  0 = AS 0 HV User space
 142      *  1 = AS 0 HV Kernel space
 143      *  2 = AS 1 HV User space
 144      *  3 = AS 1 HV Kernel space
 145      *  4 = AS 0 Guest User space
 146      *  5 = AS 0 Guest Kernel space
 147      *  6 = AS 1 Guest User space
 148      *  7 = AS 1 Guest Kernel space
 149      */
 150     unsigned immu_idx, dmmu_idx;
 151     dmmu_idx = msr & (1 << MSR_PR) ? 0 : 1;
 152     if (env->mmu_model == POWERPC_MMU_BOOKE ||
 153         env->mmu_model == POWERPC_MMU_BOOKE206) {
 154         dmmu_idx |= msr & (1 << MSR_GS) ? 4 : 0;
 155         immu_idx = dmmu_idx;
 156         immu_idx |= msr & (1 << MSR_IS) ? 2 : 0;
 157         dmmu_idx |= msr & (1 << MSR_DS) ? 2 : 0;
 158     } else {
 159         dmmu_idx |= msr & (1ull << MSR_HV) ? 4 : 0;
 160         immu_idx = dmmu_idx;
 161         immu_idx |= msr & (1 << MSR_IR) ? 0 : 2;
 162         dmmu_idx |= msr & (1 << MSR_DR) ? 0 : 2;
 163     }
 164     hflags |= immu_idx << HFLAGS_IMMU_IDX;
 165     hflags |= dmmu_idx << HFLAGS_DMMU_IDX;
 166 #endif
 167
 168     return hflags | (msr & msr_mask);
 169 }
 170
 171 void hreg_compute_hflags(CPUPPCState *env)
 172 {
 173     env->hflags = hreg_compute_hflags_value(env);
 174 }
 175
 176 #ifdef CONFIG_DEBUG_TCG
 177 void cpu_get_tb_cpu_state(CPUPPCState *env, target_ulong *pc,
 178                           target_ulong *cs_base, uint32_t *flags)
 179 {
 180     uint32_t hflags_current = env->hflags;
 181     uint32_t hflags_rebuilt;
 182
 183     *pc = env->nip;
 184     *cs_base = 0;
 185     *flags = hflags_current;
 186
 187     hflags_rebuilt = hreg_compute_hflags_value(env);
 188     if (unlikely(hflags_current != hflags_rebuilt)) {
 189         cpu_abort(env_cpu(env),
 190                   "TCG hflags mismatch (current:0x%08x rebuilt:0x%08x)\n",
 191                   hflags_current, hflags_rebuilt);
 192     }
 193 }
 194 #endif
 195
 196 void cpu_interrupt_exittb(CPUState *cs)
 197 {
 198     /*
 199      * We don't need to worry about translation blocks
 200      * when running with KVM.
 201      */
 202     if (kvm_enabled()) {
 203         return;
 204     }
 205
 206     if (!qemu_mutex_iothread_locked()) {
 207         qemu_mutex_lock_iothread();
 208         cpu_interrupt(cs, CPU_INTERRUPT_EXITTB);
 209         qemu_mutex_unlock_iothread();
 210     } else {
 211         cpu_interrupt(cs, CPU_INTERRUPT_EXITTB);
 212     }
 213 }
 214
 215 int hreg_store_msr(CPUPPCState *env, target_ulong value, int alter_hv)
 216 {
 217     int excp;
 218 #if !defined(CONFIG_USER_ONLY)
 219     CPUState *cs = env_cpu(env);
 220 #endif
 221
 222     excp = 0;
 223     value &= env->msr_mask;
 224 #if !defined(CONFIG_USER_ONLY)
 225     /* Neither mtmsr nor guest state can alter HV */
 226     if (!alter_hv || !(env->msr & MSR_HVB)) {
 227         value &= ~MSR_HVB;
 228         value |= env->msr & MSR_HVB;
 229     }
 230     if (((value >> MSR_IR) & 1) != msr_ir ||
 231         ((value >> MSR_DR) & 1) != msr_dr) {
 232         cpu_interrupt_exittb(cs);
 233     }
 234     if ((env->mmu_model == POWERPC_MMU_BOOKE ||
 235          env->mmu_model == POWERPC_MMU_BOOKE206) &&
 236         ((value >> MSR_GS) & 1) != msr_gs) {
 237         cpu_interrupt_exittb(cs);
 238     }
 239     if (unlikely((env->flags & POWERPC_FLAG_TGPR) &&
 240                  ((value ^ env->msr) & (1 << MSR_TGPR)))) {
 241         /* Swap temporary saved registers with GPRs */
 242         hreg_swap_gpr_tgpr(env);
 243     }
 244     if (unlikely((value >> MSR_EP) & 1) != msr_ep) {
 245         env->excp_prefix = ((value >> MSR_EP) & 1) * 0xFFF00000;
 246     }
 247     /*
 248      * If PR=1 then EE, IR and DR must be 1
 249      *
 250      * Note: We only enforce this on 64-bit server processors.
 251      * It appears that:
 252      * - 32-bit implementations supports PR=1 and EE/DR/IR=0 and MacOS
 253      *   exploits it.
 254      * - 64-bit embedded implementations do not need any operation to be
 255      *   performed when PR is set.
 256      */
 257     if (is_book3s_arch2x(env) && ((value >> MSR_PR) & 1)) {
 258         value |= (1 << MSR_EE) | (1 << MSR_DR) | (1 << MSR_IR);
 259     }
 260 #endif
 261     env->msr = value;
 262     hreg_compute_hflags(env);
 263 #if !defined(CONFIG_USER_ONLY)
 264     if (unlikely(msr_pow == 1)) {
 265         if (!env->pending_interrupts && (*env->check_pow)(env)) {
 266             cs->halted = 1;
 267             excp = EXCP_HALTED;
 268         }
 269     }
 270 #endif
 271
 272     return excp;
 273 }
 274
 275 #ifdef CONFIG_SOFTMMU
 276 void store_40x_sler(CPUPPCState *env, uint32_t val)
 277 {
 278     /* XXX: TO BE FIXED */
 279     if (val != 0x00000000) {
 280         cpu_abort(env_cpu(env),
 281                   "Little-endian regions are not supported by now\n");
 282     }
 283     env->spr[SPR_405_SLER] = val;
 284 }
 285 #endif /* CONFIG_SOFTMMU */
 286
 287 #ifndef CONFIG_USER_ONLY
 288 void check_tlb_flush(CPUPPCState *env, bool global)
 289 {
 290     CPUState *cs = env_cpu(env);
 291
 292     /* Handle global flushes first */
 293     if (global && (env->tlb_need_flush & TLB_NEED_GLOBAL_FLUSH)) {
 294         env->tlb_need_flush &= ~TLB_NEED_GLOBAL_FLUSH;
 295         env->tlb_need_flush &= ~TLB_NEED_LOCAL_FLUSH;
 296         tlb_flush_all_cpus_synced(cs);
 297         return;
 298     }
 299
 300     /* Then handle local ones */
 301     if (env->tlb_need_flush & TLB_NEED_LOCAL_FLUSH) {
 302         env->tlb_need_flush &= ~TLB_NEED_LOCAL_FLUSH;
 303         tlb_flush(cs);
 304     }
 305 }
 306 #endif
 307
 308 /**
 309  * _spr_register
 310  *
 311  * Register an SPR with all the callbacks required for tcg,
 312  * and the ID number for KVM.
 313  *
 314  * The reason for the conditional compilation is that the tcg functions
 315  * may be compiled out, and the system kvm header may not be available
 316  * for supplying the ID numbers.  This is ugly, but the best we can do.
 317  */
 318 void _spr_register(CPUPPCState *env, int num, const char *name,
 319                    USR_ARG(spr_callback *uea_read)
 320                    USR_ARG(spr_callback *uea_write)
 321                    SYS_ARG(spr_callback *oea_read)
 322                    SYS_ARG(spr_callback *oea_write)
 323                    SYS_ARG(spr_callback *hea_read)
 324                    SYS_ARG(spr_callback *hea_write)
 325                    KVM_ARG(uint64_t one_reg_id)
 326                    target_ulong initial_value)
 327 {
 328     ppc_spr_t *spr = &env->spr_cb[num];
 329
 330     /* No SPR should be registered twice. */
 331     assert(spr->name == NULL);
 332     assert(name != NULL);
 333
 334     spr->name = name;
 335     spr->default_value = initial_value;
 336     env->spr[num] = initial_value;
 337
 338 #ifdef CONFIG_TCG
 339     spr->uea_read = uea_read;
 340     spr->uea_write = uea_write;
 341 # ifndef CONFIG_USER_ONLY
 342     spr->oea_read = oea_read;
 343     spr->oea_write = oea_write;
 344     spr->hea_read = hea_read;
 345     spr->hea_write = hea_write;
 346 # endif
 347 #endif
 348 #ifdef CONFIG_KVM
 349     spr->one_reg_id = one_reg_id;
 350 #endif
 351 }
 352
 353 /* Generic PowerPC SPRs */
 354 void register_generic_sprs(PowerPCCPU *cpu)
 355 {
 356     PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
 357     CPUPPCState *env = &cpu->env;
 358
 359     /* Integer processing */
 360     spr_register(env, SPR_XER, "XER",
 361                  &spr_read_xer, &spr_write_xer,
 362                  &spr_read_xer, &spr_write_xer,
 363                  0x00000000);
 364     /* Branch control */
 365     spr_register(env, SPR_LR, "LR",
 366                  &spr_read_lr, &spr_write_lr,
 367                  &spr_read_lr, &spr_write_lr,
 368                  0x00000000);
 369     spr_register(env, SPR_CTR, "CTR",
 370                  &spr_read_ctr, &spr_write_ctr,
 371                  &spr_read_ctr, &spr_write_ctr,
 372                  0x00000000);
 373     /* Interrupt processing */
 374     spr_register(env, SPR_SRR0, "SRR0",
 375                  SPR_NOACCESS, SPR_NOACCESS,
 376                  &spr_read_generic, &spr_write_generic,
 377                  0x00000000);
 378     spr_register(env, SPR_SRR1, "SRR1",
 379                  SPR_NOACCESS, SPR_NOACCESS,
 380                  &spr_read_generic, &spr_write_generic,
 381                  0x00000000);
 382     /* Processor control */
 383     spr_register(env, SPR_SPRG0, "SPRG0",
 384                  SPR_NOACCESS, SPR_NOACCESS,
 385                  &spr_read_generic, &spr_write_generic,
 386                  0x00000000);
 387     spr_register(env, SPR_SPRG1, "SPRG1",
 388                  SPR_NOACCESS, SPR_NOACCESS,
 389                  &spr_read_generic, &spr_write_generic,
 390                  0x00000000);
 391     spr_register(env, SPR_SPRG2, "SPRG2",
 392                  SPR_NOACCESS, SPR_NOACCESS,
 393                  &spr_read_generic, &spr_write_generic,
 394                  0x00000000);
 395     spr_register(env, SPR_SPRG3, "SPRG3",
 396                  SPR_NOACCESS, SPR_NOACCESS,
 397                  &spr_read_generic, &spr_write_generic,
 398                  0x00000000);
 399
 400     spr_register(env, SPR_PVR, "PVR",
 401                  /* Linux permits userspace to read PVR */
 402 #if defined(CONFIG_LINUX_USER)
 403                  &spr_read_generic,
 404 #else
 405                  SPR_NOACCESS,
 406 #endif
 407                  SPR_NOACCESS,
 408                  &spr_read_generic, SPR_NOACCESS,
 409                  pcc->pvr);
 410
 411     /* Register SVR if it's defined to anything else than POWERPC_SVR_NONE */
 412     if (pcc->svr != POWERPC_SVR_NONE) {
 413         if (pcc->svr & POWERPC_SVR_E500) {
 414             spr_register(env, SPR_E500_SVR, "SVR",
 415                          SPR_NOACCESS, SPR_NOACCESS,
 416                          &spr_read_generic, SPR_NOACCESS,
 417                          pcc->svr & ~POWERPC_SVR_E500);
 418         } else {
 419             spr_register(env, SPR_SVR, "SVR",
 420                          SPR_NOACCESS, SPR_NOACCESS,
 421                          &spr_read_generic, SPR_NOACCESS,
 422                          pcc->svr);
 423         }
 424     }
 425
 426     /* Time base */
 427     spr_register(env, SPR_VTBL,  "TBL",
 428                  &spr_read_tbl, SPR_NOACCESS,
 429                  &spr_read_tbl, SPR_NOACCESS,
 430                  0x00000000);
 431     spr_register(env, SPR_TBL,   "TBL",
 432                  &spr_read_tbl, SPR_NOACCESS,
 433                  &spr_read_tbl, &spr_write_tbl,
 434                  0x00000000);
 435     spr_register(env, SPR_VTBU,  "TBU",
 436                  &spr_read_tbu, SPR_NOACCESS,
 437                  &spr_read_tbu, SPR_NOACCESS,
 438                  0x00000000);
 439     spr_register(env, SPR_TBU,   "TBU",
 440                  &spr_read_tbu, SPR_NOACCESS,
 441                  &spr_read_tbu, &spr_write_tbu,
 442                  0x00000000);
 443 }
 444
 445 void register_non_embedded_sprs(CPUPPCState *env)
 446 {
 447     /* Exception processing */
 448     spr_register_kvm(env, SPR_DSISR, "DSISR",
 449                      SPR_NOACCESS, SPR_NOACCESS,
 450                      &spr_read_generic, &spr_write_generic,
 451                      KVM_REG_PPC_DSISR, 0x00000000);
 452     spr_register_kvm(env, SPR_DAR, "DAR",
 453                      SPR_NOACCESS, SPR_NOACCESS,
 454                      &spr_read_generic, &spr_write_generic,
 455                      KVM_REG_PPC_DAR, 0x00000000);
 456     /* Timer */
 457     spr_register(env, SPR_DECR, "DECR",
 458                  SPR_NOACCESS, SPR_NOACCESS,
 459                  &spr_read_decr, &spr_write_decr,
 460                  0x00000000);
 461 }
 462
 463 /* Storage Description Register 1 */
 464 void register_sdr1_sprs(CPUPPCState *env)
 465 {
 466 #ifndef CONFIG_USER_ONLY
 467     if (env->has_hv_mode) {
 468         /*
 469          * SDR1 is a hypervisor resource on CPUs which have a
 470          * hypervisor mode
 471          */
 472         spr_register_hv(env, SPR_SDR1, "SDR1",
 473                         SPR_NOACCESS, SPR_NOACCESS,
 474                         SPR_NOACCESS, SPR_NOACCESS,
 475                         &spr_read_generic, &spr_write_sdr1,
 476                         0x00000000);
 477     } else {
 478         spr_register(env, SPR_SDR1, "SDR1",
 479                      SPR_NOACCESS, SPR_NOACCESS,
 480                      &spr_read_generic, &spr_write_sdr1,
 481                      0x00000000);
 482     }
 483 #endif
 484 }
 485
 486 /* BATs 0-3 */
 487 void register_low_BATs(CPUPPCState *env)
 488 {
 489 #if !defined(CONFIG_USER_ONLY)
 490     spr_register(env, SPR_IBAT0U, "IBAT0U",
 491                  SPR_NOACCESS, SPR_NOACCESS,
 492                  &spr_read_ibat, &spr_write_ibatu,
 493                  0x00000000);
 494     spr_register(env, SPR_IBAT0L, "IBAT0L",
 495                  SPR_NOACCESS, SPR_NOACCESS,
 496                  &spr_read_ibat, &spr_write_ibatl,
 497                  0x00000000);
 498     spr_register(env, SPR_IBAT1U, "IBAT1U",
 499                  SPR_NOACCESS, SPR_NOACCESS,
 500                  &spr_read_ibat, &spr_write_ibatu,
 501                  0x00000000);
 502     spr_register(env, SPR_IBAT1L, "IBAT1L",
 503                  SPR_NOACCESS, SPR_NOACCESS,
 504                  &spr_read_ibat, &spr_write_ibatl,
 505                  0x00000000);
 506     spr_register(env, SPR_IBAT2U, "IBAT2U",
 507                  SPR_NOACCESS, SPR_NOACCESS,
 508                  &spr_read_ibat, &spr_write_ibatu,
 509                  0x00000000);
 510     spr_register(env, SPR_IBAT2L, "IBAT2L",
 511                  SPR_NOACCESS, SPR_NOACCESS,
 512                  &spr_read_ibat, &spr_write_ibatl,
 513                  0x00000000);
 514     spr_register(env, SPR_IBAT3U, "IBAT3U",
 515                  SPR_NOACCESS, SPR_NOACCESS,
 516                  &spr_read_ibat, &spr_write_ibatu,
 517                  0x00000000);
 518     spr_register(env, SPR_IBAT3L, "IBAT3L",
 519                  SPR_NOACCESS, SPR_NOACCESS,
 520                  &spr_read_ibat, &spr_write_ibatl,
 521                  0x00000000);
 522     spr_register(env, SPR_DBAT0U, "DBAT0U",
 523                  SPR_NOACCESS, SPR_NOACCESS,
 524                  &spr_read_dbat, &spr_write_dbatu,
 525                  0x00000000);
 526     spr_register(env, SPR_DBAT0L, "DBAT0L",
 527                  SPR_NOACCESS, SPR_NOACCESS,
 528                  &spr_read_dbat, &spr_write_dbatl,
 529                  0x00000000);
 530     spr_register(env, SPR_DBAT1U, "DBAT1U",
 531                  SPR_NOACCESS, SPR_NOACCESS,
 532                  &spr_read_dbat, &spr_write_dbatu,
 533                  0x00000000);
 534     spr_register(env, SPR_DBAT1L, "DBAT1L",
 535                  SPR_NOACCESS, SPR_NOACCESS,
 536                  &spr_read_dbat, &spr_write_dbatl,
 537                  0x00000000);
 538     spr_register(env, SPR_DBAT2U, "DBAT2U",
 539                  SPR_NOACCESS, SPR_NOACCESS,
 540                  &spr_read_dbat, &spr_write_dbatu,
 541                  0x00000000);
 542     spr_register(env, SPR_DBAT2L, "DBAT2L",
 543                  SPR_NOACCESS, SPR_NOACCESS,
 544                  &spr_read_dbat, &spr_write_dbatl,
 545                  0x00000000);
 546     spr_register(env, SPR_DBAT3U, "DBAT3U",
 547                  SPR_NOACCESS, SPR_NOACCESS,
 548                  &spr_read_dbat, &spr_write_dbatu,
 549                  0x00000000);
 550     spr_register(env, SPR_DBAT3L, "DBAT3L",
 551                  SPR_NOACCESS, SPR_NOACCESS,
 552                  &spr_read_dbat, &spr_write_dbatl,
 553                  0x00000000);
 554     env->nb_BATs += 4;
 555 #endif
 556 }
 557
 558 /* BATs 4-7 */
 559 void register_high_BATs(CPUPPCState *env)
 560 {
 561 #if !defined(CONFIG_USER_ONLY)
 562     spr_register(env, SPR_IBAT4U, "IBAT4U",
 563                  SPR_NOACCESS, SPR_NOACCESS,
 564                  &spr_read_ibat_h, &spr_write_ibatu_h,
 565                  0x00000000);
 566     spr_register(env, SPR_IBAT4L, "IBAT4L",
 567                  SPR_NOACCESS, SPR_NOACCESS,
 568                  &spr_read_ibat_h, &spr_write_ibatl_h,
 569                  0x00000000);
 570     spr_register(env, SPR_IBAT5U, "IBAT5U",
 571                  SPR_NOACCESS, SPR_NOACCESS,
 572                  &spr_read_ibat_h, &spr_write_ibatu_h,
 573                  0x00000000);
 574     spr_register(env, SPR_IBAT5L, "IBAT5L",
 575                  SPR_NOACCESS, SPR_NOACCESS,
 576                  &spr_read_ibat_h, &spr_write_ibatl_h,
 577                  0x00000000);
 578     spr_register(env, SPR_IBAT6U, "IBAT6U",
 579                  SPR_NOACCESS, SPR_NOACCESS,
 580                  &spr_read_ibat_h, &spr_write_ibatu_h,
 581                  0x00000000);
 582     spr_register(env, SPR_IBAT6L, "IBAT6L",
 583                  SPR_NOACCESS, SPR_NOACCESS,
 584                  &spr_read_ibat_h, &spr_write_ibatl_h,
 585                  0x00000000);
 586     spr_register(env, SPR_IBAT7U, "IBAT7U",
 587                  SPR_NOACCESS, SPR_NOACCESS,
 588                  &spr_read_ibat_h, &spr_write_ibatu_h,
 589                  0x00000000);
 590     spr_register(env, SPR_IBAT7L, "IBAT7L",
 591                  SPR_NOACCESS, SPR_NOACCESS,
 592                  &spr_read_ibat_h, &spr_write_ibatl_h,
 593                  0x00000000);
 594     spr_register(env, SPR_DBAT4U, "DBAT4U",
 595                  SPR_NOACCESS, SPR_NOACCESS,
 596                  &spr_read_dbat_h, &spr_write_dbatu_h,
 597                  0x00000000);
 598     spr_register(env, SPR_DBAT4L, "DBAT4L",
 599                  SPR_NOACCESS, SPR_NOACCESS,
 600                  &spr_read_dbat_h, &spr_write_dbatl_h,
 601                  0x00000000);
 602     spr_register(env, SPR_DBAT5U, "DBAT5U",
 603                  SPR_NOACCESS, SPR_NOACCESS,
 604                  &spr_read_dbat_h, &spr_write_dbatu_h,
 605                  0x00000000);
 606     spr_register(env, SPR_DBAT5L, "DBAT5L",
 607                  SPR_NOACCESS, SPR_NOACCESS,
 608                  &spr_read_dbat_h, &spr_write_dbatl_h,
 609                  0x00000000);
 610     spr_register(env, SPR_DBAT6U, "DBAT6U",
 611                  SPR_NOACCESS, SPR_NOACCESS,
 612                  &spr_read_dbat_h, &spr_write_dbatu_h,
 613                  0x00000000);
 614     spr_register(env, SPR_DBAT6L, "DBAT6L",
 615                  SPR_NOACCESS, SPR_NOACCESS,
 616                  &spr_read_dbat_h, &spr_write_dbatl_h,
 617                  0x00000000);
 618     spr_register(env, SPR_DBAT7U, "DBAT7U",
 619                  SPR_NOACCESS, SPR_NOACCESS,
 620                  &spr_read_dbat_h, &spr_write_dbatu_h,
 621                  0x00000000);
 622     spr_register(env, SPR_DBAT7L, "DBAT7L",
 623                  SPR_NOACCESS, SPR_NOACCESS,
 624                  &spr_read_dbat_h, &spr_write_dbatl_h,
 625                  0x00000000);
 626     env->nb_BATs += 4;
 627 #endif
 628 }
 629
 630 /* Softare table search registers */
 631 void register_6xx_7xx_soft_tlb(CPUPPCState *env, int nb_tlbs, int nb_ways)
 632 {
 633 #if !defined(CONFIG_USER_ONLY)
 634     env->nb_tlb = nb_tlbs;
 635     env->nb_ways = nb_ways;
 636     env->id_tlbs = 1;
 637     env->tlb_type = TLB_6XX;
 638     spr_register(env, SPR_DMISS, "DMISS",
 639                  SPR_NOACCESS, SPR_NOACCESS,
 640                  &spr_read_generic, SPR_NOACCESS,
 641                  0x00000000);
 642     spr_register(env, SPR_DCMP, "DCMP",
 643                  SPR_NOACCESS, SPR_NOACCESS,
 644                  &spr_read_generic, SPR_NOACCESS,
 645                  0x00000000);
 646     spr_register(env, SPR_HASH1, "HASH1",
 647                  SPR_NOACCESS, SPR_NOACCESS,
 648                  &spr_read_generic, SPR_NOACCESS,
 649                  0x00000000);
 650     spr_register(env, SPR_HASH2, "HASH2",
 651                  SPR_NOACCESS, SPR_NOACCESS,
 652                  &spr_read_generic, SPR_NOACCESS,
 653                  0x00000000);
 654     spr_register(env, SPR_IMISS, "IMISS",
 655                  SPR_NOACCESS, SPR_NOACCESS,
 656                  &spr_read_generic, SPR_NOACCESS,
 657                  0x00000000);
 658     spr_register(env, SPR_ICMP, "ICMP",
 659                  SPR_NOACCESS, SPR_NOACCESS,
 660                  &spr_read_generic, SPR_NOACCESS,
 661                  0x00000000);
 662     spr_register(env, SPR_RPA, "RPA",
 663                  SPR_NOACCESS, SPR_NOACCESS,
 664                  &spr_read_generic, &spr_write_generic,
 665                  0x00000000);
 666 #endif
 667 }
 668
 669 void register_thrm_sprs(CPUPPCState *env)
 670 {
 671     /* Thermal management */
 672     spr_register(env, SPR_THRM1, "THRM1",
 673                  SPR_NOACCESS, SPR_NOACCESS,
 674                  &spr_read_thrm, &spr_write_generic,
 675                  0x00000000);
 676
 677     spr_register(env, SPR_THRM2, "THRM2",
 678                  SPR_NOACCESS, SPR_NOACCESS,
 679                  &spr_read_thrm, &spr_write_generic,
 680                  0x00000000);
 681
 682     spr_register(env, SPR_THRM3, "THRM3",
 683                  SPR_NOACCESS, SPR_NOACCESS,
 684                  &spr_read_thrm, &spr_write_generic,
 685                  0x00000000);
 686 }
 687
 688 void register_usprgh_sprs(CPUPPCState *env)
 689 {
 690     spr_register(env, SPR_USPRG4, "USPRG4",
 691                  &spr_read_ureg, SPR_NOACCESS,
 692                  &spr_read_ureg, SPR_NOACCESS,
 693                  0x00000000);
 694     spr_register(env, SPR_USPRG5, "USPRG5",
 695                  &spr_read_ureg, SPR_NOACCESS,
 696                  &spr_read_ureg, SPR_NOACCESS,
 697                  0x00000000);
 698     spr_register(env, SPR_USPRG6, "USPRG6",
 699                  &spr_read_ureg, SPR_NOACCESS,
 700                  &spr_read_ureg, SPR_NOACCESS,
 701                  0x00000000);
 702     spr_register(env, SPR_USPRG7, "USPRG7",
 703                  &spr_read_ureg, SPR_NOACCESS,
 704                  &spr_read_ureg, SPR_NOACCESS,
 705                  0x00000000);
 706 }