2 * Helpers for loads and stores
4 * Copyright (c) 2003-2005 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
21 #include "exec/helper-proto.h"
25 //#define DEBUG_UNALIGNED
26 //#define DEBUG_UNASSIGNED
28 //#define DEBUG_CACHE_CONTROL
31 #define DPRINTF_MMU(fmt, ...) \
32 do { printf("MMU: " fmt , ## __VA_ARGS__); } while (0)
34 #define DPRINTF_MMU(fmt, ...) do {} while (0)
38 #define DPRINTF_MXCC(fmt, ...) \
39 do { printf("MXCC: " fmt , ## __VA_ARGS__); } while (0)
41 #define DPRINTF_MXCC(fmt, ...) do {} while (0)
45 #define DPRINTF_ASI(fmt, ...) \
46 do { printf("ASI: " fmt , ## __VA_ARGS__); } while (0)
49 #ifdef DEBUG_CACHE_CONTROL
50 #define DPRINTF_CACHE_CONTROL(fmt, ...) \
51 do { printf("CACHE_CONTROL: " fmt , ## __VA_ARGS__); } while (0)
53 #define DPRINTF_CACHE_CONTROL(fmt, ...) do {} while (0)
58 #define AM_CHECK(env1) ((env1)->pstate & PS_AM)
60 #define AM_CHECK(env1) (1)
64 #define QT0 (env->qt0)
65 #define QT1 (env->qt1)
67 #if !defined(CONFIG_USER_ONLY)
68 #include "exec/softmmu_exec.h"
69 #define MMUSUFFIX _mmu
73 #include "exec/softmmu_template.h"
76 #include "exec/softmmu_template.h"
79 #include "exec/softmmu_template.h"
82 #include "exec/softmmu_template.h"
85 #if defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY)
86 /* Calculates TSB pointer value for fault page size 8k or 64k */
87 static uint64_t ultrasparc_tsb_pointer(uint64_t tsb_register
,
88 uint64_t tag_access_register
,
91 uint64_t tsb_base
= tsb_register
& ~0x1fffULL
;
92 int tsb_split
= (tsb_register
& 0x1000ULL
) ? 1 : 0;
93 int tsb_size
= tsb_register
& 0xf;
95 /* discard lower 13 bits which hold tag access context */
96 uint64_t tag_access_va
= tag_access_register
& ~0x1fffULL
;
98 /* now reorder bits */
99 uint64_t tsb_base_mask
= ~0x1fffULL
;
100 uint64_t va
= tag_access_va
;
102 /* move va bits to correct position */
103 if (page_size
== 8*1024) {
105 } else if (page_size
== 64*1024) {
110 tsb_base_mask
<<= tsb_size
;
113 /* calculate tsb_base mask and adjust va if split is in use */
115 if (page_size
== 8*1024) {
116 va
&= ~(1ULL << (13 + tsb_size
));
117 } else if (page_size
== 64*1024) {
118 va
|= (1ULL << (13 + tsb_size
));
123 return ((tsb_base
& tsb_base_mask
) | (va
& ~tsb_base_mask
)) & ~0xfULL
;
126 /* Calculates tag target register value by reordering bits
127 in tag access register */
128 static uint64_t ultrasparc_tag_target(uint64_t tag_access_register
)
130 return ((tag_access_register
& 0x1fff) << 48) | (tag_access_register
>> 22);
133 static void replace_tlb_entry(SparcTLBEntry
*tlb
,
134 uint64_t tlb_tag
, uint64_t tlb_tte
,
137 target_ulong mask
, size
, va
, offset
;
139 /* flush page range if translation is valid */
140 if (TTE_IS_VALID(tlb
->tte
)) {
141 CPUState
*cs
= CPU(sparc_env_get_cpu(env1
));
143 mask
= 0xffffffffffffe000ULL
;
144 mask
<<= 3 * ((tlb
->tte
>> 61) & 3);
147 va
= tlb
->tag
& mask
;
149 for (offset
= 0; offset
< size
; offset
+= TARGET_PAGE_SIZE
) {
150 tlb_flush_page(cs
, va
+ offset
);
158 static void demap_tlb(SparcTLBEntry
*tlb
, target_ulong demap_addr
,
159 const char *strmmu
, CPUSPARCState
*env1
)
165 int is_demap_context
= (demap_addr
>> 6) & 1;
168 switch ((demap_addr
>> 4) & 3) {
169 case 0: /* primary */
170 context
= env1
->dmmu
.mmu_primary_context
;
172 case 1: /* secondary */
173 context
= env1
->dmmu
.mmu_secondary_context
;
175 case 2: /* nucleus */
178 case 3: /* reserved */
183 for (i
= 0; i
< 64; i
++) {
184 if (TTE_IS_VALID(tlb
[i
].tte
)) {
186 if (is_demap_context
) {
187 /* will remove non-global entries matching context value */
188 if (TTE_IS_GLOBAL(tlb
[i
].tte
) ||
189 !tlb_compare_context(&tlb
[i
], context
)) {
194 will remove any entry matching VA */
195 mask
= 0xffffffffffffe000ULL
;
196 mask
<<= 3 * ((tlb
[i
].tte
>> 61) & 3);
198 if (!compare_masked(demap_addr
, tlb
[i
].tag
, mask
)) {
202 /* entry should be global or matching context value */
203 if (!TTE_IS_GLOBAL(tlb
[i
].tte
) &&
204 !tlb_compare_context(&tlb
[i
], context
)) {
209 replace_tlb_entry(&tlb
[i
], 0, 0, env1
);
211 DPRINTF_MMU("%s demap invalidated entry [%02u]\n", strmmu
, i
);
212 dump_mmu(stdout
, fprintf
, env1
);
218 static void replace_tlb_1bit_lru(SparcTLBEntry
*tlb
,
219 uint64_t tlb_tag
, uint64_t tlb_tte
,
220 const char *strmmu
, CPUSPARCState
*env1
)
222 unsigned int i
, replace_used
;
224 /* Try replacing invalid entry */
225 for (i
= 0; i
< 64; i
++) {
226 if (!TTE_IS_VALID(tlb
[i
].tte
)) {
227 replace_tlb_entry(&tlb
[i
], tlb_tag
, tlb_tte
, env1
);
229 DPRINTF_MMU("%s lru replaced invalid entry [%i]\n", strmmu
, i
);
230 dump_mmu(stdout
, fprintf
, env1
);
236 /* All entries are valid, try replacing unlocked entry */
238 for (replace_used
= 0; replace_used
< 2; ++replace_used
) {
240 /* Used entries are not replaced on first pass */
242 for (i
= 0; i
< 64; i
++) {
243 if (!TTE_IS_LOCKED(tlb
[i
].tte
) && !TTE_IS_USED(tlb
[i
].tte
)) {
245 replace_tlb_entry(&tlb
[i
], tlb_tag
, tlb_tte
, env1
);
247 DPRINTF_MMU("%s lru replaced unlocked %s entry [%i]\n",
248 strmmu
, (replace_used
? "used" : "unused"), i
);
249 dump_mmu(stdout
, fprintf
, env1
);
255 /* Now reset used bit and search for unused entries again */
257 for (i
= 0; i
< 64; i
++) {
258 TTE_SET_UNUSED(tlb
[i
].tte
);
263 DPRINTF_MMU("%s lru replacement failed: no entries available\n", strmmu
);
270 static inline target_ulong
address_mask(CPUSPARCState
*env1
, target_ulong addr
)
272 #ifdef TARGET_SPARC64
273 if (AM_CHECK(env1
)) {
274 addr
&= 0xffffffffULL
;
280 /* returns true if access using this ASI is to have address translated by MMU
281 otherwise access is to raw physical address */
282 static inline int is_translating_asi(int asi
)
284 #ifdef TARGET_SPARC64
285 /* Ultrasparc IIi translating asi
286 - note this list is defined by cpu implementation
302 /* TODO: check sparc32 bits */
307 static inline target_ulong
asi_address_mask(CPUSPARCState
*env
,
308 int asi
, target_ulong addr
)
310 if (is_translating_asi(asi
)) {
311 return address_mask(env
, addr
);
317 void helper_check_align(CPUSPARCState
*env
, target_ulong addr
, uint32_t align
)
320 #ifdef DEBUG_UNALIGNED
321 printf("Unaligned access to 0x" TARGET_FMT_lx
" from 0x" TARGET_FMT_lx
322 "\n", addr
, env
->pc
);
324 helper_raise_exception(env
, TT_UNALIGNED
);
328 #if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) && \
330 static void dump_mxcc(CPUSPARCState
*env
)
332 printf("mxccdata: %016" PRIx64
" %016" PRIx64
" %016" PRIx64
" %016" PRIx64
334 env
->mxccdata
[0], env
->mxccdata
[1],
335 env
->mxccdata
[2], env
->mxccdata
[3]);
336 printf("mxccregs: %016" PRIx64
" %016" PRIx64
" %016" PRIx64
" %016" PRIx64
338 " %016" PRIx64
" %016" PRIx64
" %016" PRIx64
" %016" PRIx64
340 env
->mxccregs
[0], env
->mxccregs
[1],
341 env
->mxccregs
[2], env
->mxccregs
[3],
342 env
->mxccregs
[4], env
->mxccregs
[5],
343 env
->mxccregs
[6], env
->mxccregs
[7]);
347 #if (defined(TARGET_SPARC64) || !defined(CONFIG_USER_ONLY)) \
348 && defined(DEBUG_ASI)
349 static void dump_asi(const char *txt
, target_ulong addr
, int asi
, int size
,
354 DPRINTF_ASI("%s "TARGET_FMT_lx
" asi 0x%02x = %02" PRIx64
"\n", txt
,
355 addr
, asi
, r1
& 0xff);
358 DPRINTF_ASI("%s "TARGET_FMT_lx
" asi 0x%02x = %04" PRIx64
"\n", txt
,
359 addr
, asi
, r1
& 0xffff);
362 DPRINTF_ASI("%s "TARGET_FMT_lx
" asi 0x%02x = %08" PRIx64
"\n", txt
,
363 addr
, asi
, r1
& 0xffffffff);
366 DPRINTF_ASI("%s "TARGET_FMT_lx
" asi 0x%02x = %016" PRIx64
"\n", txt
,
373 #ifndef TARGET_SPARC64
374 #ifndef CONFIG_USER_ONLY
377 /* Leon3 cache control */
379 static void leon3_cache_control_st(CPUSPARCState
*env
, target_ulong addr
,
380 uint64_t val
, int size
)
382 DPRINTF_CACHE_CONTROL("st addr:%08x, val:%" PRIx64
", size:%d\n",
386 DPRINTF_CACHE_CONTROL("32bits only\n");
391 case 0x00: /* Cache control */
393 /* These values must always be read as zeros */
394 val
&= ~CACHE_CTRL_FD
;
395 val
&= ~CACHE_CTRL_FI
;
396 val
&= ~CACHE_CTRL_IB
;
397 val
&= ~CACHE_CTRL_IP
;
398 val
&= ~CACHE_CTRL_DP
;
400 env
->cache_control
= val
;
402 case 0x04: /* Instruction cache configuration */
403 case 0x08: /* Data cache configuration */
407 DPRINTF_CACHE_CONTROL("write unknown register %08x\n", addr
);
412 static uint64_t leon3_cache_control_ld(CPUSPARCState
*env
, target_ulong addr
,
418 DPRINTF_CACHE_CONTROL("32bits only\n");
423 case 0x00: /* Cache control */
424 ret
= env
->cache_control
;
427 /* Configuration registers are read and only always keep those
430 case 0x04: /* Instruction cache configuration */
433 case 0x08: /* Data cache configuration */
437 DPRINTF_CACHE_CONTROL("read unknown register %08x\n", addr
);
440 DPRINTF_CACHE_CONTROL("ld addr:%08x, ret:0x%" PRIx64
", size:%d\n",
445 uint64_t helper_ld_asi(CPUSPARCState
*env
, target_ulong addr
, int asi
, int size
,
448 CPUState
*cs
= CPU(sparc_env_get_cpu(env
));
450 #if defined(DEBUG_MXCC) || defined(DEBUG_ASI)
451 uint32_t last_addr
= addr
;
454 helper_check_align(env
, addr
, size
- 1);
456 case 2: /* SuperSparc MXCC registers and Leon3 cache control */
458 case 0x00: /* Leon3 Cache Control */
459 case 0x08: /* Leon3 Instruction Cache config */
460 case 0x0C: /* Leon3 Date Cache config */
461 if (env
->def
->features
& CPU_FEATURE_CACHE_CTRL
) {
462 ret
= leon3_cache_control_ld(env
, addr
, size
);
465 case 0x01c00a00: /* MXCC control register */
467 ret
= env
->mxccregs
[3];
469 qemu_log_mask(LOG_UNIMP
,
470 "%08x: unimplemented access size: %d\n", addr
,
474 case 0x01c00a04: /* MXCC control register */
476 ret
= env
->mxccregs
[3];
478 qemu_log_mask(LOG_UNIMP
,
479 "%08x: unimplemented access size: %d\n", addr
,
483 case 0x01c00c00: /* Module reset register */
485 ret
= env
->mxccregs
[5];
486 /* should we do something here? */
488 qemu_log_mask(LOG_UNIMP
,
489 "%08x: unimplemented access size: %d\n", addr
,
493 case 0x01c00f00: /* MBus port address register */
495 ret
= env
->mxccregs
[7];
497 qemu_log_mask(LOG_UNIMP
,
498 "%08x: unimplemented access size: %d\n", addr
,
503 qemu_log_mask(LOG_UNIMP
,
504 "%08x: unimplemented address, size: %d\n", addr
,
508 DPRINTF_MXCC("asi = %d, size = %d, sign = %d, "
509 "addr = %08x -> ret = %" PRIx64
","
510 "addr = %08x\n", asi
, size
, sign
, last_addr
, ret
, addr
);
515 case 3: /* MMU probe */
516 case 0x18: /* LEON3 MMU probe */
520 mmulev
= (addr
>> 8) & 15;
524 ret
= mmu_probe(env
, addr
, mmulev
);
526 DPRINTF_MMU("mmu_probe: 0x%08x (lev %d) -> 0x%08" PRIx64
"\n",
530 case 4: /* read MMU regs */
531 case 0x19: /* LEON3 read MMU regs */
533 int reg
= (addr
>> 8) & 0x1f;
535 ret
= env
->mmuregs
[reg
];
536 if (reg
== 3) { /* Fault status cleared on read */
538 } else if (reg
== 0x13) { /* Fault status read */
539 ret
= env
->mmuregs
[3];
540 } else if (reg
== 0x14) { /* Fault address read */
541 ret
= env
->mmuregs
[4];
543 DPRINTF_MMU("mmu_read: reg[%d] = 0x%08" PRIx64
"\n", reg
, ret
);
546 case 5: /* Turbosparc ITLB Diagnostic */
547 case 6: /* Turbosparc DTLB Diagnostic */
548 case 7: /* Turbosparc IOTLB Diagnostic */
550 case 9: /* Supervisor code access */
553 ret
= cpu_ldub_code(env
, addr
);
556 ret
= cpu_lduw_code(env
, addr
);
560 ret
= cpu_ldl_code(env
, addr
);
563 ret
= cpu_ldq_code(env
, addr
);
567 case 0xa: /* User data access */
570 ret
= cpu_ldub_user(env
, addr
);
573 ret
= cpu_lduw_user(env
, addr
);
577 ret
= cpu_ldl_user(env
, addr
);
580 ret
= cpu_ldq_user(env
, addr
);
584 case 0xb: /* Supervisor data access */
588 ret
= cpu_ldub_kernel(env
, addr
);
591 ret
= cpu_lduw_kernel(env
, addr
);
595 ret
= cpu_ldl_kernel(env
, addr
);
598 ret
= cpu_ldq_kernel(env
, addr
);
602 case 0xc: /* I-cache tag */
603 case 0xd: /* I-cache data */
604 case 0xe: /* D-cache tag */
605 case 0xf: /* D-cache data */
607 case 0x20: /* MMU passthrough */
608 case 0x1c: /* LEON MMU passthrough */
611 ret
= ldub_phys(cs
->as
, addr
);
614 ret
= lduw_phys(cs
->as
, addr
);
618 ret
= ldl_phys(cs
->as
, addr
);
621 ret
= ldq_phys(cs
->as
, addr
);
625 case 0x21 ... 0x2f: /* MMU passthrough, 0x100000000 to 0xfffffffff */
628 ret
= ldub_phys(cs
->as
, (hwaddr
)addr
629 | ((hwaddr
)(asi
& 0xf) << 32));
632 ret
= lduw_phys(cs
->as
, (hwaddr
)addr
633 | ((hwaddr
)(asi
& 0xf) << 32));
637 ret
= ldl_phys(cs
->as
, (hwaddr
)addr
638 | ((hwaddr
)(asi
& 0xf) << 32));
641 ret
= ldq_phys(cs
->as
, (hwaddr
)addr
642 | ((hwaddr
)(asi
& 0xf) << 32));
646 case 0x30: /* Turbosparc secondary cache diagnostic */
647 case 0x31: /* Turbosparc RAM snoop */
648 case 0x32: /* Turbosparc page table descriptor diagnostic */
649 case 0x39: /* data cache diagnostic register */
652 case 0x38: /* SuperSPARC MMU Breakpoint Control Registers */
654 int reg
= (addr
>> 8) & 3;
657 case 0: /* Breakpoint Value (Addr) */
658 ret
= env
->mmubpregs
[reg
];
660 case 1: /* Breakpoint Mask */
661 ret
= env
->mmubpregs
[reg
];
663 case 2: /* Breakpoint Control */
664 ret
= env
->mmubpregs
[reg
];
666 case 3: /* Breakpoint Status */
667 ret
= env
->mmubpregs
[reg
];
668 env
->mmubpregs
[reg
] = 0ULL;
671 DPRINTF_MMU("read breakpoint reg[%d] 0x%016" PRIx64
"\n", reg
,
675 case 0x49: /* SuperSPARC MMU Counter Breakpoint Value */
676 ret
= env
->mmubpctrv
;
678 case 0x4a: /* SuperSPARC MMU Counter Breakpoint Control */
679 ret
= env
->mmubpctrc
;
681 case 0x4b: /* SuperSPARC MMU Counter Breakpoint Status */
682 ret
= env
->mmubpctrs
;
684 case 0x4c: /* SuperSPARC MMU Breakpoint Action */
685 ret
= env
->mmubpaction
;
687 case 8: /* User code access, XXX */
689 cpu_unassigned_access(cs
, addr
, false, false, asi
, size
);
709 dump_asi("read ", last_addr
, asi
, size
, ret
);
714 void helper_st_asi(CPUSPARCState
*env
, target_ulong addr
, uint64_t val
, int asi
,
717 SPARCCPU
*cpu
= sparc_env_get_cpu(env
);
718 CPUState
*cs
= CPU(cpu
);
720 helper_check_align(env
, addr
, size
- 1);
722 case 2: /* SuperSparc MXCC registers and Leon3 cache control */
724 case 0x00: /* Leon3 Cache Control */
725 case 0x08: /* Leon3 Instruction Cache config */
726 case 0x0C: /* Leon3 Date Cache config */
727 if (env
->def
->features
& CPU_FEATURE_CACHE_CTRL
) {
728 leon3_cache_control_st(env
, addr
, val
, size
);
732 case 0x01c00000: /* MXCC stream data register 0 */
734 env
->mxccdata
[0] = val
;
736 qemu_log_mask(LOG_UNIMP
,
737 "%08x: unimplemented access size: %d\n", addr
,
741 case 0x01c00008: /* MXCC stream data register 1 */
743 env
->mxccdata
[1] = val
;
745 qemu_log_mask(LOG_UNIMP
,
746 "%08x: unimplemented access size: %d\n", addr
,
750 case 0x01c00010: /* MXCC stream data register 2 */
752 env
->mxccdata
[2] = val
;
754 qemu_log_mask(LOG_UNIMP
,
755 "%08x: unimplemented access size: %d\n", addr
,
759 case 0x01c00018: /* MXCC stream data register 3 */
761 env
->mxccdata
[3] = val
;
763 qemu_log_mask(LOG_UNIMP
,
764 "%08x: unimplemented access size: %d\n", addr
,
768 case 0x01c00100: /* MXCC stream source */
770 env
->mxccregs
[0] = val
;
772 qemu_log_mask(LOG_UNIMP
,
773 "%08x: unimplemented access size: %d\n", addr
,
776 env
->mxccdata
[0] = ldq_phys(cs
->as
,
777 (env
->mxccregs
[0] & 0xffffffffULL
) +
779 env
->mxccdata
[1] = ldq_phys(cs
->as
,
780 (env
->mxccregs
[0] & 0xffffffffULL
) +
782 env
->mxccdata
[2] = ldq_phys(cs
->as
,
783 (env
->mxccregs
[0] & 0xffffffffULL
) +
785 env
->mxccdata
[3] = ldq_phys(cs
->as
,
786 (env
->mxccregs
[0] & 0xffffffffULL
) +
789 case 0x01c00200: /* MXCC stream destination */
791 env
->mxccregs
[1] = val
;
793 qemu_log_mask(LOG_UNIMP
,
794 "%08x: unimplemented access size: %d\n", addr
,
797 stq_phys(cs
->as
, (env
->mxccregs
[1] & 0xffffffffULL
) + 0,
799 stq_phys(cs
->as
, (env
->mxccregs
[1] & 0xffffffffULL
) + 8,
801 stq_phys(cs
->as
, (env
->mxccregs
[1] & 0xffffffffULL
) + 16,
803 stq_phys(cs
->as
, (env
->mxccregs
[1] & 0xffffffffULL
) + 24,
806 case 0x01c00a00: /* MXCC control register */
808 env
->mxccregs
[3] = val
;
810 qemu_log_mask(LOG_UNIMP
,
811 "%08x: unimplemented access size: %d\n", addr
,
815 case 0x01c00a04: /* MXCC control register */
817 env
->mxccregs
[3] = (env
->mxccregs
[3] & 0xffffffff00000000ULL
)
820 qemu_log_mask(LOG_UNIMP
,
821 "%08x: unimplemented access size: %d\n", addr
,
825 case 0x01c00e00: /* MXCC error register */
826 /* writing a 1 bit clears the error */
828 env
->mxccregs
[6] &= ~val
;
830 qemu_log_mask(LOG_UNIMP
,
831 "%08x: unimplemented access size: %d\n", addr
,
835 case 0x01c00f00: /* MBus port address register */
837 env
->mxccregs
[7] = val
;
839 qemu_log_mask(LOG_UNIMP
,
840 "%08x: unimplemented access size: %d\n", addr
,
845 qemu_log_mask(LOG_UNIMP
,
846 "%08x: unimplemented address, size: %d\n", addr
,
850 DPRINTF_MXCC("asi = %d, size = %d, addr = %08x, val = %" PRIx64
"\n",
851 asi
, size
, addr
, val
);
856 case 3: /* MMU flush */
857 case 0x18: /* LEON3 MMU flush */
861 mmulev
= (addr
>> 8) & 15;
862 DPRINTF_MMU("mmu flush level %d\n", mmulev
);
864 case 0: /* flush page */
865 tlb_flush_page(CPU(cpu
), addr
& 0xfffff000);
867 case 1: /* flush segment (256k) */
868 case 2: /* flush region (16M) */
869 case 3: /* flush context (4G) */
870 case 4: /* flush entire */
871 tlb_flush(CPU(cpu
), 1);
877 dump_mmu(stdout
, fprintf
, env
);
881 case 4: /* write MMU regs */
882 case 0x19: /* LEON3 write MMU regs */
884 int reg
= (addr
>> 8) & 0x1f;
887 oldreg
= env
->mmuregs
[reg
];
889 case 0: /* Control Register */
890 env
->mmuregs
[reg
] = (env
->mmuregs
[reg
] & 0xff000000) |
892 /* Mappings generated during no-fault mode or MMU
893 disabled mode are invalid in normal mode */
894 if ((oldreg
& (MMU_E
| MMU_NF
| env
->def
->mmu_bm
)) !=
895 (env
->mmuregs
[reg
] & (MMU_E
| MMU_NF
| env
->def
->mmu_bm
))) {
896 tlb_flush(CPU(cpu
), 1);
899 case 1: /* Context Table Pointer Register */
900 env
->mmuregs
[reg
] = val
& env
->def
->mmu_ctpr_mask
;
902 case 2: /* Context Register */
903 env
->mmuregs
[reg
] = val
& env
->def
->mmu_cxr_mask
;
904 if (oldreg
!= env
->mmuregs
[reg
]) {
905 /* we flush when the MMU context changes because
906 QEMU has no MMU context support */
907 tlb_flush(CPU(cpu
), 1);
910 case 3: /* Synchronous Fault Status Register with Clear */
911 case 4: /* Synchronous Fault Address Register */
913 case 0x10: /* TLB Replacement Control Register */
914 env
->mmuregs
[reg
] = val
& env
->def
->mmu_trcr_mask
;
916 case 0x13: /* Synchronous Fault Status Register with Read
918 env
->mmuregs
[3] = val
& env
->def
->mmu_sfsr_mask
;
920 case 0x14: /* Synchronous Fault Address Register */
921 env
->mmuregs
[4] = val
;
924 env
->mmuregs
[reg
] = val
;
927 if (oldreg
!= env
->mmuregs
[reg
]) {
928 DPRINTF_MMU("mmu change reg[%d]: 0x%08x -> 0x%08x\n",
929 reg
, oldreg
, env
->mmuregs
[reg
]);
932 dump_mmu(stdout
, fprintf
, env
);
936 case 5: /* Turbosparc ITLB Diagnostic */
937 case 6: /* Turbosparc DTLB Diagnostic */
938 case 7: /* Turbosparc IOTLB Diagnostic */
940 case 0xa: /* User data access */
943 cpu_stb_user(env
, addr
, val
);
946 cpu_stw_user(env
, addr
, val
);
950 cpu_stl_user(env
, addr
, val
);
953 cpu_stq_user(env
, addr
, val
);
957 case 0xb: /* Supervisor data access */
961 cpu_stb_kernel(env
, addr
, val
);
964 cpu_stw_kernel(env
, addr
, val
);
968 cpu_stl_kernel(env
, addr
, val
);
971 cpu_stq_kernel(env
, addr
, val
);
975 case 0xc: /* I-cache tag */
976 case 0xd: /* I-cache data */
977 case 0xe: /* D-cache tag */
978 case 0xf: /* D-cache data */
979 case 0x10: /* I/D-cache flush page */
980 case 0x11: /* I/D-cache flush segment */
981 case 0x12: /* I/D-cache flush region */
982 case 0x13: /* I/D-cache flush context */
983 case 0x14: /* I/D-cache flush user */
985 case 0x17: /* Block copy, sta access */
991 uint32_t src
= val
& ~3, dst
= addr
& ~3, temp
;
993 for (i
= 0; i
< 32; i
+= 4, src
+= 4, dst
+= 4) {
994 temp
= cpu_ldl_kernel(env
, src
);
995 cpu_stl_kernel(env
, dst
, temp
);
999 case 0x1f: /* Block fill, stda access */
1002 fill 32 bytes with val */
1004 uint32_t dst
= addr
& 7;
1006 for (i
= 0; i
< 32; i
+= 8, dst
+= 8) {
1007 cpu_stq_kernel(env
, dst
, val
);
1011 case 0x20: /* MMU passthrough */
1012 case 0x1c: /* LEON MMU passthrough */
1016 stb_phys(cs
->as
, addr
, val
);
1019 stw_phys(cs
->as
, addr
, val
);
1023 stl_phys(cs
->as
, addr
, val
);
1026 stq_phys(cs
->as
, addr
, val
);
1031 case 0x21 ... 0x2f: /* MMU passthrough, 0x100000000 to 0xfffffffff */
1035 stb_phys(cs
->as
, (hwaddr
)addr
1036 | ((hwaddr
)(asi
& 0xf) << 32), val
);
1039 stw_phys(cs
->as
, (hwaddr
)addr
1040 | ((hwaddr
)(asi
& 0xf) << 32), val
);
1044 stl_phys(cs
->as
, (hwaddr
)addr
1045 | ((hwaddr
)(asi
& 0xf) << 32), val
);
1048 stq_phys(cs
->as
, (hwaddr
)addr
1049 | ((hwaddr
)(asi
& 0xf) << 32), val
);
1054 case 0x30: /* store buffer tags or Turbosparc secondary cache diagnostic */
1055 case 0x31: /* store buffer data, Ross RT620 I-cache flush or
1056 Turbosparc snoop RAM */
1057 case 0x32: /* store buffer control or Turbosparc page table
1058 descriptor diagnostic */
1059 case 0x36: /* I-cache flash clear */
1060 case 0x37: /* D-cache flash clear */
1062 case 0x38: /* SuperSPARC MMU Breakpoint Control Registers*/
1064 int reg
= (addr
>> 8) & 3;
1067 case 0: /* Breakpoint Value (Addr) */
1068 env
->mmubpregs
[reg
] = (val
& 0xfffffffffULL
);
1070 case 1: /* Breakpoint Mask */
1071 env
->mmubpregs
[reg
] = (val
& 0xfffffffffULL
);
1073 case 2: /* Breakpoint Control */
1074 env
->mmubpregs
[reg
] = (val
& 0x7fULL
);
1076 case 3: /* Breakpoint Status */
1077 env
->mmubpregs
[reg
] = (val
& 0xfULL
);
1080 DPRINTF_MMU("write breakpoint reg[%d] 0x%016x\n", reg
,
1084 case 0x49: /* SuperSPARC MMU Counter Breakpoint Value */
1085 env
->mmubpctrv
= val
& 0xffffffff;
1087 case 0x4a: /* SuperSPARC MMU Counter Breakpoint Control */
1088 env
->mmubpctrc
= val
& 0x3;
1090 case 0x4b: /* SuperSPARC MMU Counter Breakpoint Status */
1091 env
->mmubpctrs
= val
& 0x3;
1093 case 0x4c: /* SuperSPARC MMU Breakpoint Action */
1094 env
->mmubpaction
= val
& 0x1fff;
1096 case 8: /* User code access, XXX */
1097 case 9: /* Supervisor code access, XXX */
1099 cpu_unassigned_access(CPU(sparc_env_get_cpu(env
)),
1100 addr
, true, false, asi
, size
);
1104 dump_asi("write", addr
, asi
, size
, val
);
1108 #endif /* CONFIG_USER_ONLY */
1109 #else /* TARGET_SPARC64 */
1111 #ifdef CONFIG_USER_ONLY
1112 uint64_t helper_ld_asi(CPUSPARCState
*env
, target_ulong addr
, int asi
, int size
,
1116 #if defined(DEBUG_ASI)
1117 target_ulong last_addr
= addr
;
1121 helper_raise_exception(env
, TT_PRIV_ACT
);
1124 helper_check_align(env
, addr
, size
- 1);
1125 addr
= asi_address_mask(env
, asi
, addr
);
1128 case 0x82: /* Primary no-fault */
1129 case 0x8a: /* Primary no-fault LE */
1130 if (page_check_range(addr
, size
, PAGE_READ
) == -1) {
1132 dump_asi("read ", last_addr
, asi
, size
, ret
);
1137 case 0x80: /* Primary */
1138 case 0x88: /* Primary LE */
1142 ret
= ldub_raw(addr
);
1145 ret
= lduw_raw(addr
);
1148 ret
= ldl_raw(addr
);
1152 ret
= ldq_raw(addr
);
1157 case 0x83: /* Secondary no-fault */
1158 case 0x8b: /* Secondary no-fault LE */
1159 if (page_check_range(addr
, size
, PAGE_READ
) == -1) {
1161 dump_asi("read ", last_addr
, asi
, size
, ret
);
1166 case 0x81: /* Secondary */
1167 case 0x89: /* Secondary LE */
1174 /* Convert from little endian */
1176 case 0x88: /* Primary LE */
1177 case 0x89: /* Secondary LE */
1178 case 0x8a: /* Primary no-fault LE */
1179 case 0x8b: /* Secondary no-fault LE */
1197 /* Convert to signed number */
1204 ret
= (int16_t) ret
;
1207 ret
= (int32_t) ret
;
1214 dump_asi("read ", last_addr
, asi
, size
, ret
);
1219 void helper_st_asi(CPUSPARCState
*env
, target_ulong addr
, target_ulong val
,
1223 dump_asi("write", addr
, asi
, size
, val
);
1226 helper_raise_exception(env
, TT_PRIV_ACT
);
1229 helper_check_align(env
, addr
, size
- 1);
1230 addr
= asi_address_mask(env
, asi
, addr
);
1232 /* Convert to little endian */
1234 case 0x88: /* Primary LE */
1235 case 0x89: /* Secondary LE */
1254 case 0x80: /* Primary */
1255 case 0x88: /* Primary LE */
1274 case 0x81: /* Secondary */
1275 case 0x89: /* Secondary LE */
1279 case 0x82: /* Primary no-fault, RO */
1280 case 0x83: /* Secondary no-fault, RO */
1281 case 0x8a: /* Primary no-fault LE, RO */
1282 case 0x8b: /* Secondary no-fault LE, RO */
1284 helper_raise_exception(env
, TT_DATA_ACCESS
);
1289 #else /* CONFIG_USER_ONLY */
1291 uint64_t helper_ld_asi(CPUSPARCState
*env
, target_ulong addr
, int asi
, int size
,
1294 CPUState
*cs
= CPU(sparc_env_get_cpu(env
));
1296 #if defined(DEBUG_ASI)
1297 target_ulong last_addr
= addr
;
1302 if ((asi
< 0x80 && (env
->pstate
& PS_PRIV
) == 0)
1303 || (cpu_has_hypervisor(env
)
1304 && asi
>= 0x30 && asi
< 0x80
1305 && !(env
->hpstate
& HS_PRIV
))) {
1306 helper_raise_exception(env
, TT_PRIV_ACT
);
1309 helper_check_align(env
, addr
, size
- 1);
1310 addr
= asi_address_mask(env
, asi
, addr
);
1312 /* process nonfaulting loads first */
1313 if ((asi
& 0xf6) == 0x82) {
1316 /* secondary space access has lowest asi bit equal to 1 */
1317 if (env
->pstate
& PS_PRIV
) {
1318 mmu_idx
= (asi
& 1) ? MMU_KERNEL_SECONDARY_IDX
: MMU_KERNEL_IDX
;
1320 mmu_idx
= (asi
& 1) ? MMU_USER_SECONDARY_IDX
: MMU_USER_IDX
;
1323 if (cpu_get_phys_page_nofault(env
, addr
, mmu_idx
) == -1ULL) {
1325 dump_asi("read ", last_addr
, asi
, size
, ret
);
1327 /* env->exception_index is set in get_physical_address_data(). */
1328 helper_raise_exception(env
, cs
->exception_index
);
1331 /* convert nonfaulting load ASIs to normal load ASIs */
1336 case 0x10: /* As if user primary */
1337 case 0x11: /* As if user secondary */
1338 case 0x18: /* As if user primary LE */
1339 case 0x19: /* As if user secondary LE */
1340 case 0x80: /* Primary */
1341 case 0x81: /* Secondary */
1342 case 0x88: /* Primary LE */
1343 case 0x89: /* Secondary LE */
1344 case 0xe2: /* UA2007 Primary block init */
1345 case 0xe3: /* UA2007 Secondary block init */
1346 if ((asi
& 0x80) && (env
->pstate
& PS_PRIV
)) {
1347 if (cpu_hypervisor_mode(env
)) {
1350 ret
= cpu_ldub_hypv(env
, addr
);
1353 ret
= cpu_lduw_hypv(env
, addr
);
1356 ret
= cpu_ldl_hypv(env
, addr
);
1360 ret
= cpu_ldq_hypv(env
, addr
);
1364 /* secondary space access has lowest asi bit equal to 1 */
1368 ret
= cpu_ldub_kernel_secondary(env
, addr
);
1371 ret
= cpu_lduw_kernel_secondary(env
, addr
);
1374 ret
= cpu_ldl_kernel_secondary(env
, addr
);
1378 ret
= cpu_ldq_kernel_secondary(env
, addr
);
1384 ret
= cpu_ldub_kernel(env
, addr
);
1387 ret
= cpu_lduw_kernel(env
, addr
);
1390 ret
= cpu_ldl_kernel(env
, addr
);
1394 ret
= cpu_ldq_kernel(env
, addr
);
1400 /* secondary space access has lowest asi bit equal to 1 */
1404 ret
= cpu_ldub_user_secondary(env
, addr
);
1407 ret
= cpu_lduw_user_secondary(env
, addr
);
1410 ret
= cpu_ldl_user_secondary(env
, addr
);
1414 ret
= cpu_ldq_user_secondary(env
, addr
);
1420 ret
= cpu_ldub_user(env
, addr
);
1423 ret
= cpu_lduw_user(env
, addr
);
1426 ret
= cpu_ldl_user(env
, addr
);
1430 ret
= cpu_ldq_user(env
, addr
);
1436 case 0x14: /* Bypass */
1437 case 0x15: /* Bypass, non-cacheable */
1438 case 0x1c: /* Bypass LE */
1439 case 0x1d: /* Bypass, non-cacheable LE */
1443 ret
= ldub_phys(cs
->as
, addr
);
1446 ret
= lduw_phys(cs
->as
, addr
);
1449 ret
= ldl_phys(cs
->as
, addr
);
1453 ret
= ldq_phys(cs
->as
, addr
);
1458 case 0x24: /* Nucleus quad LDD 128 bit atomic */
1459 case 0x2c: /* Nucleus quad LDD 128 bit atomic LE
1460 Only ldda allowed */
1461 helper_raise_exception(env
, TT_ILL_INSN
);
1463 case 0x04: /* Nucleus */
1464 case 0x0c: /* Nucleus Little Endian (LE) */
1468 ret
= cpu_ldub_nucleus(env
, addr
);
1471 ret
= cpu_lduw_nucleus(env
, addr
);
1474 ret
= cpu_ldl_nucleus(env
, addr
);
1478 ret
= cpu_ldq_nucleus(env
, addr
);
1483 case 0x4a: /* UPA config */
1486 case 0x45: /* LSU */
1489 case 0x50: /* I-MMU regs */
1491 int reg
= (addr
>> 3) & 0xf;
1494 /* I-TSB Tag Target register */
1495 ret
= ultrasparc_tag_target(env
->immu
.tag_access
);
1497 ret
= env
->immuregs
[reg
];
1502 case 0x51: /* I-MMU 8k TSB pointer */
1504 /* env->immuregs[5] holds I-MMU TSB register value
1505 env->immuregs[6] holds I-MMU Tag Access register value */
1506 ret
= ultrasparc_tsb_pointer(env
->immu
.tsb
, env
->immu
.tag_access
,
1510 case 0x52: /* I-MMU 64k TSB pointer */
1512 /* env->immuregs[5] holds I-MMU TSB register value
1513 env->immuregs[6] holds I-MMU Tag Access register value */
1514 ret
= ultrasparc_tsb_pointer(env
->immu
.tsb
, env
->immu
.tag_access
,
1518 case 0x55: /* I-MMU data access */
1520 int reg
= (addr
>> 3) & 0x3f;
1522 ret
= env
->itlb
[reg
].tte
;
1525 case 0x56: /* I-MMU tag read */
1527 int reg
= (addr
>> 3) & 0x3f;
1529 ret
= env
->itlb
[reg
].tag
;
1532 case 0x58: /* D-MMU regs */
1534 int reg
= (addr
>> 3) & 0xf;
1537 /* D-TSB Tag Target register */
1538 ret
= ultrasparc_tag_target(env
->dmmu
.tag_access
);
1540 ret
= env
->dmmuregs
[reg
];
1544 case 0x59: /* D-MMU 8k TSB pointer */
1546 /* env->dmmuregs[5] holds D-MMU TSB register value
1547 env->dmmuregs[6] holds D-MMU Tag Access register value */
1548 ret
= ultrasparc_tsb_pointer(env
->dmmu
.tsb
, env
->dmmu
.tag_access
,
1552 case 0x5a: /* D-MMU 64k TSB pointer */
1554 /* env->dmmuregs[5] holds D-MMU TSB register value
1555 env->dmmuregs[6] holds D-MMU Tag Access register value */
1556 ret
= ultrasparc_tsb_pointer(env
->dmmu
.tsb
, env
->dmmu
.tag_access
,
1560 case 0x5d: /* D-MMU data access */
1562 int reg
= (addr
>> 3) & 0x3f;
1564 ret
= env
->dtlb
[reg
].tte
;
1567 case 0x5e: /* D-MMU tag read */
1569 int reg
= (addr
>> 3) & 0x3f;
1571 ret
= env
->dtlb
[reg
].tag
;
1574 case 0x48: /* Interrupt dispatch, RO */
1576 case 0x49: /* Interrupt data receive */
1577 ret
= env
->ivec_status
;
1579 case 0x7f: /* Incoming interrupt vector, RO */
1581 int reg
= (addr
>> 4) & 0x3;
1583 ret
= env
->ivec_data
[reg
];
1587 case 0x46: /* D-cache data */
1588 case 0x47: /* D-cache tag access */
1589 case 0x4b: /* E-cache error enable */
1590 case 0x4c: /* E-cache asynchronous fault status */
1591 case 0x4d: /* E-cache asynchronous fault address */
1592 case 0x4e: /* E-cache tag data */
1593 case 0x66: /* I-cache instruction access */
1594 case 0x67: /* I-cache tag access */
1595 case 0x6e: /* I-cache predecode */
1596 case 0x6f: /* I-cache LRU etc. */
1597 case 0x76: /* E-cache tag */
1598 case 0x7e: /* E-cache tag */
1600 case 0x5b: /* D-MMU data pointer */
1601 case 0x54: /* I-MMU data in, WO */
1602 case 0x57: /* I-MMU demap, WO */
1603 case 0x5c: /* D-MMU data in, WO */
1604 case 0x5f: /* D-MMU demap, WO */
1605 case 0x77: /* Interrupt vector, WO */
1607 cpu_unassigned_access(cs
, addr
, false, false, 1, size
);
1612 /* Convert from little endian */
1614 case 0x0c: /* Nucleus Little Endian (LE) */
1615 case 0x18: /* As if user primary LE */
1616 case 0x19: /* As if user secondary LE */
1617 case 0x1c: /* Bypass LE */
1618 case 0x1d: /* Bypass, non-cacheable LE */
1619 case 0x88: /* Primary LE */
1620 case 0x89: /* Secondary LE */
1638 /* Convert to signed number */
1645 ret
= (int16_t) ret
;
1648 ret
= (int32_t) ret
;
1655 dump_asi("read ", last_addr
, asi
, size
, ret
);
1660 void helper_st_asi(CPUSPARCState
*env
, target_ulong addr
, target_ulong val
,
1663 SPARCCPU
*cpu
= sparc_env_get_cpu(env
);
1664 CPUState
*cs
= CPU(cpu
);
1667 dump_asi("write", addr
, asi
, size
, val
);
1672 if ((asi
< 0x80 && (env
->pstate
& PS_PRIV
) == 0)
1673 || (cpu_has_hypervisor(env
)
1674 && asi
>= 0x30 && asi
< 0x80
1675 && !(env
->hpstate
& HS_PRIV
))) {
1676 helper_raise_exception(env
, TT_PRIV_ACT
);
1679 helper_check_align(env
, addr
, size
- 1);
1680 addr
= asi_address_mask(env
, asi
, addr
);
1682 /* Convert to little endian */
1684 case 0x0c: /* Nucleus Little Endian (LE) */
1685 case 0x18: /* As if user primary LE */
1686 case 0x19: /* As if user secondary LE */
1687 case 0x1c: /* Bypass LE */
1688 case 0x1d: /* Bypass, non-cacheable LE */
1689 case 0x88: /* Primary LE */
1690 case 0x89: /* Secondary LE */
1709 case 0x10: /* As if user primary */
1710 case 0x11: /* As if user secondary */
1711 case 0x18: /* As if user primary LE */
1712 case 0x19: /* As if user secondary LE */
1713 case 0x80: /* Primary */
1714 case 0x81: /* Secondary */
1715 case 0x88: /* Primary LE */
1716 case 0x89: /* Secondary LE */
1717 case 0xe2: /* UA2007 Primary block init */
1718 case 0xe3: /* UA2007 Secondary block init */
1719 if ((asi
& 0x80) && (env
->pstate
& PS_PRIV
)) {
1720 if (cpu_hypervisor_mode(env
)) {
1723 cpu_stb_hypv(env
, addr
, val
);
1726 cpu_stw_hypv(env
, addr
, val
);
1729 cpu_stl_hypv(env
, addr
, val
);
1733 cpu_stq_hypv(env
, addr
, val
);
1737 /* secondary space access has lowest asi bit equal to 1 */
1741 cpu_stb_kernel_secondary(env
, addr
, val
);
1744 cpu_stw_kernel_secondary(env
, addr
, val
);
1747 cpu_stl_kernel_secondary(env
, addr
, val
);
1751 cpu_stq_kernel_secondary(env
, addr
, val
);
1757 cpu_stb_kernel(env
, addr
, val
);
1760 cpu_stw_kernel(env
, addr
, val
);
1763 cpu_stl_kernel(env
, addr
, val
);
1767 cpu_stq_kernel(env
, addr
, val
);
1773 /* secondary space access has lowest asi bit equal to 1 */
1777 cpu_stb_user_secondary(env
, addr
, val
);
1780 cpu_stw_user_secondary(env
, addr
, val
);
1783 cpu_stl_user_secondary(env
, addr
, val
);
1787 cpu_stq_user_secondary(env
, addr
, val
);
1793 cpu_stb_user(env
, addr
, val
);
1796 cpu_stw_user(env
, addr
, val
);
1799 cpu_stl_user(env
, addr
, val
);
1803 cpu_stq_user(env
, addr
, val
);
1809 case 0x14: /* Bypass */
1810 case 0x15: /* Bypass, non-cacheable */
1811 case 0x1c: /* Bypass LE */
1812 case 0x1d: /* Bypass, non-cacheable LE */
1816 stb_phys(cs
->as
, addr
, val
);
1819 stw_phys(cs
->as
, addr
, val
);
1822 stl_phys(cs
->as
, addr
, val
);
1826 stq_phys(cs
->as
, addr
, val
);
1831 case 0x24: /* Nucleus quad LDD 128 bit atomic */
1832 case 0x2c: /* Nucleus quad LDD 128 bit atomic LE
1833 Only ldda allowed */
1834 helper_raise_exception(env
, TT_ILL_INSN
);
1836 case 0x04: /* Nucleus */
1837 case 0x0c: /* Nucleus Little Endian (LE) */
1841 cpu_stb_nucleus(env
, addr
, val
);
1844 cpu_stw_nucleus(env
, addr
, val
);
1847 cpu_stl_nucleus(env
, addr
, val
);
1851 cpu_stq_nucleus(env
, addr
, val
);
1857 case 0x4a: /* UPA config */
1860 case 0x45: /* LSU */
1865 env
->lsu
= val
& (DMMU_E
| IMMU_E
);
1866 /* Mappings generated during D/I MMU disabled mode are
1867 invalid in normal mode */
1868 if (oldreg
!= env
->lsu
) {
1869 DPRINTF_MMU("LSU change: 0x%" PRIx64
" -> 0x%" PRIx64
"\n",
1872 dump_mmu(stdout
, fprintf
, env
);
1874 tlb_flush(CPU(cpu
), 1);
1878 case 0x50: /* I-MMU regs */
1880 int reg
= (addr
>> 3) & 0xf;
1883 oldreg
= env
->immuregs
[reg
];
1887 case 1: /* Not in I-MMU */
1891 if ((val
& 1) == 0) {
1892 val
= 0; /* Clear SFSR */
1894 env
->immu
.sfsr
= val
;
1898 case 5: /* TSB access */
1899 DPRINTF_MMU("immu TSB write: 0x%016" PRIx64
" -> 0x%016"
1900 PRIx64
"\n", env
->immu
.tsb
, val
);
1901 env
->immu
.tsb
= val
;
1903 case 6: /* Tag access */
1904 env
->immu
.tag_access
= val
;
1913 if (oldreg
!= env
->immuregs
[reg
]) {
1914 DPRINTF_MMU("immu change reg[%d]: 0x%016" PRIx64
" -> 0x%016"
1915 PRIx64
"\n", reg
, oldreg
, env
->immuregs
[reg
]);
1918 dump_mmu(stdout
, fprintf
, env
);
1922 case 0x54: /* I-MMU data in */
1923 replace_tlb_1bit_lru(env
->itlb
, env
->immu
.tag_access
, val
, "immu", env
);
1925 case 0x55: /* I-MMU data access */
1927 /* TODO: auto demap */
1929 unsigned int i
= (addr
>> 3) & 0x3f;
1931 replace_tlb_entry(&env
->itlb
[i
], env
->immu
.tag_access
, val
, env
);
1934 DPRINTF_MMU("immu data access replaced entry [%i]\n", i
);
1935 dump_mmu(stdout
, fprintf
, env
);
1939 case 0x57: /* I-MMU demap */
1940 demap_tlb(env
->itlb
, addr
, "immu", env
);
1942 case 0x58: /* D-MMU regs */
1944 int reg
= (addr
>> 3) & 0xf;
1947 oldreg
= env
->dmmuregs
[reg
];
1953 if ((val
& 1) == 0) {
1954 val
= 0; /* Clear SFSR, Fault address */
1957 env
->dmmu
.sfsr
= val
;
1959 case 1: /* Primary context */
1960 env
->dmmu
.mmu_primary_context
= val
;
1961 /* can be optimized to only flush MMU_USER_IDX
1962 and MMU_KERNEL_IDX entries */
1963 tlb_flush(CPU(cpu
), 1);
1965 case 2: /* Secondary context */
1966 env
->dmmu
.mmu_secondary_context
= val
;
1967 /* can be optimized to only flush MMU_USER_SECONDARY_IDX
1968 and MMU_KERNEL_SECONDARY_IDX entries */
1969 tlb_flush(CPU(cpu
), 1);
1971 case 5: /* TSB access */
1972 DPRINTF_MMU("dmmu TSB write: 0x%016" PRIx64
" -> 0x%016"
1973 PRIx64
"\n", env
->dmmu
.tsb
, val
);
1974 env
->dmmu
.tsb
= val
;
1976 case 6: /* Tag access */
1977 env
->dmmu
.tag_access
= val
;
1979 case 7: /* Virtual Watchpoint */
1980 case 8: /* Physical Watchpoint */
1982 env
->dmmuregs
[reg
] = val
;
1986 if (oldreg
!= env
->dmmuregs
[reg
]) {
1987 DPRINTF_MMU("dmmu change reg[%d]: 0x%016" PRIx64
" -> 0x%016"
1988 PRIx64
"\n", reg
, oldreg
, env
->dmmuregs
[reg
]);
1991 dump_mmu(stdout
, fprintf
, env
);
1995 case 0x5c: /* D-MMU data in */
1996 replace_tlb_1bit_lru(env
->dtlb
, env
->dmmu
.tag_access
, val
, "dmmu", env
);
1998 case 0x5d: /* D-MMU data access */
2000 unsigned int i
= (addr
>> 3) & 0x3f;
2002 replace_tlb_entry(&env
->dtlb
[i
], env
->dmmu
.tag_access
, val
, env
);
2005 DPRINTF_MMU("dmmu data access replaced entry [%i]\n", i
);
2006 dump_mmu(stdout
, fprintf
, env
);
2010 case 0x5f: /* D-MMU demap */
2011 demap_tlb(env
->dtlb
, addr
, "dmmu", env
);
2013 case 0x49: /* Interrupt data receive */
2014 env
->ivec_status
= val
& 0x20;
2016 case 0x46: /* D-cache data */
2017 case 0x47: /* D-cache tag access */
2018 case 0x4b: /* E-cache error enable */
2019 case 0x4c: /* E-cache asynchronous fault status */
2020 case 0x4d: /* E-cache asynchronous fault address */
2021 case 0x4e: /* E-cache tag data */
2022 case 0x66: /* I-cache instruction access */
2023 case 0x67: /* I-cache tag access */
2024 case 0x6e: /* I-cache predecode */
2025 case 0x6f: /* I-cache LRU etc. */
2026 case 0x76: /* E-cache tag */
2027 case 0x7e: /* E-cache tag */
2029 case 0x51: /* I-MMU 8k TSB pointer, RO */
2030 case 0x52: /* I-MMU 64k TSB pointer, RO */
2031 case 0x56: /* I-MMU tag read, RO */
2032 case 0x59: /* D-MMU 8k TSB pointer, RO */
2033 case 0x5a: /* D-MMU 64k TSB pointer, RO */
2034 case 0x5b: /* D-MMU data pointer, RO */
2035 case 0x5e: /* D-MMU tag read, RO */
2036 case 0x48: /* Interrupt dispatch, RO */
2037 case 0x7f: /* Incoming interrupt vector, RO */
2038 case 0x82: /* Primary no-fault, RO */
2039 case 0x83: /* Secondary no-fault, RO */
2040 case 0x8a: /* Primary no-fault LE, RO */
2041 case 0x8b: /* Secondary no-fault LE, RO */
2043 cpu_unassigned_access(cs
, addr
, true, false, 1, size
);
2047 #endif /* CONFIG_USER_ONLY */
2049 void helper_ldda_asi(CPUSPARCState
*env
, target_ulong addr
, int asi
, int rd
)
2051 if ((asi
< 0x80 && (env
->pstate
& PS_PRIV
) == 0)
2052 || (cpu_has_hypervisor(env
)
2053 && asi
>= 0x30 && asi
< 0x80
2054 && !(env
->hpstate
& HS_PRIV
))) {
2055 helper_raise_exception(env
, TT_PRIV_ACT
);
2058 addr
= asi_address_mask(env
, asi
, addr
);
2061 #if !defined(CONFIG_USER_ONLY)
2062 case 0x24: /* Nucleus quad LDD 128 bit atomic */
2063 case 0x2c: /* Nucleus quad LDD 128 bit atomic LE */
2064 helper_check_align(env
, addr
, 0xf);
2066 env
->gregs
[1] = cpu_ldq_nucleus(env
, addr
+ 8);
2068 bswap64s(&env
->gregs
[1]);
2070 } else if (rd
< 8) {
2071 env
->gregs
[rd
] = cpu_ldq_nucleus(env
, addr
);
2072 env
->gregs
[rd
+ 1] = cpu_ldq_nucleus(env
, addr
+ 8);
2074 bswap64s(&env
->gregs
[rd
]);
2075 bswap64s(&env
->gregs
[rd
+ 1]);
2078 env
->regwptr
[rd
] = cpu_ldq_nucleus(env
, addr
);
2079 env
->regwptr
[rd
+ 1] = cpu_ldq_nucleus(env
, addr
+ 8);
2081 bswap64s(&env
->regwptr
[rd
]);
2082 bswap64s(&env
->regwptr
[rd
+ 1]);
2088 helper_check_align(env
, addr
, 0x3);
2090 env
->gregs
[1] = helper_ld_asi(env
, addr
+ 4, asi
, 4, 0);
2091 } else if (rd
< 8) {
2092 env
->gregs
[rd
] = helper_ld_asi(env
, addr
, asi
, 4, 0);
2093 env
->gregs
[rd
+ 1] = helper_ld_asi(env
, addr
+ 4, asi
, 4, 0);
2095 env
->regwptr
[rd
] = helper_ld_asi(env
, addr
, asi
, 4, 0);
2096 env
->regwptr
[rd
+ 1] = helper_ld_asi(env
, addr
+ 4, asi
, 4, 0);
2102 void helper_ldf_asi(CPUSPARCState
*env
, target_ulong addr
, int asi
, int size
,
2108 helper_check_align(env
, addr
, 3);
2109 addr
= asi_address_mask(env
, asi
, addr
);
2112 case 0xf0: /* UA2007/JPS1 Block load primary */
2113 case 0xf1: /* UA2007/JPS1 Block load secondary */
2114 case 0xf8: /* UA2007/JPS1 Block load primary LE */
2115 case 0xf9: /* UA2007/JPS1 Block load secondary LE */
2117 helper_raise_exception(env
, TT_ILL_INSN
);
2120 helper_check_align(env
, addr
, 0x3f);
2121 for (i
= 0; i
< 8; i
++, rd
+= 2, addr
+= 8) {
2122 env
->fpr
[rd
/ 2].ll
= helper_ld_asi(env
, addr
, asi
& 0x8f, 8, 0);
2126 case 0x16: /* UA2007 Block load primary, user privilege */
2127 case 0x17: /* UA2007 Block load secondary, user privilege */
2128 case 0x1e: /* UA2007 Block load primary LE, user privilege */
2129 case 0x1f: /* UA2007 Block load secondary LE, user privilege */
2130 case 0x70: /* JPS1 Block load primary, user privilege */
2131 case 0x71: /* JPS1 Block load secondary, user privilege */
2132 case 0x78: /* JPS1 Block load primary LE, user privilege */
2133 case 0x79: /* JPS1 Block load secondary LE, user privilege */
2135 helper_raise_exception(env
, TT_ILL_INSN
);
2138 helper_check_align(env
, addr
, 0x3f);
2139 for (i
= 0; i
< 8; i
++, rd
+= 2, addr
+= 8) {
2140 env
->fpr
[rd
/ 2].ll
= helper_ld_asi(env
, addr
, asi
& 0x19, 8, 0);
2151 val
= helper_ld_asi(env
, addr
, asi
, size
, 0);
2153 env
->fpr
[rd
/ 2].l
.lower
= val
;
2155 env
->fpr
[rd
/ 2].l
.upper
= val
;
2159 env
->fpr
[rd
/ 2].ll
= helper_ld_asi(env
, addr
, asi
, size
, 0);
2162 env
->fpr
[rd
/ 2].ll
= helper_ld_asi(env
, addr
, asi
, 8, 0);
2163 env
->fpr
[rd
/ 2 + 1].ll
= helper_ld_asi(env
, addr
+ 8, asi
, 8, 0);
2168 void helper_stf_asi(CPUSPARCState
*env
, target_ulong addr
, int asi
, int size
,
2174 helper_check_align(env
, addr
, 3);
2175 addr
= asi_address_mask(env
, asi
, addr
);
2178 case 0xe0: /* UA2007/JPS1 Block commit store primary (cache flush) */
2179 case 0xe1: /* UA2007/JPS1 Block commit store secondary (cache flush) */
2180 case 0xf0: /* UA2007/JPS1 Block store primary */
2181 case 0xf1: /* UA2007/JPS1 Block store secondary */
2182 case 0xf8: /* UA2007/JPS1 Block store primary LE */
2183 case 0xf9: /* UA2007/JPS1 Block store secondary LE */
2185 helper_raise_exception(env
, TT_ILL_INSN
);
2188 helper_check_align(env
, addr
, 0x3f);
2189 for (i
= 0; i
< 8; i
++, rd
+= 2, addr
+= 8) {
2190 helper_st_asi(env
, addr
, env
->fpr
[rd
/ 2].ll
, asi
& 0x8f, 8);
2194 case 0x16: /* UA2007 Block load primary, user privilege */
2195 case 0x17: /* UA2007 Block load secondary, user privilege */
2196 case 0x1e: /* UA2007 Block load primary LE, user privilege */
2197 case 0x1f: /* UA2007 Block load secondary LE, user privilege */
2198 case 0x70: /* JPS1 Block store primary, user privilege */
2199 case 0x71: /* JPS1 Block store secondary, user privilege */
2200 case 0x78: /* JPS1 Block load primary LE, user privilege */
2201 case 0x79: /* JPS1 Block load secondary LE, user privilege */
2203 helper_raise_exception(env
, TT_ILL_INSN
);
2206 helper_check_align(env
, addr
, 0x3f);
2207 for (i
= 0; i
< 8; i
++, rd
+= 2, addr
+= 8) {
2208 helper_st_asi(env
, addr
, env
->fpr
[rd
/ 2].ll
, asi
& 0x19, 8);
2220 val
= env
->fpr
[rd
/ 2].l
.lower
;
2222 val
= env
->fpr
[rd
/ 2].l
.upper
;
2224 helper_st_asi(env
, addr
, val
, asi
, size
);
2227 helper_st_asi(env
, addr
, env
->fpr
[rd
/ 2].ll
, asi
, size
);
2230 helper_st_asi(env
, addr
, env
->fpr
[rd
/ 2].ll
, asi
, 8);
2231 helper_st_asi(env
, addr
+ 8, env
->fpr
[rd
/ 2 + 1].ll
, asi
, 8);
2236 target_ulong
helper_casx_asi(CPUSPARCState
*env
, target_ulong addr
,
2237 target_ulong val1
, target_ulong val2
,
2242 ret
= helper_ld_asi(env
, addr
, asi
, 8, 0);
2244 helper_st_asi(env
, addr
, val1
, asi
, 8);
2248 #endif /* TARGET_SPARC64 */
2250 #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
2251 target_ulong
helper_cas_asi(CPUSPARCState
*env
, target_ulong addr
,
2252 target_ulong val1
, target_ulong val2
, uint32_t asi
)
2256 val2
&= 0xffffffffUL
;
2257 ret
= helper_ld_asi(env
, addr
, asi
, 4, 0);
2258 ret
&= 0xffffffffUL
;
2260 helper_st_asi(env
, addr
, val1
& 0xffffffffUL
, asi
, 4);
2264 #endif /* !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64) */
2266 void helper_ldqf(CPUSPARCState
*env
, target_ulong addr
, int mem_idx
)
2268 /* XXX add 128 bit load */
2271 helper_check_align(env
, addr
, 7);
2272 #if !defined(CONFIG_USER_ONLY)
2275 u
.ll
.upper
= cpu_ldq_user(env
, addr
);
2276 u
.ll
.lower
= cpu_ldq_user(env
, addr
+ 8);
2279 case MMU_KERNEL_IDX
:
2280 u
.ll
.upper
= cpu_ldq_kernel(env
, addr
);
2281 u
.ll
.lower
= cpu_ldq_kernel(env
, addr
+ 8);
2284 #ifdef TARGET_SPARC64
2286 u
.ll
.upper
= cpu_ldq_hypv(env
, addr
);
2287 u
.ll
.lower
= cpu_ldq_hypv(env
, addr
+ 8);
2292 DPRINTF_MMU("helper_ldqf: need to check MMU idx %d\n", mem_idx
);
2296 u
.ll
.upper
= ldq_raw(address_mask(env
, addr
));
2297 u
.ll
.lower
= ldq_raw(address_mask(env
, addr
+ 8));
2302 void helper_stqf(CPUSPARCState
*env
, target_ulong addr
, int mem_idx
)
2304 /* XXX add 128 bit store */
2307 helper_check_align(env
, addr
, 7);
2308 #if !defined(CONFIG_USER_ONLY)
2312 cpu_stq_user(env
, addr
, u
.ll
.upper
);
2313 cpu_stq_user(env
, addr
+ 8, u
.ll
.lower
);
2315 case MMU_KERNEL_IDX
:
2317 cpu_stq_kernel(env
, addr
, u
.ll
.upper
);
2318 cpu_stq_kernel(env
, addr
+ 8, u
.ll
.lower
);
2320 #ifdef TARGET_SPARC64
2323 cpu_stq_hypv(env
, addr
, u
.ll
.upper
);
2324 cpu_stq_hypv(env
, addr
+ 8, u
.ll
.lower
);
2328 DPRINTF_MMU("helper_stqf: need to check MMU idx %d\n", mem_idx
);
2333 stq_raw(address_mask(env
, addr
), u
.ll
.upper
);
2334 stq_raw(address_mask(env
, addr
+ 8), u
.ll
.lower
);
2338 #if !defined(CONFIG_USER_ONLY)
2339 #ifndef TARGET_SPARC64
2340 void sparc_cpu_unassigned_access(CPUState
*cs
, hwaddr addr
,
2341 bool is_write
, bool is_exec
, int is_asi
,
2344 SPARCCPU
*cpu
= SPARC_CPU(cs
);
2345 CPUSPARCState
*env
= &cpu
->env
;
2348 #ifdef DEBUG_UNASSIGNED
2350 printf("Unassigned mem %s access of %d byte%s to " TARGET_FMT_plx
2351 " asi 0x%02x from " TARGET_FMT_lx
"\n",
2352 is_exec
? "exec" : is_write
? "write" : "read", size
,
2353 size
== 1 ? "" : "s", addr
, is_asi
, env
->pc
);
2355 printf("Unassigned mem %s access of %d byte%s to " TARGET_FMT_plx
2356 " from " TARGET_FMT_lx
"\n",
2357 is_exec
? "exec" : is_write
? "write" : "read", size
,
2358 size
== 1 ? "" : "s", addr
, env
->pc
);
2361 /* Don't overwrite translation and access faults */
2362 fault_type
= (env
->mmuregs
[3] & 0x1c) >> 2;
2363 if ((fault_type
> 4) || (fault_type
== 0)) {
2364 env
->mmuregs
[3] = 0; /* Fault status register */
2366 env
->mmuregs
[3] |= 1 << 16;
2369 env
->mmuregs
[3] |= 1 << 5;
2372 env
->mmuregs
[3] |= 1 << 6;
2375 env
->mmuregs
[3] |= 1 << 7;
2377 env
->mmuregs
[3] |= (5 << 2) | 2;
2378 /* SuperSPARC will never place instruction fault addresses in the FAR */
2380 env
->mmuregs
[4] = addr
; /* Fault address register */
2383 /* overflow (same type fault was not read before another fault) */
2384 if (fault_type
== ((env
->mmuregs
[3] & 0x1c)) >> 2) {
2385 env
->mmuregs
[3] |= 1;
2388 if ((env
->mmuregs
[0] & MMU_E
) && !(env
->mmuregs
[0] & MMU_NF
)) {
2390 helper_raise_exception(env
, TT_CODE_ACCESS
);
2392 helper_raise_exception(env
, TT_DATA_ACCESS
);
2396 /* flush neverland mappings created during no-fault mode,
2397 so the sequential MMU faults report proper fault types */
2398 if (env
->mmuregs
[0] & MMU_NF
) {
2403 void sparc_cpu_unassigned_access(CPUState
*cs
, hwaddr addr
,
2404 bool is_write
, bool is_exec
, int is_asi
,
2407 SPARCCPU
*cpu
= SPARC_CPU(cs
);
2408 CPUSPARCState
*env
= &cpu
->env
;
2410 #ifdef DEBUG_UNASSIGNED
2411 printf("Unassigned mem access to " TARGET_FMT_plx
" from " TARGET_FMT_lx
2412 "\n", addr
, env
->pc
);
2416 helper_raise_exception(env
, TT_CODE_ACCESS
);
2418 helper_raise_exception(env
, TT_DATA_ACCESS
);
2424 #if !defined(CONFIG_USER_ONLY)
2425 void QEMU_NORETURN
sparc_cpu_do_unaligned_access(CPUState
*cs
,
2426 vaddr addr
, int is_write
,
2427 int is_user
, uintptr_t retaddr
)
2429 SPARCCPU
*cpu
= SPARC_CPU(cs
);
2430 CPUSPARCState
*env
= &cpu
->env
;
2432 #ifdef DEBUG_UNALIGNED
2433 printf("Unaligned access to 0x" TARGET_FMT_lx
" from 0x" TARGET_FMT_lx
2434 "\n", addr
, env
->pc
);
2437 cpu_restore_state(CPU(cpu
), retaddr
);
2439 helper_raise_exception(env
, TT_UNALIGNED
);
2442 /* try to fill the TLB and return an exception if error. If retaddr is
2443 NULL, it means that the function was called in C code (i.e. not
2444 from generated code or from helper.c) */
2445 /* XXX: fix it to restore all registers */
2446 void tlb_fill(CPUState
*cs
, target_ulong addr
, int is_write
, int mmu_idx
,
2451 ret
= sparc_cpu_handle_mmu_fault(cs
, addr
, is_write
, mmu_idx
);
2454 cpu_restore_state(cs
, retaddr
);