2 * Copyright (c) 2007, Neocleus Corporation.
3 * Copyright (c) 2007, Intel Corporation.
5 * This work is licensed under the terms of the GNU GPL, version 2. See
6 * the COPYING file in the top-level directory.
8 * Alex Novik <alex@neocleus.com>
9 * Allen Kay <allen.m.kay@intel.com>
10 * Guy Zana <guy@neocleus.com>
12 * This file implements direct PCI assignment to a HVM guest
15 #include "qemu-timer.h"
16 #include "xen_backend.h"
19 #define XEN_PT_MERGE_VALUE(value, data, val_mask) \
20 (((value) & (val_mask)) | ((data) & ~(val_mask)))
22 #define XEN_PT_INVALID_REG 0xFFFFFFFF /* invalid register value */
26 static int xen_pt_ptr_reg_init(XenPCIPassthroughState
*s
, XenPTRegInfo
*reg
,
27 uint32_t real_offset
, uint32_t *data
);
32 /* A return value of 1 means the capability should NOT be exposed to guest. */
33 static int xen_pt_hide_dev_cap(const XenHostPCIDevice
*d
, uint8_t grp_id
)
37 /* The PCI Express Capability Structure of the VF of Intel 82599 10GbE
38 * Controller looks trivial, e.g., the PCI Express Capabilities
39 * Register is 0. We should not try to expose it to guest.
41 * The datasheet is available at
42 * http://download.intel.com/design/network/datashts/82599_datasheet.pdf
44 * See 'Table 9.7. VF PCIe Configuration Space' of the datasheet, the
45 * PCI Express Capability Structure of the VF of Intel 82599 10GbE
46 * Controller looks trivial, e.g., the PCI Express Capabilities
47 * Register is 0, so the Capability Version is 0 and
48 * xen_pt_pcie_size_init() would fail.
50 if (d
->vendor_id
== PCI_VENDOR_ID_INTEL
&&
51 d
->device_id
== PCI_DEVICE_ID_INTEL_82599_SFP_VF
) {
59 /* find emulate register group entry */
60 XenPTRegGroup
*xen_pt_find_reg_grp(XenPCIPassthroughState
*s
, uint32_t address
)
62 XenPTRegGroup
*entry
= NULL
;
64 /* find register group entry */
65 QLIST_FOREACH(entry
, &s
->reg_grps
, entries
) {
67 if ((entry
->base_offset
<= address
)
68 && ((entry
->base_offset
+ entry
->size
) > address
)) {
73 /* group entry not found */
77 /* find emulate register entry */
78 XenPTReg
*xen_pt_find_reg(XenPTRegGroup
*reg_grp
, uint32_t address
)
80 XenPTReg
*reg_entry
= NULL
;
81 XenPTRegInfo
*reg
= NULL
;
82 uint32_t real_offset
= 0;
84 /* find register entry */
85 QLIST_FOREACH(reg_entry
, ®_grp
->reg_tbl_list
, entries
) {
87 real_offset
= reg_grp
->base_offset
+ reg
->offset
;
89 if ((real_offset
<= address
)
90 && ((real_offset
+ reg
->size
) > address
)) {
100 * general register functions
103 /* register initialization function */
105 static int xen_pt_common_reg_init(XenPCIPassthroughState
*s
,
106 XenPTRegInfo
*reg
, uint32_t real_offset
,
109 *data
= reg
->init_val
;
113 /* Read register functions */
115 static int xen_pt_byte_reg_read(XenPCIPassthroughState
*s
, XenPTReg
*cfg_entry
,
116 uint8_t *value
, uint8_t valid_mask
)
118 XenPTRegInfo
*reg
= cfg_entry
->reg
;
119 uint8_t valid_emu_mask
= 0;
121 /* emulate byte register */
122 valid_emu_mask
= reg
->emu_mask
& valid_mask
;
123 *value
= XEN_PT_MERGE_VALUE(*value
, cfg_entry
->data
, ~valid_emu_mask
);
127 static int xen_pt_word_reg_read(XenPCIPassthroughState
*s
, XenPTReg
*cfg_entry
,
128 uint16_t *value
, uint16_t valid_mask
)
130 XenPTRegInfo
*reg
= cfg_entry
->reg
;
131 uint16_t valid_emu_mask
= 0;
133 /* emulate word register */
134 valid_emu_mask
= reg
->emu_mask
& valid_mask
;
135 *value
= XEN_PT_MERGE_VALUE(*value
, cfg_entry
->data
, ~valid_emu_mask
);
139 static int xen_pt_long_reg_read(XenPCIPassthroughState
*s
, XenPTReg
*cfg_entry
,
140 uint32_t *value
, uint32_t valid_mask
)
142 XenPTRegInfo
*reg
= cfg_entry
->reg
;
143 uint32_t valid_emu_mask
= 0;
145 /* emulate long register */
146 valid_emu_mask
= reg
->emu_mask
& valid_mask
;
147 *value
= XEN_PT_MERGE_VALUE(*value
, cfg_entry
->data
, ~valid_emu_mask
);
152 /* Write register functions */
154 static int xen_pt_byte_reg_write(XenPCIPassthroughState
*s
, XenPTReg
*cfg_entry
,
155 uint8_t *val
, uint8_t dev_value
,
158 XenPTRegInfo
*reg
= cfg_entry
->reg
;
159 uint8_t writable_mask
= 0;
160 uint8_t throughable_mask
= 0;
162 /* modify emulate register */
163 writable_mask
= reg
->emu_mask
& ~reg
->ro_mask
& valid_mask
;
164 cfg_entry
->data
= XEN_PT_MERGE_VALUE(*val
, cfg_entry
->data
, writable_mask
);
166 /* create value for writing to I/O device register */
167 throughable_mask
= ~reg
->emu_mask
& valid_mask
;
168 *val
= XEN_PT_MERGE_VALUE(*val
, dev_value
, throughable_mask
);
172 static int xen_pt_word_reg_write(XenPCIPassthroughState
*s
, XenPTReg
*cfg_entry
,
173 uint16_t *val
, uint16_t dev_value
,
176 XenPTRegInfo
*reg
= cfg_entry
->reg
;
177 uint16_t writable_mask
= 0;
178 uint16_t throughable_mask
= 0;
180 /* modify emulate register */
181 writable_mask
= reg
->emu_mask
& ~reg
->ro_mask
& valid_mask
;
182 cfg_entry
->data
= XEN_PT_MERGE_VALUE(*val
, cfg_entry
->data
, writable_mask
);
184 /* create value for writing to I/O device register */
185 throughable_mask
= ~reg
->emu_mask
& valid_mask
;
186 *val
= XEN_PT_MERGE_VALUE(*val
, dev_value
, throughable_mask
);
190 static int xen_pt_long_reg_write(XenPCIPassthroughState
*s
, XenPTReg
*cfg_entry
,
191 uint32_t *val
, uint32_t dev_value
,
194 XenPTRegInfo
*reg
= cfg_entry
->reg
;
195 uint32_t writable_mask
= 0;
196 uint32_t throughable_mask
= 0;
198 /* modify emulate register */
199 writable_mask
= reg
->emu_mask
& ~reg
->ro_mask
& valid_mask
;
200 cfg_entry
->data
= XEN_PT_MERGE_VALUE(*val
, cfg_entry
->data
, writable_mask
);
202 /* create value for writing to I/O device register */
203 throughable_mask
= ~reg
->emu_mask
& valid_mask
;
204 *val
= XEN_PT_MERGE_VALUE(*val
, dev_value
, throughable_mask
);
210 /* XenPTRegInfo declaration
211 * - only for emulated register (either a part or whole bit).
212 * - for passthrough register that need special behavior (like interacting with
213 * other component), set emu_mask to all 0 and specify r/w func properly.
214 * - do NOT use ALL F for init_val, otherwise the tbl will not be registered.
217 /********************
221 static int xen_pt_vendor_reg_init(XenPCIPassthroughState
*s
,
222 XenPTRegInfo
*reg
, uint32_t real_offset
,
225 *data
= s
->real_device
.vendor_id
;
228 static int xen_pt_device_reg_init(XenPCIPassthroughState
*s
,
229 XenPTRegInfo
*reg
, uint32_t real_offset
,
232 *data
= s
->real_device
.device_id
;
235 static int xen_pt_status_reg_init(XenPCIPassthroughState
*s
,
236 XenPTRegInfo
*reg
, uint32_t real_offset
,
239 XenPTRegGroup
*reg_grp_entry
= NULL
;
240 XenPTReg
*reg_entry
= NULL
;
241 uint32_t reg_field
= 0;
243 /* find Header register group */
244 reg_grp_entry
= xen_pt_find_reg_grp(s
, PCI_CAPABILITY_LIST
);
246 /* find Capabilities Pointer register */
247 reg_entry
= xen_pt_find_reg(reg_grp_entry
, PCI_CAPABILITY_LIST
);
249 /* check Capabilities Pointer register */
250 if (reg_entry
->data
) {
251 reg_field
|= PCI_STATUS_CAP_LIST
;
253 reg_field
&= ~PCI_STATUS_CAP_LIST
;
256 xen_shutdown_fatal_error("Internal error: Couldn't find XenPTReg*"
257 " for Capabilities Pointer register."
258 " (%s)\n", __func__
);
262 xen_shutdown_fatal_error("Internal error: Couldn't find XenPTRegGroup"
263 " for Header. (%s)\n", __func__
);
270 static int xen_pt_header_type_reg_init(XenPCIPassthroughState
*s
,
271 XenPTRegInfo
*reg
, uint32_t real_offset
,
274 /* read PCI_HEADER_TYPE */
275 *data
= reg
->init_val
| 0x80;
279 /* initialize Interrupt Pin register */
280 static int xen_pt_irqpin_reg_init(XenPCIPassthroughState
*s
,
281 XenPTRegInfo
*reg
, uint32_t real_offset
,
284 *data
= xen_pt_pci_read_intx(s
);
288 /* Command register */
289 static int xen_pt_cmd_reg_read(XenPCIPassthroughState
*s
, XenPTReg
*cfg_entry
,
290 uint16_t *value
, uint16_t valid_mask
)
292 XenPTRegInfo
*reg
= cfg_entry
->reg
;
293 uint16_t valid_emu_mask
= 0;
294 uint16_t emu_mask
= reg
->emu_mask
;
297 emu_mask
|= PCI_COMMAND_MEMORY
;
300 /* emulate word register */
301 valid_emu_mask
= emu_mask
& valid_mask
;
302 *value
= XEN_PT_MERGE_VALUE(*value
, cfg_entry
->data
, ~valid_emu_mask
);
306 static int xen_pt_cmd_reg_write(XenPCIPassthroughState
*s
, XenPTReg
*cfg_entry
,
307 uint16_t *val
, uint16_t dev_value
,
310 XenPTRegInfo
*reg
= cfg_entry
->reg
;
311 uint16_t writable_mask
= 0;
312 uint16_t throughable_mask
= 0;
313 uint16_t emu_mask
= reg
->emu_mask
;
316 emu_mask
|= PCI_COMMAND_MEMORY
;
319 /* modify emulate register */
320 writable_mask
= ~reg
->ro_mask
& valid_mask
;
321 cfg_entry
->data
= XEN_PT_MERGE_VALUE(*val
, cfg_entry
->data
, writable_mask
);
323 /* create value for writing to I/O device register */
324 throughable_mask
= ~emu_mask
& valid_mask
;
326 if (*val
& PCI_COMMAND_INTX_DISABLE
) {
327 throughable_mask
|= PCI_COMMAND_INTX_DISABLE
;
329 if (s
->machine_irq
) {
330 throughable_mask
|= PCI_COMMAND_INTX_DISABLE
;
334 *val
= XEN_PT_MERGE_VALUE(*val
, dev_value
, throughable_mask
);
340 #define XEN_PT_BAR_MEM_RO_MASK 0x0000000F /* BAR ReadOnly mask(Memory) */
341 #define XEN_PT_BAR_MEM_EMU_MASK 0xFFFFFFF0 /* BAR emul mask(Memory) */
342 #define XEN_PT_BAR_IO_RO_MASK 0x00000003 /* BAR ReadOnly mask(I/O) */
343 #define XEN_PT_BAR_IO_EMU_MASK 0xFFFFFFFC /* BAR emul mask(I/O) */
345 static XenPTBarFlag
xen_pt_bar_reg_parse(XenPCIPassthroughState
*s
,
348 PCIDevice
*d
= &s
->dev
;
349 XenPTRegion
*region
= NULL
;
353 /* check 64bit BAR */
354 index
= xen_pt_bar_offset_to_index(reg
->offset
);
355 if ((0 < index
) && (index
< PCI_ROM_SLOT
)) {
356 int type
= s
->real_device
.io_regions
[index
- 1].type
;
358 if ((type
& XEN_HOST_PCI_REGION_TYPE_MEM
)
359 && (type
& XEN_HOST_PCI_REGION_TYPE_MEM_64
)) {
360 region
= &s
->bases
[index
- 1];
361 if (region
->bar_flag
!= XEN_PT_BAR_FLAG_UPPER
) {
362 return XEN_PT_BAR_FLAG_UPPER
;
367 /* check unused BAR */
368 r
= &d
->io_regions
[index
];
370 return XEN_PT_BAR_FLAG_UNUSED
;
374 if (index
== PCI_ROM_SLOT
) {
375 return XEN_PT_BAR_FLAG_MEM
;
378 /* check BAR I/O indicator */
379 if (s
->real_device
.io_regions
[index
].type
& XEN_HOST_PCI_REGION_TYPE_IO
) {
380 return XEN_PT_BAR_FLAG_IO
;
382 return XEN_PT_BAR_FLAG_MEM
;
386 static inline uint32_t base_address_with_flags(XenHostPCIIORegion
*hr
)
388 if (hr
->type
& XEN_HOST_PCI_REGION_TYPE_IO
) {
389 return hr
->base_addr
| (hr
->bus_flags
& ~PCI_BASE_ADDRESS_IO_MASK
);
391 return hr
->base_addr
| (hr
->bus_flags
& ~PCI_BASE_ADDRESS_MEM_MASK
);
395 static int xen_pt_bar_reg_init(XenPCIPassthroughState
*s
, XenPTRegInfo
*reg
,
396 uint32_t real_offset
, uint32_t *data
)
398 uint32_t reg_field
= 0;
401 index
= xen_pt_bar_offset_to_index(reg
->offset
);
402 if (index
< 0 || index
>= PCI_NUM_REGIONS
) {
403 XEN_PT_ERR(&s
->dev
, "Internal error: Invalid BAR index [%d].\n", index
);
408 s
->bases
[index
].bar_flag
= xen_pt_bar_reg_parse(s
, reg
);
409 if (s
->bases
[index
].bar_flag
== XEN_PT_BAR_FLAG_UNUSED
) {
410 reg_field
= XEN_PT_INVALID_REG
;
416 static int xen_pt_bar_reg_read(XenPCIPassthroughState
*s
, XenPTReg
*cfg_entry
,
417 uint32_t *value
, uint32_t valid_mask
)
419 XenPTRegInfo
*reg
= cfg_entry
->reg
;
420 uint32_t valid_emu_mask
= 0;
421 uint32_t bar_emu_mask
= 0;
425 index
= xen_pt_bar_offset_to_index(reg
->offset
);
426 if (index
< 0 || index
>= PCI_NUM_REGIONS
) {
427 XEN_PT_ERR(&s
->dev
, "Internal error: Invalid BAR index [%d].\n", index
);
431 /* use fixed-up value from kernel sysfs */
432 *value
= base_address_with_flags(&s
->real_device
.io_regions
[index
]);
434 /* set emulate mask depend on BAR flag */
435 switch (s
->bases
[index
].bar_flag
) {
436 case XEN_PT_BAR_FLAG_MEM
:
437 bar_emu_mask
= XEN_PT_BAR_MEM_EMU_MASK
;
439 case XEN_PT_BAR_FLAG_IO
:
440 bar_emu_mask
= XEN_PT_BAR_IO_EMU_MASK
;
442 case XEN_PT_BAR_FLAG_UPPER
:
443 bar_emu_mask
= XEN_PT_BAR_ALLF
;
450 valid_emu_mask
= bar_emu_mask
& valid_mask
;
451 *value
= XEN_PT_MERGE_VALUE(*value
, cfg_entry
->data
, ~valid_emu_mask
);
455 static int xen_pt_bar_reg_write(XenPCIPassthroughState
*s
, XenPTReg
*cfg_entry
,
456 uint32_t *val
, uint32_t dev_value
,
459 XenPTRegInfo
*reg
= cfg_entry
->reg
;
460 XenPTRegion
*base
= NULL
;
461 PCIDevice
*d
= &s
->dev
;
462 const PCIIORegion
*r
;
463 uint32_t writable_mask
= 0;
464 uint32_t throughable_mask
= 0;
465 uint32_t bar_emu_mask
= 0;
466 uint32_t bar_ro_mask
= 0;
470 index
= xen_pt_bar_offset_to_index(reg
->offset
);
471 if (index
< 0 || index
>= PCI_NUM_REGIONS
) {
472 XEN_PT_ERR(d
, "Internal error: Invalid BAR index [%d].\n", index
);
476 r
= &d
->io_regions
[index
];
477 base
= &s
->bases
[index
];
478 r_size
= xen_pt_get_emul_size(base
->bar_flag
, r
->size
);
480 /* set emulate mask and read-only mask values depend on the BAR flag */
481 switch (s
->bases
[index
].bar_flag
) {
482 case XEN_PT_BAR_FLAG_MEM
:
483 bar_emu_mask
= XEN_PT_BAR_MEM_EMU_MASK
;
484 bar_ro_mask
= XEN_PT_BAR_MEM_RO_MASK
| (r_size
- 1);
486 case XEN_PT_BAR_FLAG_IO
:
487 bar_emu_mask
= XEN_PT_BAR_IO_EMU_MASK
;
488 bar_ro_mask
= XEN_PT_BAR_IO_RO_MASK
| (r_size
- 1);
490 case XEN_PT_BAR_FLAG_UPPER
:
491 bar_emu_mask
= XEN_PT_BAR_ALLF
;
492 bar_ro_mask
= 0; /* all upper 32bit are R/W */
498 /* modify emulate register */
499 writable_mask
= bar_emu_mask
& ~bar_ro_mask
& valid_mask
;
500 cfg_entry
->data
= XEN_PT_MERGE_VALUE(*val
, cfg_entry
->data
, writable_mask
);
502 /* check whether we need to update the virtual region address or not */
503 switch (s
->bases
[index
].bar_flag
) {
504 case XEN_PT_BAR_FLAG_MEM
:
507 case XEN_PT_BAR_FLAG_IO
:
510 case XEN_PT_BAR_FLAG_UPPER
:
511 if (cfg_entry
->data
) {
512 if (cfg_entry
->data
!= (XEN_PT_BAR_ALLF
& ~bar_ro_mask
)) {
513 XEN_PT_WARN(d
, "Guest attempt to set high MMIO Base Address. "
515 "(offset: 0x%02x, high address: 0x%08x)\n",
516 reg
->offset
, cfg_entry
->data
);
524 /* create value for writing to I/O device register */
525 throughable_mask
= ~bar_emu_mask
& valid_mask
;
526 *val
= XEN_PT_MERGE_VALUE(*val
, dev_value
, throughable_mask
);
531 /* write Exp ROM BAR */
532 static int xen_pt_exp_rom_bar_reg_write(XenPCIPassthroughState
*s
,
533 XenPTReg
*cfg_entry
, uint32_t *val
,
534 uint32_t dev_value
, uint32_t valid_mask
)
536 XenPTRegInfo
*reg
= cfg_entry
->reg
;
537 XenPTRegion
*base
= NULL
;
538 PCIDevice
*d
= (PCIDevice
*)&s
->dev
;
539 uint32_t writable_mask
= 0;
540 uint32_t throughable_mask
= 0;
542 uint32_t bar_emu_mask
= 0;
543 uint32_t bar_ro_mask
= 0;
545 r_size
= d
->io_regions
[PCI_ROM_SLOT
].size
;
546 base
= &s
->bases
[PCI_ROM_SLOT
];
547 /* align memory type resource size */
548 r_size
= xen_pt_get_emul_size(base
->bar_flag
, r_size
);
550 /* set emulate mask and read-only mask */
551 bar_emu_mask
= reg
->emu_mask
;
552 bar_ro_mask
= (reg
->ro_mask
| (r_size
- 1)) & ~PCI_ROM_ADDRESS_ENABLE
;
554 /* modify emulate register */
555 writable_mask
= ~bar_ro_mask
& valid_mask
;
556 cfg_entry
->data
= XEN_PT_MERGE_VALUE(*val
, cfg_entry
->data
, writable_mask
);
558 /* create value for writing to I/O device register */
559 throughable_mask
= ~bar_emu_mask
& valid_mask
;
560 *val
= XEN_PT_MERGE_VALUE(*val
, dev_value
, throughable_mask
);
565 /* Header Type0 reg static infomation table */
566 static XenPTRegInfo xen_pt_emu_reg_header0
[] = {
569 .offset
= PCI_VENDOR_ID
,
574 .init
= xen_pt_vendor_reg_init
,
575 .u
.w
.read
= xen_pt_word_reg_read
,
576 .u
.w
.write
= xen_pt_word_reg_write
,
580 .offset
= PCI_DEVICE_ID
,
585 .init
= xen_pt_device_reg_init
,
586 .u
.w
.read
= xen_pt_word_reg_read
,
587 .u
.w
.write
= xen_pt_word_reg_write
,
591 .offset
= PCI_COMMAND
,
596 .init
= xen_pt_common_reg_init
,
597 .u
.w
.read
= xen_pt_cmd_reg_read
,
598 .u
.w
.write
= xen_pt_cmd_reg_write
,
600 /* Capabilities Pointer reg */
602 .offset
= PCI_CAPABILITY_LIST
,
607 .init
= xen_pt_ptr_reg_init
,
608 .u
.b
.read
= xen_pt_byte_reg_read
,
609 .u
.b
.write
= xen_pt_byte_reg_write
,
612 /* use emulated Cap Ptr value to initialize,
613 * so need to be declared after Cap Ptr reg
616 .offset
= PCI_STATUS
,
621 .init
= xen_pt_status_reg_init
,
622 .u
.w
.read
= xen_pt_word_reg_read
,
623 .u
.w
.write
= xen_pt_word_reg_write
,
625 /* Cache Line Size reg */
627 .offset
= PCI_CACHE_LINE_SIZE
,
632 .init
= xen_pt_common_reg_init
,
633 .u
.b
.read
= xen_pt_byte_reg_read
,
634 .u
.b
.write
= xen_pt_byte_reg_write
,
636 /* Latency Timer reg */
638 .offset
= PCI_LATENCY_TIMER
,
643 .init
= xen_pt_common_reg_init
,
644 .u
.b
.read
= xen_pt_byte_reg_read
,
645 .u
.b
.write
= xen_pt_byte_reg_write
,
647 /* Header Type reg */
649 .offset
= PCI_HEADER_TYPE
,
654 .init
= xen_pt_header_type_reg_init
,
655 .u
.b
.read
= xen_pt_byte_reg_read
,
656 .u
.b
.write
= xen_pt_byte_reg_write
,
658 /* Interrupt Line reg */
660 .offset
= PCI_INTERRUPT_LINE
,
665 .init
= xen_pt_common_reg_init
,
666 .u
.b
.read
= xen_pt_byte_reg_read
,
667 .u
.b
.write
= xen_pt_byte_reg_write
,
669 /* Interrupt Pin reg */
671 .offset
= PCI_INTERRUPT_PIN
,
676 .init
= xen_pt_irqpin_reg_init
,
677 .u
.b
.read
= xen_pt_byte_reg_read
,
678 .u
.b
.write
= xen_pt_byte_reg_write
,
681 /* mask of BAR need to be decided later, depends on IO/MEM type */
683 .offset
= PCI_BASE_ADDRESS_0
,
685 .init_val
= 0x00000000,
686 .init
= xen_pt_bar_reg_init
,
687 .u
.dw
.read
= xen_pt_bar_reg_read
,
688 .u
.dw
.write
= xen_pt_bar_reg_write
,
692 .offset
= PCI_BASE_ADDRESS_1
,
694 .init_val
= 0x00000000,
695 .init
= xen_pt_bar_reg_init
,
696 .u
.dw
.read
= xen_pt_bar_reg_read
,
697 .u
.dw
.write
= xen_pt_bar_reg_write
,
701 .offset
= PCI_BASE_ADDRESS_2
,
703 .init_val
= 0x00000000,
704 .init
= xen_pt_bar_reg_init
,
705 .u
.dw
.read
= xen_pt_bar_reg_read
,
706 .u
.dw
.write
= xen_pt_bar_reg_write
,
710 .offset
= PCI_BASE_ADDRESS_3
,
712 .init_val
= 0x00000000,
713 .init
= xen_pt_bar_reg_init
,
714 .u
.dw
.read
= xen_pt_bar_reg_read
,
715 .u
.dw
.write
= xen_pt_bar_reg_write
,
719 .offset
= PCI_BASE_ADDRESS_4
,
721 .init_val
= 0x00000000,
722 .init
= xen_pt_bar_reg_init
,
723 .u
.dw
.read
= xen_pt_bar_reg_read
,
724 .u
.dw
.write
= xen_pt_bar_reg_write
,
728 .offset
= PCI_BASE_ADDRESS_5
,
730 .init_val
= 0x00000000,
731 .init
= xen_pt_bar_reg_init
,
732 .u
.dw
.read
= xen_pt_bar_reg_read
,
733 .u
.dw
.write
= xen_pt_bar_reg_write
,
735 /* Expansion ROM BAR reg */
737 .offset
= PCI_ROM_ADDRESS
,
739 .init_val
= 0x00000000,
740 .ro_mask
= 0x000007FE,
741 .emu_mask
= 0xFFFFF800,
742 .init
= xen_pt_bar_reg_init
,
743 .u
.dw
.read
= xen_pt_long_reg_read
,
744 .u
.dw
.write
= xen_pt_exp_rom_bar_reg_write
,
752 /*********************************
753 * Vital Product Data Capability
756 /* Vital Product Data Capability Structure reg static infomation table */
757 static XenPTRegInfo xen_pt_emu_reg_vpd
[] = {
759 .offset
= PCI_CAP_LIST_NEXT
,
764 .init
= xen_pt_ptr_reg_init
,
765 .u
.b
.read
= xen_pt_byte_reg_read
,
766 .u
.b
.write
= xen_pt_byte_reg_write
,
774 /**************************************
775 * Vendor Specific Capability
778 /* Vendor Specific Capability Structure reg static infomation table */
779 static XenPTRegInfo xen_pt_emu_reg_vendor
[] = {
781 .offset
= PCI_CAP_LIST_NEXT
,
786 .init
= xen_pt_ptr_reg_init
,
787 .u
.b
.read
= xen_pt_byte_reg_read
,
788 .u
.b
.write
= xen_pt_byte_reg_write
,
796 /*****************************
797 * PCI Express Capability
800 static inline uint8_t get_capability_version(XenPCIPassthroughState
*s
,
803 uint8_t flags
= pci_get_byte(s
->dev
.config
+ offset
+ PCI_EXP_FLAGS
);
804 return flags
& PCI_EXP_FLAGS_VERS
;
807 static inline uint8_t get_device_type(XenPCIPassthroughState
*s
,
810 uint8_t flags
= pci_get_byte(s
->dev
.config
+ offset
+ PCI_EXP_FLAGS
);
811 return (flags
& PCI_EXP_FLAGS_TYPE
) >> 4;
814 /* initialize Link Control register */
815 static int xen_pt_linkctrl_reg_init(XenPCIPassthroughState
*s
,
816 XenPTRegInfo
*reg
, uint32_t real_offset
,
819 uint8_t cap_ver
= get_capability_version(s
, real_offset
- reg
->offset
);
820 uint8_t dev_type
= get_device_type(s
, real_offset
- reg
->offset
);
822 /* no need to initialize in case of Root Complex Integrated Endpoint
825 if ((dev_type
== PCI_EXP_TYPE_RC_END
) && (cap_ver
== 1)) {
826 *data
= XEN_PT_INVALID_REG
;
829 *data
= reg
->init_val
;
832 /* initialize Device Control 2 register */
833 static int xen_pt_devctrl2_reg_init(XenPCIPassthroughState
*s
,
834 XenPTRegInfo
*reg
, uint32_t real_offset
,
837 uint8_t cap_ver
= get_capability_version(s
, real_offset
- reg
->offset
);
839 /* no need to initialize in case of cap_ver 1.x */
841 *data
= XEN_PT_INVALID_REG
;
844 *data
= reg
->init_val
;
847 /* initialize Link Control 2 register */
848 static int xen_pt_linkctrl2_reg_init(XenPCIPassthroughState
*s
,
849 XenPTRegInfo
*reg
, uint32_t real_offset
,
852 uint8_t cap_ver
= get_capability_version(s
, real_offset
- reg
->offset
);
853 uint32_t reg_field
= 0;
855 /* no need to initialize in case of cap_ver 1.x */
857 reg_field
= XEN_PT_INVALID_REG
;
859 /* set Supported Link Speed */
860 uint8_t lnkcap
= pci_get_byte(s
->dev
.config
+ real_offset
- reg
->offset
862 reg_field
|= PCI_EXP_LNKCAP_SLS
& lnkcap
;
869 /* PCI Express Capability Structure reg static infomation table */
870 static XenPTRegInfo xen_pt_emu_reg_pcie
[] = {
871 /* Next Pointer reg */
873 .offset
= PCI_CAP_LIST_NEXT
,
878 .init
= xen_pt_ptr_reg_init
,
879 .u
.b
.read
= xen_pt_byte_reg_read
,
880 .u
.b
.write
= xen_pt_byte_reg_write
,
882 /* Device Capabilities reg */
884 .offset
= PCI_EXP_DEVCAP
,
886 .init_val
= 0x00000000,
887 .ro_mask
= 0x1FFCFFFF,
888 .emu_mask
= 0x10000000,
889 .init
= xen_pt_common_reg_init
,
890 .u
.dw
.read
= xen_pt_long_reg_read
,
891 .u
.dw
.write
= xen_pt_long_reg_write
,
893 /* Device Control reg */
895 .offset
= PCI_EXP_DEVCTL
,
900 .init
= xen_pt_common_reg_init
,
901 .u
.w
.read
= xen_pt_word_reg_read
,
902 .u
.w
.write
= xen_pt_word_reg_write
,
904 /* Link Control reg */
906 .offset
= PCI_EXP_LNKCTL
,
911 .init
= xen_pt_linkctrl_reg_init
,
912 .u
.w
.read
= xen_pt_word_reg_read
,
913 .u
.w
.write
= xen_pt_word_reg_write
,
915 /* Device Control 2 reg */
922 .init
= xen_pt_devctrl2_reg_init
,
923 .u
.w
.read
= xen_pt_word_reg_read
,
924 .u
.w
.write
= xen_pt_word_reg_write
,
926 /* Link Control 2 reg */
933 .init
= xen_pt_linkctrl2_reg_init
,
934 .u
.w
.read
= xen_pt_word_reg_read
,
935 .u
.w
.write
= xen_pt_word_reg_write
,
943 /*********************************
944 * Power Management Capability
947 /* read Power Management Control/Status register */
948 static int xen_pt_pmcsr_reg_read(XenPCIPassthroughState
*s
, XenPTReg
*cfg_entry
,
949 uint16_t *value
, uint16_t valid_mask
)
951 XenPTRegInfo
*reg
= cfg_entry
->reg
;
952 uint16_t valid_emu_mask
= reg
->emu_mask
;
954 valid_emu_mask
|= PCI_PM_CTRL_STATE_MASK
| PCI_PM_CTRL_NO_SOFT_RESET
;
956 valid_emu_mask
= valid_emu_mask
& valid_mask
;
957 *value
= XEN_PT_MERGE_VALUE(*value
, cfg_entry
->data
, ~valid_emu_mask
);
961 /* write Power Management Control/Status register */
962 static int xen_pt_pmcsr_reg_write(XenPCIPassthroughState
*s
,
963 XenPTReg
*cfg_entry
, uint16_t *val
,
964 uint16_t dev_value
, uint16_t valid_mask
)
966 XenPTRegInfo
*reg
= cfg_entry
->reg
;
967 uint16_t emu_mask
= reg
->emu_mask
;
968 uint16_t writable_mask
= 0;
969 uint16_t throughable_mask
= 0;
971 emu_mask
|= PCI_PM_CTRL_STATE_MASK
| PCI_PM_CTRL_NO_SOFT_RESET
;
973 /* modify emulate register */
974 writable_mask
= emu_mask
& ~reg
->ro_mask
& valid_mask
;
975 cfg_entry
->data
= XEN_PT_MERGE_VALUE(*val
, cfg_entry
->data
, writable_mask
);
977 /* create value for writing to I/O device register */
978 throughable_mask
= ~emu_mask
& valid_mask
;
979 *val
= XEN_PT_MERGE_VALUE(*val
, dev_value
, throughable_mask
);
984 /* Power Management Capability reg static infomation table */
985 static XenPTRegInfo xen_pt_emu_reg_pm
[] = {
986 /* Next Pointer reg */
988 .offset
= PCI_CAP_LIST_NEXT
,
993 .init
= xen_pt_ptr_reg_init
,
994 .u
.b
.read
= xen_pt_byte_reg_read
,
995 .u
.b
.write
= xen_pt_byte_reg_write
,
997 /* Power Management Capabilities reg */
999 .offset
= PCI_CAP_FLAGS
,
1004 .init
= xen_pt_common_reg_init
,
1005 .u
.w
.read
= xen_pt_word_reg_read
,
1006 .u
.w
.write
= xen_pt_word_reg_write
,
1008 /* PCI Power Management Control/Status reg */
1010 .offset
= PCI_PM_CTRL
,
1015 .init
= xen_pt_common_reg_init
,
1016 .u
.w
.read
= xen_pt_pmcsr_reg_read
,
1017 .u
.w
.write
= xen_pt_pmcsr_reg_write
,
1025 /****************************
1029 /* capability structure register group size functions */
1031 static int xen_pt_reg_grp_size_init(XenPCIPassthroughState
*s
,
1032 const XenPTRegGroupInfo
*grp_reg
,
1033 uint32_t base_offset
, uint8_t *size
)
1035 *size
= grp_reg
->grp_size
;
1038 /* get Vendor Specific Capability Structure register group size */
1039 static int xen_pt_vendor_size_init(XenPCIPassthroughState
*s
,
1040 const XenPTRegGroupInfo
*grp_reg
,
1041 uint32_t base_offset
, uint8_t *size
)
1043 *size
= pci_get_byte(s
->dev
.config
+ base_offset
+ 0x02);
1046 /* get PCI Express Capability Structure register group size */
1047 static int xen_pt_pcie_size_init(XenPCIPassthroughState
*s
,
1048 const XenPTRegGroupInfo
*grp_reg
,
1049 uint32_t base_offset
, uint8_t *size
)
1051 PCIDevice
*d
= &s
->dev
;
1052 uint8_t version
= get_capability_version(s
, base_offset
);
1053 uint8_t type
= get_device_type(s
, base_offset
);
1054 uint8_t pcie_size
= 0;
1057 /* calculate size depend on capability version and device/port type */
1058 /* in case of PCI Express Base Specification Rev 1.x */
1060 /* The PCI Express Capabilities, Device Capabilities, and Device
1061 * Status/Control registers are required for all PCI Express devices.
1062 * The Link Capabilities and Link Status/Control are required for all
1063 * Endpoints that are not Root Complex Integrated Endpoints. Endpoints
1064 * are not required to implement registers other than those listed
1065 * above and terminate the capability structure.
1068 case PCI_EXP_TYPE_ENDPOINT
:
1069 case PCI_EXP_TYPE_LEG_END
:
1072 case PCI_EXP_TYPE_RC_END
:
1076 /* only EndPoint passthrough is supported */
1077 case PCI_EXP_TYPE_ROOT_PORT
:
1078 case PCI_EXP_TYPE_UPSTREAM
:
1079 case PCI_EXP_TYPE_DOWNSTREAM
:
1080 case PCI_EXP_TYPE_PCI_BRIDGE
:
1081 case PCI_EXP_TYPE_PCIE_BRIDGE
:
1082 case PCI_EXP_TYPE_RC_EC
:
1084 XEN_PT_ERR(d
, "Unsupported device/port type %#x.\n", type
);
1088 /* in case of PCI Express Base Specification Rev 2.0 */
1089 else if (version
== 2) {
1091 case PCI_EXP_TYPE_ENDPOINT
:
1092 case PCI_EXP_TYPE_LEG_END
:
1093 case PCI_EXP_TYPE_RC_END
:
1094 /* For Functions that do not implement the registers,
1095 * these spaces must be hardwired to 0b.
1099 /* only EndPoint passthrough is supported */
1100 case PCI_EXP_TYPE_ROOT_PORT
:
1101 case PCI_EXP_TYPE_UPSTREAM
:
1102 case PCI_EXP_TYPE_DOWNSTREAM
:
1103 case PCI_EXP_TYPE_PCI_BRIDGE
:
1104 case PCI_EXP_TYPE_PCIE_BRIDGE
:
1105 case PCI_EXP_TYPE_RC_EC
:
1107 XEN_PT_ERR(d
, "Unsupported device/port type %#x.\n", type
);
1111 XEN_PT_ERR(d
, "Unsupported capability version %#x.\n", version
);
1119 static const XenPTRegGroupInfo xen_pt_emu_reg_grps
[] = {
1120 /* Header Type0 reg group */
1123 .grp_type
= XEN_PT_GRP_TYPE_EMU
,
1125 .size_init
= xen_pt_reg_grp_size_init
,
1126 .emu_regs
= xen_pt_emu_reg_header0
,
1128 /* PCI PowerManagement Capability reg group */
1130 .grp_id
= PCI_CAP_ID_PM
,
1131 .grp_type
= XEN_PT_GRP_TYPE_EMU
,
1132 .grp_size
= PCI_PM_SIZEOF
,
1133 .size_init
= xen_pt_reg_grp_size_init
,
1134 .emu_regs
= xen_pt_emu_reg_pm
,
1136 /* AGP Capability Structure reg group */
1138 .grp_id
= PCI_CAP_ID_AGP
,
1139 .grp_type
= XEN_PT_GRP_TYPE_HARDWIRED
,
1141 .size_init
= xen_pt_reg_grp_size_init
,
1143 /* Vital Product Data Capability Structure reg group */
1145 .grp_id
= PCI_CAP_ID_VPD
,
1146 .grp_type
= XEN_PT_GRP_TYPE_EMU
,
1148 .size_init
= xen_pt_reg_grp_size_init
,
1149 .emu_regs
= xen_pt_emu_reg_vpd
,
1151 /* Slot Identification reg group */
1153 .grp_id
= PCI_CAP_ID_SLOTID
,
1154 .grp_type
= XEN_PT_GRP_TYPE_HARDWIRED
,
1156 .size_init
= xen_pt_reg_grp_size_init
,
1158 /* PCI-X Capabilities List Item reg group */
1160 .grp_id
= PCI_CAP_ID_PCIX
,
1161 .grp_type
= XEN_PT_GRP_TYPE_HARDWIRED
,
1163 .size_init
= xen_pt_reg_grp_size_init
,
1165 /* Vendor Specific Capability Structure reg group */
1167 .grp_id
= PCI_CAP_ID_VNDR
,
1168 .grp_type
= XEN_PT_GRP_TYPE_EMU
,
1170 .size_init
= xen_pt_vendor_size_init
,
1171 .emu_regs
= xen_pt_emu_reg_vendor
,
1173 /* SHPC Capability List Item reg group */
1175 .grp_id
= PCI_CAP_ID_SHPC
,
1176 .grp_type
= XEN_PT_GRP_TYPE_HARDWIRED
,
1178 .size_init
= xen_pt_reg_grp_size_init
,
1180 /* Subsystem ID and Subsystem Vendor ID Capability List Item reg group */
1182 .grp_id
= PCI_CAP_ID_SSVID
,
1183 .grp_type
= XEN_PT_GRP_TYPE_HARDWIRED
,
1185 .size_init
= xen_pt_reg_grp_size_init
,
1187 /* AGP 8x Capability Structure reg group */
1189 .grp_id
= PCI_CAP_ID_AGP3
,
1190 .grp_type
= XEN_PT_GRP_TYPE_HARDWIRED
,
1192 .size_init
= xen_pt_reg_grp_size_init
,
1194 /* PCI Express Capability Structure reg group */
1196 .grp_id
= PCI_CAP_ID_EXP
,
1197 .grp_type
= XEN_PT_GRP_TYPE_EMU
,
1199 .size_init
= xen_pt_pcie_size_init
,
1200 .emu_regs
= xen_pt_emu_reg_pcie
,
1207 /* initialize Capabilities Pointer or Next Pointer register */
1208 static int xen_pt_ptr_reg_init(XenPCIPassthroughState
*s
,
1209 XenPTRegInfo
*reg
, uint32_t real_offset
,
1213 uint8_t *config
= s
->dev
.config
;
1214 uint32_t reg_field
= pci_get_byte(config
+ real_offset
);
1217 /* find capability offset */
1219 for (i
= 0; xen_pt_emu_reg_grps
[i
].grp_size
!= 0; i
++) {
1220 if (xen_pt_hide_dev_cap(&s
->real_device
,
1221 xen_pt_emu_reg_grps
[i
].grp_id
)) {
1225 cap_id
= pci_get_byte(config
+ reg_field
+ PCI_CAP_LIST_ID
);
1226 if (xen_pt_emu_reg_grps
[i
].grp_id
== cap_id
) {
1227 if (xen_pt_emu_reg_grps
[i
].grp_type
== XEN_PT_GRP_TYPE_EMU
) {
1230 /* ignore the 0 hardwired capability, find next one */
1235 /* next capability */
1236 reg_field
= pci_get_byte(config
+ reg_field
+ PCI_CAP_LIST_NEXT
);
1249 static uint8_t find_cap_offset(XenPCIPassthroughState
*s
, uint8_t cap
)
1252 unsigned max_cap
= PCI_CAP_MAX
;
1253 uint8_t pos
= PCI_CAPABILITY_LIST
;
1256 if (xen_host_pci_get_byte(&s
->real_device
, PCI_STATUS
, &status
)) {
1259 if ((status
& PCI_STATUS_CAP_LIST
) == 0) {
1264 if (xen_host_pci_get_byte(&s
->real_device
, pos
, &pos
)) {
1267 if (pos
< PCI_CONFIG_HEADER_SIZE
) {
1272 if (xen_host_pci_get_byte(&s
->real_device
,
1273 pos
+ PCI_CAP_LIST_ID
, &id
)) {
1284 pos
+= PCI_CAP_LIST_NEXT
;
1289 static int xen_pt_config_reg_init(XenPCIPassthroughState
*s
,
1290 XenPTRegGroup
*reg_grp
, XenPTRegInfo
*reg
)
1292 XenPTReg
*reg_entry
;
1296 reg_entry
= g_new0(XenPTReg
, 1);
1297 reg_entry
->reg
= reg
;
1300 /* initialize emulate register */
1301 rc
= reg
->init(s
, reg_entry
->reg
,
1302 reg_grp
->base_offset
+ reg
->offset
, &data
);
1307 if (data
== XEN_PT_INVALID_REG
) {
1308 /* free unused BAR register entry */
1312 /* set register value */
1313 reg_entry
->data
= data
;
1315 /* list add register entry */
1316 QLIST_INSERT_HEAD(®_grp
->reg_tbl_list
, reg_entry
, entries
);
1321 int xen_pt_config_init(XenPCIPassthroughState
*s
)
1325 QLIST_INIT(&s
->reg_grps
);
1327 for (i
= 0; xen_pt_emu_reg_grps
[i
].grp_size
!= 0; i
++) {
1328 uint32_t reg_grp_offset
= 0;
1329 XenPTRegGroup
*reg_grp_entry
= NULL
;
1331 if (xen_pt_emu_reg_grps
[i
].grp_id
!= 0xFF) {
1332 if (xen_pt_hide_dev_cap(&s
->real_device
,
1333 xen_pt_emu_reg_grps
[i
].grp_id
)) {
1337 reg_grp_offset
= find_cap_offset(s
, xen_pt_emu_reg_grps
[i
].grp_id
);
1339 if (!reg_grp_offset
) {
1344 reg_grp_entry
= g_new0(XenPTRegGroup
, 1);
1345 QLIST_INIT(®_grp_entry
->reg_tbl_list
);
1346 QLIST_INSERT_HEAD(&s
->reg_grps
, reg_grp_entry
, entries
);
1348 reg_grp_entry
->base_offset
= reg_grp_offset
;
1349 reg_grp_entry
->reg_grp
= xen_pt_emu_reg_grps
+ i
;
1350 if (xen_pt_emu_reg_grps
[i
].size_init
) {
1351 /* get register group size */
1352 rc
= xen_pt_emu_reg_grps
[i
].size_init(s
, reg_grp_entry
->reg_grp
,
1354 ®_grp_entry
->size
);
1356 xen_pt_config_delete(s
);
1361 if (xen_pt_emu_reg_grps
[i
].grp_type
== XEN_PT_GRP_TYPE_EMU
) {
1362 if (xen_pt_emu_reg_grps
[i
].emu_regs
) {
1364 XenPTRegInfo
*regs
= xen_pt_emu_reg_grps
[i
].emu_regs
;
1365 /* initialize capability register */
1366 for (j
= 0; regs
->size
!= 0; j
++, regs
++) {
1367 /* initialize capability register */
1368 rc
= xen_pt_config_reg_init(s
, reg_grp_entry
, regs
);
1370 xen_pt_config_delete(s
);
1381 /* delete all emulate register */
1382 void xen_pt_config_delete(XenPCIPassthroughState
*s
)
1384 struct XenPTRegGroup
*reg_group
, *next_grp
;
1385 struct XenPTReg
*reg
, *next_reg
;
1387 /* free all register group entry */
1388 QLIST_FOREACH_SAFE(reg_group
, &s
->reg_grps
, entries
, next_grp
) {
1389 /* free all register entry */
1390 QLIST_FOREACH_SAFE(reg
, ®_group
->reg_tbl_list
, entries
, next_reg
) {
1391 QLIST_REMOVE(reg
, entries
);
1395 QLIST_REMOVE(reg_group
, entries
);