2 * High Precision Event Timer emulation
4 * Copyright (c) 2007 Alexander Graf
5 * Copyright (c) 2008 IBM Corporation
7 * Authors: Beth Kon <bkon@us.ibm.com>
9 * This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU Lesser General Public
11 * License as published by the Free Software Foundation; either
12 * version 2 of the License, or (at your option) any later version.
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * Lesser General Public License for more details.
19 * You should have received a copy of the GNU Lesser General Public
20 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
22 * *****************************************************************
24 * This driver attempts to emulate an HPET device in software.
27 #include "qemu/osdep.h"
28 #include "hw/i386/pc.h"
30 #include "qapi/error.h"
31 #include "qemu/error-report.h"
32 #include "qemu/timer.h"
33 #include "hw/timer/hpet.h"
34 #include "hw/sysbus.h"
35 #include "hw/rtc/mc146818rtc.h"
36 #include "hw/rtc/mc146818rtc_regs.h"
37 #include "migration/vmstate.h"
38 #include "hw/timer/i8254.h"
39 #include "exec/address-spaces.h"
40 #include "qom/object.h"
44 #define DPRINTF printf
49 #define HPET_MSI_SUPPORT 0
51 typedef struct HPETState HPETState
;
52 DECLARE_INSTANCE_CHECKER(HPETState
, HPET
,
56 typedef struct HPETTimer
{ /* timers */
57 uint8_t tn
; /*timer number*/
58 QEMUTimer
*qemu_timer
;
59 struct HPETState
*state
;
60 /* Memory-mapped, software visible timer registers */
61 uint64_t config
; /* configuration/cap */
62 uint64_t cmp
; /* comparator */
63 uint64_t fsb
; /* FSB route */
64 /* Hidden register state */
65 uint64_t period
; /* Last value written to comparator */
66 uint8_t wrap_flag
; /* timer pop will indicate wrap for one-shot 32-bit
67 * mode. Next pop will be actual timer expiration.
73 SysBusDevice parent_obj
;
78 bool hpet_offset_saved
;
79 qemu_irq irqs
[HPET_NUM_IRQ_ROUTES
];
81 uint8_t rtc_irq_level
;
85 HPETTimer timer
[HPET_MAX_TIMERS
];
87 /* Memory-mapped, software visible registers */
88 uint64_t capability
; /* capabilities */
89 uint64_t config
; /* configuration */
90 uint64_t isr
; /* interrupt status reg */
91 uint64_t hpet_counter
; /* main counter */
92 uint8_t hpet_id
; /* instance id */
95 static uint32_t hpet_in_legacy_mode(HPETState
*s
)
97 return s
->config
& HPET_CFG_LEGACY
;
100 static uint32_t timer_int_route(struct HPETTimer
*timer
)
102 return (timer
->config
& HPET_TN_INT_ROUTE_MASK
) >> HPET_TN_INT_ROUTE_SHIFT
;
105 static uint32_t timer_fsb_route(HPETTimer
*t
)
107 return t
->config
& HPET_TN_FSB_ENABLE
;
110 static uint32_t hpet_enabled(HPETState
*s
)
112 return s
->config
& HPET_CFG_ENABLE
;
115 static uint32_t timer_is_periodic(HPETTimer
*t
)
117 return t
->config
& HPET_TN_PERIODIC
;
120 static uint32_t timer_enabled(HPETTimer
*t
)
122 return t
->config
& HPET_TN_ENABLE
;
125 static uint32_t hpet_time_after(uint64_t a
, uint64_t b
)
127 return ((int32_t)(b
- a
) < 0);
130 static uint32_t hpet_time_after64(uint64_t a
, uint64_t b
)
132 return ((int64_t)(b
- a
) < 0);
135 static uint64_t ticks_to_ns(uint64_t value
)
137 return value
* HPET_CLK_PERIOD
;
140 static uint64_t ns_to_ticks(uint64_t value
)
142 return value
/ HPET_CLK_PERIOD
;
145 static uint64_t hpet_fixup_reg(uint64_t new, uint64_t old
, uint64_t mask
)
152 static int activating_bit(uint64_t old
, uint64_t new, uint64_t mask
)
154 return (!(old
& mask
) && (new & mask
));
157 static int deactivating_bit(uint64_t old
, uint64_t new, uint64_t mask
)
159 return ((old
& mask
) && !(new & mask
));
162 static uint64_t hpet_get_ticks(HPETState
*s
)
164 return ns_to_ticks(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) + s
->hpet_offset
);
168 * calculate diff between comparator value and current ticks
170 static inline uint64_t hpet_calculate_diff(HPETTimer
*t
, uint64_t current
)
173 if (t
->config
& HPET_TN_32BIT
) {
176 cmp
= (uint32_t)t
->cmp
;
177 diff
= cmp
- (uint32_t)current
;
178 diff
= (int32_t)diff
> 0 ? diff
: (uint32_t)1;
179 return (uint64_t)diff
;
184 diff
= cmp
- current
;
185 diff
= (int64_t)diff
> 0 ? diff
: (uint64_t)1;
190 static void update_irq(struct HPETTimer
*timer
, int set
)
196 if (timer
->tn
<= 1 && hpet_in_legacy_mode(timer
->state
)) {
197 /* if LegacyReplacementRoute bit is set, HPET specification requires
198 * timer0 be routed to IRQ0 in NON-APIC or IRQ2 in the I/O APIC,
199 * timer1 be routed to IRQ8 in NON-APIC or IRQ8 in the I/O APIC.
201 route
= (timer
->tn
== 0) ? 0 : RTC_ISA_IRQ
;
203 route
= timer_int_route(timer
);
206 mask
= 1 << timer
->tn
;
207 if (!set
|| !timer_enabled(timer
) || !hpet_enabled(timer
->state
)) {
209 if (!timer_fsb_route(timer
)) {
210 qemu_irq_lower(s
->irqs
[route
]);
212 } else if (timer_fsb_route(timer
)) {
213 address_space_stl_le(&address_space_memory
, timer
->fsb
>> 32,
214 timer
->fsb
& 0xffffffff, MEMTXATTRS_UNSPECIFIED
,
216 } else if (timer
->config
& HPET_TN_TYPE_LEVEL
) {
218 qemu_irq_raise(s
->irqs
[route
]);
221 qemu_irq_pulse(s
->irqs
[route
]);
225 static int hpet_pre_save(void *opaque
)
227 HPETState
*s
= opaque
;
229 /* save current counter value */
230 if (hpet_enabled(s
)) {
231 s
->hpet_counter
= hpet_get_ticks(s
);
237 static int hpet_pre_load(void *opaque
)
239 HPETState
*s
= opaque
;
241 /* version 1 only supports 3, later versions will load the actual value */
242 s
->num_timers
= HPET_MIN_TIMERS
;
246 static bool hpet_validate_num_timers(void *opaque
, int version_id
)
248 HPETState
*s
= opaque
;
250 if (s
->num_timers
< HPET_MIN_TIMERS
) {
252 } else if (s
->num_timers
> HPET_MAX_TIMERS
) {
258 static int hpet_post_load(void *opaque
, int version_id
)
260 HPETState
*s
= opaque
;
262 /* Recalculate the offset between the main counter and guest time */
263 if (!s
->hpet_offset_saved
) {
264 s
->hpet_offset
= ticks_to_ns(s
->hpet_counter
)
265 - qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
);
268 /* Push number of timers into capability returned via HPET_ID */
269 s
->capability
&= ~HPET_ID_NUM_TIM_MASK
;
270 s
->capability
|= (s
->num_timers
- 1) << HPET_ID_NUM_TIM_SHIFT
;
271 hpet_cfg
.hpet
[s
->hpet_id
].event_timer_block_id
= (uint32_t)s
->capability
;
273 /* Derive HPET_MSI_SUPPORT from the capability of the first timer. */
274 s
->flags
&= ~(1 << HPET_MSI_SUPPORT
);
275 if (s
->timer
[0].config
& HPET_TN_FSB_CAP
) {
276 s
->flags
|= 1 << HPET_MSI_SUPPORT
;
281 static bool hpet_offset_needed(void *opaque
)
283 HPETState
*s
= opaque
;
285 return hpet_enabled(s
) && s
->hpet_offset_saved
;
288 static bool hpet_rtc_irq_level_needed(void *opaque
)
290 HPETState
*s
= opaque
;
292 return s
->rtc_irq_level
!= 0;
295 static const VMStateDescription vmstate_hpet_rtc_irq_level
= {
296 .name
= "hpet/rtc_irq_level",
298 .minimum_version_id
= 1,
299 .needed
= hpet_rtc_irq_level_needed
,
300 .fields
= (VMStateField
[]) {
301 VMSTATE_UINT8(rtc_irq_level
, HPETState
),
302 VMSTATE_END_OF_LIST()
306 static const VMStateDescription vmstate_hpet_offset
= {
307 .name
= "hpet/offset",
309 .minimum_version_id
= 1,
310 .needed
= hpet_offset_needed
,
311 .fields
= (VMStateField
[]) {
312 VMSTATE_UINT64(hpet_offset
, HPETState
),
313 VMSTATE_END_OF_LIST()
317 static const VMStateDescription vmstate_hpet_timer
= {
318 .name
= "hpet_timer",
320 .minimum_version_id
= 1,
321 .fields
= (VMStateField
[]) {
322 VMSTATE_UINT8(tn
, HPETTimer
),
323 VMSTATE_UINT64(config
, HPETTimer
),
324 VMSTATE_UINT64(cmp
, HPETTimer
),
325 VMSTATE_UINT64(fsb
, HPETTimer
),
326 VMSTATE_UINT64(period
, HPETTimer
),
327 VMSTATE_UINT8(wrap_flag
, HPETTimer
),
328 VMSTATE_TIMER_PTR(qemu_timer
, HPETTimer
),
329 VMSTATE_END_OF_LIST()
333 static const VMStateDescription vmstate_hpet
= {
336 .minimum_version_id
= 1,
337 .pre_save
= hpet_pre_save
,
338 .pre_load
= hpet_pre_load
,
339 .post_load
= hpet_post_load
,
340 .fields
= (VMStateField
[]) {
341 VMSTATE_UINT64(config
, HPETState
),
342 VMSTATE_UINT64(isr
, HPETState
),
343 VMSTATE_UINT64(hpet_counter
, HPETState
),
344 VMSTATE_UINT8_V(num_timers
, HPETState
, 2),
345 VMSTATE_VALIDATE("num_timers in range", hpet_validate_num_timers
),
346 VMSTATE_STRUCT_VARRAY_UINT8(timer
, HPETState
, num_timers
, 0,
347 vmstate_hpet_timer
, HPETTimer
),
348 VMSTATE_END_OF_LIST()
350 .subsections
= (const VMStateDescription
*[]) {
351 &vmstate_hpet_rtc_irq_level
,
352 &vmstate_hpet_offset
,
358 * timer expiration callback
360 static void hpet_timer(void *opaque
)
362 HPETTimer
*t
= opaque
;
365 uint64_t period
= t
->period
;
366 uint64_t cur_tick
= hpet_get_ticks(t
->state
);
368 if (timer_is_periodic(t
) && period
!= 0) {
369 if (t
->config
& HPET_TN_32BIT
) {
370 while (hpet_time_after(cur_tick
, t
->cmp
)) {
371 t
->cmp
= (uint32_t)(t
->cmp
+ t
->period
);
374 while (hpet_time_after64(cur_tick
, t
->cmp
)) {
378 diff
= hpet_calculate_diff(t
, cur_tick
);
379 timer_mod(t
->qemu_timer
,
380 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) + (int64_t)ticks_to_ns(diff
));
381 } else if (t
->config
& HPET_TN_32BIT
&& !timer_is_periodic(t
)) {
383 diff
= hpet_calculate_diff(t
, cur_tick
);
384 timer_mod(t
->qemu_timer
, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) +
385 (int64_t)ticks_to_ns(diff
));
392 static void hpet_set_timer(HPETTimer
*t
)
395 uint32_t wrap_diff
; /* how many ticks until we wrap? */
396 uint64_t cur_tick
= hpet_get_ticks(t
->state
);
398 /* whenever new timer is being set up, make sure wrap_flag is 0 */
400 diff
= hpet_calculate_diff(t
, cur_tick
);
402 /* hpet spec says in one-shot 32-bit mode, generate an interrupt when
403 * counter wraps in addition to an interrupt with comparator match.
405 if (t
->config
& HPET_TN_32BIT
&& !timer_is_periodic(t
)) {
406 wrap_diff
= 0xffffffff - (uint32_t)cur_tick
;
407 if (wrap_diff
< (uint32_t)diff
) {
412 timer_mod(t
->qemu_timer
,
413 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) + (int64_t)ticks_to_ns(diff
));
416 static void hpet_del_timer(HPETTimer
*t
)
418 timer_del(t
->qemu_timer
);
422 static uint64_t hpet_ram_read(void *opaque
, hwaddr addr
,
425 HPETState
*s
= opaque
;
426 uint64_t cur_tick
, index
;
428 DPRINTF("qemu: Enter hpet_ram_readl at %" PRIx64
"\n", addr
);
430 /*address range of all TN regs*/
431 if (index
>= 0x100 && index
<= 0x3ff) {
432 uint8_t timer_id
= (addr
- 0x100) / 0x20;
433 HPETTimer
*timer
= &s
->timer
[timer_id
];
435 if (timer_id
> s
->num_timers
) {
436 DPRINTF("qemu: timer id out of range\n");
440 switch ((addr
- 0x100) % 0x20) {
442 return timer
->config
;
443 case HPET_TN_CFG
+ 4: // Interrupt capabilities
444 return timer
->config
>> 32;
445 case HPET_TN_CMP
: // comparator register
447 case HPET_TN_CMP
+ 4:
448 return timer
->cmp
>> 32;
451 case HPET_TN_ROUTE
+ 4:
452 return timer
->fsb
>> 32;
454 DPRINTF("qemu: invalid hpet_ram_readl\n");
460 return s
->capability
;
462 return s
->capability
>> 32;
466 DPRINTF("qemu: invalid HPET_CFG + 4 hpet_ram_readl\n");
469 if (hpet_enabled(s
)) {
470 cur_tick
= hpet_get_ticks(s
);
472 cur_tick
= s
->hpet_counter
;
474 DPRINTF("qemu: reading counter = %" PRIx64
"\n", cur_tick
);
476 case HPET_COUNTER
+ 4:
477 if (hpet_enabled(s
)) {
478 cur_tick
= hpet_get_ticks(s
);
480 cur_tick
= s
->hpet_counter
;
482 DPRINTF("qemu: reading counter + 4 = %" PRIx64
"\n", cur_tick
);
483 return cur_tick
>> 32;
487 DPRINTF("qemu: invalid hpet_ram_readl\n");
494 static void hpet_ram_write(void *opaque
, hwaddr addr
,
495 uint64_t value
, unsigned size
)
498 HPETState
*s
= opaque
;
499 uint64_t old_val
, new_val
, val
, index
;
501 DPRINTF("qemu: Enter hpet_ram_writel at %" PRIx64
" = 0x%" PRIx64
"\n",
504 old_val
= hpet_ram_read(opaque
, addr
, 4);
507 /*address range of all TN regs*/
508 if (index
>= 0x100 && index
<= 0x3ff) {
509 uint8_t timer_id
= (addr
- 0x100) / 0x20;
510 HPETTimer
*timer
= &s
->timer
[timer_id
];
512 DPRINTF("qemu: hpet_ram_writel timer_id = 0x%x\n", timer_id
);
513 if (timer_id
> s
->num_timers
) {
514 DPRINTF("qemu: timer id out of range\n");
517 switch ((addr
- 0x100) % 0x20) {
519 DPRINTF("qemu: hpet_ram_writel HPET_TN_CFG\n");
520 if (activating_bit(old_val
, new_val
, HPET_TN_FSB_ENABLE
)) {
521 update_irq(timer
, 0);
523 val
= hpet_fixup_reg(new_val
, old_val
, HPET_TN_CFG_WRITE_MASK
);
524 timer
->config
= (timer
->config
& 0xffffffff00000000ULL
) | val
;
525 if (new_val
& HPET_TN_32BIT
) {
526 timer
->cmp
= (uint32_t)timer
->cmp
;
527 timer
->period
= (uint32_t)timer
->period
;
529 if (activating_bit(old_val
, new_val
, HPET_TN_ENABLE
) &&
531 hpet_set_timer(timer
);
532 } else if (deactivating_bit(old_val
, new_val
, HPET_TN_ENABLE
)) {
533 hpet_del_timer(timer
);
536 case HPET_TN_CFG
+ 4: // Interrupt capabilities
537 DPRINTF("qemu: invalid HPET_TN_CFG+4 write\n");
539 case HPET_TN_CMP
: // comparator register
540 DPRINTF("qemu: hpet_ram_writel HPET_TN_CMP\n");
541 if (timer
->config
& HPET_TN_32BIT
) {
542 new_val
= (uint32_t)new_val
;
544 if (!timer_is_periodic(timer
)
545 || (timer
->config
& HPET_TN_SETVAL
)) {
546 timer
->cmp
= (timer
->cmp
& 0xffffffff00000000ULL
) | new_val
;
548 if (timer_is_periodic(timer
)) {
550 * FIXME: Clamp period to reasonable min value?
551 * Clamp period to reasonable max value
553 new_val
&= (timer
->config
& HPET_TN_32BIT
? ~0u : ~0ull) >> 1;
555 (timer
->period
& 0xffffffff00000000ULL
) | new_val
;
557 timer
->config
&= ~HPET_TN_SETVAL
;
558 if (hpet_enabled(s
)) {
559 hpet_set_timer(timer
);
562 case HPET_TN_CMP
+ 4: // comparator register high order
563 DPRINTF("qemu: hpet_ram_writel HPET_TN_CMP + 4\n");
564 if (!timer_is_periodic(timer
)
565 || (timer
->config
& HPET_TN_SETVAL
)) {
566 timer
->cmp
= (timer
->cmp
& 0xffffffffULL
) | new_val
<< 32;
569 * FIXME: Clamp period to reasonable min value?
570 * Clamp period to reasonable max value
572 new_val
&= (timer
->config
& HPET_TN_32BIT
? ~0u : ~0ull) >> 1;
574 (timer
->period
& 0xffffffffULL
) | new_val
<< 32;
576 timer
->config
&= ~HPET_TN_SETVAL
;
577 if (hpet_enabled(s
)) {
578 hpet_set_timer(timer
);
582 timer
->fsb
= (timer
->fsb
& 0xffffffff00000000ULL
) | new_val
;
584 case HPET_TN_ROUTE
+ 4:
585 timer
->fsb
= (new_val
<< 32) | (timer
->fsb
& 0xffffffff);
588 DPRINTF("qemu: invalid hpet_ram_writel\n");
597 val
= hpet_fixup_reg(new_val
, old_val
, HPET_CFG_WRITE_MASK
);
598 s
->config
= (s
->config
& 0xffffffff00000000ULL
) | val
;
599 if (activating_bit(old_val
, new_val
, HPET_CFG_ENABLE
)) {
600 /* Enable main counter and interrupt generation. */
602 ticks_to_ns(s
->hpet_counter
) - qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
);
603 for (i
= 0; i
< s
->num_timers
; i
++) {
604 if ((&s
->timer
[i
])->cmp
!= ~0ULL) {
605 hpet_set_timer(&s
->timer
[i
]);
608 } else if (deactivating_bit(old_val
, new_val
, HPET_CFG_ENABLE
)) {
609 /* Halt main counter and disable interrupt generation. */
610 s
->hpet_counter
= hpet_get_ticks(s
);
611 for (i
= 0; i
< s
->num_timers
; i
++) {
612 hpet_del_timer(&s
->timer
[i
]);
615 /* i8254 and RTC output pins are disabled
616 * when HPET is in legacy mode */
617 if (activating_bit(old_val
, new_val
, HPET_CFG_LEGACY
)) {
618 qemu_set_irq(s
->pit_enabled
, 0);
619 qemu_irq_lower(s
->irqs
[0]);
620 qemu_irq_lower(s
->irqs
[RTC_ISA_IRQ
]);
621 } else if (deactivating_bit(old_val
, new_val
, HPET_CFG_LEGACY
)) {
622 qemu_irq_lower(s
->irqs
[0]);
623 qemu_set_irq(s
->pit_enabled
, 1);
624 qemu_set_irq(s
->irqs
[RTC_ISA_IRQ
], s
->rtc_irq_level
);
628 DPRINTF("qemu: invalid HPET_CFG+4 write\n");
631 val
= new_val
& s
->isr
;
632 for (i
= 0; i
< s
->num_timers
; i
++) {
633 if (val
& (1 << i
)) {
634 update_irq(&s
->timer
[i
], 0);
639 if (hpet_enabled(s
)) {
640 DPRINTF("qemu: Writing counter while HPET enabled!\n");
643 (s
->hpet_counter
& 0xffffffff00000000ULL
) | value
;
644 DPRINTF("qemu: HPET counter written. ctr = 0x%" PRIx64
" -> "
645 "%" PRIx64
"\n", value
, s
->hpet_counter
);
647 case HPET_COUNTER
+ 4:
648 if (hpet_enabled(s
)) {
649 DPRINTF("qemu: Writing counter while HPET enabled!\n");
652 (s
->hpet_counter
& 0xffffffffULL
) | (((uint64_t)value
) << 32);
653 DPRINTF("qemu: HPET counter + 4 written. ctr = 0x%" PRIx64
" -> "
654 "%" PRIx64
"\n", value
, s
->hpet_counter
);
657 DPRINTF("qemu: invalid hpet_ram_writel\n");
663 static const MemoryRegionOps hpet_ram_ops
= {
664 .read
= hpet_ram_read
,
665 .write
= hpet_ram_write
,
667 .min_access_size
= 4,
668 .max_access_size
= 4,
670 .endianness
= DEVICE_NATIVE_ENDIAN
,
673 static void hpet_reset(DeviceState
*d
)
675 HPETState
*s
= HPET(d
);
676 SysBusDevice
*sbd
= SYS_BUS_DEVICE(d
);
679 for (i
= 0; i
< s
->num_timers
; i
++) {
680 HPETTimer
*timer
= &s
->timer
[i
];
682 hpet_del_timer(timer
);
684 timer
->config
= HPET_TN_PERIODIC_CAP
| HPET_TN_SIZE_CAP
;
685 if (s
->flags
& (1 << HPET_MSI_SUPPORT
)) {
686 timer
->config
|= HPET_TN_FSB_CAP
;
688 /* advertise availability of ioapic int */
689 timer
->config
|= (uint64_t)s
->intcap
<< 32;
690 timer
->period
= 0ULL;
691 timer
->wrap_flag
= 0;
694 qemu_set_irq(s
->pit_enabled
, 1);
695 s
->hpet_counter
= 0ULL;
696 s
->hpet_offset
= 0ULL;
698 hpet_cfg
.hpet
[s
->hpet_id
].event_timer_block_id
= (uint32_t)s
->capability
;
699 hpet_cfg
.hpet
[s
->hpet_id
].address
= sbd
->mmio
[0].addr
;
701 /* to document that the RTC lowers its output on reset as well */
702 s
->rtc_irq_level
= 0;
705 static void hpet_handle_legacy_irq(void *opaque
, int n
, int level
)
707 HPETState
*s
= HPET(opaque
);
709 if (n
== HPET_LEGACY_PIT_INT
) {
710 if (!hpet_in_legacy_mode(s
)) {
711 qemu_set_irq(s
->irqs
[0], level
);
714 s
->rtc_irq_level
= level
;
715 if (!hpet_in_legacy_mode(s
)) {
716 qemu_set_irq(s
->irqs
[RTC_ISA_IRQ
], level
);
721 static void hpet_init(Object
*obj
)
723 SysBusDevice
*sbd
= SYS_BUS_DEVICE(obj
);
724 HPETState
*s
= HPET(obj
);
727 memory_region_init_io(&s
->iomem
, obj
, &hpet_ram_ops
, s
, "hpet", HPET_LEN
);
728 sysbus_init_mmio(sbd
, &s
->iomem
);
731 static void hpet_realize(DeviceState
*dev
, Error
**errp
)
733 SysBusDevice
*sbd
= SYS_BUS_DEVICE(dev
);
734 HPETState
*s
= HPET(dev
);
739 warn_report("Hpet's intcap not initialized");
741 if (hpet_cfg
.count
== UINT8_MAX
) {
746 if (hpet_cfg
.count
== 8) {
747 error_setg(errp
, "Only 8 instances of HPET is allowed");
751 s
->hpet_id
= hpet_cfg
.count
++;
753 for (i
= 0; i
< HPET_NUM_IRQ_ROUTES
; i
++) {
754 sysbus_init_irq(sbd
, &s
->irqs
[i
]);
757 if (s
->num_timers
< HPET_MIN_TIMERS
) {
758 s
->num_timers
= HPET_MIN_TIMERS
;
759 } else if (s
->num_timers
> HPET_MAX_TIMERS
) {
760 s
->num_timers
= HPET_MAX_TIMERS
;
762 for (i
= 0; i
< HPET_MAX_TIMERS
; i
++) {
763 timer
= &s
->timer
[i
];
764 timer
->qemu_timer
= timer_new_ns(QEMU_CLOCK_VIRTUAL
, hpet_timer
, timer
);
769 /* 64-bit main counter; LegacyReplacementRoute. */
770 s
->capability
= 0x8086a001ULL
;
771 s
->capability
|= (s
->num_timers
- 1) << HPET_ID_NUM_TIM_SHIFT
;
772 s
->capability
|= ((uint64_t)(HPET_CLK_PERIOD
* FS_PER_NS
) << 32);
774 qdev_init_gpio_in(dev
, hpet_handle_legacy_irq
, 2);
775 qdev_init_gpio_out(dev
, &s
->pit_enabled
, 1);
778 static Property hpet_device_properties
[] = {
779 DEFINE_PROP_UINT8("timers", HPETState
, num_timers
, HPET_MIN_TIMERS
),
780 DEFINE_PROP_BIT("msi", HPETState
, flags
, HPET_MSI_SUPPORT
, false),
781 DEFINE_PROP_UINT32(HPET_INTCAP
, HPETState
, intcap
, 0),
782 DEFINE_PROP_BOOL("hpet-offset-saved", HPETState
, hpet_offset_saved
, true),
783 DEFINE_PROP_END_OF_LIST(),
786 static void hpet_device_class_init(ObjectClass
*klass
, void *data
)
788 DeviceClass
*dc
= DEVICE_CLASS(klass
);
790 dc
->realize
= hpet_realize
;
791 dc
->reset
= hpet_reset
;
792 dc
->vmsd
= &vmstate_hpet
;
793 device_class_set_props(dc
, hpet_device_properties
);
796 static const TypeInfo hpet_device_info
= {
798 .parent
= TYPE_SYS_BUS_DEVICE
,
799 .instance_size
= sizeof(HPETState
),
800 .instance_init
= hpet_init
,
801 .class_init
= hpet_device_class_init
,
804 static void hpet_register_types(void)
806 type_register_static(&hpet_device_info
);
809 type_init(hpet_register_types
)