hw/apic.c

   1 /*
   2  *  APIC support
   3  *
   4  *  Copyright (c) 2004-2005 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>
  18  */
  19 #include "hw.h"
  20 #include "apic.h"
  21 #include "qemu-timer.h"
  22 #include "host-utils.h"
  23 #include "sysbus.h"
  24
  25 //#define DEBUG_APIC
  26 //#define DEBUG_COALESCING
  27
  28 #ifdef DEBUG_APIC
  29 #define DPRINTF(fmt, ...)                                       \
  30     do { printf("apic: " fmt , ## __VA_ARGS__); } while (0)
  31 #else
  32 #define DPRINTF(fmt, ...)
  33 #endif
  34
  35 #ifdef DEBUG_COALESCING
  36 #define DPRINTF_C(fmt, ...)                                     \
  37     do { printf("apic: " fmt , ## __VA_ARGS__); } while (0)
  38 #else
  39 #define DPRINTF_C(fmt, ...)
  40 #endif
  41
  42 /* APIC Local Vector Table */
  43 #define APIC_LVT_TIMER   0
  44 #define APIC_LVT_THERMAL 1
  45 #define APIC_LVT_PERFORM 2
  46 #define APIC_LVT_LINT0   3
  47 #define APIC_LVT_LINT1   4
  48 #define APIC_LVT_ERROR   5
  49 #define APIC_LVT_NB      6
  50
  51 /* APIC delivery modes */
  52 #define APIC_DM_FIXED   0
  53 #define APIC_DM_LOWPRI  1
  54 #define APIC_DM_SMI     2
  55 #define APIC_DM_NMI     4
  56 #define APIC_DM_INIT    5
  57 #define APIC_DM_SIPI    6
  58 #define APIC_DM_EXTINT  7
  59
  60 /* APIC destination mode */
  61 #define APIC_DESTMODE_FLAT      0xf
  62 #define APIC_DESTMODE_CLUSTER   1
  63
  64 #define APIC_TRIGGER_EDGE  0
  65 #define APIC_TRIGGER_LEVEL 1
  66
  67 #define APIC_LVT_TIMER_PERIODIC         (1<<17)
  68 #define APIC_LVT_MASKED                 (1<<16)
  69 #define APIC_LVT_LEVEL_TRIGGER          (1<<15)
  70 #define APIC_LVT_REMOTE_IRR             (1<<14)
  71 #define APIC_INPUT_POLARITY             (1<<13)
  72 #define APIC_SEND_PENDING               (1<<12)
  73
  74 #define ESR_ILLEGAL_ADDRESS (1 << 7)
  75
  76 #define APIC_SV_ENABLE (1 << 8)
  77
  78 #define MAX_APICS 255
  79 #define MAX_APIC_WORDS 8
  80
  81 /* Intel APIC constants: from include/asm/msidef.h */
  82 #define MSI_DATA_VECTOR_SHIFT           0
  83 #define MSI_DATA_VECTOR_MASK            0x000000ff
  84 #define MSI_DATA_DELIVERY_MODE_SHIFT    8
  85 #define MSI_DATA_TRIGGER_SHIFT          15
  86 #define MSI_DATA_LEVEL_SHIFT            14
  87 #define MSI_ADDR_DEST_MODE_SHIFT        2
  88 #define MSI_ADDR_DEST_ID_SHIFT          12
  89 #define MSI_ADDR_DEST_ID_MASK           0x00ffff0
  90
  91 #define MSI_ADDR_SIZE                   0x100000
  92
  93 typedef struct APICState APICState;
  94
  95 struct APICState {
  96     SysBusDevice busdev;
  97     void *cpu_env;
  98     uint32_t apicbase;
  99     uint8_t id;
 100     uint8_t arb_id;
 101     uint8_t tpr;
 102     uint32_t spurious_vec;
 103     uint8_t log_dest;
 104     uint8_t dest_mode;
 105     uint32_t isr[8];  /* in service register */
 106     uint32_t tmr[8];  /* trigger mode register */
 107     uint32_t irr[8]; /* interrupt request register */
 108     uint32_t lvt[APIC_LVT_NB];
 109     uint32_t esr; /* error register */
 110     uint32_t icr[2];
 111
 112     uint32_t divide_conf;
 113     int count_shift;
 114     uint32_t initial_count;
 115     int64_t initial_count_load_time, next_time;
 116     uint32_t idx;
 117     QEMUTimer *timer;
 118     int sipi_vector;
 119     int wait_for_sipi;
 120 };
 121
 122 static APICState *local_apics[MAX_APICS + 1];
 123 static int apic_irq_delivered;
 124
 125 static void apic_set_irq(APICState *s, int vector_num, int trigger_mode);
 126 static void apic_update_irq(APICState *s);
 127 static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask,
 128                                       uint8_t dest, uint8_t dest_mode);
 129
 130 /* Find first bit starting from msb */
 131 static int fls_bit(uint32_t value)
 132 {
 133     return 31 - clz32(value);
 134 }
 135
 136 /* Find first bit starting from lsb */
 137 static int ffs_bit(uint32_t value)
 138 {
 139     return ctz32(value);
 140 }
 141
 142 static inline void set_bit(uint32_t *tab, int index)
 143 {
 144     int i, mask;
 145     i = index >> 5;
 146     mask = 1 << (index & 0x1f);
 147     tab[i] |= mask;
 148 }
 149
 150 static inline void reset_bit(uint32_t *tab, int index)
 151 {
 152     int i, mask;
 153     i = index >> 5;
 154     mask = 1 << (index & 0x1f);
 155     tab[i] &= ~mask;
 156 }
 157
 158 static inline int get_bit(uint32_t *tab, int index)
 159 {
 160     int i, mask;
 161     i = index >> 5;
 162     mask = 1 << (index & 0x1f);
 163     return !!(tab[i] & mask);
 164 }
 165
 166 static void apic_local_deliver(APICState *s, int vector)
 167 {
 168     uint32_t lvt = s->lvt[vector];
 169     int trigger_mode;
 170
 171     DPRINTF("%s: vector %d delivery mode %d\n", __func__, vector,
 172             (lvt >> 8) & 7);
 173     if (lvt & APIC_LVT_MASKED)
 174         return;
 175
 176     switch ((lvt >> 8) & 7) {
 177     case APIC_DM_SMI:
 178         cpu_interrupt(s->cpu_env, CPU_INTERRUPT_SMI);
 179         break;
 180
 181     case APIC_DM_NMI:
 182         cpu_interrupt(s->cpu_env, CPU_INTERRUPT_NMI);
 183         break;
 184
 185     case APIC_DM_EXTINT:
 186         cpu_interrupt(s->cpu_env, CPU_INTERRUPT_HARD);
 187         break;
 188
 189     case APIC_DM_FIXED:
 190         trigger_mode = APIC_TRIGGER_EDGE;
 191         if ((vector == APIC_LVT_LINT0 || vector == APIC_LVT_LINT1) &&
 192             (lvt & APIC_LVT_LEVEL_TRIGGER))
 193             trigger_mode = APIC_TRIGGER_LEVEL;
 194         apic_set_irq(s, lvt & 0xff, trigger_mode);
 195     }
 196 }
 197
 198 void apic_deliver_pic_intr(DeviceState *d, int level)
 199 {
 200     APICState *s = DO_UPCAST(APICState, busdev.qdev, d);
 201
 202     if (level) {
 203         apic_local_deliver(s, APIC_LVT_LINT0);
 204     } else {
 205         uint32_t lvt = s->lvt[APIC_LVT_LINT0];
 206
 207         switch ((lvt >> 8) & 7) {
 208         case APIC_DM_FIXED:
 209             if (!(lvt & APIC_LVT_LEVEL_TRIGGER))
 210                 break;
 211             reset_bit(s->irr, lvt & 0xff);
 212             /* fall through */
 213         case APIC_DM_EXTINT:
 214             cpu_reset_interrupt(s->cpu_env, CPU_INTERRUPT_HARD);
 215             break;
 216         }
 217     }
 218 }
 219
 220 #define foreach_apic(apic, deliver_bitmask, code) \
 221 {\
 222     int __i, __j, __mask;\
 223     for(__i = 0; __i < MAX_APIC_WORDS; __i++) {\
 224         __mask = deliver_bitmask[__i];\
 225         if (__mask) {\
 226             for(__j = 0; __j < 32; __j++) {\
 227                 if (__mask & (1 << __j)) {\
 228                     apic = local_apics[__i * 32 + __j];\
 229                     if (apic) {\
 230                         code;\
 231                     }\
 232                 }\
 233             }\
 234         }\
 235     }\
 236 }
 237
 238 static void apic_bus_deliver(const uint32_t *deliver_bitmask,
 239                              uint8_t delivery_mode,
 240                              uint8_t vector_num, uint8_t polarity,
 241                              uint8_t trigger_mode)
 242 {
 243     APICState *apic_iter;
 244
 245     switch (delivery_mode) {
 246         case APIC_DM_LOWPRI:
 247             /* XXX: search for focus processor, arbitration */
 248             {
 249                 int i, d;
 250                 d = -1;
 251                 for(i = 0; i < MAX_APIC_WORDS; i++) {
 252                     if (deliver_bitmask[i]) {
 253                         d = i * 32 + ffs_bit(deliver_bitmask[i]);
 254                         break;
 255                     }
 256                 }
 257                 if (d >= 0) {
 258                     apic_iter = local_apics[d];
 259                     if (apic_iter) {
 260                         apic_set_irq(apic_iter, vector_num, trigger_mode);
 261                     }
 262                 }
 263             }
 264             return;
 265
 266         case APIC_DM_FIXED:
 267             break;
 268
 269         case APIC_DM_SMI:
 270             foreach_apic(apic_iter, deliver_bitmask,
 271                 cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT_SMI) );
 272             return;
 273
 274         case APIC_DM_NMI:
 275             foreach_apic(apic_iter, deliver_bitmask,
 276                 cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT_NMI) );
 277             return;
 278
 279         case APIC_DM_INIT:
 280             /* normal INIT IPI sent to processors */
 281             foreach_apic(apic_iter, deliver_bitmask,
 282                          cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT_INIT) );
 283             return;
 284
 285         case APIC_DM_EXTINT:
 286             /* handled in I/O APIC code */
 287             break;
 288
 289         default:
 290             return;
 291     }
 292
 293     foreach_apic(apic_iter, deliver_bitmask,
 294                  apic_set_irq(apic_iter, vector_num, trigger_mode) );
 295 }
 296
 297 void apic_deliver_irq(uint8_t dest, uint8_t dest_mode,
 298                       uint8_t delivery_mode, uint8_t vector_num,
 299                       uint8_t polarity, uint8_t trigger_mode)
 300 {
 301     uint32_t deliver_bitmask[MAX_APIC_WORDS];
 302
 303     DPRINTF("%s: dest %d dest_mode %d delivery_mode %d vector %d"
 304             " polarity %d trigger_mode %d\n", __func__, dest, dest_mode,
 305             delivery_mode, vector_num, polarity, trigger_mode);
 306     apic_get_delivery_bitmask(deliver_bitmask, dest, dest_mode);
 307     apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, polarity,
 308                      trigger_mode);
 309 }
 310
 311 void cpu_set_apic_base(DeviceState *d, uint64_t val)
 312 {
 313     APICState *s = DO_UPCAST(APICState, busdev.qdev, d);
 314
 315     DPRINTF("cpu_set_apic_base: %016" PRIx64 "\n", val);
 316     if (!s)
 317         return;
 318     s->apicbase = (val & 0xfffff000) |
 319         (s->apicbase & (MSR_IA32_APICBASE_BSP | MSR_IA32_APICBASE_ENABLE));
 320     /* if disabled, cannot be enabled again */
 321     if (!(val & MSR_IA32_APICBASE_ENABLE)) {
 322         s->apicbase &= ~MSR_IA32_APICBASE_ENABLE;
 323         cpu_clear_apic_feature(s->cpu_env);
 324         s->spurious_vec &= ~APIC_SV_ENABLE;
 325     }
 326 }
 327
 328 uint64_t cpu_get_apic_base(DeviceState *d)
 329 {
 330     APICState *s = DO_UPCAST(APICState, busdev.qdev, d);
 331
 332     DPRINTF("cpu_get_apic_base: %016" PRIx64 "\n",
 333             s ? (uint64_t)s->apicbase: 0);
 334     return s ? s->apicbase : 0;
 335 }
 336
 337 void cpu_set_apic_tpr(DeviceState *d, uint8_t val)
 338 {
 339     APICState *s = DO_UPCAST(APICState, busdev.qdev, d);
 340
 341     if (!s)
 342         return;
 343     s->tpr = (val & 0x0f) << 4;
 344     apic_update_irq(s);
 345 }
 346
 347 uint8_t cpu_get_apic_tpr(DeviceState *d)
 348 {
 349     APICState *s = DO_UPCAST(APICState, busdev.qdev, d);
 350
 351     return s ? s->tpr >> 4 : 0;
 352 }
 353
 354 /* return -1 if no bit is set */
 355 static int get_highest_priority_int(uint32_t *tab)
 356 {
 357     int i;
 358     for(i = 7; i >= 0; i--) {
 359         if (tab[i] != 0) {
 360             return i * 32 + fls_bit(tab[i]);
 361         }
 362     }
 363     return -1;
 364 }
 365
 366 static int apic_get_ppr(APICState *s)
 367 {
 368     int tpr, isrv, ppr;
 369
 370     tpr = (s->tpr >> 4);
 371     isrv = get_highest_priority_int(s->isr);
 372     if (isrv < 0)
 373         isrv = 0;
 374     isrv >>= 4;
 375     if (tpr >= isrv)
 376         ppr = s->tpr;
 377     else
 378         ppr = isrv << 4;
 379     return ppr;
 380 }
 381
 382 static int apic_get_arb_pri(APICState *s)
 383 {
 384     /* XXX: arbitration */
 385     return 0;
 386 }
 387
 388 /* signal the CPU if an irq is pending */
 389 static void apic_update_irq(APICState *s)
 390 {
 391     int irrv, ppr;
 392     if (!(s->spurious_vec & APIC_SV_ENABLE))
 393         return;
 394     irrv = get_highest_priority_int(s->irr);
 395     if (irrv < 0)
 396         return;
 397     ppr = apic_get_ppr(s);
 398     if (ppr && (irrv & 0xf0) <= (ppr & 0xf0))
 399         return;
 400     cpu_interrupt(s->cpu_env, CPU_INTERRUPT_HARD);
 401 }
 402
 403 void apic_reset_irq_delivered(void)
 404 {
 405     DPRINTF_C("%s: old coalescing %d\n", __func__, apic_irq_delivered);
 406     apic_irq_delivered = 0;
 407 }
 408
 409 int apic_get_irq_delivered(void)
 410 {
 411     DPRINTF_C("%s: returning coalescing %d\n", __func__, apic_irq_delivered);
 412     return apic_irq_delivered;
 413 }
 414
 415 static void apic_set_irq(APICState *s, int vector_num, int trigger_mode)
 416 {
 417     apic_irq_delivered += !get_bit(s->irr, vector_num);
 418     DPRINTF_C("%s: coalescing %d\n", __func__, apic_irq_delivered);
 419
 420     set_bit(s->irr, vector_num);
 421     if (trigger_mode)
 422         set_bit(s->tmr, vector_num);
 423     else
 424         reset_bit(s->tmr, vector_num);
 425     apic_update_irq(s);
 426 }
 427
 428 static void apic_eoi(APICState *s)
 429 {
 430     int isrv;
 431     isrv = get_highest_priority_int(s->isr);
 432     if (isrv < 0)
 433         return;
 434     reset_bit(s->isr, isrv);
 435     /* XXX: send the EOI packet to the APIC bus to allow the I/O APIC to
 436             set the remote IRR bit for level triggered interrupts. */
 437     apic_update_irq(s);
 438 }
 439
 440 static int apic_find_dest(uint8_t dest)
 441 {
 442     APICState *apic = local_apics[dest];
 443     int i;
 444
 445     if (apic && apic->id == dest)
 446         return dest;  /* shortcut in case apic->id == apic->idx */
 447
 448     for (i = 0; i < MAX_APICS; i++) {
 449         apic = local_apics[i];
 450         if (apic && apic->id == dest)
 451             return i;
 452     }
 453
 454     return -1;
 455 }
 456
 457 static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask,
 458                                       uint8_t dest, uint8_t dest_mode)
 459 {
 460     APICState *apic_iter;
 461     int i;
 462
 463     if (dest_mode == 0) {
 464         if (dest == 0xff) {
 465             memset(deliver_bitmask, 0xff, MAX_APIC_WORDS * sizeof(uint32_t));
 466         } else {
 467             int idx = apic_find_dest(dest);
 468             memset(deliver_bitmask, 0x00, MAX_APIC_WORDS * sizeof(uint32_t));
 469             if (idx >= 0)
 470                 set_bit(deliver_bitmask, idx);
 471         }
 472     } else {
 473         /* XXX: cluster mode */
 474         memset(deliver_bitmask, 0x00, MAX_APIC_WORDS * sizeof(uint32_t));
 475         for(i = 0; i < MAX_APICS; i++) {
 476             apic_iter = local_apics[i];
 477             if (apic_iter) {
 478                 if (apic_iter->dest_mode == 0xf) {
 479                     if (dest & apic_iter->log_dest)
 480                         set_bit(deliver_bitmask, i);
 481                 } else if (apic_iter->dest_mode == 0x0) {
 482                     if ((dest & 0xf0) == (apic_iter->log_dest & 0xf0) &&
 483                         (dest & apic_iter->log_dest & 0x0f)) {
 484                         set_bit(deliver_bitmask, i);
 485                     }
 486                 }
 487             }
 488         }
 489     }
 490 }
 491
 492 void apic_init_reset(DeviceState *d)
 493 {
 494     APICState *s = DO_UPCAST(APICState, busdev.qdev, d);
 495     int i;
 496
 497     if (!s)
 498         return;
 499
 500     s->tpr = 0;
 501     s->spurious_vec = 0xff;
 502     s->log_dest = 0;
 503     s->dest_mode = 0xf;
 504     memset(s->isr, 0, sizeof(s->isr));
 505     memset(s->tmr, 0, sizeof(s->tmr));
 506     memset(s->irr, 0, sizeof(s->irr));
 507     for(i = 0; i < APIC_LVT_NB; i++)
 508         s->lvt[i] = 1 << 16; /* mask LVT */
 509     s->esr = 0;
 510     memset(s->icr, 0, sizeof(s->icr));
 511     s->divide_conf = 0;
 512     s->count_shift = 0;
 513     s->initial_count = 0;
 514     s->initial_count_load_time = 0;
 515     s->next_time = 0;
 516     s->wait_for_sipi = 1;
 517 }
 518
 519 static void apic_startup(APICState *s, int vector_num)
 520 {
 521     s->sipi_vector = vector_num;
 522     cpu_interrupt(s->cpu_env, CPU_INTERRUPT_SIPI);
 523 }
 524
 525 void apic_sipi(DeviceState *d)
 526 {
 527     APICState *s = DO_UPCAST(APICState, busdev.qdev, d);
 528
 529     cpu_reset_interrupt(s->cpu_env, CPU_INTERRUPT_SIPI);
 530
 531     if (!s->wait_for_sipi)
 532         return;
 533     cpu_x86_load_seg_cache_sipi(s->cpu_env, s->sipi_vector);
 534     s->wait_for_sipi = 0;
 535 }
 536
 537 static void apic_deliver(DeviceState *d, uint8_t dest, uint8_t dest_mode,
 538                          uint8_t delivery_mode, uint8_t vector_num,
 539                          uint8_t polarity, uint8_t trigger_mode)
 540 {
 541     APICState *s = DO_UPCAST(APICState, busdev.qdev, d);
 542     uint32_t deliver_bitmask[MAX_APIC_WORDS];
 543     int dest_shorthand = (s->icr[0] >> 18) & 3;
 544     APICState *apic_iter;
 545
 546     switch (dest_shorthand) {
 547     case 0:
 548         apic_get_delivery_bitmask(deliver_bitmask, dest, dest_mode);
 549         break;
 550     case 1:
 551         memset(deliver_bitmask, 0x00, sizeof(deliver_bitmask));
 552         set_bit(deliver_bitmask, s->idx);
 553         break;
 554     case 2:
 555         memset(deliver_bitmask, 0xff, sizeof(deliver_bitmask));
 556         break;
 557     case 3:
 558         memset(deliver_bitmask, 0xff, sizeof(deliver_bitmask));
 559         reset_bit(deliver_bitmask, s->idx);
 560         break;
 561     }
 562
 563     switch (delivery_mode) {
 564         case APIC_DM_INIT:
 565             {
 566                 int trig_mode = (s->icr[0] >> 15) & 1;
 567                 int level = (s->icr[0] >> 14) & 1;
 568                 if (level == 0 && trig_mode == 1) {
 569                     foreach_apic(apic_iter, deliver_bitmask,
 570                                  apic_iter->arb_id = apic_iter->id );
 571                     return;
 572                 }
 573             }
 574             break;
 575
 576         case APIC_DM_SIPI:
 577             foreach_apic(apic_iter, deliver_bitmask,
 578                          apic_startup(apic_iter, vector_num) );
 579             return;
 580     }
 581
 582     apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, polarity,
 583                      trigger_mode);
 584 }
 585
 586 int apic_get_interrupt(DeviceState *d)
 587 {
 588     APICState *s = DO_UPCAST(APICState, busdev.qdev, d);
 589     int intno;
 590
 591     /* if the APIC is installed or enabled, we let the 8259 handle the
 592        IRQs */
 593     if (!s)
 594         return -1;
 595     if (!(s->spurious_vec & APIC_SV_ENABLE))
 596         return -1;
 597
 598     /* XXX: spurious IRQ handling */
 599     intno = get_highest_priority_int(s->irr);
 600     if (intno < 0)
 601         return -1;
 602     if (s->tpr && intno <= s->tpr)
 603         return s->spurious_vec & 0xff;
 604     reset_bit(s->irr, intno);
 605     set_bit(s->isr, intno);
 606     apic_update_irq(s);
 607     return intno;
 608 }
 609
 610 int apic_accept_pic_intr(DeviceState *d)
 611 {
 612     APICState *s = DO_UPCAST(APICState, busdev.qdev, d);
 613     uint32_t lvt0;
 614
 615     if (!s)
 616         return -1;
 617
 618     lvt0 = s->lvt[APIC_LVT_LINT0];
 619
 620     if ((s->apicbase & MSR_IA32_APICBASE_ENABLE) == 0 ||
 621         (lvt0 & APIC_LVT_MASKED) == 0)
 622         return 1;
 623
 624     return 0;
 625 }
 626
 627 static uint32_t apic_get_current_count(APICState *s)
 628 {
 629     int64_t d;
 630     uint32_t val;
 631     d = (qemu_get_clock(vm_clock) - s->initial_count_load_time) >>
 632         s->count_shift;
 633     if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
 634         /* periodic */
 635         val = s->initial_count - (d % ((uint64_t)s->initial_count + 1));
 636     } else {
 637         if (d >= s->initial_count)
 638             val = 0;
 639         else
 640             val = s->initial_count - d;
 641     }
 642     return val;
 643 }
 644
 645 static void apic_timer_update(APICState *s, int64_t current_time)
 646 {
 647     int64_t next_time, d;
 648
 649     if (!(s->lvt[APIC_LVT_TIMER] & APIC_LVT_MASKED)) {
 650         d = (current_time - s->initial_count_load_time) >>
 651             s->count_shift;
 652         if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
 653             if (!s->initial_count)
 654                 goto no_timer;
 655             d = ((d / ((uint64_t)s->initial_count + 1)) + 1) * ((uint64_t)s->initial_count + 1);
 656         } else {
 657             if (d >= s->initial_count)
 658                 goto no_timer;
 659             d = (uint64_t)s->initial_count + 1;
 660         }
 661         next_time = s->initial_count_load_time + (d << s->count_shift);
 662         qemu_mod_timer(s->timer, next_time);
 663         s->next_time = next_time;
 664     } else {
 665     no_timer:
 666         qemu_del_timer(s->timer);
 667     }
 668 }
 669
 670 static void apic_timer(void *opaque)
 671 {
 672     APICState *s = opaque;
 673
 674     apic_local_deliver(s, APIC_LVT_TIMER);
 675     apic_timer_update(s, s->next_time);
 676 }
 677
 678 static uint32_t apic_mem_readb(void *opaque, target_phys_addr_t addr)
 679 {
 680     return 0;
 681 }
 682
 683 static uint32_t apic_mem_readw(void *opaque, target_phys_addr_t addr)
 684 {
 685     return 0;
 686 }
 687
 688 static void apic_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
 689 {
 690 }
 691
 692 static void apic_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
 693 {
 694 }
 695
 696 static uint32_t apic_mem_readl(void *opaque, target_phys_addr_t addr)
 697 {
 698     DeviceState *d;
 699     APICState *s;
 700     uint32_t val;
 701     int index;
 702
 703     d = cpu_get_current_apic();
 704     if (!d) {
 705         return 0;
 706     }
 707     s = DO_UPCAST(APICState, busdev.qdev, d);
 708
 709     index = (addr >> 4) & 0xff;
 710     switch(index) {
 711     case 0x02: /* id */
 712         val = s->id << 24;
 713         break;
 714     case 0x03: /* version */
 715         val = 0x11 | ((APIC_LVT_NB - 1) << 16); /* version 0x11 */
 716         break;
 717     case 0x08:
 718         val = s->tpr;
 719         break;
 720     case 0x09:
 721         val = apic_get_arb_pri(s);
 722         break;
 723     case 0x0a:
 724         /* ppr */
 725         val = apic_get_ppr(s);
 726         break;
 727     case 0x0b:
 728         val = 0;
 729         break;
 730     case 0x0d:
 731         val = s->log_dest << 24;
 732         break;
 733     case 0x0e:
 734         val = s->dest_mode << 28;
 735         break;
 736     case 0x0f:
 737         val = s->spurious_vec;
 738         break;
 739     case 0x10 ... 0x17:
 740         val = s->isr[index & 7];
 741         break;
 742     case 0x18 ... 0x1f:
 743         val = s->tmr[index & 7];
 744         break;
 745     case 0x20 ... 0x27:
 746         val = s->irr[index & 7];
 747         break;
 748     case 0x28:
 749         val = s->esr;
 750         break;
 751     case 0x30:
 752     case 0x31:
 753         val = s->icr[index & 1];
 754         break;
 755     case 0x32 ... 0x37:
 756         val = s->lvt[index - 0x32];
 757         break;
 758     case 0x38:
 759         val = s->initial_count;
 760         break;
 761     case 0x39:
 762         val = apic_get_current_count(s);
 763         break;
 764     case 0x3e:
 765         val = s->divide_conf;
 766         break;
 767     default:
 768         s->esr |= ESR_ILLEGAL_ADDRESS;
 769         val = 0;
 770         break;
 771     }
 772     DPRINTF("read: " TARGET_FMT_plx " = %08x\n", addr, val);
 773     return val;
 774 }
 775
 776 static void apic_send_msi(target_phys_addr_t addr, uint32 data)
 777 {
 778     uint8_t dest = (addr & MSI_ADDR_DEST_ID_MASK) >> MSI_ADDR_DEST_ID_SHIFT;
 779     uint8_t vector = (data & MSI_DATA_VECTOR_MASK) >> MSI_DATA_VECTOR_SHIFT;
 780     uint8_t dest_mode = (addr >> MSI_ADDR_DEST_MODE_SHIFT) & 0x1;
 781     uint8_t trigger_mode = (data >> MSI_DATA_TRIGGER_SHIFT) & 0x1;
 782     uint8_t delivery = (data >> MSI_DATA_DELIVERY_MODE_SHIFT) & 0x7;
 783     /* XXX: Ignore redirection hint. */
 784     apic_deliver_irq(dest, dest_mode, delivery, vector, 0, trigger_mode);
 785 }
 786
 787 static void apic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
 788 {
 789     DeviceState *d;
 790     APICState *s;
 791     int index = (addr >> 4) & 0xff;
 792     if (addr > 0xfff || !index) {
 793         /* MSI and MMIO APIC are at the same memory location,
 794          * but actually not on the global bus: MSI is on PCI bus
 795          * APIC is connected directly to the CPU.
 796          * Mapping them on the global bus happens to work because
 797          * MSI registers are reserved in APIC MMIO and vice versa. */
 798         apic_send_msi(addr, val);
 799         return;
 800     }
 801
 802     d = cpu_get_current_apic();
 803     if (!d) {
 804         return;
 805     }
 806     s = DO_UPCAST(APICState, busdev.qdev, d);
 807
 808     DPRINTF("write: " TARGET_FMT_plx " = %08x\n", addr, val);
 809
 810     switch(index) {
 811     case 0x02:
 812         s->id = (val >> 24);
 813         break;
 814     case 0x03:
 815         break;
 816     case 0x08:
 817         s->tpr = val;
 818         apic_update_irq(s);
 819         break;
 820     case 0x09:
 821     case 0x0a:
 822         break;
 823     case 0x0b: /* EOI */
 824         apic_eoi(s);
 825         break;
 826     case 0x0d:
 827         s->log_dest = val >> 24;
 828         break;
 829     case 0x0e:
 830         s->dest_mode = val >> 28;
 831         break;
 832     case 0x0f:
 833         s->spurious_vec = val & 0x1ff;
 834         apic_update_irq(s);
 835         break;
 836     case 0x10 ... 0x17:
 837     case 0x18 ... 0x1f:
 838     case 0x20 ... 0x27:
 839     case 0x28:
 840         break;
 841     case 0x30:
 842         s->icr[0] = val;
 843         apic_deliver(d, (s->icr[1] >> 24) & 0xff, (s->icr[0] >> 11) & 1,
 844                      (s->icr[0] >> 8) & 7, (s->icr[0] & 0xff),
 845                      (s->icr[0] >> 14) & 1, (s->icr[0] >> 15) & 1);
 846         break;
 847     case 0x31:
 848         s->icr[1] = val;
 849         break;
 850     case 0x32 ... 0x37:
 851         {
 852             int n = index - 0x32;
 853             s->lvt[n] = val;
 854             if (n == APIC_LVT_TIMER)
 855                 apic_timer_update(s, qemu_get_clock(vm_clock));
 856         }
 857         break;
 858     case 0x38:
 859         s->initial_count = val;
 860         s->initial_count_load_time = qemu_get_clock(vm_clock);
 861         apic_timer_update(s, s->initial_count_load_time);
 862         break;
 863     case 0x39:
 864         break;
 865     case 0x3e:
 866         {
 867             int v;
 868             s->divide_conf = val & 0xb;
 869             v = (s->divide_conf & 3) | ((s->divide_conf >> 1) & 4);
 870             s->count_shift = (v + 1) & 7;
 871         }
 872         break;
 873     default:
 874         s->esr |= ESR_ILLEGAL_ADDRESS;
 875         break;
 876     }
 877 }
 878
 879 /* This function is only used for old state version 1 and 2 */
 880 static int apic_load_old(QEMUFile *f, void *opaque, int version_id)
 881 {
 882     APICState *s = opaque;
 883     int i;
 884
 885     if (version_id > 2)
 886         return -EINVAL;
 887
 888     /* XXX: what if the base changes? (registered memory regions) */
 889     qemu_get_be32s(f, &s->apicbase);
 890     qemu_get_8s(f, &s->id);
 891     qemu_get_8s(f, &s->arb_id);
 892     qemu_get_8s(f, &s->tpr);
 893     qemu_get_be32s(f, &s->spurious_vec);
 894     qemu_get_8s(f, &s->log_dest);
 895     qemu_get_8s(f, &s->dest_mode);
 896     for (i = 0; i < 8; i++) {
 897         qemu_get_be32s(f, &s->isr[i]);
 898         qemu_get_be32s(f, &s->tmr[i]);
 899         qemu_get_be32s(f, &s->irr[i]);
 900     }
 901     for (i = 0; i < APIC_LVT_NB; i++) {
 902         qemu_get_be32s(f, &s->lvt[i]);
 903     }
 904     qemu_get_be32s(f, &s->esr);
 905     qemu_get_be32s(f, &s->icr[0]);
 906     qemu_get_be32s(f, &s->icr[1]);
 907     qemu_get_be32s(f, &s->divide_conf);
 908     s->count_shift=qemu_get_be32(f);
 909     qemu_get_be32s(f, &s->initial_count);
 910     s->initial_count_load_time=qemu_get_be64(f);
 911     s->next_time=qemu_get_be64(f);
 912
 913     if (version_id >= 2)
 914         qemu_get_timer(f, s->timer);
 915     return 0;
 916 }
 917
 918 static const VMStateDescription vmstate_apic = {
 919     .name = "apic",
 920     .version_id = 3,
 921     .minimum_version_id = 3,
 922     .minimum_version_id_old = 1,
 923     .load_state_old = apic_load_old,
 924     .fields      = (VMStateField []) {
 925         VMSTATE_UINT32(apicbase, APICState),
 926         VMSTATE_UINT8(id, APICState),
 927         VMSTATE_UINT8(arb_id, APICState),
 928         VMSTATE_UINT8(tpr, APICState),
 929         VMSTATE_UINT32(spurious_vec, APICState),
 930         VMSTATE_UINT8(log_dest, APICState),
 931         VMSTATE_UINT8(dest_mode, APICState),
 932         VMSTATE_UINT32_ARRAY(isr, APICState, 8),
 933         VMSTATE_UINT32_ARRAY(tmr, APICState, 8),
 934         VMSTATE_UINT32_ARRAY(irr, APICState, 8),
 935         VMSTATE_UINT32_ARRAY(lvt, APICState, APIC_LVT_NB),
 936         VMSTATE_UINT32(esr, APICState),
 937         VMSTATE_UINT32_ARRAY(icr, APICState, 2),
 938         VMSTATE_UINT32(divide_conf, APICState),
 939         VMSTATE_INT32(count_shift, APICState),
 940         VMSTATE_UINT32(initial_count, APICState),
 941         VMSTATE_INT64(initial_count_load_time, APICState),
 942         VMSTATE_INT64(next_time, APICState),
 943         VMSTATE_TIMER(timer, APICState),
 944         VMSTATE_END_OF_LIST()
 945     }
 946 };
 947
 948 static void apic_reset(DeviceState *d)
 949 {
 950     APICState *s = DO_UPCAST(APICState, busdev.qdev, d);
 951     int bsp;
 952
 953     bsp = cpu_is_bsp(s->cpu_env);
 954     s->apicbase = 0xfee00000 |
 955         (bsp ? MSR_IA32_APICBASE_BSP : 0) | MSR_IA32_APICBASE_ENABLE;
 956
 957     apic_init_reset(d);
 958
 959     if (bsp) {
 960         /*
 961          * LINT0 delivery mode on CPU #0 is set to ExtInt at initialization
 962          * time typically by BIOS, so PIC interrupt can be delivered to the
 963          * processor when local APIC is enabled.
 964          */
 965         s->lvt[APIC_LVT_LINT0] = 0x700;
 966     }
 967 }
 968
 969 static CPUReadMemoryFunc * const apic_mem_read[3] = {
 970     apic_mem_readb,
 971     apic_mem_readw,
 972     apic_mem_readl,
 973 };
 974
 975 static CPUWriteMemoryFunc * const apic_mem_write[3] = {
 976     apic_mem_writeb,
 977     apic_mem_writew,
 978     apic_mem_writel,
 979 };
 980
 981 static int apic_init1(SysBusDevice *dev)
 982 {
 983     APICState *s = FROM_SYSBUS(APICState, dev);
 984     int apic_io_memory;
 985     static int last_apic_idx;
 986
 987     if (last_apic_idx >= MAX_APICS) {
 988         return -1;
 989     }
 990     apic_io_memory = cpu_register_io_memory(apic_mem_read,
 991                                             apic_mem_write, NULL);
 992     sysbus_init_mmio(dev, MSI_ADDR_SIZE, apic_io_memory);
 993
 994     s->timer = qemu_new_timer(vm_clock, apic_timer, s);
 995     s->idx = last_apic_idx++;
 996     local_apics[s->idx] = s;
 997     return 0;
 998 }
 999
1000 static SysBusDeviceInfo apic_info = {
1001     .init = apic_init1,
1002     .qdev.name = "apic",
1003     .qdev.size = sizeof(APICState),
1004     .qdev.vmsd = &vmstate_apic,
1005     .qdev.reset = apic_reset,
1006     .qdev.no_user = 1,
1007     .qdev.props = (Property[]) {
1008         DEFINE_PROP_UINT8("id", APICState, id, -1),
1009         DEFINE_PROP_PTR("cpu_env", APICState, cpu_env),
1010         DEFINE_PROP_END_OF_LIST(),
1011     }
1012 };
1013
1014 static void apic_register_devices(void)
1015 {
1016     sysbus_register_withprop(&apic_info);
1017 }
1018
1019 device_init(apic_register_devices)