target-arm/helper.c

   1 #include "cpu.h"
   2 #include "internals.h"
   3 #include "exec/gdbstub.h"
   4 #include "exec/helper-proto.h"
   5 #include "qemu/host-utils.h"
   6 #include "sysemu/arch_init.h"
   7 #include "sysemu/sysemu.h"
   8 #include "qemu/bitops.h"
   9 #include "qemu/crc32c.h"
  10 #include "exec/cpu_ldst.h"
  11 #include "arm_ldst.h"
  12 #include <zlib.h> /* For crc32 */
  13
  14 #ifndef CONFIG_USER_ONLY
  15 static inline int get_phys_addr(CPUARMState *env, target_ulong address,
  16                                 int access_type, int is_user,
  17                                 hwaddr *phys_ptr, int *prot,
  18                                 target_ulong *page_size);
  19
  20 /* Definitions for the PMCCNTR and PMCR registers */
  21 #define PMCRD   0x8
  22 #define PMCRC   0x4
  23 #define PMCRE   0x1
  24 #endif
  25
  26 static int vfp_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg)
  27 {
  28     int nregs;
  29
  30     /* VFP data registers are always little-endian.  */
  31     nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16;
  32     if (reg < nregs) {
  33         stfq_le_p(buf, env->vfp.regs[reg]);
  34         return 8;
  35     }
  36     if (arm_feature(env, ARM_FEATURE_NEON)) {
  37         /* Aliases for Q regs.  */
  38         nregs += 16;
  39         if (reg < nregs) {
  40             stfq_le_p(buf, env->vfp.regs[(reg - 32) * 2]);
  41             stfq_le_p(buf + 8, env->vfp.regs[(reg - 32) * 2 + 1]);
  42             return 16;
  43         }
  44     }
  45     switch (reg - nregs) {
  46     case 0: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSID]); return 4;
  47     case 1: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSCR]); return 4;
  48     case 2: stl_p(buf, env->vfp.xregs[ARM_VFP_FPEXC]); return 4;
  49     }
  50     return 0;
  51 }
  52
  53 static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
  54 {
  55     int nregs;
  56
  57     nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16;
  58     if (reg < nregs) {
  59         env->vfp.regs[reg] = ldfq_le_p(buf);
  60         return 8;
  61     }
  62     if (arm_feature(env, ARM_FEATURE_NEON)) {
  63         nregs += 16;
  64         if (reg < nregs) {
  65             env->vfp.regs[(reg - 32) * 2] = ldfq_le_p(buf);
  66             env->vfp.regs[(reg - 32) * 2 + 1] = ldfq_le_p(buf + 8);
  67             return 16;
  68         }
  69     }
  70     switch (reg - nregs) {
  71     case 0: env->vfp.xregs[ARM_VFP_FPSID] = ldl_p(buf); return 4;
  72     case 1: env->vfp.xregs[ARM_VFP_FPSCR] = ldl_p(buf); return 4;
  73     case 2: env->vfp.xregs[ARM_VFP_FPEXC] = ldl_p(buf) & (1 << 30); return 4;
  74     }
  75     return 0;
  76 }
  77
  78 static int aarch64_fpu_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg)
  79 {
  80     switch (reg) {
  81     case 0 ... 31:
  82         /* 128 bit FP register */
  83         stfq_le_p(buf, env->vfp.regs[reg * 2]);
  84         stfq_le_p(buf + 8, env->vfp.regs[reg * 2 + 1]);
  85         return 16;
  86     case 32:
  87         /* FPSR */
  88         stl_p(buf, vfp_get_fpsr(env));
  89         return 4;
  90     case 33:
  91         /* FPCR */
  92         stl_p(buf, vfp_get_fpcr(env));
  93         return 4;
  94     default:
  95         return 0;
  96     }
  97 }
  98
  99 static int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
 100 {
 101     switch (reg) {
 102     case 0 ... 31:
 103         /* 128 bit FP register */
 104         env->vfp.regs[reg * 2] = ldfq_le_p(buf);
 105         env->vfp.regs[reg * 2 + 1] = ldfq_le_p(buf + 8);
 106         return 16;
 107     case 32:
 108         /* FPSR */
 109         vfp_set_fpsr(env, ldl_p(buf));
 110         return 4;
 111     case 33:
 112         /* FPCR */
 113         vfp_set_fpcr(env, ldl_p(buf));
 114         return 4;
 115     default:
 116         return 0;
 117     }
 118 }
 119
 120 static uint64_t raw_read(CPUARMState *env, const ARMCPRegInfo *ri)
 121 {
 122     if (cpreg_field_is_64bit(ri)) {
 123         return CPREG_FIELD64(env, ri);
 124     } else {
 125         return CPREG_FIELD32(env, ri);
 126     }
 127 }
 128
 129 static void raw_write(CPUARMState *env, const ARMCPRegInfo *ri,
 130                       uint64_t value)
 131 {
 132     if (cpreg_field_is_64bit(ri)) {
 133         CPREG_FIELD64(env, ri) = value;
 134     } else {
 135         CPREG_FIELD32(env, ri) = value;
 136     }
 137 }
 138
 139 static uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri)
 140 {
 141     /* Raw read of a coprocessor register (as needed for migration, etc). */
 142     if (ri->type & ARM_CP_CONST) {
 143         return ri->resetvalue;
 144     } else if (ri->raw_readfn) {
 145         return ri->raw_readfn(env, ri);
 146     } else if (ri->readfn) {
 147         return ri->readfn(env, ri);
 148     } else {
 149         return raw_read(env, ri);
 150     }
 151 }
 152
 153 static void write_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri,
 154                              uint64_t v)
 155 {
 156     /* Raw write of a coprocessor register (as needed for migration, etc).
 157      * Note that constant registers are treated as write-ignored; the
 158      * caller should check for success by whether a readback gives the
 159      * value written.
 160      */
 161     if (ri->type & ARM_CP_CONST) {
 162         return;
 163     } else if (ri->raw_writefn) {
 164         ri->raw_writefn(env, ri, v);
 165     } else if (ri->writefn) {
 166         ri->writefn(env, ri, v);
 167     } else {
 168         raw_write(env, ri, v);
 169     }
 170 }
 171
 172 bool write_cpustate_to_list(ARMCPU *cpu)
 173 {
 174     /* Write the coprocessor state from cpu->env to the (index,value) list. */
 175     int i;
 176     bool ok = true;
 177
 178     for (i = 0; i < cpu->cpreg_array_len; i++) {
 179         uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]);
 180         const ARMCPRegInfo *ri;
 181
 182         ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
 183         if (!ri) {
 184             ok = false;
 185             continue;
 186         }
 187         if (ri->type & ARM_CP_NO_MIGRATE) {
 188             continue;
 189         }
 190         cpu->cpreg_values[i] = read_raw_cp_reg(&cpu->env, ri);
 191     }
 192     return ok;
 193 }
 194
 195 bool write_list_to_cpustate(ARMCPU *cpu)
 196 {
 197     int i;
 198     bool ok = true;
 199
 200     for (i = 0; i < cpu->cpreg_array_len; i++) {
 201         uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]);
 202         uint64_t v = cpu->cpreg_values[i];
 203         const ARMCPRegInfo *ri;
 204
 205         ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
 206         if (!ri) {
 207             ok = false;
 208             continue;
 209         }
 210         if (ri->type & ARM_CP_NO_MIGRATE) {
 211             continue;
 212         }
 213         /* Write value and confirm it reads back as written
 214          * (to catch read-only registers and partially read-only
 215          * registers where the incoming migration value doesn't match)
 216          */
 217         write_raw_cp_reg(&cpu->env, ri, v);
 218         if (read_raw_cp_reg(&cpu->env, ri) != v) {
 219             ok = false;
 220         }
 221     }
 222     return ok;
 223 }
 224
 225 static void add_cpreg_to_list(gpointer key, gpointer opaque)
 226 {
 227     ARMCPU *cpu = opaque;
 228     uint64_t regidx;
 229     const ARMCPRegInfo *ri;
 230
 231     regidx = *(uint32_t *)key;
 232     ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
 233
 234     if (!(ri->type & ARM_CP_NO_MIGRATE)) {
 235         cpu->cpreg_indexes[cpu->cpreg_array_len] = cpreg_to_kvm_id(regidx);
 236         /* The value array need not be initialized at this point */
 237         cpu->cpreg_array_len++;
 238     }
 239 }
 240
 241 static void count_cpreg(gpointer key, gpointer opaque)
 242 {
 243     ARMCPU *cpu = opaque;
 244     uint64_t regidx;
 245     const ARMCPRegInfo *ri;
 246
 247     regidx = *(uint32_t *)key;
 248     ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
 249
 250     if (!(ri->type & ARM_CP_NO_MIGRATE)) {
 251         cpu->cpreg_array_len++;
 252     }
 253 }
 254
 255 static gint cpreg_key_compare(gconstpointer a, gconstpointer b)
 256 {
 257     uint64_t aidx = cpreg_to_kvm_id(*(uint32_t *)a);
 258     uint64_t bidx = cpreg_to_kvm_id(*(uint32_t *)b);
 259
 260     if (aidx > bidx) {
 261         return 1;
 262     }
 263     if (aidx < bidx) {
 264         return -1;
 265     }
 266     return 0;
 267 }
 268
 269 static void cpreg_make_keylist(gpointer key, gpointer value, gpointer udata)
 270 {
 271     GList **plist = udata;
 272
 273     *plist = g_list_prepend(*plist, key);
 274 }
 275
 276 void init_cpreg_list(ARMCPU *cpu)
 277 {
 278     /* Initialise the cpreg_tuples[] array based on the cp_regs hash.
 279      * Note that we require cpreg_tuples[] to be sorted by key ID.
 280      */
 281     GList *keys = NULL;
 282     int arraylen;
 283
 284     g_hash_table_foreach(cpu->cp_regs, cpreg_make_keylist, &keys);
 285
 286     keys = g_list_sort(keys, cpreg_key_compare);
 287
 288     cpu->cpreg_array_len = 0;
 289
 290     g_list_foreach(keys, count_cpreg, cpu);
 291
 292     arraylen = cpu->cpreg_array_len;
 293     cpu->cpreg_indexes = g_new(uint64_t, arraylen);
 294     cpu->cpreg_values = g_new(uint64_t, arraylen);
 295     cpu->cpreg_vmstate_indexes = g_new(uint64_t, arraylen);
 296     cpu->cpreg_vmstate_values = g_new(uint64_t, arraylen);
 297     cpu->cpreg_vmstate_array_len = cpu->cpreg_array_len;
 298     cpu->cpreg_array_len = 0;
 299
 300     g_list_foreach(keys, add_cpreg_to_list, cpu);
 301
 302     assert(cpu->cpreg_array_len == arraylen);
 303
 304     g_list_free(keys);
 305 }
 306
 307 /* Return true if extended addresses are enabled.
 308  * This is always the case if our translation regime is 64 bit,
 309  * but depends on TTBCR.EAE for 32 bit.
 310  */
 311 static inline bool extended_addresses_enabled(CPUARMState *env)
 312 {
 313     return arm_el_is_aa64(env, 1)
 314         || ((arm_feature(env, ARM_FEATURE_LPAE)
 315              && (env->cp15.c2_control & TTBCR_EAE)));
 316 }
 317
 318 static void dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
 319 {
 320     ARMCPU *cpu = arm_env_get_cpu(env);
 321
 322     raw_write(env, ri, value);
 323     tlb_flush(CPU(cpu), 1); /* Flush TLB as domain not tracked in TLB */
 324 }
 325
 326 static void fcse_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
 327 {
 328     ARMCPU *cpu = arm_env_get_cpu(env);
 329
 330     if (raw_read(env, ri) != value) {
 331         /* Unlike real hardware the qemu TLB uses virtual addresses,
 332          * not modified virtual addresses, so this causes a TLB flush.
 333          */
 334         tlb_flush(CPU(cpu), 1);
 335         raw_write(env, ri, value);
 336     }
 337 }
 338
 339 static void contextidr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 340                              uint64_t value)
 341 {
 342     ARMCPU *cpu = arm_env_get_cpu(env);
 343
 344     if (raw_read(env, ri) != value && !arm_feature(env, ARM_FEATURE_MPU)
 345         && !extended_addresses_enabled(env)) {
 346         /* For VMSA (when not using the LPAE long descriptor page table
 347          * format) this register includes the ASID, so do a TLB flush.
 348          * For PMSA it is purely a process ID and no action is needed.
 349          */
 350         tlb_flush(CPU(cpu), 1);
 351     }
 352     raw_write(env, ri, value);
 353 }
 354
 355 static void tlbiall_write(CPUARMState *env, const ARMCPRegInfo *ri,
 356                           uint64_t value)
 357 {
 358     /* Invalidate all (TLBIALL) */
 359     ARMCPU *cpu = arm_env_get_cpu(env);
 360
 361     tlb_flush(CPU(cpu), 1);
 362 }
 363
 364 static void tlbimva_write(CPUARMState *env, const ARMCPRegInfo *ri,
 365                           uint64_t value)
 366 {
 367     /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */
 368     ARMCPU *cpu = arm_env_get_cpu(env);
 369
 370     tlb_flush_page(CPU(cpu), value & TARGET_PAGE_MASK);
 371 }
 372
 373 static void tlbiasid_write(CPUARMState *env, const ARMCPRegInfo *ri,
 374                            uint64_t value)
 375 {
 376     /* Invalidate by ASID (TLBIASID) */
 377     ARMCPU *cpu = arm_env_get_cpu(env);
 378
 379     tlb_flush(CPU(cpu), value == 0);
 380 }
 381
 382 static void tlbimvaa_write(CPUARMState *env, const ARMCPRegInfo *ri,
 383                            uint64_t value)
 384 {
 385     /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */
 386     ARMCPU *cpu = arm_env_get_cpu(env);
 387
 388     tlb_flush_page(CPU(cpu), value & TARGET_PAGE_MASK);
 389 }
 390
 391 static const ARMCPRegInfo cp_reginfo[] = {
 392     { .name = "FCSEIDR", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 0,
 393       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c13_fcse),
 394       .resetvalue = 0, .writefn = fcse_write, .raw_writefn = raw_write, },
 395     { .name = "CONTEXTIDR", .state = ARM_CP_STATE_BOTH,
 396       .opc0 = 3, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 1,
 397       .access = PL1_RW,
 398       .fieldoffset = offsetof(CPUARMState, cp15.contextidr_el1),
 399       .resetvalue = 0, .writefn = contextidr_write, .raw_writefn = raw_write, },
 400     REGINFO_SENTINEL
 401 };
 402
 403 static const ARMCPRegInfo not_v8_cp_reginfo[] = {
 404     /* NB: Some of these registers exist in v8 but with more precise
 405      * definitions that don't use CP_ANY wildcards (mostly in v8_cp_reginfo[]).
 406      */
 407     /* MMU Domain access control / MPU write buffer control */
 408     { .name = "DACR", .cp = 15,
 409       .crn = 3, .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
 410       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c3),
 411       .resetvalue = 0, .writefn = dacr_write, .raw_writefn = raw_write, },
 412     /* ??? This covers not just the impdef TLB lockdown registers but also
 413      * some v7VMSA registers relating to TEX remap, so it is overly broad.
 414      */
 415     { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = CP_ANY,
 416       .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP },
 417     /* MMU TLB control. Note that the wildcarding means we cover not just
 418      * the unified TLB ops but also the dside/iside/inner-shareable variants.
 419      */
 420     { .name = "TLBIALL", .cp = 15, .crn = 8, .crm = CP_ANY,
 421       .opc1 = CP_ANY, .opc2 = 0, .access = PL1_W, .writefn = tlbiall_write,
 422       .type = ARM_CP_NO_MIGRATE },
 423     { .name = "TLBIMVA", .cp = 15, .crn = 8, .crm = CP_ANY,
 424       .opc1 = CP_ANY, .opc2 = 1, .access = PL1_W, .writefn = tlbimva_write,
 425       .type = ARM_CP_NO_MIGRATE },
 426     { .name = "TLBIASID", .cp = 15, .crn = 8, .crm = CP_ANY,
 427       .opc1 = CP_ANY, .opc2 = 2, .access = PL1_W, .writefn = tlbiasid_write,
 428       .type = ARM_CP_NO_MIGRATE },
 429     { .name = "TLBIMVAA", .cp = 15, .crn = 8, .crm = CP_ANY,
 430       .opc1 = CP_ANY, .opc2 = 3, .access = PL1_W, .writefn = tlbimvaa_write,
 431       .type = ARM_CP_NO_MIGRATE },
 432     /* Cache maintenance ops; some of this space may be overridden later. */
 433     { .name = "CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY,
 434       .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W,
 435       .type = ARM_CP_NOP | ARM_CP_OVERRIDE },
 436     REGINFO_SENTINEL
 437 };
 438
 439 static const ARMCPRegInfo not_v6_cp_reginfo[] = {
 440     /* Not all pre-v6 cores implemented this WFI, so this is slightly
 441      * over-broad.
 442      */
 443     { .name = "WFI_v5", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = 2,
 444       .access = PL1_W, .type = ARM_CP_WFI },
 445     REGINFO_SENTINEL
 446 };
 447
 448 static const ARMCPRegInfo not_v7_cp_reginfo[] = {
 449     /* Standard v6 WFI (also used in some pre-v6 cores); not in v7 (which
 450      * is UNPREDICTABLE; we choose to NOP as most implementations do).
 451      */
 452     { .name = "WFI_v6", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4,
 453       .access = PL1_W, .type = ARM_CP_WFI },
 454     /* L1 cache lockdown. Not architectural in v6 and earlier but in practice
 455      * implemented in 926, 946, 1026, 1136, 1176 and 11MPCore. StrongARM and
 456      * OMAPCP will override this space.
 457      */
 458     { .name = "DLOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 0,
 459       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_data),
 460       .resetvalue = 0 },
 461     { .name = "ILOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 1,
 462       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_insn),
 463       .resetvalue = 0 },
 464     /* v6 doesn't have the cache ID registers but Linux reads them anyway */
 465     { .name = "DUMMY", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = CP_ANY,
 466       .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE,
 467       .resetvalue = 0 },
 468     /* We don't implement pre-v7 debug but most CPUs had at least a DBGDIDR;
 469      * implementing it as RAZ means the "debug architecture version" bits
 470      * will read as a reserved value, which should cause Linux to not try
 471      * to use the debug hardware.
 472      */
 473     { .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0,
 474       .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
 475     REGINFO_SENTINEL
 476 };
 477
 478 static void cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 479                         uint64_t value)
 480 {
 481     uint32_t mask = 0;
 482
 483     /* In ARMv8 most bits of CPACR_EL1 are RES0. */
 484     if (!arm_feature(env, ARM_FEATURE_V8)) {
 485         /* ARMv7 defines bits for unimplemented coprocessors as RAZ/WI.
 486          * ASEDIS [31] and D32DIS [30] are both UNK/SBZP without VFP.
 487          * TRCDIS [28] is RAZ/WI since we do not implement a trace macrocell.
 488          */
 489         if (arm_feature(env, ARM_FEATURE_VFP)) {
 490             /* VFP coprocessor: cp10 & cp11 [23:20] */
 491             mask |= (1 << 31) | (1 << 30) | (0xf << 20);
 492
 493             if (!arm_feature(env, ARM_FEATURE_NEON)) {
 494                 /* ASEDIS [31] bit is RAO/WI */
 495                 value |= (1 << 31);
 496             }
 497
 498             /* VFPv3 and upwards with NEON implement 32 double precision
 499              * registers (D0-D31).
 500              */
 501             if (!arm_feature(env, ARM_FEATURE_NEON) ||
 502                     !arm_feature(env, ARM_FEATURE_VFP3)) {
 503                 /* D32DIS [30] is RAO/WI if D16-31 are not implemented. */
 504                 value |= (1 << 30);
 505             }
 506         }
 507         value &= mask;
 508     }
 509     env->cp15.c1_coproc = value;
 510 }
 511
 512 static const ARMCPRegInfo v6_cp_reginfo[] = {
 513     /* prefetch by MVA in v6, NOP in v7 */
 514     { .name = "MVA_prefetch",
 515       .cp = 15, .crn = 7, .crm = 13, .opc1 = 0, .opc2 = 1,
 516       .access = PL1_W, .type = ARM_CP_NOP },
 517     { .name = "ISB", .cp = 15, .crn = 7, .crm = 5, .opc1 = 0, .opc2 = 4,
 518       .access = PL0_W, .type = ARM_CP_NOP },
 519     { .name = "DSB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 4,
 520       .access = PL0_W, .type = ARM_CP_NOP },
 521     { .name = "DMB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 5,
 522       .access = PL0_W, .type = ARM_CP_NOP },
 523     { .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 2,
 524       .access = PL1_RW,
 525       .fieldoffset = offsetofhigh32(CPUARMState, cp15.far_el[1]),
 526       .resetvalue = 0, },
 527     /* Watchpoint Fault Address Register : should actually only be present
 528      * for 1136, 1176, 11MPCore.
 529      */
 530     { .name = "WFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,
 531       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, },
 532     { .name = "CPACR", .state = ARM_CP_STATE_BOTH, .opc0 = 3,
 533       .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 2,
 534       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_coproc),
 535       .resetvalue = 0, .writefn = cpacr_write },
 536     REGINFO_SENTINEL
 537 };
 538
 539 static CPAccessResult pmreg_access(CPUARMState *env, const ARMCPRegInfo *ri)
 540 {
 541     /* Performance monitor registers user accessibility is controlled
 542      * by PMUSERENR.
 543      */
 544     if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) {
 545         return CP_ACCESS_TRAP;
 546     }
 547     return CP_ACCESS_OK;
 548 }
 549
 550 #ifndef CONFIG_USER_ONLY
 551 static void pmcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 552                        uint64_t value)
 553 {
 554     /* Don't computer the number of ticks in user mode */
 555     uint32_t temp_ticks;
 556
 557     temp_ticks = qemu_clock_get_us(QEMU_CLOCK_VIRTUAL) *
 558                   get_ticks_per_sec() / 1000000;
 559
 560     if (env->cp15.c9_pmcr & PMCRE) {
 561         /* If the counter is enabled */
 562         if (env->cp15.c9_pmcr & PMCRD) {
 563             /* Increment once every 64 processor clock cycles */
 564             env->cp15.c15_ccnt = (temp_ticks/64) - env->cp15.c15_ccnt;
 565         } else {
 566             env->cp15.c15_ccnt = temp_ticks - env->cp15.c15_ccnt;
 567         }
 568     }
 569
 570     if (value & PMCRC) {
 571         /* The counter has been reset */
 572         env->cp15.c15_ccnt = 0;
 573     }
 574
 575     /* only the DP, X, D and E bits are writable */
 576     env->cp15.c9_pmcr &= ~0x39;
 577     env->cp15.c9_pmcr |= (value & 0x39);
 578
 579     if (env->cp15.c9_pmcr & PMCRE) {
 580         if (env->cp15.c9_pmcr & PMCRD) {
 581             /* Increment once every 64 processor clock cycles */
 582             temp_ticks /= 64;
 583         }
 584         env->cp15.c15_ccnt = temp_ticks - env->cp15.c15_ccnt;
 585     }
 586 }
 587
 588 static uint64_t pmccntr_read(CPUARMState *env, const ARMCPRegInfo *ri)
 589 {
 590     uint32_t total_ticks;
 591
 592     if (!(env->cp15.c9_pmcr & PMCRE)) {
 593         /* Counter is disabled, do not change value */
 594         return env->cp15.c15_ccnt;
 595     }
 596
 597     total_ticks = qemu_clock_get_us(QEMU_CLOCK_VIRTUAL) *
 598                   get_ticks_per_sec() / 1000000;
 599
 600     if (env->cp15.c9_pmcr & PMCRD) {
 601         /* Increment once every 64 processor clock cycles */
 602         total_ticks /= 64;
 603     }
 604     return total_ticks - env->cp15.c15_ccnt;
 605 }
 606
 607 static void pmccntr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 608                         uint64_t value)
 609 {
 610     uint32_t total_ticks;
 611
 612     if (!(env->cp15.c9_pmcr & PMCRE)) {
 613         /* Counter is disabled, set the absolute value */
 614         env->cp15.c15_ccnt = value;
 615         return;
 616     }
 617
 618     total_ticks = qemu_clock_get_us(QEMU_CLOCK_VIRTUAL) *
 619                   get_ticks_per_sec() / 1000000;
 620
 621     if (env->cp15.c9_pmcr & PMCRD) {
 622         /* Increment once every 64 processor clock cycles */
 623         total_ticks /= 64;
 624     }
 625     env->cp15.c15_ccnt = total_ticks - value;
 626 }
 627 #endif
 628
 629 static void pmcntenset_write(CPUARMState *env, const ARMCPRegInfo *ri,
 630                             uint64_t value)
 631 {
 632     value &= (1 << 31);
 633     env->cp15.c9_pmcnten |= value;
 634 }
 635
 636 static void pmcntenclr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 637                              uint64_t value)
 638 {
 639     value &= (1 << 31);
 640     env->cp15.c9_pmcnten &= ~value;
 641 }
 642
 643 static void pmovsr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 644                          uint64_t value)
 645 {
 646     env->cp15.c9_pmovsr &= ~value;
 647 }
 648
 649 static void pmxevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri,
 650                              uint64_t value)
 651 {
 652     env->cp15.c9_pmxevtyper = value & 0xff;
 653 }
 654
 655 static void pmuserenr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 656                             uint64_t value)
 657 {
 658     env->cp15.c9_pmuserenr = value & 1;
 659 }
 660
 661 static void pmintenset_write(CPUARMState *env, const ARMCPRegInfo *ri,
 662                              uint64_t value)
 663 {
 664     /* We have no event counters so only the C bit can be changed */
 665     value &= (1 << 31);
 666     env->cp15.c9_pminten |= value;
 667 }
 668
 669 static void pmintenclr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 670                              uint64_t value)
 671 {
 672     value &= (1 << 31);
 673     env->cp15.c9_pminten &= ~value;
 674 }
 675
 676 static void vbar_write(CPUARMState *env, const ARMCPRegInfo *ri,
 677                        uint64_t value)
 678 {
 679     /* Note that even though the AArch64 view of this register has bits
 680      * [10:0] all RES0 we can only mask the bottom 5, to comply with the
 681      * architectural requirements for bits which are RES0 only in some
 682      * contexts. (ARMv8 would permit us to do no masking at all, but ARMv7
 683      * requires the bottom five bits to be RAZ/WI because they're UNK/SBZP.)
 684      */
 685     raw_write(env, ri, value & ~0x1FULL);
 686 }
 687
 688 static uint64_t ccsidr_read(CPUARMState *env, const ARMCPRegInfo *ri)
 689 {
 690     ARMCPU *cpu = arm_env_get_cpu(env);
 691     return cpu->ccsidr[env->cp15.c0_cssel];
 692 }
 693
 694 static void csselr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 695                          uint64_t value)
 696 {
 697     raw_write(env, ri, value & 0xf);
 698 }
 699
 700 static uint64_t isr_read(CPUARMState *env, const ARMCPRegInfo *ri)
 701 {
 702     CPUState *cs = ENV_GET_CPU(env);
 703     uint64_t ret = 0;
 704
 705     if (cs->interrupt_request & CPU_INTERRUPT_HARD) {
 706         ret |= CPSR_I;
 707     }
 708     if (cs->interrupt_request & CPU_INTERRUPT_FIQ) {
 709         ret |= CPSR_F;
 710     }
 711     /* External aborts are not possible in QEMU so A bit is always clear */
 712     return ret;
 713 }
 714
 715 static const ARMCPRegInfo v7_cp_reginfo[] = {
 716     /* the old v6 WFI, UNPREDICTABLE in v7 but we choose to NOP */
 717     { .name = "NOP", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4,
 718       .access = PL1_W, .type = ARM_CP_NOP },
 719     /* Performance monitors are implementation defined in v7,
 720      * but with an ARM recommended set of registers, which we
 721      * follow (although we don't actually implement any counters)
 722      *
 723      * Performance registers fall into three categories:
 724      *  (a) always UNDEF in PL0, RW in PL1 (PMINTENSET, PMINTENCLR)
 725      *  (b) RO in PL0 (ie UNDEF on write), RW in PL1 (PMUSERENR)
 726      *  (c) UNDEF in PL0 if PMUSERENR.EN==0, otherwise accessible (all others)
 727      * For the cases controlled by PMUSERENR we must set .access to PL0_RW
 728      * or PL0_RO as appropriate and then check PMUSERENR in the helper fn.
 729      */
 730     { .name = "PMCNTENSET", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 1,
 731       .access = PL0_RW, .resetvalue = 0,
 732       .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten),
 733       .writefn = pmcntenset_write,
 734       .accessfn = pmreg_access,
 735       .raw_writefn = raw_write },
 736     { .name = "PMCNTENCLR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 2,
 737       .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten),
 738       .accessfn = pmreg_access,
 739       .writefn = pmcntenclr_write,
 740       .type = ARM_CP_NO_MIGRATE },
 741     { .name = "PMOVSR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 3,
 742       .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr),
 743       .accessfn = pmreg_access,
 744       .writefn = pmovsr_write,
 745       .raw_writefn = raw_write },
 746     /* Unimplemented so WI. */
 747     { .name = "PMSWINC", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 4,
 748       .access = PL0_W, .accessfn = pmreg_access, .type = ARM_CP_NOP },
 749     /* Since we don't implement any events, writing to PMSELR is UNPREDICTABLE.
 750      * We choose to RAZ/WI.
 751      */
 752     { .name = "PMSELR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 5,
 753       .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0,
 754       .accessfn = pmreg_access },
 755 #ifndef CONFIG_USER_ONLY
 756     { .name = "PMCCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 0,
 757       .access = PL0_RW, .resetvalue = 0, .type = ARM_CP_IO,
 758       .readfn = pmccntr_read, .writefn = pmccntr_write,
 759       .accessfn = pmreg_access },
 760 #endif
 761     { .name = "PMXEVTYPER", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 1,
 762       .access = PL0_RW,
 763       .fieldoffset = offsetof(CPUARMState, cp15.c9_pmxevtyper),
 764       .accessfn = pmreg_access, .writefn = pmxevtyper_write,
 765       .raw_writefn = raw_write },
 766     /* Unimplemented, RAZ/WI. */
 767     { .name = "PMXEVCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 2,
 768       .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0,
 769       .accessfn = pmreg_access },
 770     { .name = "PMUSERENR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 0,
 771       .access = PL0_R | PL1_RW,
 772       .fieldoffset = offsetof(CPUARMState, cp15.c9_pmuserenr),
 773       .resetvalue = 0,
 774       .writefn = pmuserenr_write, .raw_writefn = raw_write },
 775     { .name = "PMINTENSET", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 1,
 776       .access = PL1_RW,
 777       .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
 778       .resetvalue = 0,
 779       .writefn = pmintenset_write, .raw_writefn = raw_write },
 780     { .name = "PMINTENCLR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 2,
 781       .access = PL1_RW, .type = ARM_CP_NO_MIGRATE,
 782       .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
 783       .resetvalue = 0, .writefn = pmintenclr_write, },
 784     { .name = "VBAR", .state = ARM_CP_STATE_BOTH,
 785       .opc0 = 3, .crn = 12, .crm = 0, .opc1 = 0, .opc2 = 0,
 786       .access = PL1_RW, .writefn = vbar_write,
 787       .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[1]),
 788       .resetvalue = 0 },
 789     { .name = "SCR", .cp = 15, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 0,
 790       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_scr),
 791       .resetvalue = 0, },
 792     { .name = "CCSIDR", .state = ARM_CP_STATE_BOTH,
 793       .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 0,
 794       .access = PL1_R, .readfn = ccsidr_read, .type = ARM_CP_NO_MIGRATE },
 795     { .name = "CSSELR", .state = ARM_CP_STATE_BOTH,
 796       .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 2, .opc2 = 0,
 797       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c0_cssel),
 798       .writefn = csselr_write, .resetvalue = 0 },
 799     /* Auxiliary ID register: this actually has an IMPDEF value but for now
 800      * just RAZ for all cores:
 801      */
 802     { .name = "AIDR", .state = ARM_CP_STATE_BOTH,
 803       .opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 7,
 804       .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
 805     /* Auxiliary fault status registers: these also are IMPDEF, and we
 806      * choose to RAZ/WI for all cores.
 807      */
 808     { .name = "AFSR0_EL1", .state = ARM_CP_STATE_BOTH,
 809       .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 1, .opc2 = 0,
 810       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 811     { .name = "AFSR1_EL1", .state = ARM_CP_STATE_BOTH,
 812       .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 1, .opc2 = 1,
 813       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 814     /* MAIR can just read-as-written because we don't implement caches
 815      * and so don't need to care about memory attributes.
 816      */
 817     { .name = "MAIR_EL1", .state = ARM_CP_STATE_AA64,
 818       .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 0,
 819       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.mair_el1),
 820       .resetvalue = 0 },
 821     /* For non-long-descriptor page tables these are PRRR and NMRR;
 822      * regardless they still act as reads-as-written for QEMU.
 823      * The override is necessary because of the overly-broad TLB_LOCKDOWN
 824      * definition.
 825      */
 826     { .name = "MAIR0", .state = ARM_CP_STATE_AA32, .type = ARM_CP_OVERRIDE,
 827       .cp = 15, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 0, .access = PL1_RW,
 828       .fieldoffset = offsetoflow32(CPUARMState, cp15.mair_el1),
 829       .resetfn = arm_cp_reset_ignore },
 830     { .name = "MAIR1", .state = ARM_CP_STATE_AA32, .type = ARM_CP_OVERRIDE,
 831       .cp = 15, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 1, .access = PL1_RW,
 832       .fieldoffset = offsetofhigh32(CPUARMState, cp15.mair_el1),
 833       .resetfn = arm_cp_reset_ignore },
 834     { .name = "ISR_EL1", .state = ARM_CP_STATE_BOTH,
 835       .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 1, .opc2 = 0,
 836       .type = ARM_CP_NO_MIGRATE, .access = PL1_R, .readfn = isr_read },
 837     REGINFO_SENTINEL
 838 };
 839
 840 static void teecr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 841                         uint64_t value)
 842 {
 843     value &= 1;
 844     env->teecr = value;
 845 }
 846
 847 static CPAccessResult teehbr_access(CPUARMState *env, const ARMCPRegInfo *ri)
 848 {
 849     if (arm_current_pl(env) == 0 && (env->teecr & 1)) {
 850         return CP_ACCESS_TRAP;
 851     }
 852     return CP_ACCESS_OK;
 853 }
 854
 855 static const ARMCPRegInfo t2ee_cp_reginfo[] = {
 856     { .name = "TEECR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 6, .opc2 = 0,
 857       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, teecr),
 858       .resetvalue = 0,
 859       .writefn = teecr_write },
 860     { .name = "TEEHBR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 6, .opc2 = 0,
 861       .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, teehbr),
 862       .accessfn = teehbr_access, .resetvalue = 0 },
 863     REGINFO_SENTINEL
 864 };
 865
 866 static const ARMCPRegInfo v6k_cp_reginfo[] = {
 867     { .name = "TPIDR_EL0", .state = ARM_CP_STATE_AA64,
 868       .opc0 = 3, .opc1 = 3, .opc2 = 2, .crn = 13, .crm = 0,
 869       .access = PL0_RW,
 870       .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el0), .resetvalue = 0 },
 871     { .name = "TPIDRURW", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 2,
 872       .access = PL0_RW,
 873       .fieldoffset = offsetoflow32(CPUARMState, cp15.tpidr_el0),
 874       .resetfn = arm_cp_reset_ignore },
 875     { .name = "TPIDRRO_EL0", .state = ARM_CP_STATE_AA64,
 876       .opc0 = 3, .opc1 = 3, .opc2 = 3, .crn = 13, .crm = 0,
 877       .access = PL0_R|PL1_W,
 878       .fieldoffset = offsetof(CPUARMState, cp15.tpidrro_el0), .resetvalue = 0 },
 879     { .name = "TPIDRURO", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 3,
 880       .access = PL0_R|PL1_W,
 881       .fieldoffset = offsetoflow32(CPUARMState, cp15.tpidrro_el0),
 882       .resetfn = arm_cp_reset_ignore },
 883     { .name = "TPIDR_EL1", .state = ARM_CP_STATE_BOTH,
 884       .opc0 = 3, .opc1 = 0, .opc2 = 4, .crn = 13, .crm = 0,
 885       .access = PL1_RW,
 886       .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el1), .resetvalue = 0 },
 887     REGINFO_SENTINEL
 888 };
 889
 890 #ifndef CONFIG_USER_ONLY
 891
 892 static CPAccessResult gt_cntfrq_access(CPUARMState *env, const ARMCPRegInfo *ri)
 893 {
 894     /* CNTFRQ: not visible from PL0 if both PL0PCTEN and PL0VCTEN are zero */
 895     if (arm_current_pl(env) == 0 && !extract32(env->cp15.c14_cntkctl, 0, 2)) {
 896         return CP_ACCESS_TRAP;
 897     }
 898     return CP_ACCESS_OK;
 899 }
 900
 901 static CPAccessResult gt_counter_access(CPUARMState *env, int timeridx)
 902 {
 903     /* CNT[PV]CT: not visible from PL0 if ELO[PV]CTEN is zero */
 904     if (arm_current_pl(env) == 0 &&
 905         !extract32(env->cp15.c14_cntkctl, timeridx, 1)) {
 906         return CP_ACCESS_TRAP;
 907     }
 908     return CP_ACCESS_OK;
 909 }
 910
 911 static CPAccessResult gt_timer_access(CPUARMState *env, int timeridx)
 912 {
 913     /* CNT[PV]_CVAL, CNT[PV]_CTL, CNT[PV]_TVAL: not visible from PL0 if
 914      * EL0[PV]TEN is zero.
 915      */
 916     if (arm_current_pl(env) == 0 &&
 917         !extract32(env->cp15.c14_cntkctl, 9 - timeridx, 1)) {
 918         return CP_ACCESS_TRAP;
 919     }
 920     return CP_ACCESS_OK;
 921 }
 922
 923 static CPAccessResult gt_pct_access(CPUARMState *env,
 924                                          const ARMCPRegInfo *ri)
 925 {
 926     return gt_counter_access(env, GTIMER_PHYS);
 927 }
 928
 929 static CPAccessResult gt_vct_access(CPUARMState *env,
 930                                          const ARMCPRegInfo *ri)
 931 {
 932     return gt_counter_access(env, GTIMER_VIRT);
 933 }
 934
 935 static CPAccessResult gt_ptimer_access(CPUARMState *env, const ARMCPRegInfo *ri)
 936 {
 937     return gt_timer_access(env, GTIMER_PHYS);
 938 }
 939
 940 static CPAccessResult gt_vtimer_access(CPUARMState *env, const ARMCPRegInfo *ri)
 941 {
 942     return gt_timer_access(env, GTIMER_VIRT);
 943 }
 944
 945 static uint64_t gt_get_countervalue(CPUARMState *env)
 946 {
 947     return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / GTIMER_SCALE;
 948 }
 949
 950 static void gt_recalc_timer(ARMCPU *cpu, int timeridx)
 951 {
 952     ARMGenericTimer *gt = &cpu->env.cp15.c14_timer[timeridx];
 953
 954     if (gt->ctl & 1) {
 955         /* Timer enabled: calculate and set current ISTATUS, irq, and
 956          * reset timer to when ISTATUS next has to change
 957          */
 958         uint64_t count = gt_get_countervalue(&cpu->env);
 959         /* Note that this must be unsigned 64 bit arithmetic: */
 960         int istatus = count >= gt->cval;
 961         uint64_t nexttick;
 962
 963         gt->ctl = deposit32(gt->ctl, 2, 1, istatus);
 964         qemu_set_irq(cpu->gt_timer_outputs[timeridx],
 965                      (istatus && !(gt->ctl & 2)));
 966         if (istatus) {
 967             /* Next transition is when count rolls back over to zero */
 968             nexttick = UINT64_MAX;
 969         } else {
 970             /* Next transition is when we hit cval */
 971             nexttick = gt->cval;
 972         }
 973         /* Note that the desired next expiry time might be beyond the
 974          * signed-64-bit range of a QEMUTimer -- in this case we just
 975          * set the timer for as far in the future as possible. When the
 976          * timer expires we will reset the timer for any remaining period.
 977          */
 978         if (nexttick > INT64_MAX / GTIMER_SCALE) {
 979             nexttick = INT64_MAX / GTIMER_SCALE;
 980         }
 981         timer_mod(cpu->gt_timer[timeridx], nexttick);
 982     } else {
 983         /* Timer disabled: ISTATUS and timer output always clear */
 984         gt->ctl &= ~4;
 985         qemu_set_irq(cpu->gt_timer_outputs[timeridx], 0);
 986         timer_del(cpu->gt_timer[timeridx]);
 987     }
 988 }
 989
 990 static void gt_cnt_reset(CPUARMState *env, const ARMCPRegInfo *ri)
 991 {
 992     ARMCPU *cpu = arm_env_get_cpu(env);
 993     int timeridx = ri->opc1 & 1;
 994
 995     timer_del(cpu->gt_timer[timeridx]);
 996 }
 997
 998 static uint64_t gt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri)
 999 {
1000     return gt_get_countervalue(env);
1001 }
1002
1003 static void gt_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1004                           uint64_t value)
1005 {
1006     int timeridx = ri->opc1 & 1;
1007
1008     env->cp15.c14_timer[timeridx].cval = value;
1009     gt_recalc_timer(arm_env_get_cpu(env), timeridx);
1010 }
1011
1012 static uint64_t gt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri)
1013 {
1014     int timeridx = ri->crm & 1;
1015
1016     return (uint32_t)(env->cp15.c14_timer[timeridx].cval -
1017                       gt_get_countervalue(env));
1018 }
1019
1020 static void gt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1021                           uint64_t value)
1022 {
1023     int timeridx = ri->crm & 1;
1024
1025     env->cp15.c14_timer[timeridx].cval = gt_get_countervalue(env) +
1026         + sextract64(value, 0, 32);
1027     gt_recalc_timer(arm_env_get_cpu(env), timeridx);
1028 }
1029
1030 static void gt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
1031                          uint64_t value)
1032 {
1033     ARMCPU *cpu = arm_env_get_cpu(env);
1034     int timeridx = ri->crm & 1;
1035     uint32_t oldval = env->cp15.c14_timer[timeridx].ctl;
1036
1037     env->cp15.c14_timer[timeridx].ctl = deposit64(oldval, 0, 2, value);
1038     if ((oldval ^ value) & 1) {
1039         /* Enable toggled */
1040         gt_recalc_timer(cpu, timeridx);
1041     } else if ((oldval ^ value) & 2) {
1042         /* IMASK toggled: don't need to recalculate,
1043          * just set the interrupt line based on ISTATUS
1044          */
1045         qemu_set_irq(cpu->gt_timer_outputs[timeridx],
1046                      (oldval & 4) && !(value & 2));
1047     }
1048 }
1049
1050 void arm_gt_ptimer_cb(void *opaque)
1051 {
1052     ARMCPU *cpu = opaque;
1053
1054     gt_recalc_timer(cpu, GTIMER_PHYS);
1055 }
1056
1057 void arm_gt_vtimer_cb(void *opaque)
1058 {
1059     ARMCPU *cpu = opaque;
1060
1061     gt_recalc_timer(cpu, GTIMER_VIRT);
1062 }
1063
1064 static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
1065     /* Note that CNTFRQ is purely reads-as-written for the benefit
1066      * of software; writing it doesn't actually change the timer frequency.
1067      * Our reset value matches the fixed frequency we implement the timer at.
1068      */
1069     { .name = "CNTFRQ", .cp = 15, .crn = 14, .crm = 0, .opc1 = 0, .opc2 = 0,
1070       .type = ARM_CP_NO_MIGRATE,
1071       .access = PL1_RW | PL0_R, .accessfn = gt_cntfrq_access,
1072       .fieldoffset = offsetoflow32(CPUARMState, cp15.c14_cntfrq),
1073       .resetfn = arm_cp_reset_ignore,
1074     },
1075     { .name = "CNTFRQ_EL0", .state = ARM_CP_STATE_AA64,
1076       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 0,
1077       .access = PL1_RW | PL0_R, .accessfn = gt_cntfrq_access,
1078       .fieldoffset = offsetof(CPUARMState, cp15.c14_cntfrq),
1079       .resetvalue = (1000 * 1000 * 1000) / GTIMER_SCALE,
1080     },
1081     /* overall control: mostly access permissions */
1082     { .name = "CNTKCTL", .state = ARM_CP_STATE_BOTH,
1083       .opc0 = 3, .opc1 = 0, .crn = 14, .crm = 1, .opc2 = 0,
1084       .access = PL1_RW,
1085       .fieldoffset = offsetof(CPUARMState, cp15.c14_cntkctl),
1086       .resetvalue = 0,
1087     },
1088     /* per-timer control */
1089     { .name = "CNTP_CTL", .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 1,
1090       .type = ARM_CP_IO | ARM_CP_NO_MIGRATE, .access = PL1_RW | PL0_R,
1091       .accessfn = gt_ptimer_access,
1092       .fieldoffset = offsetoflow32(CPUARMState,
1093                                    cp15.c14_timer[GTIMER_PHYS].ctl),
1094       .resetfn = arm_cp_reset_ignore,
1095       .writefn = gt_ctl_write, .raw_writefn = raw_write,
1096     },
1097     { .name = "CNTP_CTL_EL0", .state = ARM_CP_STATE_AA64,
1098       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 1,
1099       .type = ARM_CP_IO, .access = PL1_RW | PL0_R,
1100       .accessfn = gt_ptimer_access,
1101       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].ctl),
1102       .resetvalue = 0,
1103       .writefn = gt_ctl_write, .raw_writefn = raw_write,
1104     },
1105     { .name = "CNTV_CTL", .cp = 15, .crn = 14, .crm = 3, .opc1 = 0, .opc2 = 1,
1106       .type = ARM_CP_IO | ARM_CP_NO_MIGRATE, .access = PL1_RW | PL0_R,
1107       .accessfn = gt_vtimer_access,
1108       .fieldoffset = offsetoflow32(CPUARMState,
1109                                    cp15.c14_timer[GTIMER_VIRT].ctl),
1110       .resetfn = arm_cp_reset_ignore,
1111       .writefn = gt_ctl_write, .raw_writefn = raw_write,
1112     },
1113     { .name = "CNTV_CTL_EL0", .state = ARM_CP_STATE_AA64,
1114       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 1,
1115       .type = ARM_CP_IO, .access = PL1_RW | PL0_R,
1116       .accessfn = gt_vtimer_access,
1117       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].ctl),
1118       .resetvalue = 0,
1119       .writefn = gt_ctl_write, .raw_writefn = raw_write,
1120     },
1121     /* TimerValue views: a 32 bit downcounting view of the underlying state */
1122     { .name = "CNTP_TVAL", .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 0,
1123       .type = ARM_CP_NO_MIGRATE | ARM_CP_IO, .access = PL1_RW | PL0_R,
1124       .accessfn = gt_ptimer_access,
1125       .readfn = gt_tval_read, .writefn = gt_tval_write,
1126     },
1127     { .name = "CNTP_TVAL_EL0", .state = ARM_CP_STATE_AA64,
1128       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 0,
1129       .type = ARM_CP_NO_MIGRATE | ARM_CP_IO, .access = PL1_RW | PL0_R,
1130       .readfn = gt_tval_read, .writefn = gt_tval_write,
1131     },
1132     { .name = "CNTV_TVAL", .cp = 15, .crn = 14, .crm = 3, .opc1 = 0, .opc2 = 0,
1133       .type = ARM_CP_NO_MIGRATE | ARM_CP_IO, .access = PL1_RW | PL0_R,
1134       .accessfn = gt_vtimer_access,
1135       .readfn = gt_tval_read, .writefn = gt_tval_write,
1136     },
1137     { .name = "CNTV_TVAL_EL0", .state = ARM_CP_STATE_AA64,
1138       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 0,
1139       .type = ARM_CP_NO_MIGRATE | ARM_CP_IO, .access = PL1_RW | PL0_R,
1140       .readfn = gt_tval_read, .writefn = gt_tval_write,
1141     },
1142     /* The counter itself */
1143     { .name = "CNTPCT", .cp = 15, .crm = 14, .opc1 = 0,
1144       .access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_MIGRATE | ARM_CP_IO,
1145       .accessfn = gt_pct_access,
1146       .readfn = gt_cnt_read, .resetfn = arm_cp_reset_ignore,
1147     },
1148     { .name = "CNTPCT_EL0", .state = ARM_CP_STATE_AA64,
1149       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 1,
1150       .access = PL0_R, .type = ARM_CP_NO_MIGRATE | ARM_CP_IO,
1151       .accessfn = gt_pct_access,
1152       .readfn = gt_cnt_read, .resetfn = gt_cnt_reset,
1153     },
1154     { .name = "CNTVCT", .cp = 15, .crm = 14, .opc1 = 1,
1155       .access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_MIGRATE | ARM_CP_IO,
1156       .accessfn = gt_vct_access,
1157       .readfn = gt_cnt_read, .resetfn = arm_cp_reset_ignore,
1158     },
1159     { .name = "CNTVCT_EL0", .state = ARM_CP_STATE_AA64,
1160       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 2,
1161       .access = PL0_R, .type = ARM_CP_NO_MIGRATE | ARM_CP_IO,
1162       .accessfn = gt_vct_access,
1163       .readfn = gt_cnt_read, .resetfn = gt_cnt_reset,
1164     },
1165     /* Comparison value, indicating when the timer goes off */
1166     { .name = "CNTP_CVAL", .cp = 15, .crm = 14, .opc1 = 2,
1167       .access = PL1_RW | PL0_R,
1168       .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_NO_MIGRATE,
1169       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval),
1170       .accessfn = gt_ptimer_access, .resetfn = arm_cp_reset_ignore,
1171       .writefn = gt_cval_write, .raw_writefn = raw_write,
1172     },
1173     { .name = "CNTP_CVAL_EL0", .state = ARM_CP_STATE_AA64,
1174       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 2,
1175       .access = PL1_RW | PL0_R,
1176       .type = ARM_CP_IO,
1177       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval),
1178       .resetvalue = 0, .accessfn = gt_vtimer_access,
1179       .writefn = gt_cval_write, .raw_writefn = raw_write,
1180     },
1181     { .name = "CNTV_CVAL", .cp = 15, .crm = 14, .opc1 = 3,
1182       .access = PL1_RW | PL0_R,
1183       .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_NO_MIGRATE,
1184       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval),
1185       .accessfn = gt_vtimer_access, .resetfn = arm_cp_reset_ignore,
1186       .writefn = gt_cval_write, .raw_writefn = raw_write,
1187     },
1188     { .name = "CNTV_CVAL_EL0", .state = ARM_CP_STATE_AA64,
1189       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 2,
1190       .access = PL1_RW | PL0_R,
1191       .type = ARM_CP_IO,
1192       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval),
1193       .resetvalue = 0, .accessfn = gt_vtimer_access,
1194       .writefn = gt_cval_write, .raw_writefn = raw_write,
1195     },
1196     REGINFO_SENTINEL
1197 };
1198
1199 #else
1200 /* In user-mode none of the generic timer registers are accessible,
1201  * and their implementation depends on QEMU_CLOCK_VIRTUAL and qdev gpio outputs,
1202  * so instead just don't register any of them.
1203  */
1204 static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
1205     REGINFO_SENTINEL
1206 };
1207
1208 #endif
1209
1210 static void par_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
1211 {
1212     if (arm_feature(env, ARM_FEATURE_LPAE)) {
1213         raw_write(env, ri, value);
1214     } else if (arm_feature(env, ARM_FEATURE_V7)) {
1215         raw_write(env, ri, value & 0xfffff6ff);
1216     } else {
1217         raw_write(env, ri, value & 0xfffff1ff);
1218     }
1219 }
1220
1221 #ifndef CONFIG_USER_ONLY
1222 /* get_phys_addr() isn't present for user-mode-only targets */
1223
1224 static CPAccessResult ats_access(CPUARMState *env, const ARMCPRegInfo *ri)
1225 {
1226     if (ri->opc2 & 4) {
1227         /* Other states are only available with TrustZone; in
1228          * a non-TZ implementation these registers don't exist
1229          * at all, which is an Uncategorized trap. This underdecoding
1230          * is safe because the reginfo is NO_MIGRATE.
1231          */
1232         return CP_ACCESS_TRAP_UNCATEGORIZED;
1233     }
1234     return CP_ACCESS_OK;
1235 }
1236
1237 static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
1238 {
1239     hwaddr phys_addr;
1240     target_ulong page_size;
1241     int prot;
1242     int ret, is_user = ri->opc2 & 2;
1243     int access_type = ri->opc2 & 1;
1244
1245     ret = get_phys_addr(env, value, access_type, is_user,
1246                         &phys_addr, &prot, &page_size);
1247     if (extended_addresses_enabled(env)) {
1248         /* ret is a DFSR/IFSR value for the long descriptor
1249          * translation table format, but with WnR always clear.
1250          * Convert it to a 64-bit PAR.
1251          */
1252         uint64_t par64 = (1 << 11); /* LPAE bit always set */
1253         if (ret == 0) {
1254             par64 |= phys_addr & ~0xfffULL;
1255             /* We don't set the ATTR or SH fields in the PAR. */
1256         } else {
1257             par64 |= 1; /* F */
1258             par64 |= (ret & 0x3f) << 1; /* FS */
1259             /* Note that S2WLK and FSTAGE are always zero, because we don't
1260              * implement virtualization and therefore there can't be a stage 2
1261              * fault.
1262              */
1263         }
1264         env->cp15.par_el1 = par64;
1265     } else {
1266         /* ret is a DFSR/IFSR value for the short descriptor
1267          * translation table format (with WnR always clear).
1268          * Convert it to a 32-bit PAR.
1269          */
1270         if (ret == 0) {
1271             /* We do not set any attribute bits in the PAR */
1272             if (page_size == (1 << 24)
1273                 && arm_feature(env, ARM_FEATURE_V7)) {
1274                 env->cp15.par_el1 = (phys_addr & 0xff000000) | 1 << 1;
1275             } else {
1276                 env->cp15.par_el1 = phys_addr & 0xfffff000;
1277             }
1278         } else {
1279             env->cp15.par_el1 = ((ret & (1 << 10)) >> 5) |
1280                 ((ret & (1 << 12)) >> 6) |
1281                 ((ret & 0xf) << 1) | 1;
1282         }
1283     }
1284 }
1285 #endif
1286
1287 static const ARMCPRegInfo vapa_cp_reginfo[] = {
1288     { .name = "PAR", .cp = 15, .crn = 7, .crm = 4, .opc1 = 0, .opc2 = 0,
1289       .access = PL1_RW, .resetvalue = 0,
1290       .fieldoffset = offsetoflow32(CPUARMState, cp15.par_el1),
1291       .writefn = par_write },
1292 #ifndef CONFIG_USER_ONLY
1293     { .name = "ATS", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = CP_ANY,
1294       .access = PL1_W, .accessfn = ats_access,
1295       .writefn = ats_write, .type = ARM_CP_NO_MIGRATE },
1296 #endif
1297     REGINFO_SENTINEL
1298 };
1299
1300 /* Return basic MPU access permission bits.  */
1301 static uint32_t simple_mpu_ap_bits(uint32_t val)
1302 {
1303     uint32_t ret;
1304     uint32_t mask;
1305     int i;
1306     ret = 0;
1307     mask = 3;
1308     for (i = 0; i < 16; i += 2) {
1309         ret |= (val >> i) & mask;
1310         mask <<= 2;
1311     }
1312     return ret;
1313 }
1314
1315 /* Pad basic MPU access permission bits to extended format.  */
1316 static uint32_t extended_mpu_ap_bits(uint32_t val)
1317 {
1318     uint32_t ret;
1319     uint32_t mask;
1320     int i;
1321     ret = 0;
1322     mask = 3;
1323     for (i = 0; i < 16; i += 2) {
1324         ret |= (val & mask) << i;
1325         mask <<= 2;
1326     }
1327     return ret;
1328 }
1329
1330 static void pmsav5_data_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
1331                                  uint64_t value)
1332 {
1333     env->cp15.pmsav5_data_ap = extended_mpu_ap_bits(value);
1334 }
1335
1336 static uint64_t pmsav5_data_ap_read(CPUARMState *env, const ARMCPRegInfo *ri)
1337 {
1338     return simple_mpu_ap_bits(env->cp15.pmsav5_data_ap);
1339 }
1340
1341 static void pmsav5_insn_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
1342                                  uint64_t value)
1343 {
1344     env->cp15.pmsav5_insn_ap = extended_mpu_ap_bits(value);
1345 }
1346
1347 static uint64_t pmsav5_insn_ap_read(CPUARMState *env, const ARMCPRegInfo *ri)
1348 {
1349     return simple_mpu_ap_bits(env->cp15.pmsav5_insn_ap);
1350 }
1351
1352 static const ARMCPRegInfo pmsav5_cp_reginfo[] = {
1353     { .name = "DATA_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0,
1354       .access = PL1_RW, .type = ARM_CP_NO_MIGRATE,
1355       .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_data_ap),
1356       .resetvalue = 0,
1357       .readfn = pmsav5_data_ap_read, .writefn = pmsav5_data_ap_write, },
1358     { .name = "INSN_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1,
1359       .access = PL1_RW, .type = ARM_CP_NO_MIGRATE,
1360       .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_insn_ap),
1361       .resetvalue = 0,
1362       .readfn = pmsav5_insn_ap_read, .writefn = pmsav5_insn_ap_write, },
1363     { .name = "DATA_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 2,
1364       .access = PL1_RW,
1365       .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_data_ap),
1366       .resetvalue = 0, },
1367     { .name = "INSN_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 3,
1368       .access = PL1_RW,
1369       .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_insn_ap),
1370       .resetvalue = 0, },
1371     { .name = "DCACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
1372       .access = PL1_RW,
1373       .fieldoffset = offsetof(CPUARMState, cp15.c2_data), .resetvalue = 0, },
1374     { .name = "ICACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 1,
1375       .access = PL1_RW,
1376       .fieldoffset = offsetof(CPUARMState, cp15.c2_insn), .resetvalue = 0, },
1377     /* Protection region base and size registers */
1378     { .name = "946_PRBS0", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0,
1379       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
1380       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[0]) },
1381     { .name = "946_PRBS1", .cp = 15, .crn = 6, .crm = 1, .opc1 = 0,
1382       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
1383       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[1]) },
1384     { .name = "946_PRBS2", .cp = 15, .crn = 6, .crm = 2, .opc1 = 0,
1385       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
1386       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[2]) },
1387     { .name = "946_PRBS3", .cp = 15, .crn = 6, .crm = 3, .opc1 = 0,
1388       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
1389       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[3]) },
1390     { .name = "946_PRBS4", .cp = 15, .crn = 6, .crm = 4, .opc1 = 0,
1391       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
1392       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[4]) },
1393     { .name = "946_PRBS5", .cp = 15, .crn = 6, .crm = 5, .opc1 = 0,
1394       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
1395       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[5]) },
1396     { .name = "946_PRBS6", .cp = 15, .crn = 6, .crm = 6, .opc1 = 0,
1397       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
1398       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[6]) },
1399     { .name = "946_PRBS7", .cp = 15, .crn = 6, .crm = 7, .opc1 = 0,
1400       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
1401       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[7]) },
1402     REGINFO_SENTINEL
1403 };
1404
1405 static void vmsa_ttbcr_raw_write(CPUARMState *env, const ARMCPRegInfo *ri,
1406                                  uint64_t value)
1407 {
1408     int maskshift = extract32(value, 0, 3);
1409
1410     if (!arm_feature(env, ARM_FEATURE_V8)) {
1411         if (arm_feature(env, ARM_FEATURE_LPAE) && (value & TTBCR_EAE)) {
1412             /* Pre ARMv8 bits [21:19], [15:14] and [6:3] are UNK/SBZP when
1413              * using Long-desciptor translation table format */
1414             value &= ~((7 << 19) | (3 << 14) | (0xf << 3));
1415         } else if (arm_feature(env, ARM_FEATURE_EL3)) {
1416             /* In an implementation that includes the Security Extensions
1417              * TTBCR has additional fields PD0 [4] and PD1 [5] for
1418              * Short-descriptor translation table format.
1419              */
1420             value &= TTBCR_PD1 | TTBCR_PD0 | TTBCR_N;
1421         } else {
1422             value &= TTBCR_N;
1423         }
1424     }
1425
1426     /* Note that we always calculate c2_mask and c2_base_mask, but
1427      * they are only used for short-descriptor tables (ie if EAE is 0);
1428      * for long-descriptor tables the TTBCR fields are used differently
1429      * and the c2_mask and c2_base_mask values are meaningless.
1430      */
1431     raw_write(env, ri, value);
1432     env->cp15.c2_mask = ~(((uint32_t)0xffffffffu) >> maskshift);
1433     env->cp15.c2_base_mask = ~((uint32_t)0x3fffu >> maskshift);
1434 }
1435
1436 static void vmsa_ttbcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1437                              uint64_t value)
1438 {
1439     ARMCPU *cpu = arm_env_get_cpu(env);
1440
1441     if (arm_feature(env, ARM_FEATURE_LPAE)) {
1442         /* With LPAE the TTBCR could result in a change of ASID
1443          * via the TTBCR.A1 bit, so do a TLB flush.
1444          */
1445         tlb_flush(CPU(cpu), 1);
1446     }
1447     vmsa_ttbcr_raw_write(env, ri, value);
1448 }
1449
1450 static void vmsa_ttbcr_reset(CPUARMState *env, const ARMCPRegInfo *ri)
1451 {
1452     env->cp15.c2_base_mask = 0xffffc000u;
1453     raw_write(env, ri, 0);
1454     env->cp15.c2_mask = 0;
1455 }
1456
1457 static void vmsa_tcr_el1_write(CPUARMState *env, const ARMCPRegInfo *ri,
1458                                uint64_t value)
1459 {
1460     ARMCPU *cpu = arm_env_get_cpu(env);
1461
1462     /* For AArch64 the A1 bit could result in a change of ASID, so TLB flush. */
1463     tlb_flush(CPU(cpu), 1);
1464     raw_write(env, ri, value);
1465 }
1466
1467 static void vmsa_ttbr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1468                             uint64_t value)
1469 {
1470     /* 64 bit accesses to the TTBRs can change the ASID and so we
1471      * must flush the TLB.
1472      */
1473     if (cpreg_field_is_64bit(ri)) {
1474         ARMCPU *cpu = arm_env_get_cpu(env);
1475
1476         tlb_flush(CPU(cpu), 1);
1477     }
1478     raw_write(env, ri, value);
1479 }
1480
1481 static const ARMCPRegInfo vmsa_cp_reginfo[] = {
1482     { .name = "DFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0,
1483       .access = PL1_RW, .type = ARM_CP_NO_MIGRATE,
1484       .fieldoffset = offsetoflow32(CPUARMState, cp15.esr_el[1]),
1485       .resetfn = arm_cp_reset_ignore, },
1486     { .name = "IFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1,
1487       .access = PL1_RW,
1488       .fieldoffset = offsetof(CPUARMState, cp15.ifsr_el2), .resetvalue = 0, },
1489     { .name = "ESR_EL1", .state = ARM_CP_STATE_AA64,
1490       .opc0 = 3, .crn = 5, .crm = 2, .opc1 = 0, .opc2 = 0,
1491       .access = PL1_RW,
1492       .fieldoffset = offsetof(CPUARMState, cp15.esr_el[1]), .resetvalue = 0, },
1493     { .name = "TTBR0_EL1", .state = ARM_CP_STATE_BOTH,
1494       .opc0 = 3, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
1495       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el1),
1496       .writefn = vmsa_ttbr_write, .resetvalue = 0 },
1497     { .name = "TTBR1_EL1", .state = ARM_CP_STATE_BOTH,
1498       .opc0 = 3, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 1,
1499       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.ttbr1_el1),
1500       .writefn = vmsa_ttbr_write, .resetvalue = 0 },
1501     { .name = "TCR_EL1", .state = ARM_CP_STATE_AA64,
1502       .opc0 = 3, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2,
1503       .access = PL1_RW, .writefn = vmsa_tcr_el1_write,
1504       .resetfn = vmsa_ttbcr_reset, .raw_writefn = raw_write,
1505       .fieldoffset = offsetof(CPUARMState, cp15.c2_control) },
1506     { .name = "TTBCR", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2,
1507       .access = PL1_RW, .type = ARM_CP_NO_MIGRATE, .writefn = vmsa_ttbcr_write,
1508       .resetfn = arm_cp_reset_ignore, .raw_writefn = vmsa_ttbcr_raw_write,
1509       .fieldoffset = offsetoflow32(CPUARMState, cp15.c2_control) },
1510     /* 64-bit FAR; this entry also gives us the AArch32 DFAR */
1511     { .name = "FAR_EL1", .state = ARM_CP_STATE_BOTH,
1512       .opc0 = 3, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 0,
1513       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[1]),
1514       .resetvalue = 0, },
1515     REGINFO_SENTINEL
1516 };
1517
1518 static void omap_ticonfig_write(CPUARMState *env, const ARMCPRegInfo *ri,
1519                                 uint64_t value)
1520 {
1521     env->cp15.c15_ticonfig = value & 0xe7;
1522     /* The OS_TYPE bit in this register changes the reported CPUID! */
1523     env->cp15.c0_cpuid = (value & (1 << 5)) ?
1524         ARM_CPUID_TI915T : ARM_CPUID_TI925T;
1525 }
1526
1527 static void omap_threadid_write(CPUARMState *env, const ARMCPRegInfo *ri,
1528                                 uint64_t value)
1529 {
1530     env->cp15.c15_threadid = value & 0xffff;
1531 }
1532
1533 static void omap_wfi_write(CPUARMState *env, const ARMCPRegInfo *ri,
1534                            uint64_t value)
1535 {
1536     /* Wait-for-interrupt (deprecated) */
1537     cpu_interrupt(CPU(arm_env_get_cpu(env)), CPU_INTERRUPT_HALT);
1538 }
1539
1540 static void omap_cachemaint_write(CPUARMState *env, const ARMCPRegInfo *ri,
1541                                   uint64_t value)
1542 {
1543     /* On OMAP there are registers indicating the max/min index of dcache lines
1544      * containing a dirty line; cache flush operations have to reset these.
1545      */
1546     env->cp15.c15_i_max = 0x000;
1547     env->cp15.c15_i_min = 0xff0;
1548 }
1549
1550 static const ARMCPRegInfo omap_cp_reginfo[] = {
1551     { .name = "DFSR", .cp = 15, .crn = 5, .crm = CP_ANY,
1552       .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_OVERRIDE,
1553       .fieldoffset = offsetoflow32(CPUARMState, cp15.esr_el[1]),
1554       .resetvalue = 0, },
1555     { .name = "", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0,
1556       .access = PL1_RW, .type = ARM_CP_NOP },
1557     { .name = "TICONFIG", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0,
1558       .access = PL1_RW,
1559       .fieldoffset = offsetof(CPUARMState, cp15.c15_ticonfig), .resetvalue = 0,
1560       .writefn = omap_ticonfig_write },
1561     { .name = "IMAX", .cp = 15, .crn = 15, .crm = 2, .opc1 = 0, .opc2 = 0,
1562       .access = PL1_RW,
1563       .fieldoffset = offsetof(CPUARMState, cp15.c15_i_max), .resetvalue = 0, },
1564     { .name = "IMIN", .cp = 15, .crn = 15, .crm = 3, .opc1 = 0, .opc2 = 0,
1565       .access = PL1_RW, .resetvalue = 0xff0,
1566       .fieldoffset = offsetof(CPUARMState, cp15.c15_i_min) },
1567     { .name = "THREADID", .cp = 15, .crn = 15, .crm = 4, .opc1 = 0, .opc2 = 0,
1568       .access = PL1_RW,
1569       .fieldoffset = offsetof(CPUARMState, cp15.c15_threadid), .resetvalue = 0,
1570       .writefn = omap_threadid_write },
1571     { .name = "TI925T_STATUS", .cp = 15, .crn = 15,
1572       .crm = 8, .opc1 = 0, .opc2 = 0, .access = PL1_RW,
1573       .type = ARM_CP_NO_MIGRATE,
1574       .readfn = arm_cp_read_zero, .writefn = omap_wfi_write, },
1575     /* TODO: Peripheral port remap register:
1576      * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt controller
1577      * base address at $rn & ~0xfff and map size of 0x200 << ($rn & 0xfff),
1578      * when MMU is off.
1579      */
1580     { .name = "OMAP_CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY,
1581       .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W,
1582       .type = ARM_CP_OVERRIDE | ARM_CP_NO_MIGRATE,
1583       .writefn = omap_cachemaint_write },
1584     { .name = "C9", .cp = 15, .crn = 9,
1585       .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW,
1586       .type = ARM_CP_CONST | ARM_CP_OVERRIDE, .resetvalue = 0 },
1587     REGINFO_SENTINEL
1588 };
1589
1590 static void xscale_cpar_write(CPUARMState *env, const ARMCPRegInfo *ri,
1591                               uint64_t value)
1592 {
1593     value &= 0x3fff;
1594     if (env->cp15.c15_cpar != value) {
1595         /* Changes cp0 to cp13 behavior, so needs a TB flush.  */
1596         tb_flush(env);
1597         env->cp15.c15_cpar = value;
1598     }
1599 }
1600
1601 static const ARMCPRegInfo xscale_cp_reginfo[] = {
1602     { .name = "XSCALE_CPAR",
1603       .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, .access = PL1_RW,
1604       .fieldoffset = offsetof(CPUARMState, cp15.c15_cpar), .resetvalue = 0,
1605       .writefn = xscale_cpar_write, },
1606     { .name = "XSCALE_AUXCR",
1607       .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 1, .access = PL1_RW,
1608       .fieldoffset = offsetof(CPUARMState, cp15.c1_xscaleauxcr),
1609       .resetvalue = 0, },
1610     /* XScale specific cache-lockdown: since we have no cache we NOP these
1611      * and hope the guest does not really rely on cache behaviour.
1612      */
1613     { .name = "XSCALE_LOCK_ICACHE_LINE",
1614       .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0,
1615       .access = PL1_W, .type = ARM_CP_NOP },
1616     { .name = "XSCALE_UNLOCK_ICACHE",
1617       .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1,
1618       .access = PL1_W, .type = ARM_CP_NOP },
1619     { .name = "XSCALE_DCACHE_LOCK",
1620       .cp = 15, .opc1 = 0, .crn = 9, .crm = 2, .opc2 = 0,
1621       .access = PL1_RW, .type = ARM_CP_NOP },
1622     { .name = "XSCALE_UNLOCK_DCACHE",
1623       .cp = 15, .opc1 = 0, .crn = 9, .crm = 2, .opc2 = 1,
1624       .access = PL1_W, .type = ARM_CP_NOP },
1625     REGINFO_SENTINEL
1626 };
1627
1628 static const ARMCPRegInfo dummy_c15_cp_reginfo[] = {
1629     /* RAZ/WI the whole crn=15 space, when we don't have a more specific
1630      * implementation of this implementation-defined space.
1631      * Ideally this should eventually disappear in favour of actually
1632      * implementing the correct behaviour for all cores.
1633      */
1634     { .name = "C15_IMPDEF", .cp = 15, .crn = 15,
1635       .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
1636       .access = PL1_RW,
1637       .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE | ARM_CP_OVERRIDE,
1638       .resetvalue = 0 },
1639     REGINFO_SENTINEL
1640 };
1641
1642 static const ARMCPRegInfo cache_dirty_status_cp_reginfo[] = {
1643     /* Cache status: RAZ because we have no cache so it's always clean */
1644     { .name = "CDSR", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 6,
1645       .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE,
1646       .resetvalue = 0 },
1647     REGINFO_SENTINEL
1648 };
1649
1650 static const ARMCPRegInfo cache_block_ops_cp_reginfo[] = {
1651     /* We never have a a block transfer operation in progress */
1652     { .name = "BXSR", .cp = 15, .crn = 7, .crm = 12, .opc1 = 0, .opc2 = 4,
1653       .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE,
1654       .resetvalue = 0 },
1655     /* The cache ops themselves: these all NOP for QEMU */
1656     { .name = "IICR", .cp = 15, .crm = 5, .opc1 = 0,
1657       .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
1658     { .name = "IDCR", .cp = 15, .crm = 6, .opc1 = 0,
1659       .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
1660     { .name = "CDCR", .cp = 15, .crm = 12, .opc1 = 0,
1661       .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
1662     { .name = "PIR", .cp = 15, .crm = 12, .opc1 = 1,
1663       .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
1664     { .name = "PDR", .cp = 15, .crm = 12, .opc1 = 2,
1665       .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
1666     { .name = "CIDCR", .cp = 15, .crm = 14, .opc1 = 0,
1667       .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
1668     REGINFO_SENTINEL
1669 };
1670
1671 static const ARMCPRegInfo cache_test_clean_cp_reginfo[] = {
1672     /* The cache test-and-clean instructions always return (1 << 30)
1673      * to indicate that there are no dirty cache lines.
1674      */
1675     { .name = "TC_DCACHE", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 3,
1676       .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE,
1677       .resetvalue = (1 << 30) },
1678     { .name = "TCI_DCACHE", .cp = 15, .crn = 7, .crm = 14, .opc1 = 0, .opc2 = 3,
1679       .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE,
1680       .resetvalue = (1 << 30) },
1681     REGINFO_SENTINEL
1682 };
1683
1684 static const ARMCPRegInfo strongarm_cp_reginfo[] = {
1685     /* Ignore ReadBuffer accesses */
1686     { .name = "C9_READBUFFER", .cp = 15, .crn = 9,
1687       .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
1688       .access = PL1_RW, .resetvalue = 0,
1689       .type = ARM_CP_CONST | ARM_CP_OVERRIDE | ARM_CP_NO_MIGRATE },
1690     REGINFO_SENTINEL
1691 };
1692
1693 static uint64_t mpidr_read(CPUARMState *env, const ARMCPRegInfo *ri)
1694 {
1695     CPUState *cs = CPU(arm_env_get_cpu(env));
1696     uint32_t mpidr = cs->cpu_index;
1697     /* We don't support setting cluster ID ([8..11]) (known as Aff1
1698      * in later ARM ARM versions), or any of the higher affinity level fields,
1699      * so these bits always RAZ.
1700      */
1701     if (arm_feature(env, ARM_FEATURE_V7MP)) {
1702         mpidr |= (1U << 31);
1703         /* Cores which are uniprocessor (non-coherent)
1704          * but still implement the MP extensions set
1705          * bit 30. (For instance, A9UP.) However we do
1706          * not currently model any of those cores.
1707          */
1708     }
1709     return mpidr;
1710 }
1711
1712 static const ARMCPRegInfo mpidr_cp_reginfo[] = {
1713     { .name = "MPIDR", .state = ARM_CP_STATE_BOTH,
1714       .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 5,
1715       .access = PL1_R, .readfn = mpidr_read, .type = ARM_CP_NO_MIGRATE },
1716     REGINFO_SENTINEL
1717 };
1718
1719 static const ARMCPRegInfo lpae_cp_reginfo[] = {
1720     /* NOP AMAIR0/1: the override is because these clash with the rather
1721      * broadly specified TLB_LOCKDOWN entry in the generic cp_reginfo.
1722      */
1723     { .name = "AMAIR0", .state = ARM_CP_STATE_BOTH,
1724       .opc0 = 3, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 0,
1725       .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_OVERRIDE,
1726       .resetvalue = 0 },
1727     /* AMAIR1 is mapped to AMAIR_EL1[63:32] */
1728     { .name = "AMAIR1", .cp = 15, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 1,
1729       .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_OVERRIDE,
1730       .resetvalue = 0 },
1731     { .name = "PAR", .cp = 15, .crm = 7, .opc1 = 0,
1732       .access = PL1_RW, .type = ARM_CP_64BIT,
1733       .fieldoffset = offsetof(CPUARMState, cp15.par_el1), .resetvalue = 0 },
1734     { .name = "TTBR0", .cp = 15, .crm = 2, .opc1 = 0,
1735       .access = PL1_RW, .type = ARM_CP_64BIT | ARM_CP_NO_MIGRATE,
1736       .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el1),
1737       .writefn = vmsa_ttbr_write, .resetfn = arm_cp_reset_ignore },
1738     { .name = "TTBR1", .cp = 15, .crm = 2, .opc1 = 1,
1739       .access = PL1_RW, .type = ARM_CP_64BIT | ARM_CP_NO_MIGRATE,
1740       .fieldoffset = offsetof(CPUARMState, cp15.ttbr1_el1),
1741       .writefn = vmsa_ttbr_write, .resetfn = arm_cp_reset_ignore },
1742     REGINFO_SENTINEL
1743 };
1744
1745 static uint64_t aa64_fpcr_read(CPUARMState *env, const ARMCPRegInfo *ri)
1746 {
1747     return vfp_get_fpcr(env);
1748 }
1749
1750 static void aa64_fpcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1751                             uint64_t value)
1752 {
1753     vfp_set_fpcr(env, value);
1754 }
1755
1756 static uint64_t aa64_fpsr_read(CPUARMState *env, const ARMCPRegInfo *ri)
1757 {
1758     return vfp_get_fpsr(env);
1759 }
1760
1761 static void aa64_fpsr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1762                             uint64_t value)
1763 {
1764     vfp_set_fpsr(env, value);
1765 }
1766
1767 static CPAccessResult aa64_daif_access(CPUARMState *env, const ARMCPRegInfo *ri)
1768 {
1769     if (arm_current_pl(env) == 0 && !(env->cp15.c1_sys & SCTLR_UMA)) {
1770         return CP_ACCESS_TRAP;
1771     }
1772     return CP_ACCESS_OK;
1773 }
1774
1775 static void aa64_daif_write(CPUARMState *env, const ARMCPRegInfo *ri,
1776                             uint64_t value)
1777 {
1778     env->daif = value & PSTATE_DAIF;
1779 }
1780
1781 static CPAccessResult aa64_cacheop_access(CPUARMState *env,
1782                                           const ARMCPRegInfo *ri)
1783 {
1784     /* Cache invalidate/clean: NOP, but EL0 must UNDEF unless
1785      * SCTLR_EL1.UCI is set.
1786      */
1787     if (arm_current_pl(env) == 0 && !(env->cp15.c1_sys & SCTLR_UCI)) {
1788         return CP_ACCESS_TRAP;
1789     }
1790     return CP_ACCESS_OK;
1791 }
1792
1793 /* See: D4.7.2 TLB maintenance requirements and the TLB maintenance instructions
1794  * Page D4-1736 (DDI0487A.b)
1795  */
1796
1797 static void tlbi_aa64_va_write(CPUARMState *env, const ARMCPRegInfo *ri,
1798                                uint64_t value)
1799 {
1800     /* Invalidate by VA (AArch64 version) */
1801     ARMCPU *cpu = arm_env_get_cpu(env);
1802     uint64_t pageaddr = sextract64(value << 12, 0, 56);
1803
1804     tlb_flush_page(CPU(cpu), pageaddr);
1805 }
1806
1807 static void tlbi_aa64_vaa_write(CPUARMState *env, const ARMCPRegInfo *ri,
1808                                 uint64_t value)
1809 {
1810     /* Invalidate by VA, all ASIDs (AArch64 version) */
1811     ARMCPU *cpu = arm_env_get_cpu(env);
1812     uint64_t pageaddr = sextract64(value << 12, 0, 56);
1813
1814     tlb_flush_page(CPU(cpu), pageaddr);
1815 }
1816
1817 static void tlbi_aa64_asid_write(CPUARMState *env, const ARMCPRegInfo *ri,
1818                                  uint64_t value)
1819 {
1820     /* Invalidate by ASID (AArch64 version) */
1821     ARMCPU *cpu = arm_env_get_cpu(env);
1822     int asid = extract64(value, 48, 16);
1823     tlb_flush(CPU(cpu), asid == 0);
1824 }
1825
1826 static CPAccessResult aa64_zva_access(CPUARMState *env, const ARMCPRegInfo *ri)
1827 {
1828     /* We don't implement EL2, so the only control on DC ZVA is the
1829      * bit in the SCTLR which can prohibit access for EL0.
1830      */
1831     if (arm_current_pl(env) == 0 && !(env->cp15.c1_sys & SCTLR_DZE)) {
1832         return CP_ACCESS_TRAP;
1833     }
1834     return CP_ACCESS_OK;
1835 }
1836
1837 static uint64_t aa64_dczid_read(CPUARMState *env, const ARMCPRegInfo *ri)
1838 {
1839     ARMCPU *cpu = arm_env_get_cpu(env);
1840     int dzp_bit = 1 << 4;
1841
1842     /* DZP indicates whether DC ZVA access is allowed */
1843     if (aa64_zva_access(env, NULL) != CP_ACCESS_OK) {
1844         dzp_bit = 0;
1845     }
1846     return cpu->dcz_blocksize | dzp_bit;
1847 }
1848
1849 static CPAccessResult sp_el0_access(CPUARMState *env, const ARMCPRegInfo *ri)
1850 {
1851     if (!(env->pstate & PSTATE_SP)) {
1852         /* Access to SP_EL0 is undefined if it's being used as
1853          * the stack pointer.
1854          */
1855         return CP_ACCESS_TRAP_UNCATEGORIZED;
1856     }
1857     return CP_ACCESS_OK;
1858 }
1859
1860 static uint64_t spsel_read(CPUARMState *env, const ARMCPRegInfo *ri)
1861 {
1862     return env->pstate & PSTATE_SP;
1863 }
1864
1865 static void spsel_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t val)
1866 {
1867     update_spsel(env, val);
1868 }
1869
1870 static const ARMCPRegInfo v8_cp_reginfo[] = {
1871     /* Minimal set of EL0-visible registers. This will need to be expanded
1872      * significantly for system emulation of AArch64 CPUs.
1873      */
1874     { .name = "NZCV", .state = ARM_CP_STATE_AA64,
1875       .opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 2,
1876       .access = PL0_RW, .type = ARM_CP_NZCV },
1877     { .name = "DAIF", .state = ARM_CP_STATE_AA64,
1878       .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 4, .crm = 2,
1879       .type = ARM_CP_NO_MIGRATE,
1880       .access = PL0_RW, .accessfn = aa64_daif_access,
1881       .fieldoffset = offsetof(CPUARMState, daif),
1882       .writefn = aa64_daif_write, .resetfn = arm_cp_reset_ignore },
1883     { .name = "FPCR", .state = ARM_CP_STATE_AA64,
1884       .opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 4,
1885       .access = PL0_RW, .readfn = aa64_fpcr_read, .writefn = aa64_fpcr_write },
1886     { .name = "FPSR", .state = ARM_CP_STATE_AA64,
1887       .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 4, .crm = 4,
1888       .access = PL0_RW, .readfn = aa64_fpsr_read, .writefn = aa64_fpsr_write },
1889     { .name = "DCZID_EL0", .state = ARM_CP_STATE_AA64,
1890       .opc0 = 3, .opc1 = 3, .opc2 = 7, .crn = 0, .crm = 0,
1891       .access = PL0_R, .type = ARM_CP_NO_MIGRATE,
1892       .readfn = aa64_dczid_read },
1893     { .name = "DC_ZVA", .state = ARM_CP_STATE_AA64,
1894       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 4, .opc2 = 1,
1895       .access = PL0_W, .type = ARM_CP_DC_ZVA,
1896 #ifndef CONFIG_USER_ONLY
1897       /* Avoid overhead of an access check that always passes in user-mode */
1898       .accessfn = aa64_zva_access,
1899 #endif
1900     },
1901     { .name = "CURRENTEL", .state = ARM_CP_STATE_AA64,
1902       .opc0 = 3, .opc1 = 0, .opc2 = 2, .crn = 4, .crm = 2,
1903       .access = PL1_R, .type = ARM_CP_CURRENTEL },
1904     /* Cache ops: all NOPs since we don't emulate caches */
1905     { .name = "IC_IALLUIS", .state = ARM_CP_STATE_AA64,
1906       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 0,
1907       .access = PL1_W, .type = ARM_CP_NOP },
1908     { .name = "IC_IALLU", .state = ARM_CP_STATE_AA64,
1909       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 0,
1910       .access = PL1_W, .type = ARM_CP_NOP },
1911     { .name = "IC_IVAU", .state = ARM_CP_STATE_AA64,
1912       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 5, .opc2 = 1,
1913       .access = PL0_W, .type = ARM_CP_NOP,
1914       .accessfn = aa64_cacheop_access },
1915     { .name = "DC_IVAC", .state = ARM_CP_STATE_AA64,
1916       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 1,
1917       .access = PL1_W, .type = ARM_CP_NOP },
1918     { .name = "DC_ISW", .state = ARM_CP_STATE_AA64,
1919       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 2,
1920       .access = PL1_W, .type = ARM_CP_NOP },
1921     { .name = "DC_CVAC", .state = ARM_CP_STATE_AA64,
1922       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 10, .opc2 = 1,
1923       .access = PL0_W, .type = ARM_CP_NOP,
1924       .accessfn = aa64_cacheop_access },
1925     { .name = "DC_CSW", .state = ARM_CP_STATE_AA64,
1926       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 2,
1927       .access = PL1_W, .type = ARM_CP_NOP },
1928     { .name = "DC_CVAU", .state = ARM_CP_STATE_AA64,
1929       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 11, .opc2 = 1,
1930       .access = PL0_W, .type = ARM_CP_NOP,
1931       .accessfn = aa64_cacheop_access },
1932     { .name = "DC_CIVAC", .state = ARM_CP_STATE_AA64,
1933       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 14, .opc2 = 1,
1934       .access = PL0_W, .type = ARM_CP_NOP,
1935       .accessfn = aa64_cacheop_access },
1936     { .name = "DC_CISW", .state = ARM_CP_STATE_AA64,
1937       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 2,
1938       .access = PL1_W, .type = ARM_CP_NOP },
1939     /* TLBI operations */
1940     { .name = "TLBI_VMALLE1IS", .state = ARM_CP_STATE_AA64,
1941       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0,
1942       .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
1943       .writefn = tlbiall_write },
1944     { .name = "TLBI_VAE1IS", .state = ARM_CP_STATE_AA64,
1945       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 1,
1946       .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
1947       .writefn = tlbi_aa64_va_write },
1948     { .name = "TLBI_ASIDE1IS", .state = ARM_CP_STATE_AA64,
1949       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 2,
1950       .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
1951       .writefn = tlbi_aa64_asid_write },
1952     { .name = "TLBI_VAAE1IS", .state = ARM_CP_STATE_AA64,
1953       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 3,
1954       .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
1955       .writefn = tlbi_aa64_vaa_write },
1956     { .name = "TLBI_VALE1IS", .state = ARM_CP_STATE_AA64,
1957       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5,
1958       .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
1959       .writefn = tlbi_aa64_va_write },
1960     { .name = "TLBI_VAALE1IS", .state = ARM_CP_STATE_AA64,
1961       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 7,
1962       .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
1963       .writefn = tlbi_aa64_vaa_write },
1964     { .name = "TLBI_VMALLE1", .state = ARM_CP_STATE_AA64,
1965       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 0,
1966       .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
1967       .writefn = tlbiall_write },
1968     { .name = "TLBI_VAE1", .state = ARM_CP_STATE_AA64,
1969       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 1,
1970       .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
1971       .writefn = tlbi_aa64_va_write },
1972     { .name = "TLBI_ASIDE1", .state = ARM_CP_STATE_AA64,
1973       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 2,
1974       .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
1975       .writefn = tlbi_aa64_asid_write },
1976     { .name = "TLBI_VAAE1", .state = ARM_CP_STATE_AA64,
1977       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 3,
1978       .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
1979       .writefn = tlbi_aa64_vaa_write },
1980     { .name = "TLBI_VALE1", .state = ARM_CP_STATE_AA64,
1981       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 5,
1982       .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
1983       .writefn = tlbi_aa64_va_write },
1984     { .name = "TLBI_VAALE1", .state = ARM_CP_STATE_AA64,
1985       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 7,
1986       .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
1987       .writefn = tlbi_aa64_vaa_write },
1988 #ifndef CONFIG_USER_ONLY
1989     /* 64 bit address translation operations */
1990     { .name = "AT_S1E1R", .state = ARM_CP_STATE_AA64,
1991       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 0,
1992       .access = PL1_W, .type = ARM_CP_NO_MIGRATE, .writefn = ats_write },
1993     { .name = "AT_S1E1W", .state = ARM_CP_STATE_AA64,
1994       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 1,
1995       .access = PL1_W, .type = ARM_CP_NO_MIGRATE, .writefn = ats_write },
1996     { .name = "AT_S1E0R", .state = ARM_CP_STATE_AA64,
1997       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 2,
1998       .access = PL1_W, .type = ARM_CP_NO_MIGRATE, .writefn = ats_write },
1999     { .name = "AT_S1E0W", .state = ARM_CP_STATE_AA64,
2000       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 3,
2001       .access = PL1_W, .type = ARM_CP_NO_MIGRATE, .writefn = ats_write },
2002 #endif
2003     /* 32 bit TLB invalidates, Inner Shareable */
2004     { .name = "TLBIALLIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0,
2005       .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbiall_write },
2006     { .name = "TLBIMVAIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 1,
2007       .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbimva_write },
2008     { .name = "TLBIASIDIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 2,
2009       .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbiasid_write },
2010     { .name = "TLBIMVAAIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 3,
2011       .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbimvaa_write },
2012     { .name = "TLBIMVALIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5,
2013       .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbimva_write },
2014     { .name = "TLBIMVAALIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 7,
2015       .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbimvaa_write },
2016     /* 32 bit ITLB invalidates */
2017     { .name = "ITLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 0,
2018       .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbiall_write },
2019     { .name = "ITLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 1,
2020       .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbimva_write },
2021     { .name = "ITLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 2,
2022       .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbiasid_write },
2023     /* 32 bit DTLB invalidates */
2024     { .name = "DTLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 0,
2025       .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbiall_write },
2026     { .name = "DTLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 1,
2027       .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbimva_write },
2028     { .name = "DTLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 2,
2029       .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbiasid_write },
2030     /* 32 bit TLB invalidates */
2031     { .name = "TLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 0,
2032       .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbiall_write },
2033     { .name = "TLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 1,
2034       .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbimva_write },
2035     { .name = "TLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 2,
2036       .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbiasid_write },
2037     { .name = "TLBIMVAA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 3,
2038       .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbimvaa_write },
2039     { .name = "TLBIMVAL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 5,
2040       .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbimva_write },
2041     { .name = "TLBIMVAAL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 7,
2042       .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbimvaa_write },
2043     /* 32 bit cache operations */
2044     { .name = "ICIALLUIS", .cp = 15, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 0,
2045       .type = ARM_CP_NOP, .access = PL1_W },
2046     { .name = "BPIALLUIS", .cp = 15, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 6,
2047       .type = ARM_CP_NOP, .access = PL1_W },
2048     { .name = "ICIALLU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 0,
2049       .type = ARM_CP_NOP, .access = PL1_W },
2050     { .name = "ICIMVAU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 1,
2051       .type = ARM_CP_NOP, .access = PL1_W },
2052     { .name = "BPIALL", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 6,
2053       .type = ARM_CP_NOP, .access = PL1_W },
2054     { .name = "BPIMVA", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 7,
2055       .type = ARM_CP_NOP, .access = PL1_W },
2056     { .name = "DCIMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 1,
2057       .type = ARM_CP_NOP, .access = PL1_W },
2058     { .name = "DCISW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 2,
2059       .type = ARM_CP_NOP, .access = PL1_W },
2060     { .name = "DCCMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 1,
2061       .type = ARM_CP_NOP, .access = PL1_W },
2062     { .name = "DCCSW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 2,
2063       .type = ARM_CP_NOP, .access = PL1_W },
2064     { .name = "DCCMVAU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 11, .opc2 = 1,
2065       .type = ARM_CP_NOP, .access = PL1_W },
2066     { .name = "DCCIMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 1,
2067       .type = ARM_CP_NOP, .access = PL1_W },
2068     { .name = "DCCISW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 2,
2069       .type = ARM_CP_NOP, .access = PL1_W },
2070     /* MMU Domain access control / MPU write buffer control */
2071     { .name = "DACR", .cp = 15,
2072       .opc1 = 0, .crn = 3, .crm = 0, .opc2 = 0,
2073       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c3),
2074       .resetvalue = 0, .writefn = dacr_write, .raw_writefn = raw_write, },
2075     { .name = "ELR_EL1", .state = ARM_CP_STATE_AA64,
2076       .type = ARM_CP_NO_MIGRATE,
2077       .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 0, .opc2 = 1,
2078       .access = PL1_RW,
2079       .fieldoffset = offsetof(CPUARMState, elr_el[1]) },
2080     { .name = "SPSR_EL1", .state = ARM_CP_STATE_AA64,
2081       .type = ARM_CP_NO_MIGRATE,
2082       .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 0, .opc2 = 0,
2083       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, banked_spsr[0]) },
2084     /* We rely on the access checks not allowing the guest to write to the
2085      * state field when SPSel indicates that it's being used as the stack
2086      * pointer.
2087      */
2088     { .name = "SP_EL0", .state = ARM_CP_STATE_AA64,
2089       .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 1, .opc2 = 0,
2090       .access = PL1_RW, .accessfn = sp_el0_access,
2091       .type = ARM_CP_NO_MIGRATE,
2092       .fieldoffset = offsetof(CPUARMState, sp_el[0]) },
2093     { .name = "SPSel", .state = ARM_CP_STATE_AA64,
2094       .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 2, .opc2 = 0,
2095       .type = ARM_CP_NO_MIGRATE,
2096       .access = PL1_RW, .readfn = spsel_read, .writefn = spsel_write },
2097     REGINFO_SENTINEL
2098 };
2099
2100 /* Used to describe the behaviour of EL2 regs when EL2 does not exist.  */
2101 static const ARMCPRegInfo v8_el3_no_el2_cp_reginfo[] = {
2102     { .name = "VBAR_EL2", .state = ARM_CP_STATE_AA64,
2103       .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 0,
2104       .access = PL2_RW,
2105       .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore },
2106     REGINFO_SENTINEL
2107 };
2108
2109 static const ARMCPRegInfo v8_el2_cp_reginfo[] = {
2110     { .name = "ELR_EL2", .state = ARM_CP_STATE_AA64,
2111       .type = ARM_CP_NO_MIGRATE,
2112       .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 1,
2113       .access = PL2_RW,
2114       .fieldoffset = offsetof(CPUARMState, elr_el[2]) },
2115     { .name = "ESR_EL2", .state = ARM_CP_STATE_AA64,
2116       .type = ARM_CP_NO_MIGRATE,
2117       .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 2, .opc2 = 0,
2118       .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.esr_el[2]) },
2119     { .name = "FAR_EL2", .state = ARM_CP_STATE_AA64,
2120       .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 0,
2121       .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[2]) },
2122     { .name = "SPSR_EL2", .state = ARM_CP_STATE_AA64,
2123       .type = ARM_CP_NO_MIGRATE,
2124       .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 0,
2125       .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, banked_spsr[6]) },
2126     { .name = "VBAR_EL2", .state = ARM_CP_STATE_AA64,
2127       .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 0,
2128       .access = PL2_RW, .writefn = vbar_write,
2129       .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[2]),
2130       .resetvalue = 0 },
2131     REGINFO_SENTINEL
2132 };
2133
2134 static const ARMCPRegInfo v8_el3_cp_reginfo[] = {
2135     { .name = "ELR_EL3", .state = ARM_CP_STATE_AA64,
2136       .type = ARM_CP_NO_MIGRATE,
2137       .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 0, .opc2 = 1,
2138       .access = PL3_RW,
2139       .fieldoffset = offsetof(CPUARMState, elr_el[3]) },
2140     { .name = "ESR_EL3", .state = ARM_CP_STATE_AA64,
2141       .type = ARM_CP_NO_MIGRATE,
2142       .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 2, .opc2 = 0,
2143       .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.esr_el[3]) },
2144     { .name = "FAR_EL3", .state = ARM_CP_STATE_AA64,
2145       .opc0 = 3, .opc1 = 6, .crn = 6, .crm = 0, .opc2 = 0,
2146       .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[3]) },
2147     { .name = "SPSR_EL3", .state = ARM_CP_STATE_AA64,
2148       .type = ARM_CP_NO_MIGRATE,
2149       .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 0, .opc2 = 0,
2150       .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, banked_spsr[7]) },
2151     { .name = "VBAR_EL3", .state = ARM_CP_STATE_AA64,
2152       .opc0 = 3, .opc1 = 6, .crn = 12, .crm = 0, .opc2 = 0,
2153       .access = PL3_RW, .writefn = vbar_write,
2154       .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[3]),
2155       .resetvalue = 0 },
2156     REGINFO_SENTINEL
2157 };
2158
2159 static void sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri,
2160                         uint64_t value)
2161 {
2162     ARMCPU *cpu = arm_env_get_cpu(env);
2163
2164     if (raw_read(env, ri) == value) {
2165         /* Skip the TLB flush if nothing actually changed; Linux likes
2166          * to do a lot of pointless SCTLR writes.
2167          */
2168         return;
2169     }
2170
2171     raw_write(env, ri, value);
2172     /* ??? Lots of these bits are not implemented.  */
2173     /* This may enable/disable the MMU, so do a TLB flush.  */
2174     tlb_flush(CPU(cpu), 1);
2175 }
2176
2177 static CPAccessResult ctr_el0_access(CPUARMState *env, const ARMCPRegInfo *ri)
2178 {
2179     /* Only accessible in EL0 if SCTLR.UCT is set (and only in AArch64,
2180      * but the AArch32 CTR has its own reginfo struct)
2181      */
2182     if (arm_current_pl(env) == 0 && !(env->cp15.c1_sys & SCTLR_UCT)) {
2183         return CP_ACCESS_TRAP;
2184     }
2185     return CP_ACCESS_OK;
2186 }
2187
2188 static const ARMCPRegInfo debug_cp_reginfo[] = {
2189     /* DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped
2190      * debug components. The AArch64 version of DBGDRAR is named MDRAR_EL1;
2191      * unlike DBGDRAR it is never accessible from EL0.
2192      * DBGDSAR is deprecated and must RAZ from v8 anyway, so it has no AArch64
2193      * accessor.
2194      */
2195     { .name = "DBGDRAR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0,
2196       .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
2197     { .name = "MDRAR_EL1", .state = ARM_CP_STATE_AA64,
2198       .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 0,
2199       .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
2200     { .name = "DBGDSAR", .cp = 14, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
2201       .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
2202     /* Dummy implementation of monitor debug system control register:
2203      * we don't support debug. (The 32-bit alias is DBGDSCRext.)
2204      */
2205     { .name = "MDSCR_EL1", .state = ARM_CP_STATE_BOTH,
2206       .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2,
2207       .access = PL1_RW,
2208       .fieldoffset = offsetof(CPUARMState, cp15.mdscr_el1),
2209       .resetvalue = 0 },
2210     /* We define a dummy WI OSLAR_EL1, because Linux writes to it. */
2211     { .name = "OSLAR_EL1", .state = ARM_CP_STATE_BOTH,
2212       .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 4,
2213       .access = PL1_W, .type = ARM_CP_NOP },
2214     REGINFO_SENTINEL
2215 };
2216
2217 static const ARMCPRegInfo debug_lpae_cp_reginfo[] = {
2218     /* 64 bit access versions of the (dummy) debug registers */
2219     { .name = "DBGDRAR", .cp = 14, .crm = 1, .opc1 = 0,
2220       .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 },
2221     { .name = "DBGDSAR", .cp = 14, .crm = 2, .opc1 = 0,
2222       .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 },
2223     REGINFO_SENTINEL
2224 };
2225
2226 static void define_debug_regs(ARMCPU *cpu)
2227 {
2228     /* Define v7 and v8 architectural debug registers.
2229      * These are just dummy implementations for now.
2230      */
2231     int i;
2232     int wrps, brps;
2233     ARMCPRegInfo dbgdidr = {
2234         .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0,
2235         .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = cpu->dbgdidr,
2236     };
2237
2238     brps = extract32(cpu->dbgdidr, 24, 4);
2239     wrps = extract32(cpu->dbgdidr, 28, 4);
2240
2241     /* The DBGDIDR and ID_AA64DFR0_EL1 define various properties
2242      * of the debug registers such as number of breakpoints;
2243      * check that if they both exist then they agree.
2244      */
2245     if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
2246         assert(extract32(cpu->id_aa64dfr0, 12, 4) == brps);
2247         assert(extract32(cpu->id_aa64dfr0, 20, 4) == wrps);
2248     }
2249
2250     define_one_arm_cp_reg(cpu, &dbgdidr);
2251     define_arm_cp_regs(cpu, debug_cp_reginfo);
2252
2253     if (arm_feature(&cpu->env, ARM_FEATURE_LPAE)) {
2254         define_arm_cp_regs(cpu, debug_lpae_cp_reginfo);
2255     }
2256
2257     for (i = 0; i < brps + 1; i++) {
2258         ARMCPRegInfo dbgregs[] = {
2259             { .name = "DBGBVR", .state = ARM_CP_STATE_BOTH,
2260               .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 4,
2261               .access = PL1_RW,
2262               .fieldoffset = offsetof(CPUARMState, cp15.dbgbvr[i]) },
2263             { .name = "DBGBCR", .state = ARM_CP_STATE_BOTH,
2264               .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 5,
2265               .access = PL1_RW,
2266               .fieldoffset = offsetof(CPUARMState, cp15.dbgbcr[i]) },
2267             REGINFO_SENTINEL
2268         };
2269         define_arm_cp_regs(cpu, dbgregs);
2270     }
2271
2272     for (i = 0; i < wrps + 1; i++) {
2273         ARMCPRegInfo dbgregs[] = {
2274             { .name = "DBGWVR", .state = ARM_CP_STATE_BOTH,
2275               .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 6,
2276               .access = PL1_RW,
2277               .fieldoffset = offsetof(CPUARMState, cp15.dbgwvr[i]) },
2278             { .name = "DBGWCR", .state = ARM_CP_STATE_BOTH,
2279               .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 7,
2280               .access = PL1_RW,
2281               .fieldoffset = offsetof(CPUARMState, cp15.dbgwcr[i]) },
2282                REGINFO_SENTINEL
2283         };
2284         define_arm_cp_regs(cpu, dbgregs);
2285     }
2286 }
2287
2288 void register_cp_regs_for_features(ARMCPU *cpu)
2289 {
2290     /* Register all the coprocessor registers based on feature bits */
2291     CPUARMState *env = &cpu->env;
2292     if (arm_feature(env, ARM_FEATURE_M)) {
2293         /* M profile has no coprocessor registers */
2294         return;
2295     }
2296
2297     define_arm_cp_regs(cpu, cp_reginfo);
2298     if (!arm_feature(env, ARM_FEATURE_V8)) {
2299         /* Must go early as it is full of wildcards that may be
2300          * overridden by later definitions.
2301          */
2302         define_arm_cp_regs(cpu, not_v8_cp_reginfo);
2303     }
2304
2305     if (arm_feature(env, ARM_FEATURE_V6)) {
2306         /* The ID registers all have impdef reset values */
2307         ARMCPRegInfo v6_idregs[] = {
2308             { .name = "ID_PFR0", .state = ARM_CP_STATE_BOTH,
2309               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0,
2310               .access = PL1_R, .type = ARM_CP_CONST,
2311               .resetvalue = cpu->id_pfr0 },
2312             { .name = "ID_PFR1", .state = ARM_CP_STATE_BOTH,
2313               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 1,
2314               .access = PL1_R, .type = ARM_CP_CONST,
2315               .resetvalue = cpu->id_pfr1 },
2316             { .name = "ID_DFR0", .state = ARM_CP_STATE_BOTH,
2317               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 2,
2318               .access = PL1_R, .type = ARM_CP_CONST,
2319               .resetvalue = cpu->id_dfr0 },
2320             { .name = "ID_AFR0", .state = ARM_CP_STATE_BOTH,
2321               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 3,
2322               .access = PL1_R, .type = ARM_CP_CONST,
2323               .resetvalue = cpu->id_afr0 },
2324             { .name = "ID_MMFR0", .state = ARM_CP_STATE_BOTH,
2325               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 4,
2326               .access = PL1_R, .type = ARM_CP_CONST,
2327               .resetvalue = cpu->id_mmfr0 },
2328             { .name = "ID_MMFR1", .state = ARM_CP_STATE_BOTH,
2329               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 5,
2330               .access = PL1_R, .type = ARM_CP_CONST,
2331               .resetvalue = cpu->id_mmfr1 },
2332             { .name = "ID_MMFR2", .state = ARM_CP_STATE_BOTH,
2333               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 6,
2334               .access = PL1_R, .type = ARM_CP_CONST,
2335               .resetvalue = cpu->id_mmfr2 },
2336             { .name = "ID_MMFR3", .state = ARM_CP_STATE_BOTH,
2337               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 7,
2338               .access = PL1_R, .type = ARM_CP_CONST,
2339               .resetvalue = cpu->id_mmfr3 },
2340             { .name = "ID_ISAR0", .state = ARM_CP_STATE_BOTH,
2341               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 0,
2342               .access = PL1_R, .type = ARM_CP_CONST,
2343               .resetvalue = cpu->id_isar0 },
2344             { .name = "ID_ISAR1", .state = ARM_CP_STATE_BOTH,
2345               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 1,
2346               .access = PL1_R, .type = ARM_CP_CONST,
2347               .resetvalue = cpu->id_isar1 },
2348             { .name = "ID_ISAR2", .state = ARM_CP_STATE_BOTH,
2349               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2,
2350               .access = PL1_R, .type = ARM_CP_CONST,
2351               .resetvalue = cpu->id_isar2 },
2352             { .name = "ID_ISAR3", .state = ARM_CP_STATE_BOTH,
2353               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 3,
2354               .access = PL1_R, .type = ARM_CP_CONST,
2355               .resetvalue = cpu->id_isar3 },
2356             { .name = "ID_ISAR4", .state = ARM_CP_STATE_BOTH,
2357               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 4,
2358               .access = PL1_R, .type = ARM_CP_CONST,
2359               .resetvalue = cpu->id_isar4 },
2360             { .name = "ID_ISAR5", .state = ARM_CP_STATE_BOTH,
2361               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 5,
2362               .access = PL1_R, .type = ARM_CP_CONST,
2363               .resetvalue = cpu->id_isar5 },
2364             /* 6..7 are as yet unallocated and must RAZ */
2365             { .name = "ID_ISAR6", .cp = 15, .crn = 0, .crm = 2,
2366               .opc1 = 0, .opc2 = 6, .access = PL1_R, .type = ARM_CP_CONST,
2367               .resetvalue = 0 },
2368             { .name = "ID_ISAR7", .cp = 15, .crn = 0, .crm = 2,
2369               .opc1 = 0, .opc2 = 7, .access = PL1_R, .type = ARM_CP_CONST,
2370               .resetvalue = 0 },
2371             REGINFO_SENTINEL
2372         };
2373         define_arm_cp_regs(cpu, v6_idregs);
2374         define_arm_cp_regs(cpu, v6_cp_reginfo);
2375     } else {
2376         define_arm_cp_regs(cpu, not_v6_cp_reginfo);
2377     }
2378     if (arm_feature(env, ARM_FEATURE_V6K)) {
2379         define_arm_cp_regs(cpu, v6k_cp_reginfo);
2380     }
2381     if (arm_feature(env, ARM_FEATURE_V7)) {
2382         /* v7 performance monitor control register: same implementor
2383          * field as main ID register, and we implement only the cycle
2384          * count register.
2385          */
2386 #ifndef CONFIG_USER_ONLY
2387         ARMCPRegInfo pmcr = {
2388             .name = "PMCR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 0,
2389             .access = PL0_RW, .resetvalue = cpu->midr & 0xff000000,
2390             .type = ARM_CP_IO,
2391             .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcr),
2392             .accessfn = pmreg_access, .writefn = pmcr_write,
2393             .raw_writefn = raw_write,
2394         };
2395         define_one_arm_cp_reg(cpu, &pmcr);
2396 #endif
2397         ARMCPRegInfo clidr = {
2398             .name = "CLIDR", .state = ARM_CP_STATE_BOTH,
2399             .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 1,
2400             .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->clidr
2401         };
2402         define_one_arm_cp_reg(cpu, &clidr);
2403         define_arm_cp_regs(cpu, v7_cp_reginfo);
2404         define_debug_regs(cpu);
2405     } else {
2406         define_arm_cp_regs(cpu, not_v7_cp_reginfo);
2407     }
2408     if (arm_feature(env, ARM_FEATURE_V8)) {
2409         /* AArch64 ID registers, which all have impdef reset values */
2410         ARMCPRegInfo v8_idregs[] = {
2411             { .name = "ID_AA64PFR0_EL1", .state = ARM_CP_STATE_AA64,
2412               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 0,
2413               .access = PL1_R, .type = ARM_CP_CONST,
2414               .resetvalue = cpu->id_aa64pfr0 },
2415             { .name = "ID_AA64PFR1_EL1", .state = ARM_CP_STATE_AA64,
2416               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 1,
2417               .access = PL1_R, .type = ARM_CP_CONST,
2418               .resetvalue = cpu->id_aa64pfr1},
2419             { .name = "ID_AA64DFR0_EL1", .state = ARM_CP_STATE_AA64,
2420               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 0,
2421               .access = PL1_R, .type = ARM_CP_CONST,
2422               /* We mask out the PMUVer field, because we don't currently
2423                * implement the PMU. Not advertising it prevents the guest
2424                * from trying to use it and getting UNDEFs on registers we
2425                * don't implement.
2426                */
2427               .resetvalue = cpu->id_aa64dfr0 & ~0xf00 },
2428             { .name = "ID_AA64DFR1_EL1", .state = ARM_CP_STATE_AA64,
2429               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 1,
2430               .access = PL1_R, .type = ARM_CP_CONST,
2431               .resetvalue = cpu->id_aa64dfr1 },
2432             { .name = "ID_AA64AFR0_EL1", .state = ARM_CP_STATE_AA64,
2433               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 4,
2434               .access = PL1_R, .type = ARM_CP_CONST,
2435               .resetvalue = cpu->id_aa64afr0 },
2436             { .name = "ID_AA64AFR1_EL1", .state = ARM_CP_STATE_AA64,
2437               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 5,
2438               .access = PL1_R, .type = ARM_CP_CONST,
2439               .resetvalue = cpu->id_aa64afr1 },
2440             { .name = "ID_AA64ISAR0_EL1", .state = ARM_CP_STATE_AA64,
2441               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 0,
2442               .access = PL1_R, .type = ARM_CP_CONST,
2443               .resetvalue = cpu->id_aa64isar0 },
2444             { .name = "ID_AA64ISAR1_EL1", .state = ARM_CP_STATE_AA64,
2445               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 1,
2446               .access = PL1_R, .type = ARM_CP_CONST,
2447               .resetvalue = cpu->id_aa64isar1 },
2448             { .name = "ID_AA64MMFR0_EL1", .state = ARM_CP_STATE_AA64,
2449               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0,
2450               .access = PL1_R, .type = ARM_CP_CONST,
2451               .resetvalue = cpu->id_aa64mmfr0 },
2452             { .name = "ID_AA64MMFR1_EL1", .state = ARM_CP_STATE_AA64,
2453               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 1,
2454               .access = PL1_R, .type = ARM_CP_CONST,
2455               .resetvalue = cpu->id_aa64mmfr1 },
2456             { .name = "MVFR0_EL1", .state = ARM_CP_STATE_AA64,
2457               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 0,
2458               .access = PL1_R, .type = ARM_CP_CONST,
2459               .resetvalue = cpu->mvfr0 },
2460             { .name = "MVFR1_EL1", .state = ARM_CP_STATE_AA64,
2461               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 1,
2462               .access = PL1_R, .type = ARM_CP_CONST,
2463               .resetvalue = cpu->mvfr1 },
2464             { .name = "MVFR2_EL1", .state = ARM_CP_STATE_AA64,
2465               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 2,
2466               .access = PL1_R, .type = ARM_CP_CONST,
2467               .resetvalue = cpu->mvfr2 },
2468             REGINFO_SENTINEL
2469         };
2470         ARMCPRegInfo rvbar = {
2471             .name = "RVBAR_EL1", .state = ARM_CP_STATE_AA64,
2472             .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 2,
2473             .type = ARM_CP_CONST, .access = PL1_R, .resetvalue = cpu->rvbar
2474         };
2475         define_one_arm_cp_reg(cpu, &rvbar);
2476         define_arm_cp_regs(cpu, v8_idregs);
2477         define_arm_cp_regs(cpu, v8_cp_reginfo);
2478     }
2479     if (arm_feature(env, ARM_FEATURE_EL2)) {
2480         define_arm_cp_regs(cpu, v8_el2_cp_reginfo);
2481     } else {
2482         /* If EL2 is missing but higher ELs are enabled, we need to
2483          * register the no_el2 reginfos.
2484          */
2485         if (arm_feature(env, ARM_FEATURE_EL3)) {
2486             define_arm_cp_regs(cpu, v8_el3_no_el2_cp_reginfo);
2487         }
2488     }
2489     if (arm_feature(env, ARM_FEATURE_EL3)) {
2490         define_arm_cp_regs(cpu, v8_el3_cp_reginfo);
2491     }
2492     if (arm_feature(env, ARM_FEATURE_MPU)) {
2493         /* These are the MPU registers prior to PMSAv6. Any new
2494          * PMSA core later than the ARM946 will require that we
2495          * implement the PMSAv6 or PMSAv7 registers, which are
2496          * completely different.
2497          */
2498         assert(!arm_feature(env, ARM_FEATURE_V6));
2499         define_arm_cp_regs(cpu, pmsav5_cp_reginfo);
2500     } else {
2501         define_arm_cp_regs(cpu, vmsa_cp_reginfo);
2502     }
2503     if (arm_feature(env, ARM_FEATURE_THUMB2EE)) {
2504         define_arm_cp_regs(cpu, t2ee_cp_reginfo);
2505     }
2506     if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) {
2507         define_arm_cp_regs(cpu, generic_timer_cp_reginfo);
2508     }
2509     if (arm_feature(env, ARM_FEATURE_VAPA)) {
2510         define_arm_cp_regs(cpu, vapa_cp_reginfo);
2511     }
2512     if (arm_feature(env, ARM_FEATURE_CACHE_TEST_CLEAN)) {
2513         define_arm_cp_regs(cpu, cache_test_clean_cp_reginfo);
2514     }
2515     if (arm_feature(env, ARM_FEATURE_CACHE_DIRTY_REG)) {
2516         define_arm_cp_regs(cpu, cache_dirty_status_cp_reginfo);
2517     }
2518     if (arm_feature(env, ARM_FEATURE_CACHE_BLOCK_OPS)) {
2519         define_arm_cp_regs(cpu, cache_block_ops_cp_reginfo);
2520     }
2521     if (arm_feature(env, ARM_FEATURE_OMAPCP)) {
2522         define_arm_cp_regs(cpu, omap_cp_reginfo);
2523     }
2524     if (arm_feature(env, ARM_FEATURE_STRONGARM)) {
2525         define_arm_cp_regs(cpu, strongarm_cp_reginfo);
2526     }
2527     if (arm_feature(env, ARM_FEATURE_XSCALE)) {
2528         define_arm_cp_regs(cpu, xscale_cp_reginfo);
2529     }
2530     if (arm_feature(env, ARM_FEATURE_DUMMY_C15_REGS)) {
2531         define_arm_cp_regs(cpu, dummy_c15_cp_reginfo);
2532     }
2533     if (arm_feature(env, ARM_FEATURE_LPAE)) {
2534         define_arm_cp_regs(cpu, lpae_cp_reginfo);
2535     }
2536     /* Slightly awkwardly, the OMAP and StrongARM cores need all of
2537      * cp15 crn=0 to be writes-ignored, whereas for other cores they should
2538      * be read-only (ie write causes UNDEF exception).
2539      */
2540     {
2541         ARMCPRegInfo id_pre_v8_midr_cp_reginfo[] = {
2542             /* Pre-v8 MIDR space.
2543              * Note that the MIDR isn't a simple constant register because
2544              * of the TI925 behaviour where writes to another register can
2545              * cause the MIDR value to change.
2546              *
2547              * Unimplemented registers in the c15 0 0 0 space default to
2548              * MIDR. Define MIDR first as this entire space, then CTR, TCMTR
2549              * and friends override accordingly.
2550              */
2551             { .name = "MIDR",
2552               .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = CP_ANY,
2553               .access = PL1_R, .resetvalue = cpu->midr,
2554               .writefn = arm_cp_write_ignore, .raw_writefn = raw_write,
2555               .fieldoffset = offsetof(CPUARMState, cp15.c0_cpuid),
2556               .type = ARM_CP_OVERRIDE },
2557             /* crn = 0 op1 = 0 crm = 3..7 : currently unassigned; we RAZ. */
2558             { .name = "DUMMY",
2559               .cp = 15, .crn = 0, .crm = 3, .opc1 = 0, .opc2 = CP_ANY,
2560               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
2561             { .name = "DUMMY",
2562               .cp = 15, .crn = 0, .crm = 4, .opc1 = 0, .opc2 = CP_ANY,
2563               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
2564             { .name = "DUMMY",
2565               .cp = 15, .crn = 0, .crm = 5, .opc1 = 0, .opc2 = CP_ANY,
2566               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
2567             { .name = "DUMMY",
2568               .cp = 15, .crn = 0, .crm = 6, .opc1 = 0, .opc2 = CP_ANY,
2569               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
2570             { .name = "DUMMY",
2571               .cp = 15, .crn = 0, .crm = 7, .opc1 = 0, .opc2 = CP_ANY,
2572               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
2573             REGINFO_SENTINEL
2574         };
2575         ARMCPRegInfo id_v8_midr_cp_reginfo[] = {
2576             /* v8 MIDR -- the wildcard isn't necessary, and nor is the
2577              * variable-MIDR TI925 behaviour. Instead we have a single
2578              * (strictly speaking IMPDEF) alias of the MIDR, REVIDR.
2579              */
2580             { .name = "MIDR_EL1", .state = ARM_CP_STATE_BOTH,
2581               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 0,
2582               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->midr },
2583             { .name = "REVIDR_EL1", .state = ARM_CP_STATE_BOTH,
2584               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 6,
2585               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->midr },
2586             REGINFO_SENTINEL
2587         };
2588         ARMCPRegInfo id_cp_reginfo[] = {
2589             /* These are common to v8 and pre-v8 */
2590             { .name = "CTR",
2591               .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 1,
2592               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->ctr },
2593             { .name = "CTR_EL0", .state = ARM_CP_STATE_AA64,
2594               .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 0, .crm = 0,
2595               .access = PL0_R, .accessfn = ctr_el0_access,
2596               .type = ARM_CP_CONST, .resetvalue = cpu->ctr },
2597             /* TCMTR and TLBTR exist in v8 but have no 64-bit versions */
2598             { .name = "TCMTR",
2599               .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 2,
2600               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
2601             { .name = "TLBTR",
2602               .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 3,
2603               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
2604             REGINFO_SENTINEL
2605         };
2606         ARMCPRegInfo crn0_wi_reginfo = {
2607             .name = "CRN0_WI", .cp = 15, .crn = 0, .crm = CP_ANY,
2608             .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_W,
2609             .type = ARM_CP_NOP | ARM_CP_OVERRIDE
2610         };
2611         if (arm_feature(env, ARM_FEATURE_OMAPCP) ||
2612             arm_feature(env, ARM_FEATURE_STRONGARM)) {
2613             ARMCPRegInfo *r;
2614             /* Register the blanket "writes ignored" value first to cover the
2615              * whole space. Then update the specific ID registers to allow write
2616              * access, so that they ignore writes rather than causing them to
2617              * UNDEF.
2618              */
2619             define_one_arm_cp_reg(cpu, &crn0_wi_reginfo);
2620             for (r = id_pre_v8_midr_cp_reginfo;
2621                  r->type != ARM_CP_SENTINEL; r++) {
2622                 r->access = PL1_RW;
2623             }
2624             for (r = id_cp_reginfo; r->type != ARM_CP_SENTINEL; r++) {
2625                 r->access = PL1_RW;
2626             }
2627         }
2628         if (arm_feature(env, ARM_FEATURE_V8)) {
2629             define_arm_cp_regs(cpu, id_v8_midr_cp_reginfo);
2630         } else {
2631             define_arm_cp_regs(cpu, id_pre_v8_midr_cp_reginfo);
2632         }
2633         define_arm_cp_regs(cpu, id_cp_reginfo);
2634     }
2635
2636     if (arm_feature(env, ARM_FEATURE_MPIDR)) {
2637         define_arm_cp_regs(cpu, mpidr_cp_reginfo);
2638     }
2639
2640     if (arm_feature(env, ARM_FEATURE_AUXCR)) {
2641         ARMCPRegInfo auxcr = {
2642             .name = "ACTLR_EL1", .state = ARM_CP_STATE_BOTH,
2643             .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 1,
2644             .access = PL1_RW, .type = ARM_CP_CONST,
2645             .resetvalue = cpu->reset_auxcr
2646         };
2647         define_one_arm_cp_reg(cpu, &auxcr);
2648     }
2649
2650     if (arm_feature(env, ARM_FEATURE_CBAR)) {
2651         if (arm_feature(env, ARM_FEATURE_AARCH64)) {
2652             /* 32 bit view is [31:18] 0...0 [43:32]. */
2653             uint32_t cbar32 = (extract64(cpu->reset_cbar, 18, 14) << 18)
2654                 | extract64(cpu->reset_cbar, 32, 12);
2655             ARMCPRegInfo cbar_reginfo[] = {
2656                 { .name = "CBAR",
2657                   .type = ARM_CP_CONST,
2658                   .cp = 15, .crn = 15, .crm = 0, .opc1 = 4, .opc2 = 0,
2659                   .access = PL1_R, .resetvalue = cpu->reset_cbar },
2660                 { .name = "CBAR_EL1", .state = ARM_CP_STATE_AA64,
2661                   .type = ARM_CP_CONST,
2662                   .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 3, .opc2 = 0,
2663                   .access = PL1_R, .resetvalue = cbar32 },
2664                 REGINFO_SENTINEL
2665             };
2666             /* We don't implement a r/w 64 bit CBAR currently */
2667             assert(arm_feature(env, ARM_FEATURE_CBAR_RO));
2668             define_arm_cp_regs(cpu, cbar_reginfo);
2669         } else {
2670             ARMCPRegInfo cbar = {
2671                 .name = "CBAR",
2672                 .cp = 15, .crn = 15, .crm = 0, .opc1 = 4, .opc2 = 0,
2673                 .access = PL1_R|PL3_W, .resetvalue = cpu->reset_cbar,
2674                 .fieldoffset = offsetof(CPUARMState,
2675                                         cp15.c15_config_base_address)
2676             };
2677             if (arm_feature(env, ARM_FEATURE_CBAR_RO)) {
2678                 cbar.access = PL1_R;
2679                 cbar.fieldoffset = 0;
2680                 cbar.type = ARM_CP_CONST;
2681             }
2682             define_one_arm_cp_reg(cpu, &cbar);
2683         }
2684     }
2685
2686     /* Generic registers whose values depend on the implementation */
2687     {
2688         ARMCPRegInfo sctlr = {
2689             .name = "SCTLR", .state = ARM_CP_STATE_BOTH,
2690             .opc0 = 3, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0,
2691             .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_sys),
2692             .writefn = sctlr_write, .resetvalue = cpu->reset_sctlr,
2693             .raw_writefn = raw_write,
2694         };
2695         if (arm_feature(env, ARM_FEATURE_XSCALE)) {
2696             /* Normally we would always end the TB on an SCTLR write, but Linux
2697              * arch/arm/mach-pxa/sleep.S expects two instructions following
2698              * an MMU enable to execute from cache.  Imitate this behaviour.
2699              */
2700             sctlr.type |= ARM_CP_SUPPRESS_TB_END;
2701         }
2702         define_one_arm_cp_reg(cpu, &sctlr);
2703     }
2704 }
2705
2706 ARMCPU *cpu_arm_init(const char *cpu_model)
2707 {
2708     return ARM_CPU(cpu_generic_init(TYPE_ARM_CPU, cpu_model));
2709 }
2710
2711 void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
2712 {
2713     CPUState *cs = CPU(cpu);
2714     CPUARMState *env = &cpu->env;
2715
2716     if (arm_feature(env, ARM_FEATURE_AARCH64)) {
2717         gdb_register_coprocessor(cs, aarch64_fpu_gdb_get_reg,
2718                                  aarch64_fpu_gdb_set_reg,
2719                                  34, "aarch64-fpu.xml", 0);
2720     } else if (arm_feature(env, ARM_FEATURE_NEON)) {
2721         gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
2722                                  51, "arm-neon.xml", 0);
2723     } else if (arm_feature(env, ARM_FEATURE_VFP3)) {
2724         gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
2725                                  35, "arm-vfp3.xml", 0);
2726     } else if (arm_feature(env, ARM_FEATURE_VFP)) {
2727         gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
2728                                  19, "arm-vfp.xml", 0);
2729     }
2730 }
2731
2732 /* Sort alphabetically by type name, except for "any". */
2733 static gint arm_cpu_list_compare(gconstpointer a, gconstpointer b)
2734 {
2735     ObjectClass *class_a = (ObjectClass *)a;
2736     ObjectClass *class_b = (ObjectClass *)b;
2737     const char *name_a, *name_b;
2738
2739     name_a = object_class_get_name(class_a);
2740     name_b = object_class_get_name(class_b);
2741     if (strcmp(name_a, "any-" TYPE_ARM_CPU) == 0) {
2742         return 1;
2743     } else if (strcmp(name_b, "any-" TYPE_ARM_CPU) == 0) {
2744         return -1;
2745     } else {
2746         return strcmp(name_a, name_b);
2747     }
2748 }
2749
2750 static void arm_cpu_list_entry(gpointer data, gpointer user_data)
2751 {
2752     ObjectClass *oc = data;
2753     CPUListState *s = user_data;
2754     const char *typename;
2755     char *name;
2756
2757     typename = object_class_get_name(oc);
2758     name = g_strndup(typename, strlen(typename) - strlen("-" TYPE_ARM_CPU));
2759     (*s->cpu_fprintf)(s->file, "  %s\n",
2760                       name);
2761     g_free(name);
2762 }
2763
2764 void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf)
2765 {
2766     CPUListState s = {
2767         .file = f,
2768         .cpu_fprintf = cpu_fprintf,
2769     };
2770     GSList *list;
2771
2772     list = object_class_get_list(TYPE_ARM_CPU, false);
2773     list = g_slist_sort(list, arm_cpu_list_compare);
2774     (*cpu_fprintf)(f, "Available CPUs:\n");
2775     g_slist_foreach(list, arm_cpu_list_entry, &s);
2776     g_slist_free(list);
2777 #ifdef CONFIG_KVM
2778     /* The 'host' CPU type is dynamically registered only if KVM is
2779      * enabled, so we have to special-case it here:
2780      */
2781     (*cpu_fprintf)(f, "  host (only available in KVM mode)\n");
2782 #endif
2783 }
2784
2785 static void arm_cpu_add_definition(gpointer data, gpointer user_data)
2786 {
2787     ObjectClass *oc = data;
2788     CpuDefinitionInfoList **cpu_list = user_data;
2789     CpuDefinitionInfoList *entry;
2790     CpuDefinitionInfo *info;
2791     const char *typename;
2792
2793     typename = object_class_get_name(oc);
2794     info = g_malloc0(sizeof(*info));
2795     info->name = g_strndup(typename,
2796                            strlen(typename) - strlen("-" TYPE_ARM_CPU));
2797
2798     entry = g_malloc0(sizeof(*entry));
2799     entry->value = info;
2800     entry->next = *cpu_list;
2801     *cpu_list = entry;
2802 }
2803
2804 CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
2805 {
2806     CpuDefinitionInfoList *cpu_list = NULL;
2807     GSList *list;
2808
2809     list = object_class_get_list(TYPE_ARM_CPU, false);
2810     g_slist_foreach(list, arm_cpu_add_definition, &cpu_list);
2811     g_slist_free(list);
2812
2813     return cpu_list;
2814 }
2815
2816 static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
2817                                    void *opaque, int state,
2818                                    int crm, int opc1, int opc2)
2819 {
2820     /* Private utility function for define_one_arm_cp_reg_with_opaque():
2821      * add a single reginfo struct to the hash table.
2822      */
2823     uint32_t *key = g_new(uint32_t, 1);
2824     ARMCPRegInfo *r2 = g_memdup(r, sizeof(ARMCPRegInfo));
2825     int is64 = (r->type & ARM_CP_64BIT) ? 1 : 0;
2826     if (r->state == ARM_CP_STATE_BOTH && state == ARM_CP_STATE_AA32) {
2827         /* The AArch32 view of a shared register sees the lower 32 bits
2828          * of a 64 bit backing field. It is not migratable as the AArch64
2829          * view handles that. AArch64 also handles reset.
2830          * We assume it is a cp15 register if the .cp field is left unset.
2831          */
2832         if (r2->cp == 0) {
2833             r2->cp = 15;
2834         }
2835         r2->type |= ARM_CP_NO_MIGRATE;
2836         r2->resetfn = arm_cp_reset_ignore;
2837 #ifdef HOST_WORDS_BIGENDIAN
2838         if (r2->fieldoffset) {
2839             r2->fieldoffset += sizeof(uint32_t);
2840         }
2841 #endif
2842     }
2843     if (state == ARM_CP_STATE_AA64) {
2844         /* To allow abbreviation of ARMCPRegInfo
2845          * definitions, we treat cp == 0 as equivalent to
2846          * the value for "standard guest-visible sysreg".
2847          * STATE_BOTH definitions are also always "standard
2848          * sysreg" in their AArch64 view (the .cp value may
2849          * be non-zero for the benefit of the AArch32 view).
2850          */
2851         if (r->cp == 0 || r->state == ARM_CP_STATE_BOTH) {
2852             r2->cp = CP_REG_ARM64_SYSREG_CP;
2853         }
2854         *key = ENCODE_AA64_CP_REG(r2->cp, r2->crn, crm,
2855                                   r2->opc0, opc1, opc2);
2856     } else {
2857         *key = ENCODE_CP_REG(r2->cp, is64, r2->crn, crm, opc1, opc2);
2858     }
2859     if (opaque) {
2860         r2->opaque = opaque;
2861     }
2862     /* reginfo passed to helpers is correct for the actual access,
2863      * and is never ARM_CP_STATE_BOTH:
2864      */
2865     r2->state = state;
2866     /* Make sure reginfo passed to helpers for wildcarded regs
2867      * has the correct crm/opc1/opc2 for this reg, not CP_ANY:
2868      */
2869     r2->crm = crm;
2870     r2->opc1 = opc1;
2871     r2->opc2 = opc2;
2872     /* By convention, for wildcarded registers only the first
2873      * entry is used for migration; the others are marked as
2874      * NO_MIGRATE so we don't try to transfer the register
2875      * multiple times. Special registers (ie NOP/WFI) are
2876      * never migratable.
2877      */
2878     if ((r->type & ARM_CP_SPECIAL) ||
2879         ((r->crm == CP_ANY) && crm != 0) ||
2880         ((r->opc1 == CP_ANY) && opc1 != 0) ||
2881         ((r->opc2 == CP_ANY) && opc2 != 0)) {
2882         r2->type |= ARM_CP_NO_MIGRATE;
2883     }
2884
2885     /* Overriding of an existing definition must be explicitly
2886      * requested.
2887      */
2888     if (!(r->type & ARM_CP_OVERRIDE)) {
2889         ARMCPRegInfo *oldreg;
2890         oldreg = g_hash_table_lookup(cpu->cp_regs, key);
2891         if (oldreg && !(oldreg->type & ARM_CP_OVERRIDE)) {
2892             fprintf(stderr, "Register redefined: cp=%d %d bit "
2893                     "crn=%d crm=%d opc1=%d opc2=%d, "
2894                     "was %s, now %s\n", r2->cp, 32 + 32 * is64,
2895                     r2->crn, r2->crm, r2->opc1, r2->opc2,
2896                     oldreg->name, r2->name);
2897             g_assert_not_reached();
2898         }
2899     }
2900     g_hash_table_insert(cpu->cp_regs, key, r2);
2901 }
2902
2903
2904 void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
2905                                        const ARMCPRegInfo *r, void *opaque)
2906 {
2907     /* Define implementations of coprocessor registers.
2908      * We store these in a hashtable because typically
2909      * there are less than 150 registers in a space which
2910      * is 16*16*16*8*8 = 262144 in size.
2911      * Wildcarding is supported for the crm, opc1 and opc2 fields.
2912      * If a register is defined twice then the second definition is
2913      * used, so this can be used to define some generic registers and
2914      * then override them with implementation specific variations.
2915      * At least one of the original and the second definition should
2916      * include ARM_CP_OVERRIDE in its type bits -- this is just a guard
2917      * against accidental use.
2918      *
2919      * The state field defines whether the register is to be
2920      * visible in the AArch32 or AArch64 execution state. If the
2921      * state is set to ARM_CP_STATE_BOTH then we synthesise a
2922      * reginfo structure for the AArch32 view, which sees the lower
2923      * 32 bits of the 64 bit register.
2924      *
2925      * Only registers visible in AArch64 may set r->opc0; opc0 cannot
2926      * be wildcarded. AArch64 registers are always considered to be 64
2927      * bits; the ARM_CP_64BIT* flag applies only to the AArch32 view of
2928      * the register, if any.
2929      */
2930     int crm, opc1, opc2, state;
2931     int crmmin = (r->crm == CP_ANY) ? 0 : r->crm;
2932     int crmmax = (r->crm == CP_ANY) ? 15 : r->crm;
2933     int opc1min = (r->opc1 == CP_ANY) ? 0 : r->opc1;
2934     int opc1max = (r->opc1 == CP_ANY) ? 7 : r->opc1;
2935     int opc2min = (r->opc2 == CP_ANY) ? 0 : r->opc2;
2936     int opc2max = (r->opc2 == CP_ANY) ? 7 : r->opc2;
2937     /* 64 bit registers have only CRm and Opc1 fields */
2938     assert(!((r->type & ARM_CP_64BIT) && (r->opc2 || r->crn)));
2939     /* op0 only exists in the AArch64 encodings */
2940     assert((r->state != ARM_CP_STATE_AA32) || (r->opc0 == 0));
2941     /* AArch64 regs are all 64 bit so ARM_CP_64BIT is meaningless */
2942     assert((r->state != ARM_CP_STATE_AA64) || !(r->type & ARM_CP_64BIT));
2943     /* The AArch64 pseudocode CheckSystemAccess() specifies that op1
2944      * encodes a minimum access level for the register. We roll this
2945      * runtime check into our general permission check code, so check
2946      * here that the reginfo's specified permissions are strict enough
2947      * to encompass the generic architectural permission check.
2948      */
2949     if (r->state != ARM_CP_STATE_AA32) {
2950         int mask = 0;
2951         switch (r->opc1) {
2952         case 0: case 1: case 2:
2953             /* min_EL EL1 */
2954             mask = PL1_RW;
2955             break;
2956         case 3:
2957             /* min_EL EL0 */
2958             mask = PL0_RW;
2959             break;
2960         case 4:
2961             /* min_EL EL2 */
2962             mask = PL2_RW;
2963             break;
2964         case 5:
2965             /* unallocated encoding, so not possible */
2966             assert(false);
2967             break;
2968         case 6:
2969             /* min_EL EL3 */
2970             mask = PL3_RW;
2971             break;
2972         case 7:
2973             /* min_EL EL1, secure mode only (we don't check the latter) */
2974             mask = PL1_RW;
2975             break;
2976         default:
2977             /* broken reginfo with out-of-range opc1 */
2978             assert(false);
2979             break;
2980         }
2981         /* assert our permissions are not too lax (stricter is fine) */
2982         assert((r->access & ~mask) == 0);
2983     }
2984
2985     /* Check that the register definition has enough info to handle
2986      * reads and writes if they are permitted.
2987      */
2988     if (!(r->type & (ARM_CP_SPECIAL|ARM_CP_CONST))) {
2989         if (r->access & PL3_R) {
2990             assert(r->fieldoffset || r->readfn);
2991         }
2992         if (r->access & PL3_W) {
2993             assert(r->fieldoffset || r->writefn);
2994         }
2995     }
2996     /* Bad type field probably means missing sentinel at end of reg list */
2997     assert(cptype_valid(r->type));
2998     for (crm = crmmin; crm <= crmmax; crm++) {
2999         for (opc1 = opc1min; opc1 <= opc1max; opc1++) {
3000             for (opc2 = opc2min; opc2 <= opc2max; opc2++) {
3001                 for (state = ARM_CP_STATE_AA32;
3002                      state <= ARM_CP_STATE_AA64; state++) {
3003                     if (r->state != state && r->state != ARM_CP_STATE_BOTH) {
3004                         continue;
3005                     }
3006                     add_cpreg_to_hashtable(cpu, r, opaque, state,
3007                                            crm, opc1, opc2);
3008                 }
3009             }
3010         }
3011     }
3012 }
3013
3014 void define_arm_cp_regs_with_opaque(ARMCPU *cpu,
3015                                     const ARMCPRegInfo *regs, void *opaque)
3016 {
3017     /* Define a whole list of registers */
3018     const ARMCPRegInfo *r;
3019     for (r = regs; r->type != ARM_CP_SENTINEL; r++) {
3020         define_one_arm_cp_reg_with_opaque(cpu, r, opaque);
3021     }
3022 }
3023
3024 const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp)
3025 {
3026     return g_hash_table_lookup(cpregs, &encoded_cp);
3027 }
3028
3029 void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri,
3030                          uint64_t value)
3031 {
3032     /* Helper coprocessor write function for write-ignore registers */
3033 }
3034
3035 uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri)
3036 {
3037     /* Helper coprocessor write function for read-as-zero registers */
3038     return 0;
3039 }
3040
3041 void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque)
3042 {
3043     /* Helper coprocessor reset function for do-nothing-on-reset registers */
3044 }
3045
3046 static int bad_mode_switch(CPUARMState *env, int mode)
3047 {
3048     /* Return true if it is not valid for us to switch to
3049      * this CPU mode (ie all the UNPREDICTABLE cases in
3050      * the ARM ARM CPSRWriteByInstr pseudocode).
3051      */
3052     switch (mode) {
3053     case ARM_CPU_MODE_USR:
3054     case ARM_CPU_MODE_SYS:
3055     case ARM_CPU_MODE_SVC:
3056     case ARM_CPU_MODE_ABT:
3057     case ARM_CPU_MODE_UND:
3058     case ARM_CPU_MODE_IRQ:
3059     case ARM_CPU_MODE_FIQ:
3060         return 0;
3061     default:
3062         return 1;
3063     }
3064 }
3065
3066 uint32_t cpsr_read(CPUARMState *env)
3067 {
3068     int ZF;
3069     ZF = (env->ZF == 0);
3070     return env->uncached_cpsr | (env->NF & 0x80000000) | (ZF << 30) |
3071         (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27)
3072         | (env->thumb << 5) | ((env->condexec_bits & 3) << 25)
3073         | ((env->condexec_bits & 0xfc) << 8)
3074         | (env->GE << 16) | (env->daif & CPSR_AIF);
3075 }
3076
3077 void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
3078 {
3079     if (mask & CPSR_NZCV) {
3080         env->ZF = (~val) & CPSR_Z;
3081         env->NF = val;
3082         env->CF = (val >> 29) & 1;
3083         env->VF = (val << 3) & 0x80000000;
3084     }
3085     if (mask & CPSR_Q)
3086         env->QF = ((val & CPSR_Q) != 0);
3087     if (mask & CPSR_T)
3088         env->thumb = ((val & CPSR_T) != 0);
3089     if (mask & CPSR_IT_0_1) {
3090         env->condexec_bits &= ~3;
3091         env->condexec_bits |= (val >> 25) & 3;
3092     }
3093     if (mask & CPSR_IT_2_7) {
3094         env->condexec_bits &= 3;
3095         env->condexec_bits |= (val >> 8) & 0xfc;
3096     }
3097     if (mask & CPSR_GE) {
3098         env->GE = (val >> 16) & 0xf;
3099     }
3100
3101     env->daif &= ~(CPSR_AIF & mask);
3102     env->daif |= val & CPSR_AIF & mask;
3103
3104     if ((env->uncached_cpsr ^ val) & mask & CPSR_M) {
3105         if (bad_mode_switch(env, val & CPSR_M)) {
3106             /* Attempt to switch to an invalid mode: this is UNPREDICTABLE.
3107              * We choose to ignore the attempt and leave the CPSR M field
3108              * untouched.
3109              */
3110             mask &= ~CPSR_M;
3111         } else {
3112             switch_mode(env, val & CPSR_M);
3113         }
3114     }
3115     mask &= ~CACHED_CPSR_BITS;
3116     env->uncached_cpsr = (env->uncached_cpsr & ~mask) | (val & mask);
3117 }
3118
3119 /* Sign/zero extend */
3120 uint32_t HELPER(sxtb16)(uint32_t x)
3121 {
3122     uint32_t res;
3123     res = (uint16_t)(int8_t)x;
3124     res |= (uint32_t)(int8_t)(x >> 16) << 16;
3125     return res;
3126 }
3127
3128 uint32_t HELPER(uxtb16)(uint32_t x)
3129 {
3130     uint32_t res;
3131     res = (uint16_t)(uint8_t)x;
3132     res |= (uint32_t)(uint8_t)(x >> 16) << 16;
3133     return res;
3134 }
3135
3136 uint32_t HELPER(clz)(uint32_t x)
3137 {
3138     return clz32(x);
3139 }
3140
3141 int32_t HELPER(sdiv)(int32_t num, int32_t den)
3142 {
3143     if (den == 0)
3144       return 0;
3145     if (num == INT_MIN && den == -1)
3146       return INT_MIN;
3147     return num / den;
3148 }
3149
3150 uint32_t HELPER(udiv)(uint32_t num, uint32_t den)
3151 {
3152     if (den == 0)
3153       return 0;
3154     return num / den;
3155 }
3156
3157 uint32_t HELPER(rbit)(uint32_t x)
3158 {
3159     x =  ((x & 0xff000000) >> 24)
3160        | ((x & 0x00ff0000) >> 8)
3161        | ((x & 0x0000ff00) << 8)
3162        | ((x & 0x000000ff) << 24);
3163     x =  ((x & 0xf0f0f0f0) >> 4)
3164        | ((x & 0x0f0f0f0f) << 4);
3165     x =  ((x & 0x88888888) >> 3)
3166        | ((x & 0x44444444) >> 1)
3167        | ((x & 0x22222222) << 1)
3168        | ((x & 0x11111111) << 3);
3169     return x;
3170 }
3171
3172 #if defined(CONFIG_USER_ONLY)
3173
3174 void arm_cpu_do_interrupt(CPUState *cs)
3175 {
3176     cs->exception_index = -1;
3177 }
3178
3179 int arm_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
3180                              int mmu_idx)
3181 {
3182     ARMCPU *cpu = ARM_CPU(cs);
3183     CPUARMState *env = &cpu->env;
3184
3185     env->exception.vaddress = address;
3186     if (rw == 2) {
3187         cs->exception_index = EXCP_PREFETCH_ABORT;
3188     } else {
3189         cs->exception_index = EXCP_DATA_ABORT;
3190     }
3191     return 1;
3192 }
3193
3194 /* These should probably raise undefined insn exceptions.  */
3195 void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val)
3196 {
3197     ARMCPU *cpu = arm_env_get_cpu(env);
3198
3199     cpu_abort(CPU(cpu), "v7m_msr %d\n", reg);
3200 }
3201
3202 uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
3203 {
3204     ARMCPU *cpu = arm_env_get_cpu(env);
3205
3206     cpu_abort(CPU(cpu), "v7m_mrs %d\n", reg);
3207     return 0;
3208 }
3209
3210 void switch_mode(CPUARMState *env, int mode)
3211 {
3212     ARMCPU *cpu = arm_env_get_cpu(env);
3213
3214     if (mode != ARM_CPU_MODE_USR) {
3215         cpu_abort(CPU(cpu), "Tried to switch out of user mode\n");
3216     }
3217 }
3218
3219 void HELPER(set_r13_banked)(CPUARMState *env, uint32_t mode, uint32_t val)
3220 {
3221     ARMCPU *cpu = arm_env_get_cpu(env);
3222
3223     cpu_abort(CPU(cpu), "banked r13 write\n");
3224 }
3225
3226 uint32_t HELPER(get_r13_banked)(CPUARMState *env, uint32_t mode)
3227 {
3228     ARMCPU *cpu = arm_env_get_cpu(env);
3229
3230     cpu_abort(CPU(cpu), "banked r13 read\n");
3231     return 0;
3232 }
3233
3234 #else
3235
3236 /* Map CPU modes onto saved register banks.  */
3237 int bank_number(int mode)
3238 {
3239     switch (mode) {
3240     case ARM_CPU_MODE_USR:
3241     case ARM_CPU_MODE_SYS:
3242         return 0;
3243     case ARM_CPU_MODE_SVC:
3244         return 1;
3245     case ARM_CPU_MODE_ABT:
3246         return 2;
3247     case ARM_CPU_MODE_UND:
3248         return 3;
3249     case ARM_CPU_MODE_IRQ:
3250         return 4;
3251     case ARM_CPU_MODE_FIQ:
3252         return 5;
3253     case ARM_CPU_MODE_HYP:
3254         return 6;
3255     case ARM_CPU_MODE_MON:
3256         return 7;
3257     }
3258     hw_error("bank number requested for bad CPSR mode value 0x%x\n", mode);
3259 }
3260
3261 void switch_mode(CPUARMState *env, int mode)
3262 {
3263     int old_mode;
3264     int i;
3265
3266     old_mode = env->uncached_cpsr & CPSR_M;
3267     if (mode == old_mode)
3268         return;
3269
3270     if (old_mode == ARM_CPU_MODE_FIQ) {
3271         memcpy (env->fiq_regs, env->regs + 8, 5 * sizeof(uint32_t));
3272         memcpy (env->regs + 8, env->usr_regs, 5 * sizeof(uint32_t));
3273     } else if (mode == ARM_CPU_MODE_FIQ) {
3274         memcpy (env->usr_regs, env->regs + 8, 5 * sizeof(uint32_t));
3275         memcpy (env->regs + 8, env->fiq_regs, 5 * sizeof(uint32_t));
3276     }
3277
3278     i = bank_number(old_mode);
3279     env->banked_r13[i] = env->regs[13];
3280     env->banked_r14[i] = env->regs[14];
3281     env->banked_spsr[i] = env->spsr;
3282
3283     i = bank_number(mode);
3284     env->regs[13] = env->banked_r13[i];
3285     env->regs[14] = env->banked_r14[i];
3286     env->spsr = env->banked_spsr[i];
3287 }
3288
3289 static void v7m_push(CPUARMState *env, uint32_t val)
3290 {
3291     CPUState *cs = CPU(arm_env_get_cpu(env));
3292
3293     env->regs[13] -= 4;
3294     stl_phys(cs->as, env->regs[13], val);
3295 }
3296
3297 static uint32_t v7m_pop(CPUARMState *env)
3298 {
3299     CPUState *cs = CPU(arm_env_get_cpu(env));
3300     uint32_t val;
3301
3302     val = ldl_phys(cs->as, env->regs[13]);
3303     env->regs[13] += 4;
3304     return val;
3305 }
3306
3307 /* Switch to V7M main or process stack pointer.  */
3308 static void switch_v7m_sp(CPUARMState *env, int process)
3309 {
3310     uint32_t tmp;
3311     if (env->v7m.current_sp != process) {
3312         tmp = env->v7m.other_sp;
3313         env->v7m.other_sp = env->regs[13];
3314         env->regs[13] = tmp;
3315         env->v7m.current_sp = process;
3316     }
3317 }
3318
3319 static void do_v7m_exception_exit(CPUARMState *env)
3320 {
3321     uint32_t type;
3322     uint32_t xpsr;
3323
3324     type = env->regs[15];
3325     if (env->v7m.exception != 0)
3326         armv7m_nvic_complete_irq(env->nvic, env->v7m.exception);
3327
3328     /* Switch to the target stack.  */
3329     switch_v7m_sp(env, (type & 4) != 0);
3330     /* Pop registers.  */
3331     env->regs[0] = v7m_pop(env);
3332     env->regs[1] = v7m_pop(env);
3333     env->regs[2] = v7m_pop(env);
3334     env->regs[3] = v7m_pop(env);
3335     env->regs[12] = v7m_pop(env);
3336     env->regs[14] = v7m_pop(env);
3337     env->regs[15] = v7m_pop(env);
3338     xpsr = v7m_pop(env);
3339     xpsr_write(env, xpsr, 0xfffffdff);
3340     /* Undo stack alignment.  */
3341     if (xpsr & 0x200)
3342         env->regs[13] |= 4;
3343     /* ??? The exception return type specifies Thread/Handler mode.  However
3344        this is also implied by the xPSR value. Not sure what to do
3345        if there is a mismatch.  */
3346     /* ??? Likewise for mismatches between the CONTROL register and the stack
3347        pointer.  */
3348 }
3349
3350 void arm_v7m_cpu_do_interrupt(CPUState *cs)
3351 {
3352     ARMCPU *cpu = ARM_CPU(cs);
3353     CPUARMState *env = &cpu->env;
3354     uint32_t xpsr = xpsr_read(env);
3355     uint32_t lr;
3356     uint32_t addr;
3357
3358     arm_log_exception(cs->exception_index);
3359
3360     lr = 0xfffffff1;
3361     if (env->v7m.current_sp)
3362         lr |= 4;
3363     if (env->v7m.exception == 0)
3364         lr |= 8;
3365
3366     /* For exceptions we just mark as pending on the NVIC, and let that
3367        handle it.  */
3368     /* TODO: Need to escalate if the current priority is higher than the
3369        one we're raising.  */
3370     switch (cs->exception_index) {
3371     case EXCP_UDEF:
3372         armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE);
3373         return;
3374     case EXCP_SWI:
3375         /* The PC already points to the next instruction.  */
3376         armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SVC);
3377         return;
3378     case EXCP_PREFETCH_ABORT:
3379     case EXCP_DATA_ABORT:
3380         /* TODO: if we implemented the MPU registers, this is where we
3381          * should set the MMFAR, etc from exception.fsr and exception.vaddress.
3382          */
3383         armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM);
3384         return;
3385     case EXCP_BKPT:
3386         if (semihosting_enabled) {
3387             int nr;
3388             nr = arm_lduw_code(env, env->regs[15], env->bswap_code) & 0xff;
3389             if (nr == 0xab) {
3390                 env->regs[15] += 2;
3391                 env->regs[0] = do_arm_semihosting(env);
3392                 qemu_log_mask(CPU_LOG_INT, "...handled as semihosting call\n");
3393                 return;
3394             }
3395         }
3396         armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_DEBUG);
3397         return;
3398     case EXCP_IRQ:
3399         env->v7m.exception = armv7m_nvic_acknowledge_irq(env->nvic);
3400         break;
3401     case EXCP_EXCEPTION_EXIT:
3402         do_v7m_exception_exit(env);
3403         return;
3404     default:
3405         cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index);
3406         return; /* Never happens.  Keep compiler happy.  */
3407     }
3408
3409     /* Align stack pointer.  */
3410     /* ??? Should only do this if Configuration Control Register
3411        STACKALIGN bit is set.  */
3412     if (env->regs[13] & 4) {
3413         env->regs[13] -= 4;
3414         xpsr |= 0x200;
3415     }
3416     /* Switch to the handler mode.  */
3417     v7m_push(env, xpsr);
3418     v7m_push(env, env->regs[15]);
3419     v7m_push(env, env->regs[14]);
3420     v7m_push(env, env->regs[12]);
3421     v7m_push(env, env->regs[3]);
3422     v7m_push(env, env->regs[2]);
3423     v7m_push(env, env->regs[1]);
3424     v7m_push(env, env->regs[0]);
3425     switch_v7m_sp(env, 0);
3426     /* Clear IT bits */
3427     env->condexec_bits = 0;
3428     env->regs[14] = lr;
3429     addr = ldl_phys(cs->as, env->v7m.vecbase + env->v7m.exception * 4);
3430     env->regs[15] = addr & 0xfffffffe;
3431     env->thumb = addr & 1;
3432 }
3433
3434 /* Handle a CPU exception.  */
3435 void arm_cpu_do_interrupt(CPUState *cs)
3436 {
3437     ARMCPU *cpu = ARM_CPU(cs);
3438     CPUARMState *env = &cpu->env;
3439     uint32_t addr;
3440     uint32_t mask;
3441     int new_mode;
3442     uint32_t offset;
3443
3444     assert(!IS_M(env));
3445
3446     arm_log_exception(cs->exception_index);
3447
3448     /* TODO: Vectored interrupt controller.  */
3449     switch (cs->exception_index) {
3450     case EXCP_UDEF:
3451         new_mode = ARM_CPU_MODE_UND;
3452         addr = 0x04;
3453         mask = CPSR_I;
3454         if (env->thumb)
3455             offset = 2;
3456         else
3457             offset = 4;
3458         break;
3459     case EXCP_SWI:
3460         if (semihosting_enabled) {
3461             /* Check for semihosting interrupt.  */
3462             if (env->thumb) {
3463                 mask = arm_lduw_code(env, env->regs[15] - 2, env->bswap_code)
3464                     & 0xff;
3465             } else {
3466                 mask = arm_ldl_code(env, env->regs[15] - 4, env->bswap_code)
3467                     & 0xffffff;
3468             }
3469             /* Only intercept calls from privileged modes, to provide some
3470                semblance of security.  */
3471             if (((mask == 0x123456 && !env->thumb)
3472                     || (mask == 0xab && env->thumb))
3473                   && (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) {
3474                 env->regs[0] = do_arm_semihosting(env);
3475                 qemu_log_mask(CPU_LOG_INT, "...handled as semihosting call\n");
3476                 return;
3477             }
3478         }
3479         new_mode = ARM_CPU_MODE_SVC;
3480         addr = 0x08;
3481         mask = CPSR_I;
3482         /* The PC already points to the next instruction.  */
3483         offset = 0;
3484         break;
3485     case EXCP_BKPT:
3486         /* See if this is a semihosting syscall.  */
3487         if (env->thumb && semihosting_enabled) {
3488             mask = arm_lduw_code(env, env->regs[15], env->bswap_code) & 0xff;
3489             if (mask == 0xab
3490                   && (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) {
3491                 env->regs[15] += 2;
3492                 env->regs[0] = do_arm_semihosting(env);
3493                 qemu_log_mask(CPU_LOG_INT, "...handled as semihosting call\n");
3494                 return;
3495             }
3496         }
3497         env->exception.fsr = 2;
3498         /* Fall through to prefetch abort.  */
3499     case EXCP_PREFETCH_ABORT:
3500         env->cp15.ifsr_el2 = env->exception.fsr;
3501         env->cp15.far_el[1] = deposit64(env->cp15.far_el[1], 32, 32,
3502                                         env->exception.vaddress);
3503         qemu_log_mask(CPU_LOG_INT, "...with IFSR 0x%x IFAR 0x%x\n",
3504                       env->cp15.ifsr_el2, (uint32_t)env->exception.vaddress);
3505         new_mode = ARM_CPU_MODE_ABT;
3506         addr = 0x0c;
3507         mask = CPSR_A | CPSR_I;
3508         offset = 4;
3509         break;
3510     case EXCP_DATA_ABORT:
3511         env->cp15.esr_el[1] = env->exception.fsr;
3512         env->cp15.far_el[1] = deposit64(env->cp15.far_el[1], 0, 32,
3513                                         env->exception.vaddress);
3514         qemu_log_mask(CPU_LOG_INT, "...with DFSR 0x%x DFAR 0x%x\n",
3515                       (uint32_t)env->cp15.esr_el[1],
3516                       (uint32_t)env->exception.vaddress);
3517         new_mode = ARM_CPU_MODE_ABT;
3518         addr = 0x10;
3519         mask = CPSR_A | CPSR_I;
3520         offset = 8;
3521         break;
3522     case EXCP_IRQ:
3523         new_mode = ARM_CPU_MODE_IRQ;
3524         addr = 0x18;
3525         /* Disable IRQ and imprecise data aborts.  */
3526         mask = CPSR_A | CPSR_I;
3527         offset = 4;
3528         break;
3529     case EXCP_FIQ:
3530         new_mode = ARM_CPU_MODE_FIQ;
3531         addr = 0x1c;
3532         /* Disable FIQ, IRQ and imprecise data aborts.  */
3533         mask = CPSR_A | CPSR_I | CPSR_F;
3534         offset = 4;
3535         break;
3536     default:
3537         cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index);
3538         return; /* Never happens.  Keep compiler happy.  */
3539     }
3540     /* High vectors.  */
3541     if (env->cp15.c1_sys & SCTLR_V) {
3542         /* when enabled, base address cannot be remapped.  */
3543         addr += 0xffff0000;
3544     } else {
3545         /* ARM v7 architectures provide a vector base address register to remap
3546          * the interrupt vector table.
3547          * This register is only followed in non-monitor mode, and has a secure
3548          * and un-secure copy. Since the cpu is always in a un-secure operation
3549          * and is never in monitor mode this feature is always active.
3550          * Note: only bits 31:5 are valid.
3551          */
3552         addr += env->cp15.vbar_el[1];
3553     }
3554     switch_mode (env, new_mode);
3555     /* For exceptions taken to AArch32 we must clear the SS bit in both
3556      * PSTATE and in the old-state value we save to SPSR_<mode>, so zero it now.
3557      */
3558     env->uncached_cpsr &= ~PSTATE_SS;
3559     env->spsr = cpsr_read(env);
3560     /* Clear IT bits.  */
3561     env->condexec_bits = 0;
3562     /* Switch to the new mode, and to the correct instruction set.  */
3563     env->uncached_cpsr = (env->uncached_cpsr & ~CPSR_M) | new_mode;
3564     env->daif |= mask;
3565     /* this is a lie, as the was no c1_sys on V4T/V5, but who cares
3566      * and we should just guard the thumb mode on V4 */
3567     if (arm_feature(env, ARM_FEATURE_V4T)) {
3568         env->thumb = (env->cp15.c1_sys & SCTLR_TE) != 0;
3569     }
3570     env->regs[14] = env->regs[15] + offset;
3571     env->regs[15] = addr;
3572     cs->interrupt_request |= CPU_INTERRUPT_EXITTB;
3573 }
3574
3575 /* Check section/page access permissions.
3576    Returns the page protection flags, or zero if the access is not
3577    permitted.  */
3578 static inline int check_ap(CPUARMState *env, int ap, int domain_prot,
3579                            int access_type, int is_user)
3580 {
3581   int prot_ro;
3582
3583   if (domain_prot == 3) {
3584     return PAGE_READ | PAGE_WRITE;
3585   }
3586
3587   if (access_type == 1)
3588       prot_ro = 0;
3589   else
3590       prot_ro = PAGE_READ;
3591
3592   switch (ap) {
3593   case 0:
3594       if (arm_feature(env, ARM_FEATURE_V7)) {
3595           return 0;
3596       }
3597       if (access_type == 1)
3598           return 0;
3599       switch (env->cp15.c1_sys & (SCTLR_S | SCTLR_R)) {
3600       case SCTLR_S:
3601           return is_user ? 0 : PAGE_READ;
3602       case SCTLR_R:
3603           return PAGE_READ;
3604       default:
3605           return 0;
3606       }
3607   case 1:
3608       return is_user ? 0 : PAGE_READ | PAGE_WRITE;
3609   case 2:
3610       if (is_user)
3611           return prot_ro;
3612       else
3613           return PAGE_READ | PAGE_WRITE;
3614   case 3:
3615       return PAGE_READ | PAGE_WRITE;
3616   case 4: /* Reserved.  */
3617       return 0;
3618   case 5:
3619       return is_user ? 0 : prot_ro;
3620   case 6:
3621       return prot_ro;
3622   case 7:
3623       if (!arm_feature (env, ARM_FEATURE_V6K))
3624           return 0;
3625       return prot_ro;
3626   default:
3627       abort();
3628   }
3629 }
3630
3631 static bool get_level1_table_address(CPUARMState *env, uint32_t *table,
3632                                          uint32_t address)
3633 {
3634     if (address & env->cp15.c2_mask) {
3635         if ((env->cp15.c2_control & TTBCR_PD1)) {
3636             /* Translation table walk disabled for TTBR1 */
3637             return false;
3638         }
3639         *table = env->cp15.ttbr1_el1 & 0xffffc000;
3640     } else {
3641         if ((env->cp15.c2_control & TTBCR_PD0)) {
3642             /* Translation table walk disabled for TTBR0 */
3643             return false;
3644         }
3645         *table = env->cp15.ttbr0_el1 & env->cp15.c2_base_mask;
3646     }
3647     *table |= (address >> 18) & 0x3ffc;
3648     return true;
3649 }
3650
3651 static int get_phys_addr_v5(CPUARMState *env, uint32_t address, int access_type,
3652                             int is_user, hwaddr *phys_ptr,
3653                             int *prot, target_ulong *page_size)
3654 {
3655     CPUState *cs = CPU(arm_env_get_cpu(env));
3656     int code;
3657     uint32_t table;
3658     uint32_t desc;
3659     int type;
3660     int ap;
3661     int domain = 0;
3662     int domain_prot;
3663     hwaddr phys_addr;
3664
3665     /* Pagetable walk.  */
3666     /* Lookup l1 descriptor.  */
3667     if (!get_level1_table_address(env, &table, address)) {
3668         /* Section translation fault if page walk is disabled by PD0 or PD1 */
3669         code = 5;
3670         goto do_fault;
3671     }
3672     desc = ldl_phys(cs->as, table);
3673     type = (desc & 3);
3674     domain = (desc >> 5) & 0x0f;
3675     domain_prot = (env->cp15.c3 >> (domain * 2)) & 3;
3676     if (type == 0) {
3677         /* Section translation fault.  */
3678         code = 5;
3679         goto do_fault;
3680     }
3681     if (domain_prot == 0 || domain_prot == 2) {
3682         if (type == 2)
3683             code = 9; /* Section domain fault.  */
3684         else
3685             code = 11; /* Page domain fault.  */
3686         goto do_fault;
3687     }
3688     if (type == 2) {
3689         /* 1Mb section.  */
3690         phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
3691         ap = (desc >> 10) & 3;
3692         code = 13;
3693         *page_size = 1024 * 1024;
3694     } else {
3695         /* Lookup l2 entry.  */
3696         if (type == 1) {
3697             /* Coarse pagetable.  */
3698             table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
3699         } else {
3700             /* Fine pagetable.  */
3701             table = (desc & 0xfffff000) | ((address >> 8) & 0xffc);
3702         }
3703         desc = ldl_phys(cs->as, table);
3704         switch (desc & 3) {
3705         case 0: /* Page translation fault.  */
3706             code = 7;
3707             goto do_fault;
3708         case 1: /* 64k page.  */
3709             phys_addr = (desc & 0xffff0000) | (address & 0xffff);
3710             ap = (desc >> (4 + ((address >> 13) & 6))) & 3;
3711             *page_size = 0x10000;
3712             break;
3713         case 2: /* 4k page.  */
3714             phys_addr = (desc & 0xfffff000) | (address & 0xfff);
3715             ap = (desc >> (4 + ((address >> 9) & 6))) & 3;
3716             *page_size = 0x1000;
3717             break;
3718         case 3: /* 1k page.  */
3719             if (type == 1) {
3720                 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
3721                     phys_addr = (desc & 0xfffff000) | (address & 0xfff);
3722                 } else {
3723                     /* Page translation fault.  */
3724                     code = 7;
3725                     goto do_fault;
3726                 }
3727             } else {
3728                 phys_addr = (desc & 0xfffffc00) | (address & 0x3ff);
3729             }
3730             ap = (desc >> 4) & 3;
3731             *page_size = 0x400;
3732             break;
3733         default:
3734             /* Never happens, but compiler isn't smart enough to tell.  */
3735             abort();
3736         }
3737         code = 15;
3738     }
3739     *prot = check_ap(env, ap, domain_prot, access_type, is_user);
3740     if (!*prot) {
3741         /* Access permission fault.  */
3742         goto do_fault;
3743     }
3744     *prot |= PAGE_EXEC;
3745     *phys_ptr = phys_addr;
3746     return 0;
3747 do_fault:
3748     return code | (domain << 4);
3749 }
3750
3751 static int get_phys_addr_v6(CPUARMState *env, uint32_t address, int access_type,
3752                             int is_user, hwaddr *phys_ptr,
3753                             int *prot, target_ulong *page_size)
3754 {
3755     CPUState *cs = CPU(arm_env_get_cpu(env));
3756     int code;
3757     uint32_t table;
3758     uint32_t desc;
3759     uint32_t xn;
3760     uint32_t pxn = 0;
3761     int type;
3762     int ap;
3763     int domain = 0;
3764     int domain_prot;
3765     hwaddr phys_addr;
3766
3767     /* Pagetable walk.  */
3768     /* Lookup l1 descriptor.  */
3769     if (!get_level1_table_address(env, &table, address)) {
3770         /* Section translation fault if page walk is disabled by PD0 or PD1 */
3771         code = 5;
3772         goto do_fault;
3773     }
3774     desc = ldl_phys(cs->as, table);
3775     type = (desc & 3);
3776     if (type == 0 || (type == 3 && !arm_feature(env, ARM_FEATURE_PXN))) {
3777         /* Section translation fault, or attempt to use the encoding
3778          * which is Reserved on implementations without PXN.
3779          */
3780         code = 5;
3781         goto do_fault;
3782     }
3783     if ((type == 1) || !(desc & (1 << 18))) {
3784         /* Page or Section.  */
3785         domain = (desc >> 5) & 0x0f;
3786     }
3787     domain_prot = (env->cp15.c3 >> (domain * 2)) & 3;
3788     if (domain_prot == 0 || domain_prot == 2) {
3789         if (type != 1) {
3790             code = 9; /* Section domain fault.  */
3791         } else {
3792             code = 11; /* Page domain fault.  */
3793         }
3794         goto do_fault;
3795     }
3796     if (type != 1) {
3797         if (desc & (1 << 18)) {
3798             /* Supersection.  */
3799             phys_addr = (desc & 0xff000000) | (address & 0x00ffffff);
3800             *page_size = 0x1000000;
3801         } else {
3802             /* Section.  */
3803             phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
3804             *page_size = 0x100000;
3805         }
3806         ap = ((desc >> 10) & 3) | ((desc >> 13) & 4);
3807         xn = desc & (1 << 4);
3808         pxn = desc & 1;
3809         code = 13;
3810     } else {
3811         if (arm_feature(env, ARM_FEATURE_PXN)) {
3812             pxn = (desc >> 2) & 1;
3813         }
3814         /* Lookup l2 entry.  */
3815         table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
3816         desc = ldl_phys(cs->as, table);
3817         ap = ((desc >> 4) & 3) | ((desc >> 7) & 4);
3818         switch (desc & 3) {
3819         case 0: /* Page translation fault.  */
3820             code = 7;
3821             goto do_fault;
3822         case 1: /* 64k page.  */
3823             phys_addr = (desc & 0xffff0000) | (address & 0xffff);
3824             xn = desc & (1 << 15);
3825             *page_size = 0x10000;
3826             break;
3827         case 2: case 3: /* 4k page.  */
3828             phys_addr = (desc & 0xfffff000) | (address & 0xfff);
3829             xn = desc & 1;
3830             *page_size = 0x1000;
3831             break;
3832         default:
3833             /* Never happens, but compiler isn't smart enough to tell.  */
3834             abort();
3835         }
3836         code = 15;
3837     }
3838     if (domain_prot == 3) {
3839         *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
3840     } else {
3841         if (pxn && !is_user) {
3842             xn = 1;
3843         }
3844         if (xn && access_type == 2)
3845             goto do_fault;
3846
3847         /* The simplified model uses AP[0] as an access control bit.  */
3848         if ((env->cp15.c1_sys & SCTLR_AFE) && (ap & 1) == 0) {
3849             /* Access flag fault.  */
3850             code = (code == 15) ? 6 : 3;
3851             goto do_fault;
3852         }
3853         *prot = check_ap(env, ap, domain_prot, access_type, is_user);
3854         if (!*prot) {
3855             /* Access permission fault.  */
3856             goto do_fault;
3857         }
3858         if (!xn) {
3859             *prot |= PAGE_EXEC;
3860         }
3861     }
3862     *phys_ptr = phys_addr;
3863     return 0;
3864 do_fault:
3865     return code | (domain << 4);
3866 }
3867
3868 /* Fault type for long-descriptor MMU fault reporting; this corresponds
3869  * to bits [5..2] in the STATUS field in long-format DFSR/IFSR.
3870  */
3871 typedef enum {
3872     translation_fault = 1,
3873     access_fault = 2,
3874     permission_fault = 3,
3875 } MMUFaultType;
3876
3877 static int get_phys_addr_lpae(CPUARMState *env, target_ulong address,
3878                               int access_type, int is_user,
3879                               hwaddr *phys_ptr, int *prot,
3880                               target_ulong *page_size_ptr)
3881 {
3882     CPUState *cs = CPU(arm_env_get_cpu(env));
3883     /* Read an LPAE long-descriptor translation table. */
3884     MMUFaultType fault_type = translation_fault;
3885     uint32_t level = 1;
3886     uint32_t epd;
3887     int32_t tsz;
3888     uint32_t tg;
3889     uint64_t ttbr;
3890     int ttbr_select;
3891     hwaddr descaddr, descmask;
3892     uint32_t tableattrs;
3893     target_ulong page_size;
3894     uint32_t attrs;
3895     int32_t granule_sz = 9;
3896     int32_t va_size = 32;
3897     int32_t tbi = 0;
3898
3899     if (arm_el_is_aa64(env, 1)) {
3900         va_size = 64;
3901         if (extract64(address, 55, 1))
3902             tbi = extract64(env->cp15.c2_control, 38, 1);
3903         else
3904             tbi = extract64(env->cp15.c2_control, 37, 1);
3905         tbi *= 8;
3906     }
3907
3908     /* Determine whether this address is in the region controlled by
3909      * TTBR0 or TTBR1 (or if it is in neither region and should fault).
3910      * This is a Non-secure PL0/1 stage 1 translation, so controlled by
3911      * TTBCR/TTBR0/TTBR1 in accordance with ARM ARM DDI0406C table B-32:
3912      */
3913     uint32_t t0sz = extract32(env->cp15.c2_control, 0, 6);
3914     if (arm_el_is_aa64(env, 1)) {
3915         t0sz = MIN(t0sz, 39);
3916         t0sz = MAX(t0sz, 16);
3917     }
3918     uint32_t t1sz = extract32(env->cp15.c2_control, 16, 6);
3919     if (arm_el_is_aa64(env, 1)) {
3920         t1sz = MIN(t1sz, 39);
3921         t1sz = MAX(t1sz, 16);
3922     }
3923     if (t0sz && !extract64(address, va_size - t0sz, t0sz - tbi)) {
3924         /* there is a ttbr0 region and we are in it (high bits all zero) */
3925         ttbr_select = 0;
3926     } else if (t1sz && !extract64(~address, va_size - t1sz, t1sz - tbi)) {
3927         /* there is a ttbr1 region and we are in it (high bits all one) */
3928         ttbr_select = 1;
3929     } else if (!t0sz) {
3930         /* ttbr0 region is "everything not in the ttbr1 region" */
3931         ttbr_select = 0;
3932     } else if (!t1sz) {
3933         /* ttbr1 region is "everything not in the ttbr0 region" */
3934         ttbr_select = 1;
3935     } else {
3936         /* in the gap between the two regions, this is a Translation fault */
3937         fault_type = translation_fault;
3938         goto do_fault;
3939     }
3940
3941     /* Note that QEMU ignores shareability and cacheability attributes,
3942      * so we don't need to do anything with the SH, ORGN, IRGN fields
3943      * in the TTBCR.  Similarly, TTBCR:A1 selects whether we get the
3944      * ASID from TTBR0 or TTBR1, but QEMU's TLB doesn't currently
3945      * implement any ASID-like capability so we can ignore it (instead
3946      * we will always flush the TLB any time the ASID is changed).
3947      */
3948     if (ttbr_select == 0) {
3949         ttbr = env->cp15.ttbr0_el1;
3950         epd = extract32(env->cp15.c2_control, 7, 1);
3951         tsz = t0sz;
3952
3953         tg = extract32(env->cp15.c2_control, 14, 2);
3954         if (tg == 1) { /* 64KB pages */
3955             granule_sz = 13;
3956         }
3957         if (tg == 2) { /* 16KB pages */
3958             granule_sz = 11;
3959         }
3960     } else {
3961         ttbr = env->cp15.ttbr1_el1;
3962         epd = extract32(env->cp15.c2_control, 23, 1);
3963         tsz = t1sz;
3964
3965         tg = extract32(env->cp15.c2_control, 30, 2);
3966         if (tg == 3)  { /* 64KB pages */
3967             granule_sz = 13;
3968         }
3969         if (tg == 1) { /* 16KB pages */
3970             granule_sz = 11;
3971         }
3972     }
3973
3974     if (epd) {
3975         /* Translation table walk disabled => Translation fault on TLB miss */
3976         goto do_fault;
3977     }
3978
3979     /* The starting level depends on the virtual address size which can be
3980      * up to 48-bits and the translation granule size.
3981      */
3982     if ((va_size - tsz) > (granule_sz * 4 + 3)) {
3983         level = 0;
3984     } else if ((va_size - tsz) > (granule_sz * 3 + 3)) {
3985         level = 1;
3986     } else {
3987         level = 2;
3988     }
3989
3990     /* Clear the vaddr bits which aren't part of the within-region address,
3991      * so that we don't have to special case things when calculating the
3992      * first descriptor address.
3993      */
3994     if (tsz) {
3995         address &= (1ULL << (va_size - tsz)) - 1;
3996     }
3997
3998     descmask = (1ULL << (granule_sz + 3)) - 1;
3999
4000     /* Now we can extract the actual base address from the TTBR */
4001     descaddr = extract64(ttbr, 0, 48);
4002     descaddr &= ~((1ULL << (va_size - tsz - (granule_sz * (4 - level)))) - 1);
4003
4004     tableattrs = 0;
4005     for (;;) {
4006         uint64_t descriptor;
4007
4008         descaddr |= (address >> (granule_sz * (4 - level))) & descmask;
4009         descaddr &= ~7ULL;
4010         descriptor = ldq_phys(cs->as, descaddr);
4011         if (!(descriptor & 1) ||
4012             (!(descriptor & 2) && (level == 3))) {
4013             /* Invalid, or the Reserved level 3 encoding */
4014             goto do_fault;
4015         }
4016         descaddr = descriptor & 0xfffffff000ULL;
4017
4018         if ((descriptor & 2) && (level < 3)) {
4019             /* Table entry. The top five bits are attributes which  may
4020              * propagate down through lower levels of the table (and
4021              * which are all arranged so that 0 means "no effect", so
4022              * we can gather them up by ORing in the bits at each level).
4023              */
4024             tableattrs |= extract64(descriptor, 59, 5);
4025             level++;
4026             continue;
4027         }
4028         /* Block entry at level 1 or 2, or page entry at level 3.
4029          * These are basically the same thing, although the number
4030          * of bits we pull in from the vaddr varies.
4031          */
4032         page_size = (1ULL << ((granule_sz * (4 - level)) + 3));
4033         descaddr |= (address & (page_size - 1));
4034         /* Extract attributes from the descriptor and merge with table attrs */
4035         attrs = extract64(descriptor, 2, 10)
4036             | (extract64(descriptor, 52, 12) << 10);
4037         attrs |= extract32(tableattrs, 0, 2) << 11; /* XN, PXN */
4038         attrs |= extract32(tableattrs, 3, 1) << 5; /* APTable[1] => AP[2] */
4039         /* The sense of AP[1] vs APTable[0] is reversed, as APTable[0] == 1
4040          * means "force PL1 access only", which means forcing AP[1] to 0.
4041          */
4042         if (extract32(tableattrs, 2, 1)) {
4043             attrs &= ~(1 << 4);
4044         }
4045         /* Since we're always in the Non-secure state, NSTable is ignored. */
4046         break;
4047     }
4048     /* Here descaddr is the final physical address, and attributes
4049      * are all in attrs.
4050      */
4051     fault_type = access_fault;
4052     if ((attrs & (1 << 8)) == 0) {
4053         /* Access flag */
4054         goto do_fault;
4055     }
4056     fault_type = permission_fault;
4057     if (is_user && !(attrs & (1 << 4))) {
4058         /* Unprivileged access not enabled */
4059         goto do_fault;
4060     }
4061     *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
4062     if ((arm_feature(env, ARM_FEATURE_V8) && is_user && (attrs & (1 << 12))) ||
4063         (!arm_feature(env, ARM_FEATURE_V8) && (attrs & (1 << 12))) ||
4064         (!is_user && (attrs & (1 << 11)))) {
4065         /* XN/UXN or PXN. Since we only implement EL0/EL1 we unconditionally
4066          * treat XN/UXN as UXN for v8.
4067          */
4068         if (access_type == 2) {
4069             goto do_fault;
4070         }
4071         *prot &= ~PAGE_EXEC;
4072     }
4073     if (attrs & (1 << 5)) {
4074         /* Write access forbidden */
4075         if (access_type == 1) {
4076             goto do_fault;
4077         }
4078         *prot &= ~PAGE_WRITE;
4079     }
4080
4081     *phys_ptr = descaddr;
4082     *page_size_ptr = page_size;
4083     return 0;
4084
4085 do_fault:
4086     /* Long-descriptor format IFSR/DFSR value */
4087     return (1 << 9) | (fault_type << 2) | level;
4088 }
4089
4090 static int get_phys_addr_mpu(CPUARMState *env, uint32_t address,
4091                              int access_type, int is_user,
4092                              hwaddr *phys_ptr, int *prot)
4093 {
4094     int n;
4095     uint32_t mask;
4096     uint32_t base;
4097
4098     *phys_ptr = address;
4099     for (n = 7; n >= 0; n--) {
4100         base = env->cp15.c6_region[n];
4101         if ((base & 1) == 0)
4102             continue;
4103         mask = 1 << ((base >> 1) & 0x1f);
4104         /* Keep this shift separate from the above to avoid an
4105            (undefined) << 32.  */
4106         mask = (mask << 1) - 1;
4107         if (((base ^ address) & ~mask) == 0)
4108             break;
4109     }
4110     if (n < 0)
4111         return 2;
4112
4113     if (access_type == 2) {
4114         mask = env->cp15.pmsav5_insn_ap;
4115     } else {
4116         mask = env->cp15.pmsav5_data_ap;
4117     }
4118     mask = (mask >> (n * 4)) & 0xf;
4119     switch (mask) {
4120     case 0:
4121         return 1;
4122     case 1:
4123         if (is_user)
4124           return 1;
4125         *prot = PAGE_READ | PAGE_WRITE;
4126         break;
4127     case 2:
4128         *prot = PAGE_READ;
4129         if (!is_user)
4130             *prot |= PAGE_WRITE;
4131         break;
4132     case 3:
4133         *prot = PAGE_READ | PAGE_WRITE;
4134         break;
4135     case 5:
4136         if (is_user)
4137             return 1;
4138         *prot = PAGE_READ;
4139         break;
4140     case 6:
4141         *prot = PAGE_READ;
4142         break;
4143     default:
4144         /* Bad permission.  */
4145         return 1;
4146     }
4147     *prot |= PAGE_EXEC;
4148     return 0;
4149 }
4150
4151 /* get_phys_addr - get the physical address for this virtual address
4152  *
4153  * Find the physical address corresponding to the given virtual address,
4154  * by doing a translation table walk on MMU based systems or using the
4155  * MPU state on MPU based systems.
4156  *
4157  * Returns 0 if the translation was successful. Otherwise, phys_ptr,
4158  * prot and page_size are not filled in, and the return value provides
4159  * information on why the translation aborted, in the format of a
4160  * DFSR/IFSR fault register, with the following caveats:
4161  *  * we honour the short vs long DFSR format differences.
4162  *  * the WnR bit is never set (the caller must do this).
4163  *  * for MPU based systems we don't bother to return a full FSR format
4164  *    value.
4165  *
4166  * @env: CPUARMState
4167  * @address: virtual address to get physical address for
4168  * @access_type: 0 for read, 1 for write, 2 for execute
4169  * @is_user: 0 for privileged access, 1 for user
4170  * @phys_ptr: set to the physical address corresponding to the virtual address
4171  * @prot: set to the permissions for the page containing phys_ptr
4172  * @page_size: set to the size of the page containing phys_ptr
4173  */
4174 static inline int get_phys_addr(CPUARMState *env, target_ulong address,
4175                                 int access_type, int is_user,
4176                                 hwaddr *phys_ptr, int *prot,
4177                                 target_ulong *page_size)
4178 {
4179     /* Fast Context Switch Extension.  */
4180     if (address < 0x02000000)
4181         address += env->cp15.c13_fcse;
4182
4183     if ((env->cp15.c1_sys & SCTLR_M) == 0) {
4184         /* MMU/MPU disabled.  */
4185         *phys_ptr = address;
4186         *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
4187         *page_size = TARGET_PAGE_SIZE;
4188         return 0;
4189     } else if (arm_feature(env, ARM_FEATURE_MPU)) {
4190         *page_size = TARGET_PAGE_SIZE;
4191         return get_phys_addr_mpu(env, address, access_type, is_user, phys_ptr,
4192                                  prot);
4193     } else if (extended_addresses_enabled(env)) {
4194         return get_phys_addr_lpae(env, address, access_type, is_user, phys_ptr,
4195                                   prot, page_size);
4196     } else if (env->cp15.c1_sys & SCTLR_XP) {
4197         return get_phys_addr_v6(env, address, access_type, is_user, phys_ptr,
4198                                 prot, page_size);
4199     } else {
4200         return get_phys_addr_v5(env, address, access_type, is_user, phys_ptr,
4201                                 prot, page_size);
4202     }
4203 }
4204
4205 int arm_cpu_handle_mmu_fault(CPUState *cs, vaddr address,
4206                              int access_type, int mmu_idx)
4207 {
4208     ARMCPU *cpu = ARM_CPU(cs);
4209     CPUARMState *env = &cpu->env;
4210     hwaddr phys_addr;
4211     target_ulong page_size;
4212     int prot;
4213     int ret, is_user;
4214     uint32_t syn;
4215     bool same_el = (arm_current_pl(env) != 0);
4216
4217     is_user = mmu_idx == MMU_USER_IDX;
4218     ret = get_phys_addr(env, address, access_type, is_user, &phys_addr, &prot,
4219                         &page_size);
4220     if (ret == 0) {
4221         /* Map a single [sub]page.  */
4222         phys_addr &= TARGET_PAGE_MASK;
4223         address &= TARGET_PAGE_MASK;
4224         tlb_set_page(cs, address, phys_addr, prot, mmu_idx, page_size);
4225         return 0;
4226     }
4227
4228     /* AArch64 syndrome does not have an LPAE bit */
4229     syn = ret & ~(1 << 9);
4230
4231     /* For insn and data aborts we assume there is no instruction syndrome
4232      * information; this is always true for exceptions reported to EL1.
4233      */
4234     if (access_type == 2) {
4235         syn = syn_insn_abort(same_el, 0, 0, syn);
4236         cs->exception_index = EXCP_PREFETCH_ABORT;
4237     } else {
4238         syn = syn_data_abort(same_el, 0, 0, 0, access_type == 1, syn);
4239         if (access_type == 1 && arm_feature(env, ARM_FEATURE_V6)) {
4240             ret |= (1 << 11);
4241         }
4242         cs->exception_index = EXCP_DATA_ABORT;
4243     }
4244
4245     env->exception.syndrome = syn;
4246     env->exception.vaddress = address;
4247     env->exception.fsr = ret;
4248     return 1;
4249 }
4250
4251 hwaddr arm_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
4252 {
4253     ARMCPU *cpu = ARM_CPU(cs);
4254     hwaddr phys_addr;
4255     target_ulong page_size;
4256     int prot;
4257     int ret;
4258
4259     ret = get_phys_addr(&cpu->env, addr, 0, 0, &phys_addr, &prot, &page_size);
4260
4261     if (ret != 0) {
4262         return -1;
4263     }
4264
4265     return phys_addr;
4266 }
4267
4268 void HELPER(set_r13_banked)(CPUARMState *env, uint32_t mode, uint32_t val)
4269 {
4270     if ((env->uncached_cpsr & CPSR_M) == mode) {
4271         env->regs[13] = val;
4272     } else {
4273         env->banked_r13[bank_number(mode)] = val;
4274     }
4275 }
4276
4277 uint32_t HELPER(get_r13_banked)(CPUARMState *env, uint32_t mode)
4278 {
4279     if ((env->uncached_cpsr & CPSR_M) == mode) {
4280         return env->regs[13];
4281     } else {
4282         return env->banked_r13[bank_number(mode)];
4283     }
4284 }
4285
4286 uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
4287 {
4288     ARMCPU *cpu = arm_env_get_cpu(env);
4289
4290     switch (reg) {
4291     case 0: /* APSR */
4292         return xpsr_read(env) & 0xf8000000;
4293     case 1: /* IAPSR */
4294         return xpsr_read(env) & 0xf80001ff;
4295     case 2: /* EAPSR */
4296         return xpsr_read(env) & 0xff00fc00;
4297     case 3: /* xPSR */
4298         return xpsr_read(env) & 0xff00fdff;
4299     case 5: /* IPSR */
4300         return xpsr_read(env) & 0x000001ff;
4301     case 6: /* EPSR */
4302         return xpsr_read(env) & 0x0700fc00;
4303     case 7: /* IEPSR */
4304         return xpsr_read(env) & 0x0700edff;
4305     case 8: /* MSP */
4306         return env->v7m.current_sp ? env->v7m.other_sp : env->regs[13];
4307     case 9: /* PSP */
4308         return env->v7m.current_sp ? env->regs[13] : env->v7m.other_sp;
4309     case 16: /* PRIMASK */
4310         return (env->daif & PSTATE_I) != 0;
4311     case 17: /* BASEPRI */
4312     case 18: /* BASEPRI_MAX */
4313         return env->v7m.basepri;
4314     case 19: /* FAULTMASK */
4315         return (env->daif & PSTATE_F) != 0;
4316     case 20: /* CONTROL */
4317         return env->v7m.control;
4318     default:
4319         /* ??? For debugging only.  */
4320         cpu_abort(CPU(cpu), "Unimplemented system register read (%d)\n", reg);
4321         return 0;
4322     }
4323 }
4324
4325 void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val)
4326 {
4327     ARMCPU *cpu = arm_env_get_cpu(env);
4328
4329     switch (reg) {
4330     case 0: /* APSR */
4331         xpsr_write(env, val, 0xf8000000);
4332         break;
4333     case 1: /* IAPSR */
4334         xpsr_write(env, val, 0xf8000000);
4335         break;
4336     case 2: /* EAPSR */
4337         xpsr_write(env, val, 0xfe00fc00);
4338         break;
4339     case 3: /* xPSR */
4340         xpsr_write(env, val, 0xfe00fc00);
4341         break;
4342     case 5: /* IPSR */
4343         /* IPSR bits are readonly.  */
4344         break;
4345     case 6: /* EPSR */
4346         xpsr_write(env, val, 0x0600fc00);
4347         break;
4348     case 7: /* IEPSR */
4349         xpsr_write(env, val, 0x0600fc00);
4350         break;
4351     case 8: /* MSP */
4352         if (env->v7m.current_sp)
4353             env->v7m.other_sp = val;
4354         else
4355             env->regs[13] = val;
4356         break;
4357     case 9: /* PSP */
4358         if (env->v7m.current_sp)
4359             env->regs[13] = val;
4360         else
4361             env->v7m.other_sp = val;
4362         break;
4363     case 16: /* PRIMASK */
4364         if (val & 1) {
4365             env->daif |= PSTATE_I;
4366         } else {
4367             env->daif &= ~PSTATE_I;
4368         }
4369         break;
4370     case 17: /* BASEPRI */
4371         env->v7m.basepri = val & 0xff;
4372         break;
4373     case 18: /* BASEPRI_MAX */
4374         val &= 0xff;
4375         if (val != 0 && (val < env->v7m.basepri || env->v7m.basepri == 0))
4376             env->v7m.basepri = val;
4377         break;
4378     case 19: /* FAULTMASK */
4379         if (val & 1) {
4380             env->daif |= PSTATE_F;
4381         } else {
4382             env->daif &= ~PSTATE_F;
4383         }
4384         break;
4385     case 20: /* CONTROL */
4386         env->v7m.control = val & 3;
4387         switch_v7m_sp(env, (val & 2) != 0);
4388         break;
4389     default:
4390         /* ??? For debugging only.  */
4391         cpu_abort(CPU(cpu), "Unimplemented system register write (%d)\n", reg);
4392         return;
4393     }
4394 }
4395
4396 #endif
4397
4398 void HELPER(dc_zva)(CPUARMState *env, uint64_t vaddr_in)
4399 {
4400     /* Implement DC ZVA, which zeroes a fixed-length block of memory.
4401      * Note that we do not implement the (architecturally mandated)
4402      * alignment fault for attempts to use this on Device memory
4403      * (which matches the usual QEMU behaviour of not implementing either
4404      * alignment faults or any memory attribute handling).
4405      */
4406
4407     ARMCPU *cpu = arm_env_get_cpu(env);
4408     uint64_t blocklen = 4 << cpu->dcz_blocksize;
4409     uint64_t vaddr = vaddr_in & ~(blocklen - 1);
4410
4411 #ifndef CONFIG_USER_ONLY
4412     {
4413         /* Slightly awkwardly, QEMU's TARGET_PAGE_SIZE may be less than
4414          * the block size so we might have to do more than one TLB lookup.
4415          * We know that in fact for any v8 CPU the page size is at least 4K
4416          * and the block size must be 2K or less, but TARGET_PAGE_SIZE is only
4417          * 1K as an artefact of legacy v5 subpage support being present in the
4418          * same QEMU executable.
4419          */
4420         int maxidx = DIV_ROUND_UP(blocklen, TARGET_PAGE_SIZE);
4421         void *hostaddr[maxidx];
4422         int try, i;
4423
4424         for (try = 0; try < 2; try++) {
4425
4426             for (i = 0; i < maxidx; i++) {
4427                 hostaddr[i] = tlb_vaddr_to_host(env,
4428                                                 vaddr + TARGET_PAGE_SIZE * i,
4429                                                 1, cpu_mmu_index(env));
4430                 if (!hostaddr[i]) {
4431                     break;
4432                 }
4433             }
4434             if (i == maxidx) {
4435                 /* If it's all in the TLB it's fair game for just writing to;
4436                  * we know we don't need to update dirty status, etc.
4437                  */
4438                 for (i = 0; i < maxidx - 1; i++) {
4439                     memset(hostaddr[i], 0, TARGET_PAGE_SIZE);
4440                 }
4441                 memset(hostaddr[i], 0, blocklen - (i * TARGET_PAGE_SIZE));
4442                 return;
4443             }
4444             /* OK, try a store and see if we can populate the tlb. This
4445              * might cause an exception if the memory isn't writable,
4446              * in which case we will longjmp out of here. We must for
4447              * this purpose use the actual register value passed to us
4448              * so that we get the fault address right.
4449              */
4450             helper_ret_stb_mmu(env, vaddr_in, 0, cpu_mmu_index(env), GETRA());
4451             /* Now we can populate the other TLB entries, if any */
4452             for (i = 0; i < maxidx; i++) {
4453                 uint64_t va = vaddr + TARGET_PAGE_SIZE * i;
4454                 if (va != (vaddr_in & TARGET_PAGE_MASK)) {
4455                     helper_ret_stb_mmu(env, va, 0, cpu_mmu_index(env), GETRA());
4456                 }
4457             }
4458         }
4459
4460         /* Slow path (probably attempt to do this to an I/O device or
4461          * similar, or clearing of a block of code we have translations
4462          * cached for). Just do a series of byte writes as the architecture
4463          * demands. It's not worth trying to use a cpu_physical_memory_map(),
4464          * memset(), unmap() sequence here because:
4465          *  + we'd need to account for the blocksize being larger than a page
4466          *  + the direct-RAM access case is almost always going to be dealt
4467          *    with in the fastpath code above, so there's no speed benefit
4468          *  + we would have to deal with the map returning NULL because the
4469          *    bounce buffer was in use
4470          */
4471         for (i = 0; i < blocklen; i++) {
4472             helper_ret_stb_mmu(env, vaddr + i, 0, cpu_mmu_index(env), GETRA());
4473         }
4474     }
4475 #else
4476     memset(g2h(vaddr), 0, blocklen);
4477 #endif
4478 }
4479
4480 /* Note that signed overflow is undefined in C.  The following routines are
4481    careful to use unsigned types where modulo arithmetic is required.
4482    Failure to do so _will_ break on newer gcc.  */
4483
4484 /* Signed saturating arithmetic.  */
4485
4486 /* Perform 16-bit signed saturating addition.  */
4487 static inline uint16_t add16_sat(uint16_t a, uint16_t b)
4488 {
4489     uint16_t res;
4490
4491     res = a + b;
4492     if (((res ^ a) & 0x8000) && !((a ^ b) & 0x8000)) {
4493         if (a & 0x8000)
4494             res = 0x8000;
4495         else
4496             res = 0x7fff;
4497     }
4498     return res;
4499 }
4500
4501 /* Perform 8-bit signed saturating addition.  */
4502 static inline uint8_t add8_sat(uint8_t a, uint8_t b)
4503 {
4504     uint8_t res;
4505
4506     res = a + b;
4507     if (((res ^ a) & 0x80) && !((a ^ b) & 0x80)) {
4508         if (a & 0x80)
4509             res = 0x80;
4510         else
4511             res = 0x7f;
4512     }
4513     return res;
4514 }
4515
4516 /* Perform 16-bit signed saturating subtraction.  */
4517 static inline uint16_t sub16_sat(uint16_t a, uint16_t b)
4518 {
4519     uint16_t res;
4520
4521     res = a - b;
4522     if (((res ^ a) & 0x8000) && ((a ^ b) & 0x8000)) {
4523         if (a & 0x8000)
4524             res = 0x8000;
4525         else
4526             res = 0x7fff;
4527     }
4528     return res;
4529 }
4530
4531 /* Perform 8-bit signed saturating subtraction.  */
4532 static inline uint8_t sub8_sat(uint8_t a, uint8_t b)
4533 {
4534     uint8_t res;
4535
4536     res = a - b;
4537     if (((res ^ a) & 0x80) && ((a ^ b) & 0x80)) {
4538         if (a & 0x80)
4539             res = 0x80;
4540         else
4541             res = 0x7f;
4542     }
4543     return res;
4544 }
4545
4546 #define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16);
4547 #define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16);
4548 #define ADD8(a, b, n)  RESULT(add8_sat(a, b), n, 8);
4549 #define SUB8(a, b, n)  RESULT(sub8_sat(a, b), n, 8);
4550 #define PFX q
4551
4552 #include "op_addsub.h"
4553
4554 /* Unsigned saturating arithmetic.  */
4555 static inline uint16_t add16_usat(uint16_t a, uint16_t b)
4556 {
4557     uint16_t res;
4558     res = a + b;
4559     if (res < a)
4560         res = 0xffff;
4561     return res;
4562 }
4563
4564 static inline uint16_t sub16_usat(uint16_t a, uint16_t b)
4565 {
4566     if (a > b)
4567         return a - b;
4568     else
4569         return 0;
4570 }
4571
4572 static inline uint8_t add8_usat(uint8_t a, uint8_t b)
4573 {
4574     uint8_t res;
4575     res = a + b;
4576     if (res < a)
4577         res = 0xff;
4578     return res;
4579 }
4580
4581 static inline uint8_t sub8_usat(uint8_t a, uint8_t b)
4582 {
4583     if (a > b)
4584         return a - b;
4585     else
4586         return 0;
4587 }
4588
4589 #define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16);
4590 #define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16);
4591 #define ADD8(a, b, n)  RESULT(add8_usat(a, b), n, 8);
4592 #define SUB8(a, b, n)  RESULT(sub8_usat(a, b), n, 8);
4593 #define PFX uq
4594
4595 #include "op_addsub.h"
4596
4597 /* Signed modulo arithmetic.  */
4598 #define SARITH16(a, b, n, op) do { \
4599     int32_t sum; \
4600     sum = (int32_t)(int16_t)(a) op (int32_t)(int16_t)(b); \
4601     RESULT(sum, n, 16); \
4602     if (sum >= 0) \
4603         ge |= 3 << (n * 2); \
4604     } while(0)
4605
4606 #define SARITH8(a, b, n, op) do { \
4607     int32_t sum; \
4608     sum = (int32_t)(int8_t)(a) op (int32_t)(int8_t)(b); \
4609     RESULT(sum, n, 8); \
4610     if (sum >= 0) \
4611         ge |= 1 << n; \
4612     } while(0)
4613
4614
4615 #define ADD16(a, b, n) SARITH16(a, b, n, +)
4616 #define SUB16(a, b, n) SARITH16(a, b, n, -)
4617 #define ADD8(a, b, n)  SARITH8(a, b, n, +)
4618 #define SUB8(a, b, n)  SARITH8(a, b, n, -)
4619 #define PFX s
4620 #define ARITH_GE
4621
4622 #include "op_addsub.h"
4623
4624 /* Unsigned modulo arithmetic.  */
4625 #define ADD16(a, b, n) do { \
4626     uint32_t sum; \
4627     sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \
4628     RESULT(sum, n, 16); \
4629     if ((sum >> 16) == 1) \
4630         ge |= 3 << (n * 2); \
4631     } while(0)
4632
4633 #define ADD8(a, b, n) do { \
4634     uint32_t sum; \
4635     sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \
4636     RESULT(sum, n, 8); \
4637     if ((sum >> 8) == 1) \
4638         ge |= 1 << n; \
4639     } while(0)
4640
4641 #define SUB16(a, b, n) do { \
4642     uint32_t sum; \
4643     sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \
4644     RESULT(sum, n, 16); \
4645     if ((sum >> 16) == 0) \
4646         ge |= 3 << (n * 2); \
4647     } while(0)
4648
4649 #define SUB8(a, b, n) do { \
4650     uint32_t sum; \
4651     sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \
4652     RESULT(sum, n, 8); \
4653     if ((sum >> 8) == 0) \
4654         ge |= 1 << n; \
4655     } while(0)
4656
4657 #define PFX u
4658 #define ARITH_GE
4659
4660 #include "op_addsub.h"
4661
4662 /* Halved signed arithmetic.  */
4663 #define ADD16(a, b, n) \
4664   RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16)
4665 #define SUB16(a, b, n) \
4666   RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16)
4667 #define ADD8(a, b, n) \
4668   RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8)
4669 #define SUB8(a, b, n) \
4670   RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8)
4671 #define PFX sh
4672
4673 #include "op_addsub.h"
4674
4675 /* Halved unsigned arithmetic.  */
4676 #define ADD16(a, b, n) \
4677   RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16)
4678 #define SUB16(a, b, n) \
4679   RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16)
4680 #define ADD8(a, b, n) \
4681   RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8)
4682 #define SUB8(a, b, n) \
4683   RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8)
4684 #define PFX uh
4685
4686 #include "op_addsub.h"
4687
4688 static inline uint8_t do_usad(uint8_t a, uint8_t b)
4689 {
4690     if (a > b)
4691         return a - b;
4692     else
4693         return b - a;
4694 }
4695
4696 /* Unsigned sum of absolute byte differences.  */
4697 uint32_t HELPER(usad8)(uint32_t a, uint32_t b)
4698 {
4699     uint32_t sum;
4700     sum = do_usad(a, b);
4701     sum += do_usad(a >> 8, b >> 8);
4702     sum += do_usad(a >> 16, b >>16);
4703     sum += do_usad(a >> 24, b >> 24);
4704     return sum;
4705 }
4706
4707 /* For ARMv6 SEL instruction.  */
4708 uint32_t HELPER(sel_flags)(uint32_t flags, uint32_t a, uint32_t b)
4709 {
4710     uint32_t mask;
4711
4712     mask = 0;
4713     if (flags & 1)
4714         mask |= 0xff;
4715     if (flags & 2)
4716         mask |= 0xff00;
4717     if (flags & 4)
4718         mask |= 0xff0000;
4719     if (flags & 8)
4720         mask |= 0xff000000;
4721     return (a & mask) | (b & ~mask);
4722 }
4723
4724 /* VFP support.  We follow the convention used for VFP instructions:
4725    Single precision routines have a "s" suffix, double precision a
4726    "d" suffix.  */
4727
4728 /* Convert host exception flags to vfp form.  */
4729 static inline int vfp_exceptbits_from_host(int host_bits)
4730 {
4731     int target_bits = 0;
4732
4733     if (host_bits & float_flag_invalid)
4734         target_bits |= 1;
4735     if (host_bits & float_flag_divbyzero)
4736         target_bits |= 2;
4737     if (host_bits & float_flag_overflow)
4738         target_bits |= 4;
4739     if (host_bits & (float_flag_underflow | float_flag_output_denormal))
4740         target_bits |= 8;
4741     if (host_bits & float_flag_inexact)
4742         target_bits |= 0x10;
4743     if (host_bits & float_flag_input_denormal)
4744         target_bits |= 0x80;
4745     return target_bits;
4746 }
4747
4748 uint32_t HELPER(vfp_get_fpscr)(CPUARMState *env)
4749 {
4750     int i;
4751     uint32_t fpscr;
4752
4753     fpscr = (env->vfp.xregs[ARM_VFP_FPSCR] & 0xffc8ffff)
4754             | (env->vfp.vec_len << 16)
4755             | (env->vfp.vec_stride << 20);
4756     i = get_float_exception_flags(&env->vfp.fp_status);
4757     i |= get_float_exception_flags(&env->vfp.standard_fp_status);
4758     fpscr |= vfp_exceptbits_from_host(i);
4759     return fpscr;
4760 }
4761
4762 uint32_t vfp_get_fpscr(CPUARMState *env)
4763 {
4764     return HELPER(vfp_get_fpscr)(env);
4765 }
4766
4767 /* Convert vfp exception flags to target form.  */
4768 static inline int vfp_exceptbits_to_host(int target_bits)
4769 {
4770     int host_bits = 0;
4771
4772     if (target_bits & 1)
4773         host_bits |= float_flag_invalid;
4774     if (target_bits & 2)
4775         host_bits |= float_flag_divbyzero;
4776     if (target_bits & 4)
4777         host_bits |= float_flag_overflow;
4778     if (target_bits & 8)
4779         host_bits |= float_flag_underflow;
4780     if (target_bits & 0x10)
4781         host_bits |= float_flag_inexact;
4782     if (target_bits & 0x80)
4783         host_bits |= float_flag_input_denormal;
4784     return host_bits;
4785 }
4786
4787 void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val)
4788 {
4789     int i;
4790     uint32_t changed;
4791
4792     changed = env->vfp.xregs[ARM_VFP_FPSCR];
4793     env->vfp.xregs[ARM_VFP_FPSCR] = (val & 0xffc8ffff);
4794     env->vfp.vec_len = (val >> 16) & 7;
4795     env->vfp.vec_stride = (val >> 20) & 3;
4796
4797     changed ^= val;
4798     if (changed & (3 << 22)) {
4799         i = (val >> 22) & 3;
4800         switch (i) {
4801         case FPROUNDING_TIEEVEN:
4802             i = float_round_nearest_even;
4803             break;
4804         case FPROUNDING_POSINF:
4805             i = float_round_up;
4806             break;
4807         case FPROUNDING_NEGINF:
4808             i = float_round_down;
4809             break;
4810         case FPROUNDING_ZERO:
4811             i = float_round_to_zero;
4812             break;
4813         }
4814         set_float_rounding_mode(i, &env->vfp.fp_status);
4815     }
4816     if (changed & (1 << 24)) {
4817         set_flush_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status);
4818         set_flush_inputs_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status);
4819     }
4820     if (changed & (1 << 25))
4821         set_default_nan_mode((val & (1 << 25)) != 0, &env->vfp.fp_status);
4822
4823     i = vfp_exceptbits_to_host(val);
4824     set_float_exception_flags(i, &env->vfp.fp_status);
4825     set_float_exception_flags(0, &env->vfp.standard_fp_status);
4826 }
4827
4828 void vfp_set_fpscr(CPUARMState *env, uint32_t val)
4829 {
4830     HELPER(vfp_set_fpscr)(env, val);
4831 }
4832
4833 #define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p))
4834
4835 #define VFP_BINOP(name) \
4836 float32 VFP_HELPER(name, s)(float32 a, float32 b, void *fpstp) \
4837 { \
4838     float_status *fpst = fpstp; \
4839     return float32_ ## name(a, b, fpst); \
4840 } \
4841 float64 VFP_HELPER(name, d)(float64 a, float64 b, void *fpstp) \
4842 { \
4843     float_status *fpst = fpstp; \
4844     return float64_ ## name(a, b, fpst); \
4845 }
4846 VFP_BINOP(add)
4847 VFP_BINOP(sub)
4848 VFP_BINOP(mul)
4849 VFP_BINOP(div)
4850 VFP_BINOP(min)
4851 VFP_BINOP(max)
4852 VFP_BINOP(minnum)
4853 VFP_BINOP(maxnum)
4854 #undef VFP_BINOP
4855
4856 float32 VFP_HELPER(neg, s)(float32 a)
4857 {
4858     return float32_chs(a);
4859 }
4860
4861 float64 VFP_HELPER(neg, d)(float64 a)
4862 {
4863     return float64_chs(a);
4864 }
4865
4866 float32 VFP_HELPER(abs, s)(float32 a)
4867 {
4868     return float32_abs(a);
4869 }
4870
4871 float64 VFP_HELPER(abs, d)(float64 a)
4872 {
4873     return float64_abs(a);
4874 }
4875
4876 float32 VFP_HELPER(sqrt, s)(float32 a, CPUARMState *env)
4877 {
4878     return float32_sqrt(a, &env->vfp.fp_status);
4879 }
4880
4881 float64 VFP_HELPER(sqrt, d)(float64 a, CPUARMState *env)
4882 {
4883     return float64_sqrt(a, &env->vfp.fp_status);
4884 }
4885
4886 /* XXX: check quiet/signaling case */
4887 #define DO_VFP_cmp(p, type) \
4888 void VFP_HELPER(cmp, p)(type a, type b, CPUARMState *env)  \
4889 { \
4890     uint32_t flags; \
4891     switch(type ## _compare_quiet(a, b, &env->vfp.fp_status)) { \
4892     case 0: flags = 0x6; break; \
4893     case -1: flags = 0x8; break; \
4894     case 1: flags = 0x2; break; \
4895     default: case 2: flags = 0x3; break; \
4896     } \
4897     env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
4898         | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
4899 } \
4900 void VFP_HELPER(cmpe, p)(type a, type b, CPUARMState *env) \
4901 { \
4902     uint32_t flags; \
4903     switch(type ## _compare(a, b, &env->vfp.fp_status)) { \
4904     case 0: flags = 0x6; break; \
4905     case -1: flags = 0x8; break; \
4906     case 1: flags = 0x2; break; \
4907     default: case 2: flags = 0x3; break; \
4908     } \
4909     env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
4910         | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
4911 }
4912 DO_VFP_cmp(s, float32)
4913 DO_VFP_cmp(d, float64)
4914 #undef DO_VFP_cmp
4915
4916 /* Integer to float and float to integer conversions */
4917
4918 #define CONV_ITOF(name, fsz, sign) \
4919     float##fsz HELPER(name)(uint32_t x, void *fpstp) \
4920 { \
4921     float_status *fpst = fpstp; \
4922     return sign##int32_to_##float##fsz((sign##int32_t)x, fpst); \
4923 }
4924
4925 #define CONV_FTOI(name, fsz, sign, round) \
4926 uint32_t HELPER(name)(float##fsz x, void *fpstp) \
4927 { \
4928     float_status *fpst = fpstp; \
4929     if (float##fsz##_is_any_nan(x)) { \
4930         float_raise(float_flag_invalid, fpst); \
4931         return 0; \
4932     } \
4933     return float##fsz##_to_##sign##int32##round(x, fpst); \
4934 }
4935
4936 #define FLOAT_CONVS(name, p, fsz, sign) \
4937 CONV_ITOF(vfp_##name##to##p, fsz, sign) \
4938 CONV_FTOI(vfp_to##name##p, fsz, sign, ) \
4939 CONV_FTOI(vfp_to##name##z##p, fsz, sign, _round_to_zero)
4940
4941 FLOAT_CONVS(si, s, 32, )
4942 FLOAT_CONVS(si, d, 64, )
4943 FLOAT_CONVS(ui, s, 32, u)
4944 FLOAT_CONVS(ui, d, 64, u)
4945
4946 #undef CONV_ITOF
4947 #undef CONV_FTOI
4948 #undef FLOAT_CONVS
4949
4950 /* floating point conversion */
4951 float64 VFP_HELPER(fcvtd, s)(float32 x, CPUARMState *env)
4952 {
4953     float64 r = float32_to_float64(x, &env->vfp.fp_status);
4954     /* ARM requires that S<->D conversion of any kind of NaN generates
4955      * a quiet NaN by forcing the most significant frac bit to 1.
4956      */
4957     return float64_maybe_silence_nan(r);
4958 }
4959
4960 float32 VFP_HELPER(fcvts, d)(float64 x, CPUARMState *env)
4961 {
4962     float32 r =  float64_to_float32(x, &env->vfp.fp_status);
4963     /* ARM requires that S<->D conversion of any kind of NaN generates
4964      * a quiet NaN by forcing the most significant frac bit to 1.
4965      */
4966     return float32_maybe_silence_nan(r);
4967 }
4968
4969 /* VFP3 fixed point conversion.  */
4970 #define VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \
4971 float##fsz HELPER(vfp_##name##to##p)(uint##isz##_t  x, uint32_t shift, \
4972                                      void *fpstp) \
4973 { \
4974     float_status *fpst = fpstp; \
4975     float##fsz tmp; \
4976     tmp = itype##_to_##float##fsz(x, fpst); \
4977     return float##fsz##_scalbn(tmp, -(int)shift, fpst); \
4978 }
4979
4980 /* Notice that we want only input-denormal exception flags from the
4981  * scalbn operation: the other possible flags (overflow+inexact if
4982  * we overflow to infinity, output-denormal) aren't correct for the
4983  * complete scale-and-convert operation.
4984  */
4985 #define VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, round) \
4986 uint##isz##_t HELPER(vfp_to##name##p##round)(float##fsz x, \
4987                                              uint32_t shift, \
4988                                              void *fpstp) \
4989 { \
4990     float_status *fpst = fpstp; \
4991     int old_exc_flags = get_float_exception_flags(fpst); \
4992     float##fsz tmp; \
4993     if (float##fsz##_is_any_nan(x)) { \
4994         float_raise(float_flag_invalid, fpst); \
4995         return 0; \
4996     } \
4997     tmp = float##fsz##_scalbn(x, shift, fpst); \
4998     old_exc_flags |= get_float_exception_flags(fpst) \
4999         & float_flag_input_denormal; \
5000     set_float_exception_flags(old_exc_flags, fpst); \
5001     return float##fsz##_to_##itype##round(tmp, fpst); \
5002 }
5003
5004 #define VFP_CONV_FIX(name, p, fsz, isz, itype)                   \
5005 VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype)                     \
5006 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, _round_to_zero) \
5007 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, )
5008
5009 #define VFP_CONV_FIX_A64(name, p, fsz, isz, itype)               \
5010 VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype)                     \
5011 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, )
5012
5013 VFP_CONV_FIX(sh, d, 64, 64, int16)
5014 VFP_CONV_FIX(sl, d, 64, 64, int32)
5015 VFP_CONV_FIX_A64(sq, d, 64, 64, int64)
5016 VFP_CONV_FIX(uh, d, 64, 64, uint16)
5017 VFP_CONV_FIX(ul, d, 64, 64, uint32)
5018 VFP_CONV_FIX_A64(uq, d, 64, 64, uint64)
5019 VFP_CONV_FIX(sh, s, 32, 32, int16)
5020 VFP_CONV_FIX(sl, s, 32, 32, int32)
5021 VFP_CONV_FIX_A64(sq, s, 32, 64, int64)
5022 VFP_CONV_FIX(uh, s, 32, 32, uint16)
5023 VFP_CONV_FIX(ul, s, 32, 32, uint32)
5024 VFP_CONV_FIX_A64(uq, s, 32, 64, uint64)
5025 #undef VFP_CONV_FIX
5026 #undef VFP_CONV_FIX_FLOAT
5027 #undef VFP_CONV_FLOAT_FIX_ROUND
5028
5029 /* Set the current fp rounding mode and return the old one.
5030  * The argument is a softfloat float_round_ value.
5031  */
5032 uint32_t HELPER(set_rmode)(uint32_t rmode, CPUARMState *env)
5033 {
5034     float_status *fp_status = &env->vfp.fp_status;
5035
5036     uint32_t prev_rmode = get_float_rounding_mode(fp_status);
5037     set_float_rounding_mode(rmode, fp_status);
5038
5039     return prev_rmode;
5040 }
5041
5042 /* Set the current fp rounding mode in the standard fp status and return
5043  * the old one. This is for NEON instructions that need to change the
5044  * rounding mode but wish to use the standard FPSCR values for everything
5045  * else. Always set the rounding mode back to the correct value after
5046  * modifying it.
5047  * The argument is a softfloat float_round_ value.
5048  */
5049 uint32_t HELPER(set_neon_rmode)(uint32_t rmode, CPUARMState *env)
5050 {
5051     float_status *fp_status = &env->vfp.standard_fp_status;
5052
5053     uint32_t prev_rmode = get_float_rounding_mode(fp_status);
5054     set_float_rounding_mode(rmode, fp_status);
5055
5056     return prev_rmode;
5057 }
5058
5059 /* Half precision conversions.  */
5060 static float32 do_fcvt_f16_to_f32(uint32_t a, CPUARMState *env, float_status *s)
5061 {
5062     int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
5063     float32 r = float16_to_float32(make_float16(a), ieee, s);
5064     if (ieee) {
5065         return float32_maybe_silence_nan(r);
5066     }
5067     return r;
5068 }
5069
5070 static uint32_t do_fcvt_f32_to_f16(float32 a, CPUARMState *env, float_status *s)
5071 {
5072     int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
5073     float16 r = float32_to_float16(a, ieee, s);
5074     if (ieee) {
5075         r = float16_maybe_silence_nan(r);
5076     }
5077     return float16_val(r);
5078 }
5079
5080 float32 HELPER(neon_fcvt_f16_to_f32)(uint32_t a, CPUARMState *env)
5081 {
5082     return do_fcvt_f16_to_f32(a, env, &env->vfp.standard_fp_status);
5083 }
5084
5085 uint32_t HELPER(neon_fcvt_f32_to_f16)(float32 a, CPUARMState *env)
5086 {
5087     return do_fcvt_f32_to_f16(a, env, &env->vfp.standard_fp_status);
5088 }
5089
5090 float32 HELPER(vfp_fcvt_f16_to_f32)(uint32_t a, CPUARMState *env)
5091 {
5092     return do_fcvt_f16_to_f32(a, env, &env->vfp.fp_status);
5093 }
5094
5095 uint32_t HELPER(vfp_fcvt_f32_to_f16)(float32 a, CPUARMState *env)
5096 {
5097     return do_fcvt_f32_to_f16(a, env, &env->vfp.fp_status);
5098 }
5099
5100 float64 HELPER(vfp_fcvt_f16_to_f64)(uint32_t a, CPUARMState *env)
5101 {
5102     int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
5103     float64 r = float16_to_float64(make_float16(a), ieee, &env->vfp.fp_status);
5104     if (ieee) {
5105         return float64_maybe_silence_nan(r);
5106     }
5107     return r;
5108 }
5109
5110 uint32_t HELPER(vfp_fcvt_f64_to_f16)(float64 a, CPUARMState *env)
5111 {
5112     int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
5113     float16 r = float64_to_float16(a, ieee, &env->vfp.fp_status);
5114     if (ieee) {
5115         r = float16_maybe_silence_nan(r);
5116     }
5117     return float16_val(r);
5118 }
5119
5120 #define float32_two make_float32(0x40000000)
5121 #define float32_three make_float32(0x40400000)
5122 #define float32_one_point_five make_float32(0x3fc00000)
5123
5124 float32 HELPER(recps_f32)(float32 a, float32 b, CPUARMState *env)
5125 {
5126     float_status *s = &env->vfp.standard_fp_status;
5127     if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) ||
5128         (float32_is_infinity(b) && float32_is_zero_or_denormal(a))) {
5129         if (!(float32_is_zero(a) || float32_is_zero(b))) {
5130             float_raise(float_flag_input_denormal, s);
5131         }
5132         return float32_two;
5133     }
5134     return float32_sub(float32_two, float32_mul(a, b, s), s);
5135 }
5136
5137 float32 HELPER(rsqrts_f32)(float32 a, float32 b, CPUARMState *env)
5138 {
5139     float_status *s = &env->vfp.standard_fp_status;
5140     float32 product;
5141     if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) ||
5142         (float32_is_infinity(b) && float32_is_zero_or_denormal(a))) {
5143         if (!(float32_is_zero(a) || float32_is_zero(b))) {
5144             float_raise(float_flag_input_denormal, s);
5145         }
5146         return float32_one_point_five;
5147     }
5148     product = float32_mul(a, b, s);
5149     return float32_div(float32_sub(float32_three, product, s), float32_two, s);
5150 }
5151
5152 /* NEON helpers.  */
5153
5154 /* Constants 256 and 512 are used in some helpers; we avoid relying on
5155  * int->float conversions at run-time.  */
5156 #define float64_256 make_float64(0x4070000000000000LL)
5157 #define float64_512 make_float64(0x4080000000000000LL)
5158 #define float32_maxnorm make_float32(0x7f7fffff)
5159 #define float64_maxnorm make_float64(0x7fefffffffffffffLL)
5160
5161 /* Reciprocal functions
5162  *
5163  * The algorithm that must be used to calculate the estimate
5164  * is specified by the ARM ARM, see FPRecipEstimate()
5165  */
5166
5167 static float64 recip_estimate(float64 a, float_status *real_fp_status)
5168 {
5169     /* These calculations mustn't set any fp exception flags,
5170      * so we use a local copy of the fp_status.
5171      */
5172     float_status dummy_status = *real_fp_status;
5173     float_status *s = &dummy_status;
5174     /* q = (int)(a * 512.0) */
5175     float64 q = float64_mul(float64_512, a, s);
5176     int64_t q_int = float64_to_int64_round_to_zero(q, s);
5177
5178     /* r = 1.0 / (((double)q + 0.5) / 512.0) */
5179     q = int64_to_float64(q_int, s);
5180     q = float64_add(q, float64_half, s);
5181     q = float64_div(q, float64_512, s);
5182     q = float64_div(float64_one, q, s);
5183
5184     /* s = (int)(256.0 * r + 0.5) */
5185     q = float64_mul(q, float64_256, s);
5186     q = float64_add(q, float64_half, s);
5187     q_int = float64_to_int64_round_to_zero(q, s);
5188
5189     /* return (double)s / 256.0 */
5190     return float64_div(int64_to_float64(q_int, s), float64_256, s);
5191 }
5192
5193 /* Common wrapper to call recip_estimate */
5194 static float64 call_recip_estimate(float64 num, int off, float_status *fpst)
5195 {
5196     uint64_t val64 = float64_val(num);
5197     uint64_t frac = extract64(val64, 0, 52);
5198     int64_t exp = extract64(val64, 52, 11);
5199     uint64_t sbit;
5200     float64 scaled, estimate;
5201
5202     /* Generate the scaled number for the estimate function */
5203     if (exp == 0) {
5204         if (extract64(frac, 51, 1) == 0) {
5205             exp = -1;
5206             frac = extract64(frac, 0, 50) << 2;
5207         } else {
5208             frac = extract64(frac, 0, 51) << 1;
5209         }
5210     }
5211
5212     /* scaled = '0' : '01111111110' : fraction<51:44> : Zeros(44); */
5213     scaled = make_float64((0x3feULL << 52)
5214                           | extract64(frac, 44, 8) << 44);
5215
5216     estimate = recip_estimate(scaled, fpst);
5217
5218     /* Build new result */
5219     val64 = float64_val(estimate);
5220     sbit = 0x8000000000000000ULL & val64;
5221     exp = off - exp;
5222     frac = extract64(val64, 0, 52);
5223
5224     if (exp == 0) {
5225         frac = 1ULL << 51 | extract64(frac, 1, 51);
5226     } else if (exp == -1) {
5227         frac = 1ULL << 50 | extract64(frac, 2, 50);
5228         exp = 0;
5229     }
5230
5231     return make_float64(sbit | (exp << 52) | frac);
5232 }
5233
5234 static bool round_to_inf(float_status *fpst, bool sign_bit)
5235 {
5236     switch (fpst->float_rounding_mode) {
5237     case float_round_nearest_even: /* Round to Nearest */
5238         return true;
5239     case float_round_up: /* Round to +Inf */
5240         return !sign_bit;
5241     case float_round_down: /* Round to -Inf */
5242         return sign_bit;
5243     case float_round_to_zero: /* Round to Zero */
5244         return false;
5245     }
5246
5247     g_assert_not_reached();
5248 }
5249
5250 float32 HELPER(recpe_f32)(float32 input, void *fpstp)
5251 {
5252     float_status *fpst = fpstp;
5253     float32 f32 = float32_squash_input_denormal(input, fpst);
5254     uint32_t f32_val = float32_val(f32);
5255     uint32_t f32_sbit = 0x80000000ULL & f32_val;
5256     int32_t f32_exp = extract32(f32_val, 23, 8);
5257     uint32_t f32_frac = extract32(f32_val, 0, 23);
5258     float64 f64, r64;
5259     uint64_t r64_val;
5260     int64_t r64_exp;
5261     uint64_t r64_frac;
5262
5263     if (float32_is_any_nan(f32)) {
5264         float32 nan = f32;
5265         if (float32_is_signaling_nan(f32)) {
5266             float_raise(float_flag_invalid, fpst);
5267             nan = float32_maybe_silence_nan(f32);
5268         }
5269         if (fpst->default_nan_mode) {
5270             nan =  float32_default_nan;
5271         }
5272         return nan;
5273     } else if (float32_is_infinity(f32)) {
5274         return float32_set_sign(float32_zero, float32_is_neg(f32));
5275     } else if (float32_is_zero(f32)) {
5276         float_raise(float_flag_divbyzero, fpst);
5277         return float32_set_sign(float32_infinity, float32_is_neg(f32));
5278     } else if ((f32_val & ~(1ULL << 31)) < (1ULL << 21)) {
5279         /* Abs(value) < 2.0^-128 */
5280         float_raise(float_flag_overflow | float_flag_inexact, fpst);
5281         if (round_to_inf(fpst, f32_sbit)) {
5282             return float32_set_sign(float32_infinity, float32_is_neg(f32));
5283         } else {
5284             return float32_set_sign(float32_maxnorm, float32_is_neg(f32));
5285         }
5286     } else if (f32_exp >= 253 && fpst->flush_to_zero) {
5287         float_raise(float_flag_underflow, fpst);
5288         return float32_set_sign(float32_zero, float32_is_neg(f32));
5289     }
5290
5291
5292     f64 = make_float64(((int64_t)(f32_exp) << 52) | (int64_t)(f32_frac) << 29);
5293     r64 = call_recip_estimate(f64, 253, fpst);
5294     r64_val = float64_val(r64);
5295     r64_exp = extract64(r64_val, 52, 11);
5296     r64_frac = extract64(r64_val, 0, 52);
5297
5298     /* result = sign : result_exp<7:0> : fraction<51:29>; */
5299     return make_float32(f32_sbit |
5300                         (r64_exp & 0xff) << 23 |
5301                         extract64(r64_frac, 29, 24));
5302 }
5303
5304 float64 HELPER(recpe_f64)(float64 input, void *fpstp)
5305 {
5306     float_status *fpst = fpstp;
5307     float64 f64 = float64_squash_input_denormal(input, fpst);
5308     uint64_t f64_val = float64_val(f64);
5309     uint64_t f64_sbit = 0x8000000000000000ULL & f64_val;
5310     int64_t f64_exp = extract64(f64_val, 52, 11);
5311     float64 r64;
5312     uint64_t r64_val;
5313     int64_t r64_exp;
5314     uint64_t r64_frac;
5315
5316     /* Deal with any special cases */
5317     if (float64_is_any_nan(f64)) {
5318         float64 nan = f64;
5319         if (float64_is_signaling_nan(f64)) {
5320             float_raise(float_flag_invalid, fpst);
5321             nan = float64_maybe_silence_nan(f64);
5322         }
5323         if (fpst->default_nan_mode) {
5324             nan =  float64_default_nan;
5325         }
5326         return nan;
5327     } else if (float64_is_infinity(f64)) {
5328         return float64_set_sign(float64_zero, float64_is_neg(f64));
5329     } else if (float64_is_zero(f64)) {
5330         float_raise(float_flag_divbyzero, fpst);
5331         return float64_set_sign(float64_infinity, float64_is_neg(f64));
5332     } else if ((f64_val & ~(1ULL << 63)) < (1ULL << 50)) {
5333         /* Abs(value) < 2.0^-1024 */
5334         float_raise(float_flag_overflow | float_flag_inexact, fpst);
5335         if (round_to_inf(fpst, f64_sbit)) {
5336             return float64_set_sign(float64_infinity, float64_is_neg(f64));
5337         } else {
5338             return float64_set_sign(float64_maxnorm, float64_is_neg(f64));
5339         }
5340     } else if (f64_exp >= 1023 && fpst->flush_to_zero) {
5341         float_raise(float_flag_underflow, fpst);
5342         return float64_set_sign(float64_zero, float64_is_neg(f64));
5343     }
5344
5345     r64 = call_recip_estimate(f64, 2045, fpst);
5346     r64_val = float64_val(r64);
5347     r64_exp = extract64(r64_val, 52, 11);
5348     r64_frac = extract64(r64_val, 0, 52);
5349
5350     /* result = sign : result_exp<10:0> : fraction<51:0> */
5351     return make_float64(f64_sbit |
5352                         ((r64_exp & 0x7ff) << 52) |
5353                         r64_frac);
5354 }
5355
5356 /* The algorithm that must be used to calculate the estimate
5357  * is specified by the ARM ARM.
5358  */
5359 static float64 recip_sqrt_estimate(float64 a, float_status *real_fp_status)
5360 {
5361     /* These calculations mustn't set any fp exception flags,
5362      * so we use a local copy of the fp_status.
5363      */
5364     float_status dummy_status = *real_fp_status;
5365     float_status *s = &dummy_status;
5366     float64 q;
5367     int64_t q_int;
5368
5369     if (float64_lt(a, float64_half, s)) {
5370         /* range 0.25 <= a < 0.5 */
5371
5372         /* a in units of 1/512 rounded down */
5373         /* q0 = (int)(a * 512.0);  */
5374         q = float64_mul(float64_512, a, s);
5375         q_int = float64_to_int64_round_to_zero(q, s);
5376
5377         /* reciprocal root r */
5378         /* r = 1.0 / sqrt(((double)q0 + 0.5) / 512.0);  */
5379         q = int64_to_float64(q_int, s);
5380         q = float64_add(q, float64_half, s);
5381         q = float64_div(q, float64_512, s);
5382         q = float64_sqrt(q, s);
5383         q = float64_div(float64_one, q, s);
5384     } else {
5385         /* range 0.5 <= a < 1.0 */
5386
5387         /* a in units of 1/256 rounded down */
5388         /* q1 = (int)(a * 256.0); */
5389         q = float64_mul(float64_256, a, s);
5390         int64_t q_int = float64_to_int64_round_to_zero(q, s);
5391
5392         /* reciprocal root r */
5393         /* r = 1.0 /sqrt(((double)q1 + 0.5) / 256); */
5394         q = int64_to_float64(q_int, s);
5395         q = float64_add(q, float64_half, s);
5396         q = float64_div(q, float64_256, s);
5397         q = float64_sqrt(q, s);
5398         q = float64_div(float64_one, q, s);
5399     }
5400     /* r in units of 1/256 rounded to nearest */
5401     /* s = (int)(256.0 * r + 0.5); */
5402
5403     q = float64_mul(q, float64_256,s );
5404     q = float64_add(q, float64_half, s);
5405     q_int = float64_to_int64_round_to_zero(q, s);
5406
5407     /* return (double)s / 256.0;*/
5408     return float64_div(int64_to_float64(q_int, s), float64_256, s);
5409 }
5410
5411 float32 HELPER(rsqrte_f32)(float32 input, void *fpstp)
5412 {
5413     float_status *s = fpstp;
5414     float32 f32 = float32_squash_input_denormal(input, s);
5415     uint32_t val = float32_val(f32);
5416     uint32_t f32_sbit = 0x80000000 & val;
5417     int32_t f32_exp = extract32(val, 23, 8);
5418     uint32_t f32_frac = extract32(val, 0, 23);
5419     uint64_t f64_frac;
5420     uint64_t val64;
5421     int result_exp;
5422     float64 f64;
5423
5424     if (float32_is_any_nan(f32)) {
5425         float32 nan = f32;
5426         if (float32_is_signaling_nan(f32)) {
5427             float_raise(float_flag_invalid, s);
5428             nan = float32_maybe_silence_nan(f32);
5429         }
5430         if (s->default_nan_mode) {
5431             nan =  float32_default_nan;
5432         }
5433         return nan;
5434     } else if (float32_is_zero(f32)) {
5435         float_raise(float_flag_divbyzero, s);
5436         return float32_set_sign(float32_infinity, float32_is_neg(f32));
5437     } else if (float32_is_neg(f32)) {
5438         float_raise(float_flag_invalid, s);
5439         return float32_default_nan;
5440     } else if (float32_is_infinity(f32)) {
5441         return float32_zero;
5442     }
5443
5444     /* Scale and normalize to a double-precision value between 0.25 and 1.0,
5445      * preserving the parity of the exponent.  */
5446
5447     f64_frac = ((uint64_t) f32_frac) << 29;
5448     if (f32_exp == 0) {
5449         while (extract64(f64_frac, 51, 1) == 0) {
5450             f64_frac = f64_frac << 1;
5451             f32_exp = f32_exp-1;
5452         }
5453         f64_frac = extract64(f64_frac, 0, 51) << 1;
5454     }
5455
5456     if (extract64(f32_exp, 0, 1) == 0) {
5457         f64 = make_float64(((uint64_t) f32_sbit) << 32
5458                            | (0x3feULL << 52)
5459                            | f64_frac);
5460     } else {
5461         f64 = make_float64(((uint64_t) f32_sbit) << 32
5462                            | (0x3fdULL << 52)
5463                            | f64_frac);
5464     }
5465
5466     result_exp = (380 - f32_exp) / 2;
5467
5468     f64 = recip_sqrt_estimate(f64, s);
5469
5470     val64 = float64_val(f64);
5471
5472     val = ((result_exp & 0xff) << 23)
5473         | ((val64 >> 29)  & 0x7fffff);
5474     return make_float32(val);
5475 }
5476
5477 float64 HELPER(rsqrte_f64)(float64 input, void *fpstp)
5478 {
5479     float_status *s = fpstp;
5480     float64 f64 = float64_squash_input_denormal(input, s);
5481     uint64_t val = float64_val(f64);
5482     uint64_t f64_sbit = 0x8000000000000000ULL & val;
5483     int64_t f64_exp = extract64(val, 52, 11);
5484     uint64_t f64_frac = extract64(val, 0, 52);
5485     int64_t result_exp;
5486     uint64_t result_frac;
5487
5488     if (float64_is_any_nan(f64)) {
5489         float64 nan = f64;
5490         if (float64_is_signaling_nan(f64)) {
5491             float_raise(float_flag_invalid, s);
5492             nan = float64_maybe_silence_nan(f64);
5493         }
5494         if (s->default_nan_mode) {
5495             nan =  float64_default_nan;
5496         }
5497         return nan;
5498     } else if (float64_is_zero(f64)) {
5499         float_raise(float_flag_divbyzero, s);
5500         return float64_set_sign(float64_infinity, float64_is_neg(f64));
5501     } else if (float64_is_neg(f64)) {
5502         float_raise(float_flag_invalid, s);
5503         return float64_default_nan;
5504     } else if (float64_is_infinity(f64)) {
5505         return float64_zero;
5506     }
5507
5508     /* Scale and normalize to a double-precision value between 0.25 and 1.0,
5509      * preserving the parity of the exponent.  */
5510
5511     if (f64_exp == 0) {
5512         while (extract64(f64_frac, 51, 1) == 0) {
5513             f64_frac = f64_frac << 1;
5514             f64_exp = f64_exp - 1;
5515         }
5516         f64_frac = extract64(f64_frac, 0, 51) << 1;
5517     }
5518
5519     if (extract64(f64_exp, 0, 1) == 0) {
5520         f64 = make_float64(f64_sbit
5521                            | (0x3feULL << 52)
5522                            | f64_frac);
5523     } else {
5524         f64 = make_float64(f64_sbit
5525                            | (0x3fdULL << 52)
5526                            | f64_frac);
5527     }
5528
5529     result_exp = (3068 - f64_exp) / 2;
5530
5531     f64 = recip_sqrt_estimate(f64, s);
5532
5533     result_frac = extract64(float64_val(f64), 0, 52);
5534
5535     return make_float64(f64_sbit |
5536                         ((result_exp & 0x7ff) << 52) |
5537                         result_frac);
5538 }
5539
5540 uint32_t HELPER(recpe_u32)(uint32_t a, void *fpstp)
5541 {
5542     float_status *s = fpstp;
5543     float64 f64;
5544
5545     if ((a & 0x80000000) == 0) {
5546         return 0xffffffff;
5547     }
5548
5549     f64 = make_float64((0x3feULL << 52)
5550                        | ((int64_t)(a & 0x7fffffff) << 21));
5551
5552     f64 = recip_estimate(f64, s);
5553
5554     return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff);
5555 }
5556
5557 uint32_t HELPER(rsqrte_u32)(uint32_t a, void *fpstp)
5558 {
5559     float_status *fpst = fpstp;
5560     float64 f64;
5561
5562     if ((a & 0xc0000000) == 0) {
5563         return 0xffffffff;
5564     }
5565
5566     if (a & 0x80000000) {
5567         f64 = make_float64((0x3feULL << 52)
5568                            | ((uint64_t)(a & 0x7fffffff) << 21));
5569     } else { /* bits 31-30 == '01' */
5570         f64 = make_float64((0x3fdULL << 52)
5571                            | ((uint64_t)(a & 0x3fffffff) << 22));
5572     }
5573
5574     f64 = recip_sqrt_estimate(f64, fpst);
5575
5576     return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff);
5577 }
5578
5579 /* VFPv4 fused multiply-accumulate */
5580 float32 VFP_HELPER(muladd, s)(float32 a, float32 b, float32 c, void *fpstp)
5581 {
5582     float_status *fpst = fpstp;
5583     return float32_muladd(a, b, c, 0, fpst);
5584 }
5585
5586 float64 VFP_HELPER(muladd, d)(float64 a, float64 b, float64 c, void *fpstp)
5587 {
5588     float_status *fpst = fpstp;
5589     return float64_muladd(a, b, c, 0, fpst);
5590 }
5591
5592 /* ARMv8 round to integral */
5593 float32 HELPER(rints_exact)(float32 x, void *fp_status)
5594 {
5595     return float32_round_to_int(x, fp_status);
5596 }
5597
5598 float64 HELPER(rintd_exact)(float64 x, void *fp_status)
5599 {
5600     return float64_round_to_int(x, fp_status);
5601 }
5602
5603 float32 HELPER(rints)(float32 x, void *fp_status)
5604 {
5605     int old_flags = get_float_exception_flags(fp_status), new_flags;
5606     float32 ret;
5607
5608     ret = float32_round_to_int(x, fp_status);
5609
5610     /* Suppress any inexact exceptions the conversion produced */
5611     if (!(old_flags & float_flag_inexact)) {
5612         new_flags = get_float_exception_flags(fp_status);
5613         set_float_exception_flags(new_flags & ~float_flag_inexact, fp_status);
5614     }
5615
5616     return ret;
5617 }
5618
5619 float64 HELPER(rintd)(float64 x, void *fp_status)
5620 {
5621     int old_flags = get_float_exception_flags(fp_status), new_flags;
5622     float64 ret;
5623
5624     ret = float64_round_to_int(x, fp_status);
5625
5626     new_flags = get_float_exception_flags(fp_status);
5627
5628     /* Suppress any inexact exceptions the conversion produced */
5629     if (!(old_flags & float_flag_inexact)) {
5630         new_flags = get_float_exception_flags(fp_status);
5631         set_float_exception_flags(new_flags & ~float_flag_inexact, fp_status);
5632     }
5633
5634     return ret;
5635 }
5636
5637 /* Convert ARM rounding mode to softfloat */
5638 int arm_rmode_to_sf(int rmode)
5639 {
5640     switch (rmode) {
5641     case FPROUNDING_TIEAWAY:
5642         rmode = float_round_ties_away;
5643         break;
5644     case FPROUNDING_ODD:
5645         /* FIXME: add support for TIEAWAY and ODD */
5646         qemu_log_mask(LOG_UNIMP, "arm: unimplemented rounding mode: %d\n",
5647                       rmode);
5648     case FPROUNDING_TIEEVEN:
5649     default:
5650         rmode = float_round_nearest_even;
5651         break;
5652     case FPROUNDING_POSINF:
5653         rmode = float_round_up;
5654         break;
5655     case FPROUNDING_NEGINF:
5656         rmode = float_round_down;
5657         break;
5658     case FPROUNDING_ZERO:
5659         rmode = float_round_to_zero;
5660         break;
5661     }
5662     return rmode;
5663 }
5664
5665 /* CRC helpers.
5666  * The upper bytes of val (above the number specified by 'bytes') must have
5667  * been zeroed out by the caller.
5668  */
5669 uint32_t HELPER(crc32)(uint32_t acc, uint32_t val, uint32_t bytes)
5670 {
5671     uint8_t buf[4];
5672
5673     stl_le_p(buf, val);
5674
5675     /* zlib crc32 converts the accumulator and output to one's complement.  */
5676     return crc32(acc ^ 0xffffffff, buf, bytes) ^ 0xffffffff;
5677 }
5678
5679 uint32_t HELPER(crc32c)(uint32_t acc, uint32_t val, uint32_t bytes)
5680 {
5681     uint8_t buf[4];
5682
5683     stl_le_p(buf, val);
5684
5685     /* Linux crc32c converts the output to one's complement.  */
5686     return crc32c(acc, buf, bytes) ^ 0xffffffff;
5687 }