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add win32 qemu-thread implementation
[qemu.git] / hw / e1000.c
blob0a4574cf93e40f85cb3be961c1d78f6c358c5b26
1 /*
2 * QEMU e1000 emulation
3 *
4 * Software developer's manual:
5 * http://download.intel.com/design/network/manuals/8254x_GBe_SDM.pdf
6 *
7 * Nir Peleg, Tutis Systems Ltd. for Qumranet Inc.
8 * Copyright (c) 2008 Qumranet
9 * Based on work done by:
10 * Copyright (c) 2007 Dan Aloni
11 * Copyright (c) 2004 Antony T Curtis
12 *
13 * This library is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU Lesser General Public
15 * License as published by the Free Software Foundation; either
16 * version 2 of the License, or (at your option) any later version.
17 *
18 * This library is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
21 * Lesser General Public License for more details.
22 *
23 * You should have received a copy of the GNU Lesser General Public
24 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
25 */
26
27
28 #include "hw.h"
29 #include "pci.h"
30 #include "net.h"
31 #include "net/checksum.h"
32 #include "loader.h"
33 #include "sysemu.h"
34
35 #include "e1000_hw.h"
36
37 #define E1000_DEBUG
38
39 #ifdef E1000_DEBUG
40 enum {
41 DEBUG_GENERAL, DEBUG_IO, DEBUG_MMIO, DEBUG_INTERRUPT,
42 DEBUG_RX, DEBUG_TX, DEBUG_MDIC, DEBUG_EEPROM,
43 DEBUG_UNKNOWN, DEBUG_TXSUM, DEBUG_TXERR, DEBUG_RXERR,
44 DEBUG_RXFILTER, DEBUG_NOTYET,
45 };
46 #define DBGBIT(x) (1<<DEBUG_##x)
47 static int debugflags = DBGBIT(TXERR) | DBGBIT(GENERAL);
48
49 #define DBGOUT(what, fmt, ...) do { \
50 if (debugflags & DBGBIT(what)) \
51 fprintf(stderr, "e1000: " fmt, ## __VA_ARGS__); \
52 } while (0)
53 #else
54 #define DBGOUT(what, fmt, ...) do {} while (0)
55 #endif
56
57 #define IOPORT_SIZE 0x40
58 #define PNPMMIO_SIZE 0x20000
59 #define MIN_BUF_SIZE 60 /* Min. octets in an ethernet frame sans FCS */
60
61 /*
62 * HW models:
63 * E1000_DEV_ID_82540EM works with Windows and Linux
64 * E1000_DEV_ID_82573L OK with windoze and Linux 2.6.22,
65 * appears to perform better than 82540EM, but breaks with Linux 2.6.18
66 * E1000_DEV_ID_82544GC_COPPER appears to work; not well tested
67 * Others never tested
68 */
69 enum { E1000_DEVID = E1000_DEV_ID_82540EM };
70
71 /*
72 * May need to specify additional MAC-to-PHY entries --
73 * Intel's Windows driver refuses to initialize unless they match
74 */
75 enum {
76 PHY_ID2_INIT = E1000_DEVID == E1000_DEV_ID_82573L ? 0xcc2 :
77 E1000_DEVID == E1000_DEV_ID_82544GC_COPPER ? 0xc30 :
78 /* default to E1000_DEV_ID_82540EM */ 0xc20
79 };
80
81 typedef struct E1000State_st {
82 PCIDevice dev;
83 NICState *nic;
84 NICConf conf;
85 int mmio_index;
86
87 uint32_t mac_reg[0x8000];
88 uint16_t phy_reg[0x20];
89 uint16_t eeprom_data[64];
90
91 uint32_t rxbuf_size;
92 uint32_t rxbuf_min_shift;
93 int check_rxov;
94 struct e1000_tx {
95 unsigned char header[256];
96 unsigned char vlan_header[4];
97 /* Fields vlan and data must not be reordered or separated. */
98 unsigned char vlan[4];
99 unsigned char data[0x10000];
100 uint16_t size;
101 unsigned char sum_needed;
102 unsigned char vlan_needed;
103 uint8_t ipcss;
104 uint8_t ipcso;
105 uint16_t ipcse;
106 uint8_t tucss;
107 uint8_t tucso;
108 uint16_t tucse;
109 uint8_t hdr_len;
110 uint16_t mss;
111 uint32_t paylen;
112 uint16_t tso_frames;
113 char tse;
114 int8_t ip;
115 int8_t tcp;
116 char cptse; // current packet tse bit
117 } tx;
118
119 struct {
120 uint32_t val_in; // shifted in from guest driver
121 uint16_t bitnum_in;
122 uint16_t bitnum_out;
123 uint16_t reading;
124 uint32_t old_eecd;
125 } eecd_state;
126 } E1000State;
127
128 #define defreg(x) x = (E1000_##x>>2)
129 enum {
130 defreg(CTRL), defreg(EECD), defreg(EERD), defreg(GPRC),
131 defreg(GPTC), defreg(ICR), defreg(ICS), defreg(IMC),
132 defreg(IMS), defreg(LEDCTL), defreg(MANC), defreg(MDIC),
133 defreg(MPC), defreg(PBA), defreg(RCTL), defreg(RDBAH),
134 defreg(RDBAL), defreg(RDH), defreg(RDLEN), defreg(RDT),
135 defreg(STATUS), defreg(SWSM), defreg(TCTL), defreg(TDBAH),
136 defreg(TDBAL), defreg(TDH), defreg(TDLEN), defreg(TDT),
137 defreg(TORH), defreg(TORL), defreg(TOTH), defreg(TOTL),
138 defreg(TPR), defreg(TPT), defreg(TXDCTL), defreg(WUFC),
139 defreg(RA), defreg(MTA), defreg(CRCERRS),defreg(VFTA),
140 defreg(VET),
141 };
142
143 enum { PHY_R = 1, PHY_W = 2, PHY_RW = PHY_R | PHY_W };
144 static const char phy_regcap[0x20] = {
145 [PHY_STATUS] = PHY_R, [M88E1000_EXT_PHY_SPEC_CTRL] = PHY_RW,
146 [PHY_ID1] = PHY_R, [M88E1000_PHY_SPEC_CTRL] = PHY_RW,
147 [PHY_CTRL] = PHY_RW, [PHY_1000T_CTRL] = PHY_RW,
148 [PHY_LP_ABILITY] = PHY_R, [PHY_1000T_STATUS] = PHY_R,
149 [PHY_AUTONEG_ADV] = PHY_RW, [M88E1000_RX_ERR_CNTR] = PHY_R,
150 [PHY_ID2] = PHY_R, [M88E1000_PHY_SPEC_STATUS] = PHY_R
151 };
152
153 static void
154 ioport_map(PCIDevice *pci_dev, int region_num, pcibus_t addr,
155 pcibus_t size, int type)
156 {
157 DBGOUT(IO, "e1000_ioport_map addr=0x%04"FMT_PCIBUS
158 " size=0x%08"FMT_PCIBUS"\n", addr, size);
159 }
160
161 static void
162 set_interrupt_cause(E1000State *s, int index, uint32_t val)
163 {
164 if (val)
165 val |= E1000_ICR_INT_ASSERTED;
166 s->mac_reg[ICR] = val;
167 s->mac_reg[ICS] = val;
168 qemu_set_irq(s->dev.irq[0], (s->mac_reg[IMS] & s->mac_reg[ICR]) != 0);
169 }
170
171 static void
172 set_ics(E1000State *s, int index, uint32_t val)
173 {
174 DBGOUT(INTERRUPT, "set_ics %x, ICR %x, IMR %x\n", val, s->mac_reg[ICR],
175 s->mac_reg[IMS]);
176 set_interrupt_cause(s, 0, val | s->mac_reg[ICR]);
177 }
178
179 static int
180 rxbufsize(uint32_t v)
181 {
182 v &= E1000_RCTL_BSEX | E1000_RCTL_SZ_16384 | E1000_RCTL_SZ_8192 |
183 E1000_RCTL_SZ_4096 | E1000_RCTL_SZ_2048 | E1000_RCTL_SZ_1024 |
184 E1000_RCTL_SZ_512 | E1000_RCTL_SZ_256;
185 switch (v) {
186 case E1000_RCTL_BSEX | E1000_RCTL_SZ_16384:
187 return 16384;
188 case E1000_RCTL_BSEX | E1000_RCTL_SZ_8192:
189 return 8192;
190 case E1000_RCTL_BSEX | E1000_RCTL_SZ_4096:
191 return 4096;
192 case E1000_RCTL_SZ_1024:
193 return 1024;
194 case E1000_RCTL_SZ_512:
195 return 512;
196 case E1000_RCTL_SZ_256:
197 return 256;
198 }
199 return 2048;
200 }
201
202 static void
203 set_ctrl(E1000State *s, int index, uint32_t val)
204 {
205 /* RST is self clearing */
206 s->mac_reg[CTRL] = val & ~E1000_CTRL_RST;
207 }
208
209 static void
210 set_rx_control(E1000State *s, int index, uint32_t val)
211 {
212 s->mac_reg[RCTL] = val;
213 s->rxbuf_size = rxbufsize(val);
214 s->rxbuf_min_shift = ((val / E1000_RCTL_RDMTS_QUAT) & 3) + 1;
215 DBGOUT(RX, "RCTL: %d, mac_reg[RCTL] = 0x%x\n", s->mac_reg[RDT],
216 s->mac_reg[RCTL]);
217 }
218
219 static void
220 set_mdic(E1000State *s, int index, uint32_t val)
221 {
222 uint32_t data = val & E1000_MDIC_DATA_MASK;
223 uint32_t addr = ((val & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT);
224
225 if ((val & E1000_MDIC_PHY_MASK) >> E1000_MDIC_PHY_SHIFT != 1) // phy #
226 val = s->mac_reg[MDIC] | E1000_MDIC_ERROR;
227 else if (val & E1000_MDIC_OP_READ) {
228 DBGOUT(MDIC, "MDIC read reg 0x%x\n", addr);
229 if (!(phy_regcap[addr] & PHY_R)) {
230 DBGOUT(MDIC, "MDIC read reg %x unhandled\n", addr);
231 val |= E1000_MDIC_ERROR;
232 } else
233 val = (val ^ data) | s->phy_reg[addr];
234 } else if (val & E1000_MDIC_OP_WRITE) {
235 DBGOUT(MDIC, "MDIC write reg 0x%x, value 0x%x\n", addr, data);
236 if (!(phy_regcap[addr] & PHY_W)) {
237 DBGOUT(MDIC, "MDIC write reg %x unhandled\n", addr);
238 val |= E1000_MDIC_ERROR;
239 } else
240 s->phy_reg[addr] = data;
241 }
242 s->mac_reg[MDIC] = val | E1000_MDIC_READY;
243 set_ics(s, 0, E1000_ICR_MDAC);
244 }
245
246 static uint32_t
247 get_eecd(E1000State *s, int index)
248 {
249 uint32_t ret = E1000_EECD_PRES|E1000_EECD_GNT | s->eecd_state.old_eecd;
250
251 DBGOUT(EEPROM, "reading eeprom bit %d (reading %d)\n",
252 s->eecd_state.bitnum_out, s->eecd_state.reading);
253 if (!s->eecd_state.reading ||
254 ((s->eeprom_data[(s->eecd_state.bitnum_out >> 4) & 0x3f] >>
255 ((s->eecd_state.bitnum_out & 0xf) ^ 0xf))) & 1)
256 ret |= E1000_EECD_DO;
257 return ret;
258 }
259
260 static void
261 set_eecd(E1000State *s, int index, uint32_t val)
262 {
263 uint32_t oldval = s->eecd_state.old_eecd;
264
265 s->eecd_state.old_eecd = val & (E1000_EECD_SK | E1000_EECD_CS |
266 E1000_EECD_DI|E1000_EECD_FWE_MASK|E1000_EECD_REQ);
267 if (!(E1000_EECD_CS & val)) // CS inactive; nothing to do
268 return;
269 if (E1000_EECD_CS & (val ^ oldval)) { // CS rise edge; reset state
270 s->eecd_state.val_in = 0;
271 s->eecd_state.bitnum_in = 0;
272 s->eecd_state.bitnum_out = 0;
273 s->eecd_state.reading = 0;
274 }
275 if (!(E1000_EECD_SK & (val ^ oldval))) // no clock edge
276 return;
277 if (!(E1000_EECD_SK & val)) { // falling edge
278 s->eecd_state.bitnum_out++;
279 return;
280 }
281 s->eecd_state.val_in <<= 1;
282 if (val & E1000_EECD_DI)
283 s->eecd_state.val_in |= 1;
284 if (++s->eecd_state.bitnum_in == 9 && !s->eecd_state.reading) {
285 s->eecd_state.bitnum_out = ((s->eecd_state.val_in & 0x3f)<<4)-1;
286 s->eecd_state.reading = (((s->eecd_state.val_in >> 6) & 7) ==
287 EEPROM_READ_OPCODE_MICROWIRE);
288 }
289 DBGOUT(EEPROM, "eeprom bitnum in %d out %d, reading %d\n",
290 s->eecd_state.bitnum_in, s->eecd_state.bitnum_out,
291 s->eecd_state.reading);
292 }
293
294 static uint32_t
295 flash_eerd_read(E1000State *s, int x)
296 {
297 unsigned int index, r = s->mac_reg[EERD] & ~E1000_EEPROM_RW_REG_START;
298
299 if ((s->mac_reg[EERD] & E1000_EEPROM_RW_REG_START) == 0)
300 return (s->mac_reg[EERD]);
301
302 if ((index = r >> E1000_EEPROM_RW_ADDR_SHIFT) > EEPROM_CHECKSUM_REG)
303 return (E1000_EEPROM_RW_REG_DONE | r);
304
305 return ((s->eeprom_data[index] << E1000_EEPROM_RW_REG_DATA) |
306 E1000_EEPROM_RW_REG_DONE | r);
307 }
308
309 static void
310 putsum(uint8_t *data, uint32_t n, uint32_t sloc, uint32_t css, uint32_t cse)
311 {
312 uint32_t sum;
313
314 if (cse && cse < n)
315 n = cse + 1;
316 if (sloc < n-1) {
317 sum = net_checksum_add(n-css, data+css);
318 cpu_to_be16wu((uint16_t *)(data + sloc),
319 net_checksum_finish(sum));
320 }
321 }
322
323 static inline int
324 vlan_enabled(E1000State *s)
325 {
326 return ((s->mac_reg[CTRL] & E1000_CTRL_VME) != 0);
327 }
328
329 static inline int
330 vlan_rx_filter_enabled(E1000State *s)
331 {
332 return ((s->mac_reg[RCTL] & E1000_RCTL_VFE) != 0);
333 }
334
335 static inline int
336 is_vlan_packet(E1000State *s, const uint8_t *buf)
337 {
338 return (be16_to_cpup((uint16_t *)(buf + 12)) ==
339 le16_to_cpup((uint16_t *)(s->mac_reg + VET)));
340 }
341
342 static inline int
343 is_vlan_txd(uint32_t txd_lower)
344 {
345 return ((txd_lower & E1000_TXD_CMD_VLE) != 0);
346 }
347
348 /* FCS aka Ethernet CRC-32. We don't get it from backends and can't
349 * fill it in, just pad descriptor length by 4 bytes unless guest
350 * told us to strip it off the packet. */
351 static inline int
352 fcs_len(E1000State *s)
353 {
354 return (s->mac_reg[RCTL] & E1000_RCTL_SECRC) ? 0 : 4;
355 }
356
357 static void
358 xmit_seg(E1000State *s)
359 {
360 uint16_t len, *sp;
361 unsigned int frames = s->tx.tso_frames, css, sofar, n;
362 struct e1000_tx *tp = &s->tx;
363
364 if (tp->tse && tp->cptse) {
365 css = tp->ipcss;
366 DBGOUT(TXSUM, "frames %d size %d ipcss %d\n",
367 frames, tp->size, css);
368 if (tp->ip) { // IPv4
369 cpu_to_be16wu((uint16_t *)(tp->data+css+2),
370 tp->size - css);
371 cpu_to_be16wu((uint16_t *)(tp->data+css+4),
372 be16_to_cpup((uint16_t *)(tp->data+css+4))+frames);
373 } else // IPv6
374 cpu_to_be16wu((uint16_t *)(tp->data+css+4),
375 tp->size - css);
376 css = tp->tucss;
377 len = tp->size - css;
378 DBGOUT(TXSUM, "tcp %d tucss %d len %d\n", tp->tcp, css, len);
379 if (tp->tcp) {
380 sofar = frames * tp->mss;
381 cpu_to_be32wu((uint32_t *)(tp->data+css+4), // seq
382 be32_to_cpupu((uint32_t *)(tp->data+css+4))+sofar);
383 if (tp->paylen - sofar > tp->mss)
384 tp->data[css + 13] &= ~9; // PSH, FIN
385 } else // UDP
386 cpu_to_be16wu((uint16_t *)(tp->data+css+4), len);
387 if (tp->sum_needed & E1000_TXD_POPTS_TXSM) {
388 unsigned int phsum;
389 // add pseudo-header length before checksum calculation
390 sp = (uint16_t *)(tp->data + tp->tucso);
391 phsum = be16_to_cpup(sp) + len;
392 phsum = (phsum >> 16) + (phsum & 0xffff);
393 cpu_to_be16wu(sp, phsum);
394 }
395 tp->tso_frames++;
396 }
397
398 if (tp->sum_needed & E1000_TXD_POPTS_TXSM)
399 putsum(tp->data, tp->size, tp->tucso, tp->tucss, tp->tucse);
400 if (tp->sum_needed & E1000_TXD_POPTS_IXSM)
401 putsum(tp->data, tp->size, tp->ipcso, tp->ipcss, tp->ipcse);
402 if (tp->vlan_needed) {
403 memmove(tp->vlan, tp->data, 4);
404 memmove(tp->data, tp->data + 4, 8);
405 memcpy(tp->data + 8, tp->vlan_header, 4);
406 qemu_send_packet(&s->nic->nc, tp->vlan, tp->size + 4);
407 } else
408 qemu_send_packet(&s->nic->nc, tp->data, tp->size);
409 s->mac_reg[TPT]++;
410 s->mac_reg[GPTC]++;
411 n = s->mac_reg[TOTL];
412 if ((s->mac_reg[TOTL] += s->tx.size) < n)
413 s->mac_reg[TOTH]++;
414 }
415
416 static void
417 process_tx_desc(E1000State *s, struct e1000_tx_desc *dp)
418 {
419 uint32_t txd_lower = le32_to_cpu(dp->lower.data);
420 uint32_t dtype = txd_lower & (E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D);
421 unsigned int split_size = txd_lower & 0xffff, bytes, sz, op;
422 unsigned int msh = 0xfffff, hdr = 0;
423 uint64_t addr;
424 struct e1000_context_desc *xp = (struct e1000_context_desc *)dp;
425 struct e1000_tx *tp = &s->tx;
426
427 if (dtype == E1000_TXD_CMD_DEXT) { // context descriptor
428 op = le32_to_cpu(xp->cmd_and_length);
429 tp->ipcss = xp->lower_setup.ip_fields.ipcss;
430 tp->ipcso = xp->lower_setup.ip_fields.ipcso;
431 tp->ipcse = le16_to_cpu(xp->lower_setup.ip_fields.ipcse);
432 tp->tucss = xp->upper_setup.tcp_fields.tucss;
433 tp->tucso = xp->upper_setup.tcp_fields.tucso;
434 tp->tucse = le16_to_cpu(xp->upper_setup.tcp_fields.tucse);
435 tp->paylen = op & 0xfffff;
436 tp->hdr_len = xp->tcp_seg_setup.fields.hdr_len;
437 tp->mss = le16_to_cpu(xp->tcp_seg_setup.fields.mss);
438 tp->ip = (op & E1000_TXD_CMD_IP) ? 1 : 0;
439 tp->tcp = (op & E1000_TXD_CMD_TCP) ? 1 : 0;
440 tp->tse = (op & E1000_TXD_CMD_TSE) ? 1 : 0;
441 tp->tso_frames = 0;
442 if (tp->tucso == 0) { // this is probably wrong
443 DBGOUT(TXSUM, "TCP/UDP: cso 0!\n");
444 tp->tucso = tp->tucss + (tp->tcp ? 16 : 6);
445 }
446 return;
447 } else if (dtype == (E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D)) {
448 // data descriptor
449 tp->sum_needed = le32_to_cpu(dp->upper.data) >> 8;
450 tp->cptse = ( txd_lower & E1000_TXD_CMD_TSE ) ? 1 : 0;
451 } else {
452 // legacy descriptor
453 tp->cptse = 0;
454 }
455
456 if (vlan_enabled(s) && is_vlan_txd(txd_lower) &&
457 (tp->cptse || txd_lower & E1000_TXD_CMD_EOP)) {
458 tp->vlan_needed = 1;
459 cpu_to_be16wu((uint16_t *)(tp->vlan_header),
460 le16_to_cpup((uint16_t *)(s->mac_reg + VET)));
461 cpu_to_be16wu((uint16_t *)(tp->vlan_header + 2),
462 le16_to_cpu(dp->upper.fields.special));
463 }
464
465 addr = le64_to_cpu(dp->buffer_addr);
466 if (tp->tse && tp->cptse) {
467 hdr = tp->hdr_len;
468 msh = hdr + tp->mss;
469 do {
470 bytes = split_size;
471 if (tp->size + bytes > msh)
472 bytes = msh - tp->size;
473 cpu_physical_memory_read(addr, tp->data + tp->size, bytes);
474 if ((sz = tp->size + bytes) >= hdr && tp->size < hdr)
475 memmove(tp->header, tp->data, hdr);
476 tp->size = sz;
477 addr += bytes;
478 if (sz == msh) {
479 xmit_seg(s);
480 memmove(tp->data, tp->header, hdr);
481 tp->size = hdr;
482 }
483 } while (split_size -= bytes);
484 } else if (!tp->tse && tp->cptse) {
485 // context descriptor TSE is not set, while data descriptor TSE is set
486 DBGOUT(TXERR, "TCP segmentaion Error\n");
487 } else {
488 cpu_physical_memory_read(addr, tp->data + tp->size, split_size);
489 tp->size += split_size;
490 }
491
492 if (!(txd_lower & E1000_TXD_CMD_EOP))
493 return;
494 if (!(tp->tse && tp->cptse && tp->size < hdr))
495 xmit_seg(s);
496 tp->tso_frames = 0;
497 tp->sum_needed = 0;
498 tp->vlan_needed = 0;
499 tp->size = 0;
500 tp->cptse = 0;
501 }
502
503 static uint32_t
504 txdesc_writeback(target_phys_addr_t base, struct e1000_tx_desc *dp)
505 {
506 uint32_t txd_upper, txd_lower = le32_to_cpu(dp->lower.data);
507
508 if (!(txd_lower & (E1000_TXD_CMD_RS|E1000_TXD_CMD_RPS)))
509 return 0;
510 txd_upper = (le32_to_cpu(dp->upper.data) | E1000_TXD_STAT_DD) &
511 ~(E1000_TXD_STAT_EC | E1000_TXD_STAT_LC | E1000_TXD_STAT_TU);
512 dp->upper.data = cpu_to_le32(txd_upper);
513 cpu_physical_memory_write(base + ((char *)&dp->upper - (char *)dp),
514 (void *)&dp->upper, sizeof(dp->upper));
515 return E1000_ICR_TXDW;
516 }
517
518 static void
519 start_xmit(E1000State *s)
520 {
521 target_phys_addr_t base;
522 struct e1000_tx_desc desc;
523 uint32_t tdh_start = s->mac_reg[TDH], cause = E1000_ICS_TXQE;
524
525 if (!(s->mac_reg[TCTL] & E1000_TCTL_EN)) {
526 DBGOUT(TX, "tx disabled\n");
527 return;
528 }
529
530 while (s->mac_reg[TDH] != s->mac_reg[TDT]) {
531 base = ((uint64_t)s->mac_reg[TDBAH] << 32) + s->mac_reg[TDBAL] +
532 sizeof(struct e1000_tx_desc) * s->mac_reg[TDH];
533 cpu_physical_memory_read(base, (void *)&desc, sizeof(desc));
534
535 DBGOUT(TX, "index %d: %p : %x %x\n", s->mac_reg[TDH],
536 (void *)(intptr_t)desc.buffer_addr, desc.lower.data,
537 desc.upper.data);
538
539 process_tx_desc(s, &desc);
540 cause |= txdesc_writeback(base, &desc);
541
542 if (++s->mac_reg[TDH] * sizeof(desc) >= s->mac_reg[TDLEN])
543 s->mac_reg[TDH] = 0;
544 /*
545 * the following could happen only if guest sw assigns
546 * bogus values to TDT/TDLEN.
547 * there's nothing too intelligent we could do about this.
548 */
549 if (s->mac_reg[TDH] == tdh_start) {
550 DBGOUT(TXERR, "TDH wraparound @%x, TDT %x, TDLEN %x\n",
551 tdh_start, s->mac_reg[TDT], s->mac_reg[TDLEN]);
552 break;
553 }
554 }
555 set_ics(s, 0, cause);
556 }
557
558 static int
559 receive_filter(E1000State *s, const uint8_t *buf, int size)
560 {
561 static const uint8_t bcast[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
562 static const int mta_shift[] = {4, 3, 2, 0};
563 uint32_t f, rctl = s->mac_reg[RCTL], ra[2], *rp;
564
565 if (is_vlan_packet(s, buf) && vlan_rx_filter_enabled(s)) {
566 uint16_t vid = be16_to_cpup((uint16_t *)(buf + 14));
567 uint32_t vfta = le32_to_cpup((uint32_t *)(s->mac_reg + VFTA) +
568 ((vid >> 5) & 0x7f));
569 if ((vfta & (1 << (vid & 0x1f))) == 0)
570 return 0;
571 }
572
573 if (rctl & E1000_RCTL_UPE) // promiscuous
574 return 1;
575
576 if ((buf[0] & 1) && (rctl & E1000_RCTL_MPE)) // promiscuous mcast
577 return 1;
578
579 if ((rctl & E1000_RCTL_BAM) && !memcmp(buf, bcast, sizeof bcast))
580 return 1;
581
582 for (rp = s->mac_reg + RA; rp < s->mac_reg + RA + 32; rp += 2) {
583 if (!(rp[1] & E1000_RAH_AV))
584 continue;
585 ra[0] = cpu_to_le32(rp[0]);
586 ra[1] = cpu_to_le32(rp[1]);
587 if (!memcmp(buf, (uint8_t *)ra, 6)) {
588 DBGOUT(RXFILTER,
589 "unicast match[%d]: %02x:%02x:%02x:%02x:%02x:%02x\n",
590 (int)(rp - s->mac_reg - RA)/2,
591 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5]);
592 return 1;
593 }
594 }
595 DBGOUT(RXFILTER, "unicast mismatch: %02x:%02x:%02x:%02x:%02x:%02x\n",
596 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5]);
597
598 f = mta_shift[(rctl >> E1000_RCTL_MO_SHIFT) & 3];
599 f = (((buf[5] << 8) | buf[4]) >> f) & 0xfff;
600 if (s->mac_reg[MTA + (f >> 5)] & (1 << (f & 0x1f)))
601 return 1;
602 DBGOUT(RXFILTER,
603 "dropping, inexact filter mismatch: %02x:%02x:%02x:%02x:%02x:%02x MO %d MTA[%d] %x\n",
604 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5],
605 (rctl >> E1000_RCTL_MO_SHIFT) & 3, f >> 5,
606 s->mac_reg[MTA + (f >> 5)]);
607
608 return 0;
609 }
610
611 static void
612 e1000_set_link_status(VLANClientState *nc)
613 {
614 E1000State *s = DO_UPCAST(NICState, nc, nc)->opaque;
615 uint32_t old_status = s->mac_reg[STATUS];
616
617 if (nc->link_down)
618 s->mac_reg[STATUS] &= ~E1000_STATUS_LU;
619 else
620 s->mac_reg[STATUS] |= E1000_STATUS_LU;
621
622 if (s->mac_reg[STATUS] != old_status)
623 set_ics(s, 0, E1000_ICR_LSC);
624 }
625
626 static int
627 e1000_can_receive(VLANClientState *nc)
628 {
629 E1000State *s = DO_UPCAST(NICState, nc, nc)->opaque;
630
631 return (s->mac_reg[RCTL] & E1000_RCTL_EN);
632 }
633
634 static bool e1000_has_rxbufs(E1000State *s, size_t total_size)
635 {
636 int bufs;
637 /* Fast-path short packets */
638 if (total_size <= s->rxbuf_size) {
639 return s->mac_reg[RDH] != s->mac_reg[RDT] || !s->check_rxov;
640 }
641 if (s->mac_reg[RDH] < s->mac_reg[RDT]) {
642 bufs = s->mac_reg[RDT] - s->mac_reg[RDH];
643 } else if (s->mac_reg[RDH] > s->mac_reg[RDT] || !s->check_rxov) {
644 bufs = s->mac_reg[RDLEN] / sizeof(struct e1000_rx_desc) +
645 s->mac_reg[RDT] - s->mac_reg[RDH];
646 } else {
647 return false;
648 }
649 return total_size <= bufs * s->rxbuf_size;
650 }
651
652 static ssize_t
653 e1000_receive(VLANClientState *nc, const uint8_t *buf, size_t size)
654 {
655 E1000State *s = DO_UPCAST(NICState, nc, nc)->opaque;
656 struct e1000_rx_desc desc;
657 target_phys_addr_t base;
658 unsigned int n, rdt;
659 uint32_t rdh_start;
660 uint16_t vlan_special = 0;
661 uint8_t vlan_status = 0, vlan_offset = 0;
662 uint8_t min_buf[MIN_BUF_SIZE];
663 size_t desc_offset;
664 size_t desc_size;
665 size_t total_size;
666
667 if (!(s->mac_reg[RCTL] & E1000_RCTL_EN))
668 return -1;
669
670 /* Pad to minimum Ethernet frame length */
671 if (size < sizeof(min_buf)) {
672 memcpy(min_buf, buf, size);
673 memset(&min_buf[size], 0, sizeof(min_buf) - size);
674 buf = min_buf;
675 size = sizeof(min_buf);
676 }
677
678 if (!receive_filter(s, buf, size))
679 return size;
680
681 if (vlan_enabled(s) && is_vlan_packet(s, buf)) {
682 vlan_special = cpu_to_le16(be16_to_cpup((uint16_t *)(buf + 14)));
683 memmove((uint8_t *)buf + 4, buf, 12);
684 vlan_status = E1000_RXD_STAT_VP;
685 vlan_offset = 4;
686 size -= 4;
687 }
688
689 rdh_start = s->mac_reg[RDH];
690 desc_offset = 0;
691 total_size = size + fcs_len(s);
692 if (!e1000_has_rxbufs(s, total_size)) {
693 set_ics(s, 0, E1000_ICS_RXO);
694 return -1;
695 }
696 do {
697 desc_size = total_size - desc_offset;
698 if (desc_size > s->rxbuf_size) {
699 desc_size = s->rxbuf_size;
700 }
701 base = ((uint64_t)s->mac_reg[RDBAH] << 32) + s->mac_reg[RDBAL] +
702 sizeof(desc) * s->mac_reg[RDH];
703 cpu_physical_memory_read(base, (void *)&desc, sizeof(desc));
704 desc.special = vlan_special;
705 desc.status |= (vlan_status | E1000_RXD_STAT_DD);
706 if (desc.buffer_addr) {
707 if (desc_offset < size) {
708 size_t copy_size = size - desc_offset;
709 if (copy_size > s->rxbuf_size) {
710 copy_size = s->rxbuf_size;
711 }
712 cpu_physical_memory_write(le64_to_cpu(desc.buffer_addr),
713 (void *)(buf + desc_offset + vlan_offset),
714 copy_size);
715 }
716 desc_offset += desc_size;
717 desc.length = cpu_to_le16(desc_size);
718 if (desc_offset >= total_size) {
719 desc.status |= E1000_RXD_STAT_EOP | E1000_RXD_STAT_IXSM;
720 } else {
721 /* Guest zeroing out status is not a hardware requirement.
722 Clear EOP in case guest didn't do it. */
723 desc.status &= ~E1000_RXD_STAT_EOP;
724 }
725 } else { // as per intel docs; skip descriptors with null buf addr
726 DBGOUT(RX, "Null RX descriptor!!\n");
727 }
728 cpu_physical_memory_write(base, (void *)&desc, sizeof(desc));
729
730 if (++s->mac_reg[RDH] * sizeof(desc) >= s->mac_reg[RDLEN])
731 s->mac_reg[RDH] = 0;
732 s->check_rxov = 1;
733 /* see comment in start_xmit; same here */
734 if (s->mac_reg[RDH] == rdh_start) {
735 DBGOUT(RXERR, "RDH wraparound @%x, RDT %x, RDLEN %x\n",
736 rdh_start, s->mac_reg[RDT], s->mac_reg[RDLEN]);
737 set_ics(s, 0, E1000_ICS_RXO);
738 return -1;
739 }
740 } while (desc_offset < total_size);
741
742 s->mac_reg[GPRC]++;
743 s->mac_reg[TPR]++;
744 /* TOR - Total Octets Received:
745 * This register includes bytes received in a packet from the <Destination
746 * Address> field through the <CRC> field, inclusively.
747 */
748 n = s->mac_reg[TORL] + size + /* Always include FCS length. */ 4;
749 if (n < s->mac_reg[TORL])
750 s->mac_reg[TORH]++;
751 s->mac_reg[TORL] = n;
752
753 n = E1000_ICS_RXT0;
754 if ((rdt = s->mac_reg[RDT]) < s->mac_reg[RDH])
755 rdt += s->mac_reg[RDLEN] / sizeof(desc);
756 if (((rdt - s->mac_reg[RDH]) * sizeof(desc)) <= s->mac_reg[RDLEN] >>
757 s->rxbuf_min_shift)
758 n |= E1000_ICS_RXDMT0;
759
760 set_ics(s, 0, n);
761
762 return size;
763 }
764
765 static uint32_t
766 mac_readreg(E1000State *s, int index)
767 {
768 return s->mac_reg[index];
769 }
770
771 static uint32_t
772 mac_icr_read(E1000State *s, int index)
773 {
774 uint32_t ret = s->mac_reg[ICR];
775
776 DBGOUT(INTERRUPT, "ICR read: %x\n", ret);
777 set_interrupt_cause(s, 0, 0);
778 return ret;
779 }
780
781 static uint32_t
782 mac_read_clr4(E1000State *s, int index)
783 {
784 uint32_t ret = s->mac_reg[index];
785
786 s->mac_reg[index] = 0;
787 return ret;
788 }
789
790 static uint32_t
791 mac_read_clr8(E1000State *s, int index)
792 {
793 uint32_t ret = s->mac_reg[index];
794
795 s->mac_reg[index] = 0;
796 s->mac_reg[index-1] = 0;
797 return ret;
798 }
799
800 static void
801 mac_writereg(E1000State *s, int index, uint32_t val)
802 {
803 s->mac_reg[index] = val;
804 }
805
806 static void
807 set_rdt(E1000State *s, int index, uint32_t val)
808 {
809 s->check_rxov = 0;
810 s->mac_reg[index] = val & 0xffff;
811 }
812
813 static void
814 set_16bit(E1000State *s, int index, uint32_t val)
815 {
816 s->mac_reg[index] = val & 0xffff;
817 }
818
819 static void
820 set_dlen(E1000State *s, int index, uint32_t val)
821 {
822 s->mac_reg[index] = val & 0xfff80;
823 }
824
825 static void
826 set_tctl(E1000State *s, int index, uint32_t val)
827 {
828 s->mac_reg[index] = val;
829 s->mac_reg[TDT] &= 0xffff;
830 start_xmit(s);
831 }
832
833 static void
834 set_icr(E1000State *s, int index, uint32_t val)
835 {
836 DBGOUT(INTERRUPT, "set_icr %x\n", val);
837 set_interrupt_cause(s, 0, s->mac_reg[ICR] & ~val);
838 }
839
840 static void
841 set_imc(E1000State *s, int index, uint32_t val)
842 {
843 s->mac_reg[IMS] &= ~val;
844 set_ics(s, 0, 0);
845 }
846
847 static void
848 set_ims(E1000State *s, int index, uint32_t val)
849 {
850 s->mac_reg[IMS] |= val;
851 set_ics(s, 0, 0);
852 }
853
854 #define getreg(x) [x] = mac_readreg
855 static uint32_t (*macreg_readops[])(E1000State *, int) = {
856 getreg(PBA), getreg(RCTL), getreg(TDH), getreg(TXDCTL),
857 getreg(WUFC), getreg(TDT), getreg(CTRL), getreg(LEDCTL),
858 getreg(MANC), getreg(MDIC), getreg(SWSM), getreg(STATUS),
859 getreg(TORL), getreg(TOTL), getreg(IMS), getreg(TCTL),
860 getreg(RDH), getreg(RDT), getreg(VET), getreg(ICS),
861 getreg(TDBAL), getreg(TDBAH), getreg(RDBAH), getreg(RDBAL),
862 getreg(TDLEN), getreg(RDLEN),
863
864 [TOTH] = mac_read_clr8, [TORH] = mac_read_clr8, [GPRC] = mac_read_clr4,
865 [GPTC] = mac_read_clr4, [TPR] = mac_read_clr4, [TPT] = mac_read_clr4,
866 [ICR] = mac_icr_read, [EECD] = get_eecd, [EERD] = flash_eerd_read,
867 [CRCERRS ... MPC] = &mac_readreg,
868 [RA ... RA+31] = &mac_readreg,
869 [MTA ... MTA+127] = &mac_readreg,
870 [VFTA ... VFTA+127] = &mac_readreg,
871 };
872 enum { NREADOPS = ARRAY_SIZE(macreg_readops) };
873
874 #define putreg(x) [x] = mac_writereg
875 static void (*macreg_writeops[])(E1000State *, int, uint32_t) = {
876 putreg(PBA), putreg(EERD), putreg(SWSM), putreg(WUFC),
877 putreg(TDBAL), putreg(TDBAH), putreg(TXDCTL), putreg(RDBAH),
878 putreg(RDBAL), putreg(LEDCTL), putreg(VET),
879 [TDLEN] = set_dlen, [RDLEN] = set_dlen, [TCTL] = set_tctl,
880 [TDT] = set_tctl, [MDIC] = set_mdic, [ICS] = set_ics,
881 [TDH] = set_16bit, [RDH] = set_16bit, [RDT] = set_rdt,
882 [IMC] = set_imc, [IMS] = set_ims, [ICR] = set_icr,
883 [EECD] = set_eecd, [RCTL] = set_rx_control, [CTRL] = set_ctrl,
884 [RA ... RA+31] = &mac_writereg,
885 [MTA ... MTA+127] = &mac_writereg,
886 [VFTA ... VFTA+127] = &mac_writereg,
887 };
888 enum { NWRITEOPS = ARRAY_SIZE(macreg_writeops) };
889
890 static void
891 e1000_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
892 {
893 E1000State *s = opaque;
894 unsigned int index = (addr & 0x1ffff) >> 2;
895
896 if (index < NWRITEOPS && macreg_writeops[index]) {
897 macreg_writeops[index](s, index, val);
898 } else if (index < NREADOPS && macreg_readops[index]) {
899 DBGOUT(MMIO, "e1000_mmio_writel RO %x: 0x%04x\n", index<<2, val);
900 } else {
901 DBGOUT(UNKNOWN, "MMIO unknown write addr=0x%08x,val=0x%08x\n",
902 index<<2, val);
903 }
904 }
905
906 static void
907 e1000_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
908 {
909 // emulate hw without byte enables: no RMW
910 e1000_mmio_writel(opaque, addr & ~3,
911 (val & 0xffff) << (8*(addr & 3)));
912 }
913
914 static void
915 e1000_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
916 {
917 // emulate hw without byte enables: no RMW
918 e1000_mmio_writel(opaque, addr & ~3,
919 (val & 0xff) << (8*(addr & 3)));
920 }
921
922 static uint32_t
923 e1000_mmio_readl(void *opaque, target_phys_addr_t addr)
924 {
925 E1000State *s = opaque;
926 unsigned int index = (addr & 0x1ffff) >> 2;
927
928 if (index < NREADOPS && macreg_readops[index])
929 {
930 return macreg_readops[index](s, index);
931 }
932 DBGOUT(UNKNOWN, "MMIO unknown read addr=0x%08x\n", index<<2);
933 return 0;
934 }
935
936 static uint32_t
937 e1000_mmio_readb(void *opaque, target_phys_addr_t addr)
938 {
939 return ((e1000_mmio_readl(opaque, addr & ~3)) >>
940 (8 * (addr & 3))) & 0xff;
941 }
942
943 static uint32_t
944 e1000_mmio_readw(void *opaque, target_phys_addr_t addr)
945 {
946 return ((e1000_mmio_readl(opaque, addr & ~3)) >>
947 (8 * (addr & 3))) & 0xffff;
948 }
949
950 static bool is_version_1(void *opaque, int version_id)
951 {
952 return version_id == 1;
953 }
954
955 static const VMStateDescription vmstate_e1000 = {
956 .name = "e1000",
957 .version_id = 2,
958 .minimum_version_id = 1,
959 .minimum_version_id_old = 1,
960 .fields = (VMStateField []) {
961 VMSTATE_PCI_DEVICE(dev, E1000State),
962 VMSTATE_UNUSED_TEST(is_version_1, 4), /* was instance id */
963 VMSTATE_UNUSED(4), /* Was mmio_base. */
964 VMSTATE_UINT32(rxbuf_size, E1000State),
965 VMSTATE_UINT32(rxbuf_min_shift, E1000State),
966 VMSTATE_UINT32(eecd_state.val_in, E1000State),
967 VMSTATE_UINT16(eecd_state.bitnum_in, E1000State),
968 VMSTATE_UINT16(eecd_state.bitnum_out, E1000State),
969 VMSTATE_UINT16(eecd_state.reading, E1000State),
970 VMSTATE_UINT32(eecd_state.old_eecd, E1000State),
971 VMSTATE_UINT8(tx.ipcss, E1000State),
972 VMSTATE_UINT8(tx.ipcso, E1000State),
973 VMSTATE_UINT16(tx.ipcse, E1000State),
974 VMSTATE_UINT8(tx.tucss, E1000State),
975 VMSTATE_UINT8(tx.tucso, E1000State),
976 VMSTATE_UINT16(tx.tucse, E1000State),
977 VMSTATE_UINT32(tx.paylen, E1000State),
978 VMSTATE_UINT8(tx.hdr_len, E1000State),
979 VMSTATE_UINT16(tx.mss, E1000State),
980 VMSTATE_UINT16(tx.size, E1000State),
981 VMSTATE_UINT16(tx.tso_frames, E1000State),
982 VMSTATE_UINT8(tx.sum_needed, E1000State),
983 VMSTATE_INT8(tx.ip, E1000State),
984 VMSTATE_INT8(tx.tcp, E1000State),
985 VMSTATE_BUFFER(tx.header, E1000State),
986 VMSTATE_BUFFER(tx.data, E1000State),
987 VMSTATE_UINT16_ARRAY(eeprom_data, E1000State, 64),
988 VMSTATE_UINT16_ARRAY(phy_reg, E1000State, 0x20),
989 VMSTATE_UINT32(mac_reg[CTRL], E1000State),
990 VMSTATE_UINT32(mac_reg[EECD], E1000State),
991 VMSTATE_UINT32(mac_reg[EERD], E1000State),
992 VMSTATE_UINT32(mac_reg[GPRC], E1000State),
993 VMSTATE_UINT32(mac_reg[GPTC], E1000State),
994 VMSTATE_UINT32(mac_reg[ICR], E1000State),
995 VMSTATE_UINT32(mac_reg[ICS], E1000State),
996 VMSTATE_UINT32(mac_reg[IMC], E1000State),
997 VMSTATE_UINT32(mac_reg[IMS], E1000State),
998 VMSTATE_UINT32(mac_reg[LEDCTL], E1000State),
999 VMSTATE_UINT32(mac_reg[MANC], E1000State),
1000 VMSTATE_UINT32(mac_reg[MDIC], E1000State),
1001 VMSTATE_UINT32(mac_reg[MPC], E1000State),
1002 VMSTATE_UINT32(mac_reg[PBA], E1000State),
1003 VMSTATE_UINT32(mac_reg[RCTL], E1000State),
1004 VMSTATE_UINT32(mac_reg[RDBAH], E1000State),
1005 VMSTATE_UINT32(mac_reg[RDBAL], E1000State),
1006 VMSTATE_UINT32(mac_reg[RDH], E1000State),
1007 VMSTATE_UINT32(mac_reg[RDLEN], E1000State),
1008 VMSTATE_UINT32(mac_reg[RDT], E1000State),
1009 VMSTATE_UINT32(mac_reg[STATUS], E1000State),
1010 VMSTATE_UINT32(mac_reg[SWSM], E1000State),
1011 VMSTATE_UINT32(mac_reg[TCTL], E1000State),
1012 VMSTATE_UINT32(mac_reg[TDBAH], E1000State),
1013 VMSTATE_UINT32(mac_reg[TDBAL], E1000State),
1014 VMSTATE_UINT32(mac_reg[TDH], E1000State),
1015 VMSTATE_UINT32(mac_reg[TDLEN], E1000State),
1016 VMSTATE_UINT32(mac_reg[TDT], E1000State),
1017 VMSTATE_UINT32(mac_reg[TORH], E1000State),
1018 VMSTATE_UINT32(mac_reg[TORL], E1000State),
1019 VMSTATE_UINT32(mac_reg[TOTH], E1000State),
1020 VMSTATE_UINT32(mac_reg[TOTL], E1000State),
1021 VMSTATE_UINT32(mac_reg[TPR], E1000State),
1022 VMSTATE_UINT32(mac_reg[TPT], E1000State),
1023 VMSTATE_UINT32(mac_reg[TXDCTL], E1000State),
1024 VMSTATE_UINT32(mac_reg[WUFC], E1000State),
1025 VMSTATE_UINT32(mac_reg[VET], E1000State),
1026 VMSTATE_UINT32_SUB_ARRAY(mac_reg, E1000State, RA, 32),
1027 VMSTATE_UINT32_SUB_ARRAY(mac_reg, E1000State, MTA, 128),
1028 VMSTATE_UINT32_SUB_ARRAY(mac_reg, E1000State, VFTA, 128),
1029 VMSTATE_END_OF_LIST()
1030 }
1031 };
1032
1033 static const uint16_t e1000_eeprom_template[64] = {
1034 0x0000, 0x0000, 0x0000, 0x0000, 0xffff, 0x0000, 0x0000, 0x0000,
1035 0x3000, 0x1000, 0x6403, E1000_DEVID, 0x8086, E1000_DEVID, 0x8086, 0x3040,
1036 0x0008, 0x2000, 0x7e14, 0x0048, 0x1000, 0x00d8, 0x0000, 0x2700,
1037 0x6cc9, 0x3150, 0x0722, 0x040b, 0x0984, 0x0000, 0xc000, 0x0706,
1038 0x1008, 0x0000, 0x0f04, 0x7fff, 0x4d01, 0xffff, 0xffff, 0xffff,
1039 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
1040 0x0100, 0x4000, 0x121c, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
1041 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0x0000,
1042 };
1043
1044 static const uint16_t phy_reg_init[] = {
1045 [PHY_CTRL] = 0x1140, [PHY_STATUS] = 0x796d, // link initially up
1046 [PHY_ID1] = 0x141, [PHY_ID2] = PHY_ID2_INIT,
1047 [PHY_1000T_CTRL] = 0x0e00, [M88E1000_PHY_SPEC_CTRL] = 0x360,
1048 [M88E1000_EXT_PHY_SPEC_CTRL] = 0x0d60, [PHY_AUTONEG_ADV] = 0xde1,
1049 [PHY_LP_ABILITY] = 0x1e0, [PHY_1000T_STATUS] = 0x3c00,
1050 [M88E1000_PHY_SPEC_STATUS] = 0xac00,
1051 };
1052
1053 static const uint32_t mac_reg_init[] = {
1054 [PBA] = 0x00100030,
1055 [LEDCTL] = 0x602,
1056 [CTRL] = E1000_CTRL_SWDPIN2 | E1000_CTRL_SWDPIN0 |
1057 E1000_CTRL_SPD_1000 | E1000_CTRL_SLU,
1058 [STATUS] = 0x80000000 | E1000_STATUS_GIO_MASTER_ENABLE |
1059 E1000_STATUS_ASDV | E1000_STATUS_MTXCKOK |
1060 E1000_STATUS_SPEED_1000 | E1000_STATUS_FD |
1061 E1000_STATUS_LU,
1062 [MANC] = E1000_MANC_EN_MNG2HOST | E1000_MANC_RCV_TCO_EN |
1063 E1000_MANC_ARP_EN | E1000_MANC_0298_EN |
1064 E1000_MANC_RMCP_EN,
1065 };
1066
1067 /* PCI interface */
1068
1069 static CPUWriteMemoryFunc * const e1000_mmio_write[] = {
1070 e1000_mmio_writeb, e1000_mmio_writew, e1000_mmio_writel
1071 };
1072
1073 static CPUReadMemoryFunc * const e1000_mmio_read[] = {
1074 e1000_mmio_readb, e1000_mmio_readw, e1000_mmio_readl
1075 };
1076
1077 static void
1078 e1000_mmio_map(PCIDevice *pci_dev, int region_num,
1079 pcibus_t addr, pcibus_t size, int type)
1080 {
1081 E1000State *d = DO_UPCAST(E1000State, dev, pci_dev);
1082 int i;
1083 const uint32_t excluded_regs[] = {
1084 E1000_MDIC, E1000_ICR, E1000_ICS, E1000_IMS,
1085 E1000_IMC, E1000_TCTL, E1000_TDT, PNPMMIO_SIZE
1086 };
1087
1088
1089 DBGOUT(MMIO, "e1000_mmio_map addr=0x%08"FMT_PCIBUS" 0x%08"FMT_PCIBUS"\n",
1090 addr, size);
1091
1092 cpu_register_physical_memory(addr, PNPMMIO_SIZE, d->mmio_index);
1093 qemu_register_coalesced_mmio(addr, excluded_regs[0]);
1094
1095 for (i = 0; excluded_regs[i] != PNPMMIO_SIZE; i++)
1096 qemu_register_coalesced_mmio(addr + excluded_regs[i] + 4,
1097 excluded_regs[i + 1] -
1098 excluded_regs[i] - 4);
1099 }
1100
1101 static void
1102 e1000_cleanup(VLANClientState *nc)
1103 {
1104 E1000State *s = DO_UPCAST(NICState, nc, nc)->opaque;
1105
1106 s->nic = NULL;
1107 }
1108
1109 static int
1110 pci_e1000_uninit(PCIDevice *dev)
1111 {
1112 E1000State *d = DO_UPCAST(E1000State, dev, dev);
1113
1114 cpu_unregister_io_memory(d->mmio_index);
1115 qemu_del_vlan_client(&d->nic->nc);
1116 return 0;
1117 }
1118
1119 static void e1000_reset(void *opaque)
1120 {
1121 E1000State *d = opaque;
1122
1123 memset(d->phy_reg, 0, sizeof d->phy_reg);
1124 memmove(d->phy_reg, phy_reg_init, sizeof phy_reg_init);
1125 memset(d->mac_reg, 0, sizeof d->mac_reg);
1126 memmove(d->mac_reg, mac_reg_init, sizeof mac_reg_init);
1127 d->rxbuf_min_shift = 1;
1128 memset(&d->tx, 0, sizeof d->tx);
1129 }
1130
1131 static NetClientInfo net_e1000_info = {
1132 .type = NET_CLIENT_TYPE_NIC,
1133 .size = sizeof(NICState),
1134 .can_receive = e1000_can_receive,
1135 .receive = e1000_receive,
1136 .cleanup = e1000_cleanup,
1137 .link_status_changed = e1000_set_link_status,
1138 };
1139
1140 static int pci_e1000_init(PCIDevice *pci_dev)
1141 {
1142 E1000State *d = DO_UPCAST(E1000State, dev, pci_dev);
1143 uint8_t *pci_conf;
1144 uint16_t checksum = 0;
1145 int i;
1146 uint8_t *macaddr;
1147
1148 pci_conf = d->dev.config;
1149
1150 pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
1151 pci_config_set_device_id(pci_conf, E1000_DEVID);
1152 /* TODO: we have no capabilities, so why is this bit set? */
1153 pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_CAP_LIST);
1154 pci_conf[PCI_REVISION_ID] = 0x03;
1155 pci_config_set_class(pci_conf, PCI_CLASS_NETWORK_ETHERNET);
1156 /* TODO: RST# value should be 0, PCI spec 6.2.4 */
1157 pci_conf[PCI_CACHE_LINE_SIZE] = 0x10;
1158
1159 /* TODO: RST# value should be 0 if programmable, PCI spec 6.2.4 */
1160 pci_conf[PCI_INTERRUPT_PIN] = 1; // interrupt pin 0
1161
1162 d->mmio_index = cpu_register_io_memory(e1000_mmio_read,
1163 e1000_mmio_write, d, DEVICE_LITTLE_ENDIAN);
1164
1165 pci_register_bar(&d->dev, 0, PNPMMIO_SIZE,
1166 PCI_BASE_ADDRESS_SPACE_MEMORY, e1000_mmio_map);
1167
1168 pci_register_bar(&d->dev, 1, IOPORT_SIZE,
1169 PCI_BASE_ADDRESS_SPACE_IO, ioport_map);
1170
1171 memmove(d->eeprom_data, e1000_eeprom_template,
1172 sizeof e1000_eeprom_template);
1173 qemu_macaddr_default_if_unset(&d->conf.macaddr);
1174 macaddr = d->conf.macaddr.a;
1175 for (i = 0; i < 3; i++)
1176 d->eeprom_data[i] = (macaddr[2*i+1]<<8) | macaddr[2*i];
1177 for (i = 0; i < EEPROM_CHECKSUM_REG; i++)
1178 checksum += d->eeprom_data[i];
1179 checksum = (uint16_t) EEPROM_SUM - checksum;
1180 d->eeprom_data[EEPROM_CHECKSUM_REG] = checksum;
1181
1182 d->nic = qemu_new_nic(&net_e1000_info, &d->conf,
1183 d->dev.qdev.info->name, d->dev.qdev.id, d);
1184
1185 qemu_format_nic_info_str(&d->nic->nc, macaddr);
1186
1187 add_boot_device_path(d->conf.bootindex, &pci_dev->qdev, "/ethernet-phy@0");
1188
1189 return 0;
1190 }
1191
1192 static void qdev_e1000_reset(DeviceState *dev)
1193 {
1194 E1000State *d = DO_UPCAST(E1000State, dev.qdev, dev);
1195 e1000_reset(d);
1196 }
1197
1198 static PCIDeviceInfo e1000_info = {
1199 .qdev.name = "e1000",
1200 .qdev.desc = "Intel Gigabit Ethernet",
1201 .qdev.size = sizeof(E1000State),
1202 .qdev.reset = qdev_e1000_reset,
1203 .qdev.vmsd = &vmstate_e1000,
1204 .init = pci_e1000_init,
1205 .exit = pci_e1000_uninit,
1206 .romfile = "pxe-e1000.bin",
1207 .qdev.props = (Property[]) {
1208 DEFINE_NIC_PROPERTIES(E1000State, conf),
1209 DEFINE_PROP_END_OF_LIST(),
1210 }
1211 };
1212
1213 static void e1000_register_devices(void)
1214 {
1215 pci_qdev_register(&e1000_info);
1216 }
1217
1218 device_init(e1000_register_devices)
QEmu