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target-arm: Don't mention PMU in debug feature register
[qemu.git] / tcg / ppc64 / tcg-target.c
blob06e440f9bc6b85f4574344f86060e709f969f9a0
1 /*
2 * Tiny Code Generator for QEMU
3 *
4 * Copyright (c) 2008 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25 #include "tcg-be-ldst.h"
26
27 #define TCG_CT_CONST_S16 0x100
28 #define TCG_CT_CONST_U16 0x200
29 #define TCG_CT_CONST_S32 0x400
30 #define TCG_CT_CONST_U32 0x800
31 #define TCG_CT_CONST_ZERO 0x1000
32 #define TCG_CT_CONST_MONE 0x2000
33
34 static uint8_t *tb_ret_addr;
35
36 #if TARGET_LONG_BITS == 32
37 #define LD_ADDR LWZ
38 #define CMP_L 0
39 #else
40 #define LD_ADDR LD
41 #define CMP_L (1<<21)
42 #endif
43
44 #ifndef GUEST_BASE
45 #define GUEST_BASE 0
46 #endif
47
48 #include "elf.h"
49 static bool have_isa_2_06;
50 #define HAVE_ISA_2_06 have_isa_2_06
51 #define HAVE_ISEL have_isa_2_06
52
53 #ifdef CONFIG_USE_GUEST_BASE
54 #define TCG_GUEST_BASE_REG 30
55 #else
56 #define TCG_GUEST_BASE_REG 0
57 #endif
58
59 #ifndef NDEBUG
60 static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
61 "r0",
62 "r1",
63 "r2",
64 "r3",
65 "r4",
66 "r5",
67 "r6",
68 "r7",
69 "r8",
70 "r9",
71 "r10",
72 "r11",
73 "r12",
74 "r13",
75 "r14",
76 "r15",
77 "r16",
78 "r17",
79 "r18",
80 "r19",
81 "r20",
82 "r21",
83 "r22",
84 "r23",
85 "r24",
86 "r25",
87 "r26",
88 "r27",
89 "r28",
90 "r29",
91 "r30",
92 "r31"
93 };
94 #endif
95
96 static const int tcg_target_reg_alloc_order[] = {
97 TCG_REG_R14, /* call saved registers */
98 TCG_REG_R15,
99 TCG_REG_R16,
100 TCG_REG_R17,
101 TCG_REG_R18,
102 TCG_REG_R19,
103 TCG_REG_R20,
104 TCG_REG_R21,
105 TCG_REG_R22,
106 TCG_REG_R23,
107 TCG_REG_R24,
108 TCG_REG_R25,
109 TCG_REG_R26,
110 TCG_REG_R27,
111 TCG_REG_R28,
112 TCG_REG_R29,
113 TCG_REG_R30,
114 TCG_REG_R31,
115 TCG_REG_R12, /* call clobbered, non-arguments */
116 TCG_REG_R11,
117 TCG_REG_R10, /* call clobbered, arguments */
118 TCG_REG_R9,
119 TCG_REG_R8,
120 TCG_REG_R7,
121 TCG_REG_R6,
122 TCG_REG_R5,
123 TCG_REG_R4,
124 TCG_REG_R3,
125 };
126
127 static const int tcg_target_call_iarg_regs[] = {
128 TCG_REG_R3,
129 TCG_REG_R4,
130 TCG_REG_R5,
131 TCG_REG_R6,
132 TCG_REG_R7,
133 TCG_REG_R8,
134 TCG_REG_R9,
135 TCG_REG_R10
136 };
137
138 static const int tcg_target_call_oarg_regs[] = {
139 TCG_REG_R3
140 };
141
142 static const int tcg_target_callee_save_regs[] = {
143 #ifdef __APPLE__
144 TCG_REG_R11,
145 #endif
146 TCG_REG_R14,
147 TCG_REG_R15,
148 TCG_REG_R16,
149 TCG_REG_R17,
150 TCG_REG_R18,
151 TCG_REG_R19,
152 TCG_REG_R20,
153 TCG_REG_R21,
154 TCG_REG_R22,
155 TCG_REG_R23,
156 TCG_REG_R24,
157 TCG_REG_R25,
158 TCG_REG_R26,
159 TCG_REG_R27, /* currently used for the global env */
160 TCG_REG_R28,
161 TCG_REG_R29,
162 TCG_REG_R30,
163 TCG_REG_R31
164 };
165
166 static inline bool in_range_b(tcg_target_long target)
167 {
168 return target == sextract64(target, 0, 26);
169 }
170
171 static uint32_t reloc_pc24_val(void *pc, tcg_target_long target)
172 {
173 tcg_target_long disp;
174
175 disp = target - (tcg_target_long)pc;
176 assert(in_range_b(disp));
177
178 return disp & 0x3fffffc;
179 }
180
181 static void reloc_pc24(void *pc, tcg_target_long target)
182 {
183 *(uint32_t *)pc = (*(uint32_t *)pc & ~0x3fffffc)
184 | reloc_pc24_val(pc, target);
185 }
186
187 static uint16_t reloc_pc14_val(void *pc, tcg_target_long target)
188 {
189 tcg_target_long disp;
190
191 disp = target - (tcg_target_long)pc;
192 if (disp != (int16_t) disp) {
193 tcg_abort();
194 }
195
196 return disp & 0xfffc;
197 }
198
199 static void reloc_pc14(void *pc, tcg_target_long target)
200 {
201 *(uint32_t *)pc = (*(uint32_t *)pc & ~0xfffc) | reloc_pc14_val(pc, target);
202 }
203
204 static inline void tcg_out_b_noaddr(TCGContext *s, int insn)
205 {
206 unsigned retrans = *(uint32_t *)s->code_ptr & 0x3fffffc;
207 tcg_out32(s, insn | retrans);
208 }
209
210 static inline void tcg_out_bc_noaddr(TCGContext *s, int insn)
211 {
212 unsigned retrans = *(uint32_t *)s->code_ptr & 0xfffc;
213 tcg_out32(s, insn | retrans);
214 }
215
216 static void patch_reloc(uint8_t *code_ptr, int type,
217 intptr_t value, intptr_t addend)
218 {
219 value += addend;
220 switch (type) {
221 case R_PPC_REL14:
222 reloc_pc14(code_ptr, value);
223 break;
224 case R_PPC_REL24:
225 reloc_pc24(code_ptr, value);
226 break;
227 default:
228 tcg_abort();
229 }
230 }
231
232 /* parse target specific constraints */
233 static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
234 {
235 const char *ct_str;
236
237 ct_str = *pct_str;
238 switch (ct_str[0]) {
239 case 'A': case 'B': case 'C': case 'D':
240 ct->ct |= TCG_CT_REG;
241 tcg_regset_set_reg(ct->u.regs, 3 + ct_str[0] - 'A');
242 break;
243 case 'r':
244 ct->ct |= TCG_CT_REG;
245 tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
246 break;
247 case 'L': /* qemu_ld constraint */
248 ct->ct |= TCG_CT_REG;
249 tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
250 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
251 #ifdef CONFIG_SOFTMMU
252 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4);
253 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R5);
254 #endif
255 break;
256 case 'S': /* qemu_st constraint */
257 ct->ct |= TCG_CT_REG;
258 tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
259 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
260 #ifdef CONFIG_SOFTMMU
261 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4);
262 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R5);
263 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R6);
264 #endif
265 break;
266 case 'I':
267 ct->ct |= TCG_CT_CONST_S16;
268 break;
269 case 'J':
270 ct->ct |= TCG_CT_CONST_U16;
271 break;
272 case 'M':
273 ct->ct |= TCG_CT_CONST_MONE;
274 break;
275 case 'T':
276 ct->ct |= TCG_CT_CONST_S32;
277 break;
278 case 'U':
279 ct->ct |= TCG_CT_CONST_U32;
280 break;
281 case 'Z':
282 ct->ct |= TCG_CT_CONST_ZERO;
283 break;
284 default:
285 return -1;
286 }
287 ct_str++;
288 *pct_str = ct_str;
289 return 0;
290 }
291
292 /* test if a constant matches the constraint */
293 static int tcg_target_const_match(tcg_target_long val,
294 const TCGArgConstraint *arg_ct)
295 {
296 int ct = arg_ct->ct;
297 if (ct & TCG_CT_CONST) {
298 return 1;
299 } else if ((ct & TCG_CT_CONST_S16) && val == (int16_t)val) {
300 return 1;
301 } else if ((ct & TCG_CT_CONST_U16) && val == (uint16_t)val) {
302 return 1;
303 } else if ((ct & TCG_CT_CONST_S32) && val == (int32_t)val) {
304 return 1;
305 } else if ((ct & TCG_CT_CONST_U32) && val == (uint32_t)val) {
306 return 1;
307 } else if ((ct & TCG_CT_CONST_ZERO) && val == 0) {
308 return 1;
309 } else if ((ct & TCG_CT_CONST_MONE) && val == -1) {
310 return 1;
311 }
312 return 0;
313 }
314
315 #define OPCD(opc) ((opc)<<26)
316 #define XO19(opc) (OPCD(19)|((opc)<<1))
317 #define MD30(opc) (OPCD(30)|((opc)<<2))
318 #define MDS30(opc) (OPCD(30)|((opc)<<1))
319 #define XO31(opc) (OPCD(31)|((opc)<<1))
320 #define XO58(opc) (OPCD(58)|(opc))
321 #define XO62(opc) (OPCD(62)|(opc))
322
323 #define B OPCD( 18)
324 #define BC OPCD( 16)
325 #define LBZ OPCD( 34)
326 #define LHZ OPCD( 40)
327 #define LHA OPCD( 42)
328 #define LWZ OPCD( 32)
329 #define STB OPCD( 38)
330 #define STH OPCD( 44)
331 #define STW OPCD( 36)
332
333 #define STD XO62( 0)
334 #define STDU XO62( 1)
335 #define STDX XO31(149)
336
337 #define LD XO58( 0)
338 #define LDX XO31( 21)
339 #define LDU XO58( 1)
340 #define LWA XO58( 2)
341 #define LWAX XO31(341)
342
343 #define ADDIC OPCD( 12)
344 #define ADDI OPCD( 14)
345 #define ADDIS OPCD( 15)
346 #define ORI OPCD( 24)
347 #define ORIS OPCD( 25)
348 #define XORI OPCD( 26)
349 #define XORIS OPCD( 27)
350 #define ANDI OPCD( 28)
351 #define ANDIS OPCD( 29)
352 #define MULLI OPCD( 7)
353 #define CMPLI OPCD( 10)
354 #define CMPI OPCD( 11)
355 #define SUBFIC OPCD( 8)
356
357 #define LWZU OPCD( 33)
358 #define STWU OPCD( 37)
359
360 #define RLWIMI OPCD( 20)
361 #define RLWINM OPCD( 21)
362 #define RLWNM OPCD( 23)
363
364 #define RLDICL MD30( 0)
365 #define RLDICR MD30( 1)
366 #define RLDIMI MD30( 3)
367 #define RLDCL MDS30( 8)
368
369 #define BCLR XO19( 16)
370 #define BCCTR XO19(528)
371 #define CRAND XO19(257)
372 #define CRANDC XO19(129)
373 #define CRNAND XO19(225)
374 #define CROR XO19(449)
375 #define CRNOR XO19( 33)
376
377 #define EXTSB XO31(954)
378 #define EXTSH XO31(922)
379 #define EXTSW XO31(986)
380 #define ADD XO31(266)
381 #define ADDE XO31(138)
382 #define ADDME XO31(234)
383 #define ADDZE XO31(202)
384 #define ADDC XO31( 10)
385 #define AND XO31( 28)
386 #define SUBF XO31( 40)
387 #define SUBFC XO31( 8)
388 #define SUBFE XO31(136)
389 #define SUBFME XO31(232)
390 #define SUBFZE XO31(200)
391 #define OR XO31(444)
392 #define XOR XO31(316)
393 #define MULLW XO31(235)
394 #define MULHWU XO31( 11)
395 #define DIVW XO31(491)
396 #define DIVWU XO31(459)
397 #define CMP XO31( 0)
398 #define CMPL XO31( 32)
399 #define LHBRX XO31(790)
400 #define LWBRX XO31(534)
401 #define LDBRX XO31(532)
402 #define STHBRX XO31(918)
403 #define STWBRX XO31(662)
404 #define STDBRX XO31(660)
405 #define MFSPR XO31(339)
406 #define MTSPR XO31(467)
407 #define SRAWI XO31(824)
408 #define NEG XO31(104)
409 #define MFCR XO31( 19)
410 #define MFOCRF (MFCR | (1u << 20))
411 #define NOR XO31(124)
412 #define CNTLZW XO31( 26)
413 #define CNTLZD XO31( 58)
414 #define ANDC XO31( 60)
415 #define ORC XO31(412)
416 #define EQV XO31(284)
417 #define NAND XO31(476)
418 #define ISEL XO31( 15)
419
420 #define MULLD XO31(233)
421 #define MULHD XO31( 73)
422 #define MULHDU XO31( 9)
423 #define DIVD XO31(489)
424 #define DIVDU XO31(457)
425
426 #define LBZX XO31( 87)
427 #define LHZX XO31(279)
428 #define LHAX XO31(343)
429 #define LWZX XO31( 23)
430 #define STBX XO31(215)
431 #define STHX XO31(407)
432 #define STWX XO31(151)
433
434 #define SPR(a, b) ((((a)<<5)|(b))<<11)
435 #define LR SPR(8, 0)
436 #define CTR SPR(9, 0)
437
438 #define SLW XO31( 24)
439 #define SRW XO31(536)
440 #define SRAW XO31(792)
441
442 #define SLD XO31( 27)
443 #define SRD XO31(539)
444 #define SRAD XO31(794)
445 #define SRADI XO31(413<<1)
446
447 #define TW XO31( 4)
448 #define TRAP (TW | TO(31))
449
450 #define RT(r) ((r)<<21)
451 #define RS(r) ((r)<<21)
452 #define RA(r) ((r)<<16)
453 #define RB(r) ((r)<<11)
454 #define TO(t) ((t)<<21)
455 #define SH(s) ((s)<<11)
456 #define MB(b) ((b)<<6)
457 #define ME(e) ((e)<<1)
458 #define BO(o) ((o)<<21)
459 #define MB64(b) ((b)<<5)
460 #define FXM(b) (1 << (19 - (b)))
461
462 #define LK 1
463
464 #define TAB(t, a, b) (RT(t) | RA(a) | RB(b))
465 #define SAB(s, a, b) (RS(s) | RA(a) | RB(b))
466 #define TAI(s, a, i) (RT(s) | RA(a) | ((i) & 0xffff))
467 #define SAI(s, a, i) (RS(s) | RA(a) | ((i) & 0xffff))
468
469 #define BF(n) ((n)<<23)
470 #define BI(n, c) (((c)+((n)*4))<<16)
471 #define BT(n, c) (((c)+((n)*4))<<21)
472 #define BA(n, c) (((c)+((n)*4))<<16)
473 #define BB(n, c) (((c)+((n)*4))<<11)
474 #define BC_(n, c) (((c)+((n)*4))<<6)
475
476 #define BO_COND_TRUE BO(12)
477 #define BO_COND_FALSE BO( 4)
478 #define BO_ALWAYS BO(20)
479
480 enum {
481 CR_LT,
482 CR_GT,
483 CR_EQ,
484 CR_SO
485 };
486
487 static const uint32_t tcg_to_bc[] = {
488 [TCG_COND_EQ] = BC | BI(7, CR_EQ) | BO_COND_TRUE,
489 [TCG_COND_NE] = BC | BI(7, CR_EQ) | BO_COND_FALSE,
490 [TCG_COND_LT] = BC | BI(7, CR_LT) | BO_COND_TRUE,
491 [TCG_COND_GE] = BC | BI(7, CR_LT) | BO_COND_FALSE,
492 [TCG_COND_LE] = BC | BI(7, CR_GT) | BO_COND_FALSE,
493 [TCG_COND_GT] = BC | BI(7, CR_GT) | BO_COND_TRUE,
494 [TCG_COND_LTU] = BC | BI(7, CR_LT) | BO_COND_TRUE,
495 [TCG_COND_GEU] = BC | BI(7, CR_LT) | BO_COND_FALSE,
496 [TCG_COND_LEU] = BC | BI(7, CR_GT) | BO_COND_FALSE,
497 [TCG_COND_GTU] = BC | BI(7, CR_GT) | BO_COND_TRUE,
498 };
499
500 /* The low bit here is set if the RA and RB fields must be inverted. */
501 static const uint32_t tcg_to_isel[] = {
502 [TCG_COND_EQ] = ISEL | BC_(7, CR_EQ),
503 [TCG_COND_NE] = ISEL | BC_(7, CR_EQ) | 1,
504 [TCG_COND_LT] = ISEL | BC_(7, CR_LT),
505 [TCG_COND_GE] = ISEL | BC_(7, CR_LT) | 1,
506 [TCG_COND_LE] = ISEL | BC_(7, CR_GT) | 1,
507 [TCG_COND_GT] = ISEL | BC_(7, CR_GT),
508 [TCG_COND_LTU] = ISEL | BC_(7, CR_LT),
509 [TCG_COND_GEU] = ISEL | BC_(7, CR_LT) | 1,
510 [TCG_COND_LEU] = ISEL | BC_(7, CR_GT) | 1,
511 [TCG_COND_GTU] = ISEL | BC_(7, CR_GT),
512 };
513
514 static inline void tcg_out_mov(TCGContext *s, TCGType type,
515 TCGReg ret, TCGReg arg)
516 {
517 if (ret != arg) {
518 tcg_out32(s, OR | SAB(arg, ret, arg));
519 }
520 }
521
522 static inline void tcg_out_rld(TCGContext *s, int op, TCGReg ra, TCGReg rs,
523 int sh, int mb)
524 {
525 sh = SH(sh & 0x1f) | (((sh >> 5) & 1) << 1);
526 mb = MB64((mb >> 5) | ((mb << 1) & 0x3f));
527 tcg_out32(s, op | RA(ra) | RS(rs) | sh | mb);
528 }
529
530 static inline void tcg_out_rlw(TCGContext *s, int op, TCGReg ra, TCGReg rs,
531 int sh, int mb, int me)
532 {
533 tcg_out32(s, op | RA(ra) | RS(rs) | SH(sh) | MB(mb) | ME(me));
534 }
535
536 static inline void tcg_out_ext32u(TCGContext *s, TCGReg dst, TCGReg src)
537 {
538 tcg_out_rld(s, RLDICL, dst, src, 0, 32);
539 }
540
541 static inline void tcg_out_shli64(TCGContext *s, TCGReg dst, TCGReg src, int c)
542 {
543 tcg_out_rld(s, RLDICR, dst, src, c, 63 - c);
544 }
545
546 static inline void tcg_out_shri64(TCGContext *s, TCGReg dst, TCGReg src, int c)
547 {
548 tcg_out_rld(s, RLDICL, dst, src, 64 - c, c);
549 }
550
551 static void tcg_out_movi32(TCGContext *s, TCGReg ret, int32_t arg)
552 {
553 if (arg == (int16_t) arg) {
554 tcg_out32(s, ADDI | TAI(ret, 0, arg));
555 } else {
556 tcg_out32(s, ADDIS | TAI(ret, 0, arg >> 16));
557 if (arg & 0xffff) {
558 tcg_out32(s, ORI | SAI(ret, ret, arg));
559 }
560 }
561 }
562
563 static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg ret,
564 tcg_target_long arg)
565 {
566 if (type == TCG_TYPE_I32 || arg == (int32_t)arg) {
567 tcg_out_movi32(s, ret, arg);
568 } else if (arg == (uint32_t)arg && !(arg & 0x8000)) {
569 tcg_out32(s, ADDI | TAI(ret, 0, arg));
570 tcg_out32(s, ORIS | SAI(ret, ret, arg >> 16));
571 } else {
572 int32_t high = arg >> 32;
573 tcg_out_movi32(s, ret, high);
574 if (high) {
575 tcg_out_shli64(s, ret, ret, 32);
576 }
577 if (arg & 0xffff0000) {
578 tcg_out32(s, ORIS | SAI(ret, ret, arg >> 16));
579 }
580 if (arg & 0xffff) {
581 tcg_out32(s, ORI | SAI(ret, ret, arg));
582 }
583 }
584 }
585
586 static bool mask_operand(uint32_t c, int *mb, int *me)
587 {
588 uint32_t lsb, test;
589
590 /* Accept a bit pattern like:
591 0....01....1
592 1....10....0
593 0..01..10..0
594 Keep track of the transitions. */
595 if (c == 0 || c == -1) {
596 return false;
597 }
598 test = c;
599 lsb = test & -test;
600 test += lsb;
601 if (test & (test - 1)) {
602 return false;
603 }
604
605 *me = clz32(lsb);
606 *mb = test ? clz32(test & -test) + 1 : 0;
607 return true;
608 }
609
610 static bool mask64_operand(uint64_t c, int *mb, int *me)
611 {
612 uint64_t lsb;
613
614 if (c == 0) {
615 return false;
616 }
617
618 lsb = c & -c;
619 /* Accept 1..10..0. */
620 if (c == -lsb) {
621 *mb = 0;
622 *me = clz64(lsb);
623 return true;
624 }
625 /* Accept 0..01..1. */
626 if (lsb == 1 && (c & (c + 1)) == 0) {
627 *mb = clz64(c + 1) + 1;
628 *me = 63;
629 return true;
630 }
631 return false;
632 }
633
634 static void tcg_out_andi32(TCGContext *s, TCGReg dst, TCGReg src, uint32_t c)
635 {
636 int mb, me;
637
638 if ((c & 0xffff) == c) {
639 tcg_out32(s, ANDI | SAI(src, dst, c));
640 return;
641 } else if ((c & 0xffff0000) == c) {
642 tcg_out32(s, ANDIS | SAI(src, dst, c >> 16));
643 return;
644 } else if (mask_operand(c, &mb, &me)) {
645 tcg_out_rlw(s, RLWINM, dst, src, 0, mb, me);
646 } else {
647 tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_R0, c);
648 tcg_out32(s, AND | SAB(src, dst, TCG_REG_R0));
649 }
650 }
651
652 static void tcg_out_andi64(TCGContext *s, TCGReg dst, TCGReg src, uint64_t c)
653 {
654 int mb, me;
655
656 if ((c & 0xffff) == c) {
657 tcg_out32(s, ANDI | SAI(src, dst, c));
658 return;
659 } else if ((c & 0xffff0000) == c) {
660 tcg_out32(s, ANDIS | SAI(src, dst, c >> 16));
661 return;
662 } else if (mask64_operand(c, &mb, &me)) {
663 if (mb == 0) {
664 tcg_out_rld(s, RLDICR, dst, src, 0, me);
665 } else {
666 tcg_out_rld(s, RLDICL, dst, src, 0, mb);
667 }
668 } else {
669 tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_R0, c);
670 tcg_out32(s, AND | SAB(src, dst, TCG_REG_R0));
671 }
672 }
673
674 static void tcg_out_zori32(TCGContext *s, TCGReg dst, TCGReg src, uint32_t c,
675 int op_lo, int op_hi)
676 {
677 if (c >> 16) {
678 tcg_out32(s, op_hi | SAI(src, dst, c >> 16));
679 src = dst;
680 }
681 if (c & 0xffff) {
682 tcg_out32(s, op_lo | SAI(src, dst, c));
683 src = dst;
684 }
685 }
686
687 static void tcg_out_ori32(TCGContext *s, TCGReg dst, TCGReg src, uint32_t c)
688 {
689 tcg_out_zori32(s, dst, src, c, ORI, ORIS);
690 }
691
692 static void tcg_out_xori32(TCGContext *s, TCGReg dst, TCGReg src, uint32_t c)
693 {
694 tcg_out_zori32(s, dst, src, c, XORI, XORIS);
695 }
696
697 static void tcg_out_b(TCGContext *s, int mask, tcg_target_long target)
698 {
699 tcg_target_long disp;
700
701 disp = target - (tcg_target_long)s->code_ptr;
702 if (in_range_b(disp)) {
703 tcg_out32(s, B | (disp & 0x3fffffc) | mask);
704 } else {
705 tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_R0, (tcg_target_long)target);
706 tcg_out32(s, MTSPR | RS(TCG_REG_R0) | CTR);
707 tcg_out32(s, BCCTR | BO_ALWAYS | mask);
708 }
709 }
710
711 static void tcg_out_call(TCGContext *s, tcg_target_long arg, int const_arg)
712 {
713 #ifdef __APPLE__
714 if (const_arg) {
715 tcg_out_b(s, LK, arg);
716 } else {
717 tcg_out32(s, MTSPR | RS(arg) | LR);
718 tcg_out32(s, BCLR | BO_ALWAYS | LK);
719 }
720 #else
721 TCGReg reg = arg;
722 int ofs = 0;
723
724 if (const_arg) {
725 /* Look through the descriptor. If the branch is in range, and we
726 don't have to spend too much effort on building the toc. */
727 intptr_t tgt = ((intptr_t *)arg)[0];
728 intptr_t toc = ((intptr_t *)arg)[1];
729 intptr_t diff = tgt - (intptr_t)s->code_ptr;
730
731 if (in_range_b(diff) && toc == (uint32_t)toc) {
732 tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_R2, toc);
733 tcg_out_b(s, LK, tgt);
734 return;
735 }
736
737 /* Fold the low bits of the constant into the addresses below. */
738 ofs = (int16_t)arg;
739 if (ofs + 8 < 0x8000) {
740 arg -= ofs;
741 } else {
742 ofs = 0;
743 }
744 reg = TCG_REG_R2;
745 tcg_out_movi(s, TCG_TYPE_I64, reg, arg);
746 }
747
748 tcg_out32(s, LD | TAI(TCG_REG_R0, reg, ofs));
749 tcg_out32(s, MTSPR | RA(TCG_REG_R0) | CTR);
750 tcg_out32(s, LD | TAI(TCG_REG_R2, reg, ofs + 8));
751 tcg_out32(s, BCCTR | BO_ALWAYS | LK);
752 #endif
753 }
754
755 static void tcg_out_mem_long(TCGContext *s, int opi, int opx, TCGReg rt,
756 TCGReg base, tcg_target_long offset)
757 {
758 tcg_target_long orig = offset, l0, l1, extra = 0, align = 0;
759 TCGReg rs = TCG_REG_R2;
760
761 assert(rt != TCG_REG_R2 && base != TCG_REG_R2);
762
763 switch (opi) {
764 case LD: case LWA:
765 align = 3;
766 /* FALLTHRU */
767 default:
768 if (rt != TCG_REG_R0) {
769 rs = rt;
770 }
771 break;
772 case STD:
773 align = 3;
774 break;
775 case STB: case STH: case STW:
776 break;
777 }
778
779 /* For unaligned, or very large offsets, use the indexed form. */
780 if (offset & align || offset != (int32_t)offset) {
781 tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_R2, orig);
782 tcg_out32(s, opx | TAB(rt, base, TCG_REG_R2));
783 return;
784 }
785
786 l0 = (int16_t)offset;
787 offset = (offset - l0) >> 16;
788 l1 = (int16_t)offset;
789
790 if (l1 < 0 && orig >= 0) {
791 extra = 0x4000;
792 l1 = (int16_t)(offset - 0x4000);
793 }
794 if (l1) {
795 tcg_out32(s, ADDIS | TAI(rs, base, l1));
796 base = rs;
797 }
798 if (extra) {
799 tcg_out32(s, ADDIS | TAI(rs, base, extra));
800 base = rs;
801 }
802 if (opi != ADDI || base != rt || l0 != 0) {
803 tcg_out32(s, opi | TAI(rt, base, l0));
804 }
805 }
806
807 static const uint32_t qemu_ldx_opc[16] = {
808 [MO_UB] = LBZX,
809 [MO_UW] = LHZX,
810 [MO_UL] = LWZX,
811 [MO_Q] = LDX,
812 [MO_SW] = LHAX,
813 [MO_SL] = LWAX,
814 [MO_BSWAP | MO_UB] = LBZX,
815 [MO_BSWAP | MO_UW] = LHBRX,
816 [MO_BSWAP | MO_UL] = LWBRX,
817 [MO_BSWAP | MO_Q] = LDBRX,
818 };
819
820 static const uint32_t qemu_stx_opc[16] = {
821 [MO_UB] = STBX,
822 [MO_UW] = STHX,
823 [MO_UL] = STWX,
824 [MO_Q] = STDX,
825 [MO_BSWAP | MO_UB] = STBX,
826 [MO_BSWAP | MO_UW] = STHBRX,
827 [MO_BSWAP | MO_UL] = STWBRX,
828 [MO_BSWAP | MO_Q] = STDBRX,
829 };
830
831 static const uint32_t qemu_exts_opc[4] = {
832 EXTSB, EXTSH, EXTSW, 0
833 };
834
835 #if defined (CONFIG_SOFTMMU)
836 /* helper signature: helper_ld_mmu(CPUState *env, target_ulong addr,
837 * int mmu_idx, uintptr_t ra)
838 */
839 static const void * const qemu_ld_helpers[16] = {
840 [MO_UB] = helper_ret_ldub_mmu,
841 [MO_LEUW] = helper_le_lduw_mmu,
842 [MO_LEUL] = helper_le_ldul_mmu,
843 [MO_LEQ] = helper_le_ldq_mmu,
844 [MO_BEUW] = helper_be_lduw_mmu,
845 [MO_BEUL] = helper_be_ldul_mmu,
846 [MO_BEQ] = helper_be_ldq_mmu,
847 };
848
849 /* helper signature: helper_st_mmu(CPUState *env, target_ulong addr,
850 * uintxx_t val, int mmu_idx, uintptr_t ra)
851 */
852 static const void * const qemu_st_helpers[16] = {
853 [MO_UB] = helper_ret_stb_mmu,
854 [MO_LEUW] = helper_le_stw_mmu,
855 [MO_LEUL] = helper_le_stl_mmu,
856 [MO_LEQ] = helper_le_stq_mmu,
857 [MO_BEUW] = helper_be_stw_mmu,
858 [MO_BEUL] = helper_be_stl_mmu,
859 [MO_BEQ] = helper_be_stq_mmu,
860 };
861
862 /* Perform the TLB load and compare. Places the result of the comparison
863 in CR7, loads the addend of the TLB into R3, and returns the register
864 containing the guest address (zero-extended into R4). Clobbers R0 and R2. */
865
866 static TCGReg tcg_out_tlb_read(TCGContext *s, TCGMemOp s_bits, TCGReg addr_reg,
867 int mem_index, bool is_read)
868 {
869 int cmp_off
870 = (is_read
871 ? offsetof(CPUArchState, tlb_table[mem_index][0].addr_read)
872 : offsetof(CPUArchState, tlb_table[mem_index][0].addr_write));
873 int add_off = offsetof(CPUArchState, tlb_table[mem_index][0].addend);
874 TCGReg base = TCG_AREG0;
875
876 /* Extract the page index, shifted into place for tlb index. */
877 if (TARGET_LONG_BITS == 32) {
878 /* Zero-extend the address into a place helpful for further use. */
879 tcg_out_ext32u(s, TCG_REG_R4, addr_reg);
880 addr_reg = TCG_REG_R4;
881 } else {
882 tcg_out_rld(s, RLDICL, TCG_REG_R3, addr_reg,
883 64 - TARGET_PAGE_BITS, 64 - CPU_TLB_BITS);
884 }
885
886 /* Compensate for very large offsets. */
887 if (add_off >= 0x8000) {
888 /* Most target env are smaller than 32k; none are larger than 64k.
889 Simplify the logic here merely to offset by 0x7ff0, giving us a
890 range just shy of 64k. Check this assumption. */
891 QEMU_BUILD_BUG_ON(offsetof(CPUArchState,
892 tlb_table[NB_MMU_MODES - 1][1])
893 > 0x7ff0 + 0x7fff);
894 tcg_out32(s, ADDI | TAI(TCG_REG_R2, base, 0x7ff0));
895 base = TCG_REG_R2;
896 cmp_off -= 0x7ff0;
897 add_off -= 0x7ff0;
898 }
899
900 /* Extraction and shifting, part 2. */
901 if (TARGET_LONG_BITS == 32) {
902 tcg_out_rlw(s, RLWINM, TCG_REG_R3, addr_reg,
903 32 - (TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS),
904 32 - (CPU_TLB_BITS + CPU_TLB_ENTRY_BITS),
905 31 - CPU_TLB_ENTRY_BITS);
906 } else {
907 tcg_out_shli64(s, TCG_REG_R3, TCG_REG_R3, CPU_TLB_ENTRY_BITS);
908 }
909
910 tcg_out32(s, ADD | TAB(TCG_REG_R3, TCG_REG_R3, base));
911
912 /* Load the tlb comparator. */
913 tcg_out32(s, LD_ADDR | TAI(TCG_REG_R2, TCG_REG_R3, cmp_off));
914
915 /* Load the TLB addend for use on the fast path. Do this asap
916 to minimize any load use delay. */
917 tcg_out32(s, LD | TAI(TCG_REG_R3, TCG_REG_R3, add_off));
918
919 /* Clear the non-page, non-alignment bits from the address. */
920 if (TARGET_LONG_BITS == 32) {
921 tcg_out_rlw(s, RLWINM, TCG_REG_R0, addr_reg, 0,
922 (32 - s_bits) & 31, 31 - TARGET_PAGE_BITS);
923 } else if (!s_bits) {
924 tcg_out_rld(s, RLDICR, TCG_REG_R0, addr_reg, 0, 63 - TARGET_PAGE_BITS);
925 } else {
926 tcg_out_rld(s, RLDICL, TCG_REG_R0, addr_reg,
927 64 - TARGET_PAGE_BITS, TARGET_PAGE_BITS - s_bits);
928 tcg_out_rld(s, RLDICL, TCG_REG_R0, TCG_REG_R0, TARGET_PAGE_BITS, 0);
929 }
930
931 tcg_out32(s, CMP | BF(7) | RA(TCG_REG_R0) | RB(TCG_REG_R2) | CMP_L);
932
933 return addr_reg;
934 }
935
936 /* Record the context of a call to the out of line helper code for the slow
937 path for a load or store, so that we can later generate the correct
938 helper code. */
939 static void add_qemu_ldst_label(TCGContext *s, bool is_ld, TCGMemOp opc,
940 int data_reg, int addr_reg, int mem_index,
941 uint8_t *raddr, uint8_t *label_ptr)
942 {
943 TCGLabelQemuLdst *label = new_ldst_label(s);
944
945 label->is_ld = is_ld;
946 label->opc = opc;
947 label->datalo_reg = data_reg;
948 label->addrlo_reg = addr_reg;
949 label->mem_index = mem_index;
950 label->raddr = raddr;
951 label->label_ptr[0] = label_ptr;
952 }
953
954 static void tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
955 {
956 TCGMemOp opc = lb->opc;
957
958 reloc_pc14(lb->label_ptr[0], (uintptr_t)s->code_ptr);
959
960 tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_R3, TCG_AREG0);
961
962 /* If the address needed to be zero-extended, we'll have already
963 placed it in R4. The only remaining case is 64-bit guest. */
964 tcg_out_mov(s, TCG_TYPE_I64, TCG_REG_R4, lb->addrlo_reg);
965
966 tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_R5, lb->mem_index);
967 tcg_out32(s, MFSPR | RT(TCG_REG_R6) | LR);
968
969 tcg_out_call(s, (tcg_target_long)qemu_ld_helpers[opc & ~MO_SIGN], 1);
970
971 if (opc & MO_SIGN) {
972 uint32_t insn = qemu_exts_opc[opc & MO_SIZE];
973 tcg_out32(s, insn | RA(lb->datalo_reg) | RS(TCG_REG_R3));
974 } else {
975 tcg_out_mov(s, TCG_TYPE_I64, lb->datalo_reg, TCG_REG_R3);
976 }
977
978 tcg_out_b(s, 0, (uintptr_t)lb->raddr);
979 }
980
981 static void tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
982 {
983 TCGMemOp opc = lb->opc;
984 TCGMemOp s_bits = opc & MO_SIZE;
985
986 reloc_pc14(lb->label_ptr[0], (uintptr_t)s->code_ptr);
987
988 tcg_out_mov(s, TCG_TYPE_I64, TCG_REG_R3, TCG_AREG0);
989
990 /* If the address needed to be zero-extended, we'll have already
991 placed it in R4. The only remaining case is 64-bit guest. */
992 tcg_out_mov(s, TCG_TYPE_I64, TCG_REG_R4, lb->addrlo_reg);
993
994 tcg_out_rld(s, RLDICL, TCG_REG_R5, lb->datalo_reg,
995 0, 64 - (1 << (3 + s_bits)));
996 tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_R6, lb->mem_index);
997 tcg_out32(s, MFSPR | RT(TCG_REG_R7) | LR);
998
999 tcg_out_call(s, (tcg_target_long)qemu_st_helpers[opc], 1);
1000
1001 tcg_out_b(s, 0, (uintptr_t)lb->raddr);
1002 }
1003 #endif /* SOFTMMU */
1004
1005 static void tcg_out_qemu_ld(TCGContext *s, TCGReg data_reg, TCGReg addr_reg,
1006 TCGMemOp opc, int mem_index)
1007 {
1008 TCGReg rbase;
1009 uint32_t insn;
1010 TCGMemOp s_bits = opc & MO_SIZE;
1011 #ifdef CONFIG_SOFTMMU
1012 void *label_ptr;
1013 #endif
1014
1015 #ifdef CONFIG_SOFTMMU
1016 addr_reg = tcg_out_tlb_read(s, s_bits, addr_reg, mem_index, true);
1017
1018 /* Load a pointer into the current opcode w/conditional branch-link. */
1019 label_ptr = s->code_ptr;
1020 tcg_out_bc_noaddr(s, BC | BI(7, CR_EQ) | BO_COND_FALSE | LK);
1021
1022 rbase = TCG_REG_R3;
1023 #else /* !CONFIG_SOFTMMU */
1024 rbase = GUEST_BASE ? TCG_GUEST_BASE_REG : 0;
1025 if (TARGET_LONG_BITS == 32) {
1026 tcg_out_ext32u(s, TCG_REG_R2, addr_reg);
1027 addr_reg = TCG_REG_R2;
1028 }
1029 #endif
1030
1031 insn = qemu_ldx_opc[opc];
1032 if (!HAVE_ISA_2_06 && insn == LDBRX) {
1033 tcg_out32(s, ADDI | TAI(TCG_REG_R0, addr_reg, 4));
1034 tcg_out32(s, LWBRX | TAB(data_reg, rbase, addr_reg));
1035 tcg_out32(s, LWBRX | TAB(TCG_REG_R0, rbase, TCG_REG_R0));
1036 tcg_out_rld(s, RLDIMI, data_reg, TCG_REG_R0, 32, 0);
1037 } else if (insn) {
1038 tcg_out32(s, insn | TAB(data_reg, rbase, addr_reg));
1039 } else {
1040 insn = qemu_ldx_opc[opc & (MO_SIZE | MO_BSWAP)];
1041 tcg_out32(s, insn | TAB(data_reg, rbase, addr_reg));
1042 insn = qemu_exts_opc[s_bits];
1043 tcg_out32(s, insn | RA(data_reg) | RS(data_reg));
1044 }
1045
1046 #ifdef CONFIG_SOFTMMU
1047 add_qemu_ldst_label(s, true, opc, data_reg, addr_reg, mem_index,
1048 s->code_ptr, label_ptr);
1049 #endif
1050 }
1051
1052 static void tcg_out_qemu_st(TCGContext *s, TCGReg data_reg, TCGReg addr_reg,
1053 TCGMemOp opc, int mem_index)
1054 {
1055 TCGReg rbase;
1056 uint32_t insn;
1057 #ifdef CONFIG_SOFTMMU
1058 void *label_ptr;
1059 #endif
1060
1061 #ifdef CONFIG_SOFTMMU
1062 addr_reg = tcg_out_tlb_read(s, opc & MO_SIZE, addr_reg, mem_index, false);
1063
1064 /* Load a pointer into the current opcode w/conditional branch-link. */
1065 label_ptr = s->code_ptr;
1066 tcg_out_bc_noaddr(s, BC | BI(7, CR_EQ) | BO_COND_FALSE | LK);
1067
1068 rbase = TCG_REG_R3;
1069 #else /* !CONFIG_SOFTMMU */
1070 rbase = GUEST_BASE ? TCG_GUEST_BASE_REG : 0;
1071 if (TARGET_LONG_BITS == 32) {
1072 tcg_out_ext32u(s, TCG_REG_R2, addr_reg);
1073 addr_reg = TCG_REG_R2;
1074 }
1075 #endif
1076
1077 insn = qemu_stx_opc[opc];
1078 if (!HAVE_ISA_2_06 && insn == STDBRX) {
1079 tcg_out32(s, STWBRX | SAB(data_reg, rbase, addr_reg));
1080 tcg_out32(s, ADDI | TAI(TCG_REG_R2, addr_reg, 4));
1081 tcg_out_shri64(s, TCG_REG_R0, data_reg, 32);
1082 tcg_out32(s, STWBRX | SAB(TCG_REG_R0, rbase, TCG_REG_R2));
1083 } else {
1084 tcg_out32(s, insn | SAB(data_reg, rbase, addr_reg));
1085 }
1086
1087 #ifdef CONFIG_SOFTMMU
1088 add_qemu_ldst_label(s, false, opc, data_reg, addr_reg, mem_index,
1089 s->code_ptr, label_ptr);
1090 #endif
1091 }
1092
1093 #define FRAME_SIZE ((int) \
1094 ((8 /* back chain */ \
1095 + 8 /* CR */ \
1096 + 8 /* LR */ \
1097 + 8 /* compiler doubleword */ \
1098 + 8 /* link editor doubleword */ \
1099 + 8 /* TOC save area */ \
1100 + TCG_STATIC_CALL_ARGS_SIZE \
1101 + CPU_TEMP_BUF_NLONGS * sizeof(long) \
1102 + ARRAY_SIZE(tcg_target_callee_save_regs) * 8 \
1103 + 15) & ~15))
1104
1105 #define REG_SAVE_BOT (FRAME_SIZE - ARRAY_SIZE(tcg_target_callee_save_regs) * 8)
1106
1107 static void tcg_target_qemu_prologue(TCGContext *s)
1108 {
1109 int i;
1110
1111 tcg_set_frame(s, TCG_REG_CALL_STACK,
1112 REG_SAVE_BOT - CPU_TEMP_BUF_NLONGS * sizeof(long),
1113 CPU_TEMP_BUF_NLONGS * sizeof(long));
1114
1115 #ifndef __APPLE__
1116 /* First emit adhoc function descriptor */
1117 tcg_out64(s, (uint64_t)s->code_ptr + 24); /* entry point */
1118 s->code_ptr += 16; /* skip TOC and environment pointer */
1119 #endif
1120
1121 /* Prologue */
1122 tcg_out32(s, MFSPR | RT(TCG_REG_R0) | LR);
1123 tcg_out32(s, STDU | SAI(TCG_REG_R1, TCG_REG_R1, -FRAME_SIZE));
1124 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); ++i) {
1125 tcg_out32(s, STD | SAI(tcg_target_callee_save_regs[i], 1,
1126 REG_SAVE_BOT + i * 8));
1127 }
1128 tcg_out32(s, STD | SAI(TCG_REG_R0, TCG_REG_R1, FRAME_SIZE + 16));
1129
1130 #ifdef CONFIG_USE_GUEST_BASE
1131 if (GUEST_BASE) {
1132 tcg_out_movi(s, TCG_TYPE_I64, TCG_GUEST_BASE_REG, GUEST_BASE);
1133 tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG);
1134 }
1135 #endif
1136
1137 tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]);
1138 tcg_out32(s, MTSPR | RS(tcg_target_call_iarg_regs[1]) | CTR);
1139 tcg_out32(s, BCCTR | BO_ALWAYS);
1140
1141 /* Epilogue */
1142 tb_ret_addr = s->code_ptr;
1143
1144 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); ++i) {
1145 tcg_out32(s, LD | TAI(tcg_target_callee_save_regs[i], TCG_REG_R1,
1146 REG_SAVE_BOT + i * 8));
1147 }
1148 tcg_out32(s, LD | TAI(TCG_REG_R0, TCG_REG_R1, FRAME_SIZE + 16));
1149 tcg_out32(s, MTSPR | RS(TCG_REG_R0) | LR);
1150 tcg_out32(s, ADDI | TAI(TCG_REG_R1, TCG_REG_R1, FRAME_SIZE));
1151 tcg_out32(s, BCLR | BO_ALWAYS);
1152 }
1153
1154 static inline void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret,
1155 TCGReg arg1, intptr_t arg2)
1156 {
1157 int opi, opx;
1158
1159 if (type == TCG_TYPE_I32) {
1160 opi = LWZ, opx = LWZX;
1161 } else {
1162 opi = LD, opx = LDX;
1163 }
1164 tcg_out_mem_long(s, opi, opx, ret, arg1, arg2);
1165 }
1166
1167 static inline void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg,
1168 TCGReg arg1, intptr_t arg2)
1169 {
1170 int opi, opx;
1171
1172 if (type == TCG_TYPE_I32) {
1173 opi = STW, opx = STWX;
1174 } else {
1175 opi = STD, opx = STDX;
1176 }
1177 tcg_out_mem_long(s, opi, opx, arg, arg1, arg2);
1178 }
1179
1180 static void tcg_out_cmp(TCGContext *s, int cond, TCGArg arg1, TCGArg arg2,
1181 int const_arg2, int cr, TCGType type)
1182 {
1183 int imm;
1184 uint32_t op;
1185
1186 /* Simplify the comparisons below wrt CMPI. */
1187 if (type == TCG_TYPE_I32) {
1188 arg2 = (int32_t)arg2;
1189 }
1190
1191 switch (cond) {
1192 case TCG_COND_EQ:
1193 case TCG_COND_NE:
1194 if (const_arg2) {
1195 if ((int16_t) arg2 == arg2) {
1196 op = CMPI;
1197 imm = 1;
1198 break;
1199 } else if ((uint16_t) arg2 == arg2) {
1200 op = CMPLI;
1201 imm = 1;
1202 break;
1203 }
1204 }
1205 op = CMPL;
1206 imm = 0;
1207 break;
1208
1209 case TCG_COND_LT:
1210 case TCG_COND_GE:
1211 case TCG_COND_LE:
1212 case TCG_COND_GT:
1213 if (const_arg2) {
1214 if ((int16_t) arg2 == arg2) {
1215 op = CMPI;
1216 imm = 1;
1217 break;
1218 }
1219 }
1220 op = CMP;
1221 imm = 0;
1222 break;
1223
1224 case TCG_COND_LTU:
1225 case TCG_COND_GEU:
1226 case TCG_COND_LEU:
1227 case TCG_COND_GTU:
1228 if (const_arg2) {
1229 if ((uint16_t) arg2 == arg2) {
1230 op = CMPLI;
1231 imm = 1;
1232 break;
1233 }
1234 }
1235 op = CMPL;
1236 imm = 0;
1237 break;
1238
1239 default:
1240 tcg_abort();
1241 }
1242 op |= BF(cr) | ((type == TCG_TYPE_I64) << 21);
1243
1244 if (imm) {
1245 tcg_out32(s, op | RA(arg1) | (arg2 & 0xffff));
1246 } else {
1247 if (const_arg2) {
1248 tcg_out_movi(s, type, TCG_REG_R0, arg2);
1249 arg2 = TCG_REG_R0;
1250 }
1251 tcg_out32(s, op | RA(arg1) | RB(arg2));
1252 }
1253 }
1254
1255 static void tcg_out_setcond_eq0(TCGContext *s, TCGType type,
1256 TCGReg dst, TCGReg src)
1257 {
1258 tcg_out32(s, (type == TCG_TYPE_I64 ? CNTLZD : CNTLZW) | RS(src) | RA(dst));
1259 tcg_out_shri64(s, dst, dst, type == TCG_TYPE_I64 ? 6 : 5);
1260 }
1261
1262 static void tcg_out_setcond_ne0(TCGContext *s, TCGReg dst, TCGReg src)
1263 {
1264 /* X != 0 implies X + -1 generates a carry. Extra addition
1265 trickery means: R = X-1 + ~X + C = X-1 + (-X+1) + C = C. */
1266 if (dst != src) {
1267 tcg_out32(s, ADDIC | TAI(dst, src, -1));
1268 tcg_out32(s, SUBFE | TAB(dst, dst, src));
1269 } else {
1270 tcg_out32(s, ADDIC | TAI(TCG_REG_R0, src, -1));
1271 tcg_out32(s, SUBFE | TAB(dst, TCG_REG_R0, src));
1272 }
1273 }
1274
1275 static TCGReg tcg_gen_setcond_xor(TCGContext *s, TCGReg arg1, TCGArg arg2,
1276 bool const_arg2)
1277 {
1278 if (const_arg2) {
1279 if ((uint32_t)arg2 == arg2) {
1280 tcg_out_xori32(s, TCG_REG_R0, arg1, arg2);
1281 } else {
1282 tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_R0, arg2);
1283 tcg_out32(s, XOR | SAB(arg1, TCG_REG_R0, TCG_REG_R0));
1284 }
1285 } else {
1286 tcg_out32(s, XOR | SAB(arg1, TCG_REG_R0, arg2));
1287 }
1288 return TCG_REG_R0;
1289 }
1290
1291 static void tcg_out_setcond(TCGContext *s, TCGType type, TCGCond cond,
1292 TCGArg arg0, TCGArg arg1, TCGArg arg2,
1293 int const_arg2)
1294 {
1295 int crop, sh;
1296
1297 /* Ignore high bits of a potential constant arg2. */
1298 if (type == TCG_TYPE_I32) {
1299 arg2 = (uint32_t)arg2;
1300 }
1301
1302 /* Handle common and trivial cases before handling anything else. */
1303 if (arg2 == 0) {
1304 switch (cond) {
1305 case TCG_COND_EQ:
1306 tcg_out_setcond_eq0(s, type, arg0, arg1);
1307 return;
1308 case TCG_COND_NE:
1309 if (type == TCG_TYPE_I32) {
1310 tcg_out_ext32u(s, TCG_REG_R0, arg1);
1311 arg1 = TCG_REG_R0;
1312 }
1313 tcg_out_setcond_ne0(s, arg0, arg1);
1314 return;
1315 case TCG_COND_GE:
1316 tcg_out32(s, NOR | SAB(arg1, arg0, arg1));
1317 arg1 = arg0;
1318 /* FALLTHRU */
1319 case TCG_COND_LT:
1320 /* Extract the sign bit. */
1321 tcg_out_rld(s, RLDICL, arg0, arg1,
1322 type == TCG_TYPE_I64 ? 1 : 33, 63);
1323 return;
1324 default:
1325 break;
1326 }
1327 }
1328
1329 /* If we have ISEL, we can implement everything with 3 or 4 insns.
1330 All other cases below are also at least 3 insns, so speed up the
1331 code generator by not considering them and always using ISEL. */
1332 if (HAVE_ISEL) {
1333 int isel, tab;
1334
1335 tcg_out_cmp(s, cond, arg1, arg2, const_arg2, 7, type);
1336
1337 isel = tcg_to_isel[cond];
1338
1339 tcg_out_movi(s, type, arg0, 1);
1340 if (isel & 1) {
1341 /* arg0 = (bc ? 0 : 1) */
1342 tab = TAB(arg0, 0, arg0);
1343 isel &= ~1;
1344 } else {
1345 /* arg0 = (bc ? 1 : 0) */
1346 tcg_out_movi(s, type, TCG_REG_R0, 0);
1347 tab = TAB(arg0, arg0, TCG_REG_R0);
1348 }
1349 tcg_out32(s, isel | tab);
1350 return;
1351 }
1352
1353 switch (cond) {
1354 case TCG_COND_EQ:
1355 arg1 = tcg_gen_setcond_xor(s, arg1, arg2, const_arg2);
1356 tcg_out_setcond_eq0(s, type, arg0, arg1);
1357 return;
1358
1359 case TCG_COND_NE:
1360 arg1 = tcg_gen_setcond_xor(s, arg1, arg2, const_arg2);
1361 /* Discard the high bits only once, rather than both inputs. */
1362 if (type == TCG_TYPE_I32) {
1363 tcg_out_ext32u(s, TCG_REG_R0, arg1);
1364 arg1 = TCG_REG_R0;
1365 }
1366 tcg_out_setcond_ne0(s, arg0, arg1);
1367 return;
1368
1369 case TCG_COND_GT:
1370 case TCG_COND_GTU:
1371 sh = 30;
1372 crop = 0;
1373 goto crtest;
1374
1375 case TCG_COND_LT:
1376 case TCG_COND_LTU:
1377 sh = 29;
1378 crop = 0;
1379 goto crtest;
1380
1381 case TCG_COND_GE:
1382 case TCG_COND_GEU:
1383 sh = 31;
1384 crop = CRNOR | BT(7, CR_EQ) | BA(7, CR_LT) | BB(7, CR_LT);
1385 goto crtest;
1386
1387 case TCG_COND_LE:
1388 case TCG_COND_LEU:
1389 sh = 31;
1390 crop = CRNOR | BT(7, CR_EQ) | BA(7, CR_GT) | BB(7, CR_GT);
1391 crtest:
1392 tcg_out_cmp(s, cond, arg1, arg2, const_arg2, 7, type);
1393 if (crop) {
1394 tcg_out32(s, crop);
1395 }
1396 tcg_out32(s, MFOCRF | RT(TCG_REG_R0) | FXM(7));
1397 tcg_out_rlw(s, RLWINM, arg0, TCG_REG_R0, sh, 31, 31);
1398 break;
1399
1400 default:
1401 tcg_abort();
1402 }
1403 }
1404
1405 static void tcg_out_bc(TCGContext *s, int bc, int label_index)
1406 {
1407 TCGLabel *l = &s->labels[label_index];
1408
1409 if (l->has_value) {
1410 tcg_out32(s, bc | reloc_pc14_val(s->code_ptr, l->u.value));
1411 } else {
1412 tcg_out_reloc(s, s->code_ptr, R_PPC_REL14, label_index, 0);
1413 tcg_out_bc_noaddr(s, bc);
1414 }
1415 }
1416
1417 static void tcg_out_brcond(TCGContext *s, TCGCond cond,
1418 TCGArg arg1, TCGArg arg2, int const_arg2,
1419 int label_index, TCGType type)
1420 {
1421 tcg_out_cmp(s, cond, arg1, arg2, const_arg2, 7, type);
1422 tcg_out_bc(s, tcg_to_bc[cond], label_index);
1423 }
1424
1425 static void tcg_out_movcond(TCGContext *s, TCGType type, TCGCond cond,
1426 TCGArg dest, TCGArg c1, TCGArg c2, TCGArg v1,
1427 TCGArg v2, bool const_c2)
1428 {
1429 /* If for some reason both inputs are zero, don't produce bad code. */
1430 if (v1 == 0 && v2 == 0) {
1431 tcg_out_movi(s, type, dest, 0);
1432 return;
1433 }
1434
1435 tcg_out_cmp(s, cond, c1, c2, const_c2, 7, type);
1436
1437 if (HAVE_ISEL) {
1438 int isel = tcg_to_isel[cond];
1439
1440 /* Swap the V operands if the operation indicates inversion. */
1441 if (isel & 1) {
1442 int t = v1;
1443 v1 = v2;
1444 v2 = t;
1445 isel &= ~1;
1446 }
1447 /* V1 == 0 is handled by isel; V2 == 0 must be handled by hand. */
1448 if (v2 == 0) {
1449 tcg_out_movi(s, type, TCG_REG_R0, 0);
1450 }
1451 tcg_out32(s, isel | TAB(dest, v1, v2));
1452 } else {
1453 if (dest == v2) {
1454 cond = tcg_invert_cond(cond);
1455 v2 = v1;
1456 } else if (dest != v1) {
1457 if (v1 == 0) {
1458 tcg_out_movi(s, type, dest, 0);
1459 } else {
1460 tcg_out_mov(s, type, dest, v1);
1461 }
1462 }
1463 /* Branch forward over one insn */
1464 tcg_out32(s, tcg_to_bc[cond] | 8);
1465 if (v2 == 0) {
1466 tcg_out_movi(s, type, dest, 0);
1467 } else {
1468 tcg_out_mov(s, type, dest, v2);
1469 }
1470 }
1471 }
1472
1473 void ppc_tb_set_jmp_target(unsigned long jmp_addr, unsigned long addr)
1474 {
1475 TCGContext s;
1476 unsigned long patch_size;
1477
1478 s.code_ptr = (uint8_t *) jmp_addr;
1479 tcg_out_b(&s, 0, addr);
1480 patch_size = s.code_ptr - (uint8_t *) jmp_addr;
1481 flush_icache_range(jmp_addr, jmp_addr + patch_size);
1482 }
1483
1484 static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
1485 const int *const_args)
1486 {
1487 TCGArg a0, a1, a2;
1488 int c;
1489
1490 switch (opc) {
1491 case INDEX_op_exit_tb:
1492 tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_R3, args[0]);
1493 tcg_out_b(s, 0, (tcg_target_long)tb_ret_addr);
1494 break;
1495 case INDEX_op_goto_tb:
1496 if (s->tb_jmp_offset) {
1497 /* Direct jump method. */
1498 s->tb_jmp_offset[args[0]] = s->code_ptr - s->code_buf;
1499 s->code_ptr += 28;
1500 } else {
1501 /* Indirect jump method. */
1502 tcg_abort();
1503 }
1504 s->tb_next_offset[args[0]] = s->code_ptr - s->code_buf;
1505 break;
1506 case INDEX_op_br:
1507 {
1508 TCGLabel *l = &s->labels[args[0]];
1509
1510 if (l->has_value) {
1511 tcg_out_b(s, 0, l->u.value);
1512 } else {
1513 tcg_out_reloc(s, s->code_ptr, R_PPC_REL24, args[0], 0);
1514 tcg_out_b_noaddr(s, B);
1515 }
1516 }
1517 break;
1518 case INDEX_op_call:
1519 tcg_out_call(s, args[0], const_args[0]);
1520 break;
1521 case INDEX_op_movi_i32:
1522 tcg_out_movi(s, TCG_TYPE_I32, args[0], args[1]);
1523 break;
1524 case INDEX_op_movi_i64:
1525 tcg_out_movi(s, TCG_TYPE_I64, args[0], args[1]);
1526 break;
1527 case INDEX_op_ld8u_i32:
1528 case INDEX_op_ld8u_i64:
1529 tcg_out_mem_long(s, LBZ, LBZX, args[0], args[1], args[2]);
1530 break;
1531 case INDEX_op_ld8s_i32:
1532 case INDEX_op_ld8s_i64:
1533 tcg_out_mem_long(s, LBZ, LBZX, args[0], args[1], args[2]);
1534 tcg_out32(s, EXTSB | RS(args[0]) | RA(args[0]));
1535 break;
1536 case INDEX_op_ld16u_i32:
1537 case INDEX_op_ld16u_i64:
1538 tcg_out_mem_long(s, LHZ, LHZX, args[0], args[1], args[2]);
1539 break;
1540 case INDEX_op_ld16s_i32:
1541 case INDEX_op_ld16s_i64:
1542 tcg_out_mem_long(s, LHA, LHAX, args[0], args[1], args[2]);
1543 break;
1544 case INDEX_op_ld_i32:
1545 case INDEX_op_ld32u_i64:
1546 tcg_out_mem_long(s, LWZ, LWZX, args[0], args[1], args[2]);
1547 break;
1548 case INDEX_op_ld32s_i64:
1549 tcg_out_mem_long(s, LWA, LWAX, args[0], args[1], args[2]);
1550 break;
1551 case INDEX_op_ld_i64:
1552 tcg_out_mem_long(s, LD, LDX, args[0], args[1], args[2]);
1553 break;
1554 case INDEX_op_st8_i32:
1555 case INDEX_op_st8_i64:
1556 tcg_out_mem_long(s, STB, STBX, args[0], args[1], args[2]);
1557 break;
1558 case INDEX_op_st16_i32:
1559 case INDEX_op_st16_i64:
1560 tcg_out_mem_long(s, STH, STHX, args[0], args[1], args[2]);
1561 break;
1562 case INDEX_op_st_i32:
1563 case INDEX_op_st32_i64:
1564 tcg_out_mem_long(s, STW, STWX, args[0], args[1], args[2]);
1565 break;
1566 case INDEX_op_st_i64:
1567 tcg_out_mem_long(s, STD, STDX, args[0], args[1], args[2]);
1568 break;
1569
1570 case INDEX_op_add_i32:
1571 a0 = args[0], a1 = args[1], a2 = args[2];
1572 if (const_args[2]) {
1573 do_addi_32:
1574 tcg_out_mem_long(s, ADDI, ADD, a0, a1, (int32_t)a2);
1575 } else {
1576 tcg_out32(s, ADD | TAB(a0, a1, a2));
1577 }
1578 break;
1579 case INDEX_op_sub_i32:
1580 a0 = args[0], a1 = args[1], a2 = args[2];
1581 if (const_args[1]) {
1582 if (const_args[2]) {
1583 tcg_out_movi(s, TCG_TYPE_I32, a0, a1 - a2);
1584 } else {
1585 tcg_out32(s, SUBFIC | TAI(a0, a2, a1));
1586 }
1587 } else if (const_args[2]) {
1588 a2 = -a2;
1589 goto do_addi_32;
1590 } else {
1591 tcg_out32(s, SUBF | TAB(a0, a2, a1));
1592 }
1593 break;
1594
1595 case INDEX_op_and_i32:
1596 a0 = args[0], a1 = args[1], a2 = args[2];
1597 if (const_args[2]) {
1598 tcg_out_andi32(s, a0, a1, a2);
1599 } else {
1600 tcg_out32(s, AND | SAB(a1, a0, a2));
1601 }
1602 break;
1603 case INDEX_op_and_i64:
1604 a0 = args[0], a1 = args[1], a2 = args[2];
1605 if (const_args[2]) {
1606 tcg_out_andi64(s, a0, a1, a2);
1607 } else {
1608 tcg_out32(s, AND | SAB(a1, a0, a2));
1609 }
1610 break;
1611 case INDEX_op_or_i64:
1612 case INDEX_op_or_i32:
1613 a0 = args[0], a1 = args[1], a2 = args[2];
1614 if (const_args[2]) {
1615 tcg_out_ori32(s, a0, a1, a2);
1616 } else {
1617 tcg_out32(s, OR | SAB(a1, a0, a2));
1618 }
1619 break;
1620 case INDEX_op_xor_i64:
1621 case INDEX_op_xor_i32:
1622 a0 = args[0], a1 = args[1], a2 = args[2];
1623 if (const_args[2]) {
1624 tcg_out_xori32(s, a0, a1, a2);
1625 } else {
1626 tcg_out32(s, XOR | SAB(a1, a0, a2));
1627 }
1628 break;
1629 case INDEX_op_andc_i32:
1630 a0 = args[0], a1 = args[1], a2 = args[2];
1631 if (const_args[2]) {
1632 tcg_out_andi32(s, a0, a1, ~a2);
1633 } else {
1634 tcg_out32(s, ANDC | SAB(a1, a0, a2));
1635 }
1636 break;
1637 case INDEX_op_andc_i64:
1638 a0 = args[0], a1 = args[1], a2 = args[2];
1639 if (const_args[2]) {
1640 tcg_out_andi64(s, a0, a1, ~a2);
1641 } else {
1642 tcg_out32(s, ANDC | SAB(a1, a0, a2));
1643 }
1644 break;
1645 case INDEX_op_orc_i32:
1646 if (const_args[2]) {
1647 tcg_out_ori32(s, args[0], args[1], ~args[2]);
1648 break;
1649 }
1650 /* FALLTHRU */
1651 case INDEX_op_orc_i64:
1652 tcg_out32(s, ORC | SAB(args[1], args[0], args[2]));
1653 break;
1654 case INDEX_op_eqv_i32:
1655 if (const_args[2]) {
1656 tcg_out_xori32(s, args[0], args[1], ~args[2]);
1657 break;
1658 }
1659 /* FALLTHRU */
1660 case INDEX_op_eqv_i64:
1661 tcg_out32(s, EQV | SAB(args[1], args[0], args[2]));
1662 break;
1663 case INDEX_op_nand_i32:
1664 case INDEX_op_nand_i64:
1665 tcg_out32(s, NAND | SAB(args[1], args[0], args[2]));
1666 break;
1667 case INDEX_op_nor_i32:
1668 case INDEX_op_nor_i64:
1669 tcg_out32(s, NOR | SAB(args[1], args[0], args[2]));
1670 break;
1671
1672 case INDEX_op_mul_i32:
1673 a0 = args[0], a1 = args[1], a2 = args[2];
1674 if (const_args[2]) {
1675 tcg_out32(s, MULLI | TAI(a0, a1, a2));
1676 } else {
1677 tcg_out32(s, MULLW | TAB(a0, a1, a2));
1678 }
1679 break;
1680
1681 case INDEX_op_div_i32:
1682 tcg_out32(s, DIVW | TAB(args[0], args[1], args[2]));
1683 break;
1684
1685 case INDEX_op_divu_i32:
1686 tcg_out32(s, DIVWU | TAB(args[0], args[1], args[2]));
1687 break;
1688
1689 case INDEX_op_shl_i32:
1690 if (const_args[2]) {
1691 tcg_out_rlw(s, RLWINM, args[0], args[1], args[2], 0, 31 - args[2]);
1692 } else {
1693 tcg_out32(s, SLW | SAB(args[1], args[0], args[2]));
1694 }
1695 break;
1696 case INDEX_op_shr_i32:
1697 if (const_args[2]) {
1698 tcg_out_rlw(s, RLWINM, args[0], args[1], 32 - args[2], args[2], 31);
1699 } else {
1700 tcg_out32(s, SRW | SAB(args[1], args[0], args[2]));
1701 }
1702 break;
1703 case INDEX_op_sar_i32:
1704 if (const_args[2]) {
1705 tcg_out32(s, SRAWI | RS(args[1]) | RA(args[0]) | SH(args[2]));
1706 } else {
1707 tcg_out32(s, SRAW | SAB(args[1], args[0], args[2]));
1708 }
1709 break;
1710 case INDEX_op_rotl_i32:
1711 if (const_args[2]) {
1712 tcg_out_rlw(s, RLWINM, args[0], args[1], args[2], 0, 31);
1713 } else {
1714 tcg_out32(s, RLWNM | SAB(args[1], args[0], args[2])
1715 | MB(0) | ME(31));
1716 }
1717 break;
1718 case INDEX_op_rotr_i32:
1719 if (const_args[2]) {
1720 tcg_out_rlw(s, RLWINM, args[0], args[1], 32 - args[2], 0, 31);
1721 } else {
1722 tcg_out32(s, SUBFIC | TAI(TCG_REG_R0, args[2], 32));
1723 tcg_out32(s, RLWNM | SAB(args[1], args[0], TCG_REG_R0)
1724 | MB(0) | ME(31));
1725 }
1726 break;
1727
1728 case INDEX_op_brcond_i32:
1729 tcg_out_brcond(s, args[2], args[0], args[1], const_args[1],
1730 args[3], TCG_TYPE_I32);
1731 break;
1732
1733 case INDEX_op_brcond_i64:
1734 tcg_out_brcond(s, args[2], args[0], args[1], const_args[1],
1735 args[3], TCG_TYPE_I64);
1736 break;
1737
1738 case INDEX_op_neg_i32:
1739 case INDEX_op_neg_i64:
1740 tcg_out32(s, NEG | RT(args[0]) | RA(args[1]));
1741 break;
1742
1743 case INDEX_op_not_i32:
1744 case INDEX_op_not_i64:
1745 tcg_out32(s, NOR | SAB(args[1], args[0], args[1]));
1746 break;
1747
1748 case INDEX_op_add_i64:
1749 a0 = args[0], a1 = args[1], a2 = args[2];
1750 if (const_args[2]) {
1751 do_addi_64:
1752 tcg_out_mem_long(s, ADDI, ADD, a0, a1, a2);
1753 } else {
1754 tcg_out32(s, ADD | TAB(a0, a1, a2));
1755 }
1756 break;
1757 case INDEX_op_sub_i64:
1758 a0 = args[0], a1 = args[1], a2 = args[2];
1759 if (const_args[1]) {
1760 if (const_args[2]) {
1761 tcg_out_movi(s, TCG_TYPE_I64, a0, a1 - a2);
1762 } else {
1763 tcg_out32(s, SUBFIC | TAI(a0, a2, a1));
1764 }
1765 } else if (const_args[2]) {
1766 a2 = -a2;
1767 goto do_addi_64;
1768 } else {
1769 tcg_out32(s, SUBF | TAB(a0, a2, a1));
1770 }
1771 break;
1772
1773 case INDEX_op_shl_i64:
1774 if (const_args[2]) {
1775 tcg_out_shli64(s, args[0], args[1], args[2]);
1776 } else {
1777 tcg_out32(s, SLD | SAB(args[1], args[0], args[2]));
1778 }
1779 break;
1780 case INDEX_op_shr_i64:
1781 if (const_args[2]) {
1782 tcg_out_shri64(s, args[0], args[1], args[2]);
1783 } else {
1784 tcg_out32(s, SRD | SAB(args[1], args[0], args[2]));
1785 }
1786 break;
1787 case INDEX_op_sar_i64:
1788 if (const_args[2]) {
1789 int sh = SH(args[2] & 0x1f) | (((args[2] >> 5) & 1) << 1);
1790 tcg_out32(s, SRADI | RA(args[0]) | RS(args[1]) | sh);
1791 } else {
1792 tcg_out32(s, SRAD | SAB(args[1], args[0], args[2]));
1793 }
1794 break;
1795 case INDEX_op_rotl_i64:
1796 if (const_args[2]) {
1797 tcg_out_rld(s, RLDICL, args[0], args[1], args[2], 0);
1798 } else {
1799 tcg_out32(s, RLDCL | SAB(args[1], args[0], args[2]) | MB64(0));
1800 }
1801 break;
1802 case INDEX_op_rotr_i64:
1803 if (const_args[2]) {
1804 tcg_out_rld(s, RLDICL, args[0], args[1], 64 - args[2], 0);
1805 } else {
1806 tcg_out32(s, SUBFIC | TAI(TCG_REG_R0, args[2], 64));
1807 tcg_out32(s, RLDCL | SAB(args[1], args[0], TCG_REG_R0) | MB64(0));
1808 }
1809 break;
1810
1811 case INDEX_op_mul_i64:
1812 a0 = args[0], a1 = args[1], a2 = args[2];
1813 if (const_args[2]) {
1814 tcg_out32(s, MULLI | TAI(a0, a1, a2));
1815 } else {
1816 tcg_out32(s, MULLD | TAB(a0, a1, a2));
1817 }
1818 break;
1819 case INDEX_op_div_i64:
1820 tcg_out32(s, DIVD | TAB(args[0], args[1], args[2]));
1821 break;
1822 case INDEX_op_divu_i64:
1823 tcg_out32(s, DIVDU | TAB(args[0], args[1], args[2]));
1824 break;
1825
1826 case INDEX_op_qemu_ld_i32:
1827 case INDEX_op_qemu_ld_i64:
1828 tcg_out_qemu_ld(s, args[0], args[1], args[2], args[3]);
1829 break;
1830 case INDEX_op_qemu_st_i32:
1831 case INDEX_op_qemu_st_i64:
1832 tcg_out_qemu_st(s, args[0], args[1], args[2], args[3]);
1833 break;
1834
1835 case INDEX_op_ext8s_i32:
1836 case INDEX_op_ext8s_i64:
1837 c = EXTSB;
1838 goto gen_ext;
1839 case INDEX_op_ext16s_i32:
1840 case INDEX_op_ext16s_i64:
1841 c = EXTSH;
1842 goto gen_ext;
1843 case INDEX_op_ext32s_i64:
1844 c = EXTSW;
1845 goto gen_ext;
1846 gen_ext:
1847 tcg_out32(s, c | RS(args[1]) | RA(args[0]));
1848 break;
1849
1850 case INDEX_op_setcond_i32:
1851 tcg_out_setcond(s, TCG_TYPE_I32, args[3], args[0], args[1], args[2],
1852 const_args[2]);
1853 break;
1854 case INDEX_op_setcond_i64:
1855 tcg_out_setcond(s, TCG_TYPE_I64, args[3], args[0], args[1], args[2],
1856 const_args[2]);
1857 break;
1858
1859 case INDEX_op_bswap16_i32:
1860 case INDEX_op_bswap16_i64:
1861 a0 = args[0], a1 = args[1];
1862 /* a1 = abcd */
1863 if (a0 != a1) {
1864 /* a0 = (a1 r<< 24) & 0xff # 000c */
1865 tcg_out_rlw(s, RLWINM, a0, a1, 24, 24, 31);
1866 /* a0 = (a0 & ~0xff00) | (a1 r<< 8) & 0xff00 # 00dc */
1867 tcg_out_rlw(s, RLWIMI, a0, a1, 8, 16, 23);
1868 } else {
1869 /* r0 = (a1 r<< 8) & 0xff00 # 00d0 */
1870 tcg_out_rlw(s, RLWINM, TCG_REG_R0, a1, 8, 16, 23);
1871 /* a0 = (a1 r<< 24) & 0xff # 000c */
1872 tcg_out_rlw(s, RLWINM, a0, a1, 24, 24, 31);
1873 /* a0 = a0 | r0 # 00dc */
1874 tcg_out32(s, OR | SAB(TCG_REG_R0, a0, a0));
1875 }
1876 break;
1877
1878 case INDEX_op_bswap32_i32:
1879 case INDEX_op_bswap32_i64:
1880 /* Stolen from gcc's builtin_bswap32 */
1881 a1 = args[1];
1882 a0 = args[0] == a1 ? TCG_REG_R0 : args[0];
1883
1884 /* a1 = args[1] # abcd */
1885 /* a0 = rotate_left (a1, 8) # bcda */
1886 tcg_out_rlw(s, RLWINM, a0, a1, 8, 0, 31);
1887 /* a0 = (a0 & ~0xff000000) | ((a1 r<< 24) & 0xff000000) # dcda */
1888 tcg_out_rlw(s, RLWIMI, a0, a1, 24, 0, 7);
1889 /* a0 = (a0 & ~0x0000ff00) | ((a1 r<< 24) & 0x0000ff00) # dcba */
1890 tcg_out_rlw(s, RLWIMI, a0, a1, 24, 16, 23);
1891
1892 if (a0 == TCG_REG_R0) {
1893 tcg_out_mov(s, TCG_TYPE_I64, args[0], a0);
1894 }
1895 break;
1896
1897 case INDEX_op_bswap64_i64:
1898 a0 = args[0], a1 = args[1], a2 = TCG_REG_R0;
1899 if (a0 == a1) {
1900 a0 = TCG_REG_R0;
1901 a2 = a1;
1902 }
1903
1904 /* a1 = # abcd efgh */
1905 /* a0 = rl32(a1, 8) # 0000 fghe */
1906 tcg_out_rlw(s, RLWINM, a0, a1, 8, 0, 31);
1907 /* a0 = dep(a0, rl32(a1, 24), 0xff000000) # 0000 hghe */
1908 tcg_out_rlw(s, RLWIMI, a0, a1, 24, 0, 7);
1909 /* a0 = dep(a0, rl32(a1, 24), 0x0000ff00) # 0000 hgfe */
1910 tcg_out_rlw(s, RLWIMI, a0, a1, 24, 16, 23);
1911
1912 /* a0 = rl64(a0, 32) # hgfe 0000 */
1913 /* a2 = rl64(a1, 32) # efgh abcd */
1914 tcg_out_rld(s, RLDICL, a0, a0, 32, 0);
1915 tcg_out_rld(s, RLDICL, a2, a1, 32, 0);
1916
1917 /* a0 = dep(a0, rl32(a2, 8), 0xffffffff) # hgfe bcda */
1918 tcg_out_rlw(s, RLWIMI, a0, a2, 8, 0, 31);
1919 /* a0 = dep(a0, rl32(a2, 24), 0xff000000) # hgfe dcda */
1920 tcg_out_rlw(s, RLWIMI, a0, a2, 24, 0, 7);
1921 /* a0 = dep(a0, rl32(a2, 24), 0x0000ff00) # hgfe dcba */
1922 tcg_out_rlw(s, RLWIMI, a0, a2, 24, 16, 23);
1923
1924 if (a0 == 0) {
1925 tcg_out_mov(s, TCG_TYPE_I64, args[0], a0);
1926 }
1927 break;
1928
1929 case INDEX_op_deposit_i32:
1930 if (const_args[2]) {
1931 uint32_t mask = ((2u << (args[4] - 1)) - 1) << args[3];
1932 tcg_out_andi32(s, args[0], args[0], ~mask);
1933 } else {
1934 tcg_out_rlw(s, RLWIMI, args[0], args[2], args[3],
1935 32 - args[3] - args[4], 31 - args[3]);
1936 }
1937 break;
1938 case INDEX_op_deposit_i64:
1939 if (const_args[2]) {
1940 uint64_t mask = ((2ull << (args[4] - 1)) - 1) << args[3];
1941 tcg_out_andi64(s, args[0], args[0], ~mask);
1942 } else {
1943 tcg_out_rld(s, RLDIMI, args[0], args[2], args[3],
1944 64 - args[3] - args[4]);
1945 }
1946 break;
1947
1948 case INDEX_op_movcond_i32:
1949 tcg_out_movcond(s, TCG_TYPE_I32, args[5], args[0], args[1], args[2],
1950 args[3], args[4], const_args[2]);
1951 break;
1952 case INDEX_op_movcond_i64:
1953 tcg_out_movcond(s, TCG_TYPE_I64, args[5], args[0], args[1], args[2],
1954 args[3], args[4], const_args[2]);
1955 break;
1956
1957 case INDEX_op_add2_i64:
1958 /* Note that the CA bit is defined based on the word size of the
1959 environment. So in 64-bit mode it's always carry-out of bit 63.
1960 The fallback code using deposit works just as well for 32-bit. */
1961 a0 = args[0], a1 = args[1];
1962 if (a0 == args[3] || (!const_args[5] && a0 == args[5])) {
1963 a0 = TCG_REG_R0;
1964 }
1965 if (const_args[4]) {
1966 tcg_out32(s, ADDIC | TAI(a0, args[2], args[4]));
1967 } else {
1968 tcg_out32(s, ADDC | TAB(a0, args[2], args[4]));
1969 }
1970 if (const_args[5]) {
1971 tcg_out32(s, (args[5] ? ADDME : ADDZE) | RT(a1) | RA(args[3]));
1972 } else {
1973 tcg_out32(s, ADDE | TAB(a1, args[3], args[5]));
1974 }
1975 if (a0 != args[0]) {
1976 tcg_out_mov(s, TCG_TYPE_I64, args[0], a0);
1977 }
1978 break;
1979
1980 case INDEX_op_sub2_i64:
1981 a0 = args[0], a1 = args[1];
1982 if (a0 == args[5] || (!const_args[4] && a0 == args[4])) {
1983 a0 = TCG_REG_R0;
1984 }
1985 if (const_args[2]) {
1986 tcg_out32(s, SUBFIC | TAI(a0, args[3], args[2]));
1987 } else {
1988 tcg_out32(s, SUBFC | TAB(a0, args[3], args[2]));
1989 }
1990 if (const_args[4]) {
1991 tcg_out32(s, (args[4] ? SUBFME : SUBFZE) | RT(a1) | RA(args[5]));
1992 } else {
1993 tcg_out32(s, SUBFE | TAB(a1, args[5], args[4]));
1994 }
1995 if (a0 != args[0]) {
1996 tcg_out_mov(s, TCG_TYPE_I64, args[0], a0);
1997 }
1998 break;
1999
2000 case INDEX_op_muluh_i64:
2001 tcg_out32(s, MULHDU | TAB(args[0], args[1], args[2]));
2002 break;
2003 case INDEX_op_mulsh_i64:
2004 tcg_out32(s, MULHD | TAB(args[0], args[1], args[2]));
2005 break;
2006
2007 default:
2008 tcg_dump_ops(s);
2009 tcg_abort();
2010 }
2011 }
2012
2013 static const TCGTargetOpDef ppc_op_defs[] = {
2014 { INDEX_op_exit_tb, { } },
2015 { INDEX_op_goto_tb, { } },
2016 { INDEX_op_call, { "ri" } },
2017 { INDEX_op_br, { } },
2018
2019 { INDEX_op_mov_i32, { "r", "r" } },
2020 { INDEX_op_mov_i64, { "r", "r" } },
2021 { INDEX_op_movi_i32, { "r" } },
2022 { INDEX_op_movi_i64, { "r" } },
2023
2024 { INDEX_op_ld8u_i32, { "r", "r" } },
2025 { INDEX_op_ld8s_i32, { "r", "r" } },
2026 { INDEX_op_ld16u_i32, { "r", "r" } },
2027 { INDEX_op_ld16s_i32, { "r", "r" } },
2028 { INDEX_op_ld_i32, { "r", "r" } },
2029 { INDEX_op_ld_i64, { "r", "r" } },
2030 { INDEX_op_st8_i32, { "r", "r" } },
2031 { INDEX_op_st8_i64, { "r", "r" } },
2032 { INDEX_op_st16_i32, { "r", "r" } },
2033 { INDEX_op_st16_i64, { "r", "r" } },
2034 { INDEX_op_st_i32, { "r", "r" } },
2035 { INDEX_op_st_i64, { "r", "r" } },
2036 { INDEX_op_st32_i64, { "r", "r" } },
2037
2038 { INDEX_op_ld8u_i64, { "r", "r" } },
2039 { INDEX_op_ld8s_i64, { "r", "r" } },
2040 { INDEX_op_ld16u_i64, { "r", "r" } },
2041 { INDEX_op_ld16s_i64, { "r", "r" } },
2042 { INDEX_op_ld32u_i64, { "r", "r" } },
2043 { INDEX_op_ld32s_i64, { "r", "r" } },
2044
2045 { INDEX_op_add_i32, { "r", "r", "ri" } },
2046 { INDEX_op_mul_i32, { "r", "r", "rI" } },
2047 { INDEX_op_div_i32, { "r", "r", "r" } },
2048 { INDEX_op_divu_i32, { "r", "r", "r" } },
2049 { INDEX_op_sub_i32, { "r", "rI", "ri" } },
2050 { INDEX_op_and_i32, { "r", "r", "ri" } },
2051 { INDEX_op_or_i32, { "r", "r", "ri" } },
2052 { INDEX_op_xor_i32, { "r", "r", "ri" } },
2053 { INDEX_op_andc_i32, { "r", "r", "ri" } },
2054 { INDEX_op_orc_i32, { "r", "r", "ri" } },
2055 { INDEX_op_eqv_i32, { "r", "r", "ri" } },
2056 { INDEX_op_nand_i32, { "r", "r", "r" } },
2057 { INDEX_op_nor_i32, { "r", "r", "r" } },
2058
2059 { INDEX_op_shl_i32, { "r", "r", "ri" } },
2060 { INDEX_op_shr_i32, { "r", "r", "ri" } },
2061 { INDEX_op_sar_i32, { "r", "r", "ri" } },
2062 { INDEX_op_rotl_i32, { "r", "r", "ri" } },
2063 { INDEX_op_rotr_i32, { "r", "r", "ri" } },
2064
2065 { INDEX_op_brcond_i32, { "r", "ri" } },
2066 { INDEX_op_brcond_i64, { "r", "ri" } },
2067
2068 { INDEX_op_neg_i32, { "r", "r" } },
2069 { INDEX_op_not_i32, { "r", "r" } },
2070
2071 { INDEX_op_add_i64, { "r", "r", "rT" } },
2072 { INDEX_op_sub_i64, { "r", "rI", "rT" } },
2073 { INDEX_op_and_i64, { "r", "r", "ri" } },
2074 { INDEX_op_or_i64, { "r", "r", "rU" } },
2075 { INDEX_op_xor_i64, { "r", "r", "rU" } },
2076 { INDEX_op_andc_i64, { "r", "r", "ri" } },
2077 { INDEX_op_orc_i64, { "r", "r", "r" } },
2078 { INDEX_op_eqv_i64, { "r", "r", "r" } },
2079 { INDEX_op_nand_i64, { "r", "r", "r" } },
2080 { INDEX_op_nor_i64, { "r", "r", "r" } },
2081
2082 { INDEX_op_shl_i64, { "r", "r", "ri" } },
2083 { INDEX_op_shr_i64, { "r", "r", "ri" } },
2084 { INDEX_op_sar_i64, { "r", "r", "ri" } },
2085 { INDEX_op_rotl_i64, { "r", "r", "ri" } },
2086 { INDEX_op_rotr_i64, { "r", "r", "ri" } },
2087
2088 { INDEX_op_mul_i64, { "r", "r", "rI" } },
2089 { INDEX_op_div_i64, { "r", "r", "r" } },
2090 { INDEX_op_divu_i64, { "r", "r", "r" } },
2091
2092 { INDEX_op_neg_i64, { "r", "r" } },
2093 { INDEX_op_not_i64, { "r", "r" } },
2094
2095 { INDEX_op_qemu_ld_i32, { "r", "L" } },
2096 { INDEX_op_qemu_ld_i64, { "r", "L" } },
2097 { INDEX_op_qemu_st_i32, { "S", "S" } },
2098 { INDEX_op_qemu_st_i64, { "S", "S" } },
2099
2100 { INDEX_op_ext8s_i32, { "r", "r" } },
2101 { INDEX_op_ext16s_i32, { "r", "r" } },
2102 { INDEX_op_ext8s_i64, { "r", "r" } },
2103 { INDEX_op_ext16s_i64, { "r", "r" } },
2104 { INDEX_op_ext32s_i64, { "r", "r" } },
2105
2106 { INDEX_op_setcond_i32, { "r", "r", "ri" } },
2107 { INDEX_op_setcond_i64, { "r", "r", "ri" } },
2108 { INDEX_op_movcond_i32, { "r", "r", "ri", "rZ", "rZ" } },
2109 { INDEX_op_movcond_i64, { "r", "r", "ri", "rZ", "rZ" } },
2110
2111 { INDEX_op_bswap16_i32, { "r", "r" } },
2112 { INDEX_op_bswap16_i64, { "r", "r" } },
2113 { INDEX_op_bswap32_i32, { "r", "r" } },
2114 { INDEX_op_bswap32_i64, { "r", "r" } },
2115 { INDEX_op_bswap64_i64, { "r", "r" } },
2116
2117 { INDEX_op_deposit_i32, { "r", "0", "rZ" } },
2118 { INDEX_op_deposit_i64, { "r", "0", "rZ" } },
2119
2120 { INDEX_op_add2_i64, { "r", "r", "r", "r", "rI", "rZM" } },
2121 { INDEX_op_sub2_i64, { "r", "r", "rI", "r", "rZM", "r" } },
2122 { INDEX_op_mulsh_i64, { "r", "r", "r" } },
2123 { INDEX_op_muluh_i64, { "r", "r", "r" } },
2124
2125 { -1 },
2126 };
2127
2128 static void tcg_target_init(TCGContext *s)
2129 {
2130 unsigned long hwcap = qemu_getauxval(AT_HWCAP);
2131 if (hwcap & PPC_FEATURE_ARCH_2_06) {
2132 have_isa_2_06 = true;
2133 }
2134
2135 tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffffffff);
2136 tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I64], 0, 0xffffffff);
2137 tcg_regset_set32(tcg_target_call_clobber_regs, 0,
2138 (1 << TCG_REG_R0) |
2139 (1 << TCG_REG_R2) |
2140 (1 << TCG_REG_R3) |
2141 (1 << TCG_REG_R4) |
2142 (1 << TCG_REG_R5) |
2143 (1 << TCG_REG_R6) |
2144 (1 << TCG_REG_R7) |
2145 (1 << TCG_REG_R8) |
2146 (1 << TCG_REG_R9) |
2147 (1 << TCG_REG_R10) |
2148 (1 << TCG_REG_R11) |
2149 (1 << TCG_REG_R12));
2150
2151 tcg_regset_clear(s->reserved_regs);
2152 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R0); /* tcg temp */
2153 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R1); /* stack pointer */
2154 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R2); /* mem temp */
2155 #ifdef __APPLE__
2156 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R11); /* ??? */
2157 #endif
2158 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R13); /* thread pointer */
2159
2160 tcg_add_target_add_op_defs(ppc_op_defs);
2161 }
2162
2163 typedef struct {
2164 DebugFrameCIE cie;
2165 DebugFrameFDEHeader fde;
2166 uint8_t fde_def_cfa[4];
2167 uint8_t fde_reg_ofs[ARRAY_SIZE(tcg_target_callee_save_regs) * 2 + 3];
2168 } DebugFrame;
2169
2170 /* We're expecting a 2 byte uleb128 encoded value. */
2171 QEMU_BUILD_BUG_ON(FRAME_SIZE >= (1 << 14));
2172
2173 #define ELF_HOST_MACHINE EM_PPC64
2174
2175 static DebugFrame debug_frame = {
2176 .cie.len = sizeof(DebugFrameCIE)-4, /* length after .len member */
2177 .cie.id = -1,
2178 .cie.version = 1,
2179 .cie.code_align = 1,
2180 .cie.data_align = 0x78, /* sleb128 -8 */
2181 .cie.return_column = 65,
2182
2183 /* Total FDE size does not include the "len" member. */
2184 .fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, fde.cie_offset),
2185
2186 .fde_def_cfa = {
2187 12, 1, /* DW_CFA_def_cfa r1, ... */
2188 (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */
2189 (FRAME_SIZE >> 7)
2190 },
2191 .fde_reg_ofs = {
2192 0x11, 65, 0x7e, /* DW_CFA_offset_extended_sf, lr, 16 */
2193 }
2194 };
2195
2196 void tcg_register_jit(void *buf, size_t buf_size)
2197 {
2198 uint8_t *p = &debug_frame.fde_reg_ofs[3];
2199 int i;
2200
2201 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); ++i, p += 2) {
2202 p[0] = 0x80 + tcg_target_callee_save_regs[i];
2203 p[1] = (FRAME_SIZE - (REG_SAVE_BOT + i * 8)) / 8;
2204 }
2205
2206 debug_frame.fde.func_start = (tcg_target_long) buf;
2207 debug_frame.fde.func_len = buf_size;
2208
2209 tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame));
2210 }
QEmu