target-ppc/mmu-hash64.c

   1 /*
   2  *  PowerPC MMU, TLB, SLB and BAT emulation helpers for QEMU.
   3  *
   4  *  Copyright (c) 2003-2007 Jocelyn Mayer
   5  *  Copyright (c) 2013 David Gibson, IBM Corporation
   6  *
   7  * This library is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU Lesser General Public
   9  * License as published by the Free Software Foundation; either
  10  * version 2 of the License, or (at your option) any later version.
  11  *
  12  * This library is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * Lesser General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU Lesser General Public
  18  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  19  */
  20 #include "qemu/osdep.h"
  21 #include "qapi/error.h"
  22 #include "cpu.h"
  23 #include "exec/exec-all.h"
  24 #include "exec/helper-proto.h"
  25 #include "qemu/error-report.h"
  26 #include "sysemu/kvm.h"
  27 #include "qemu/error-report.h"
  28 #include "kvm_ppc.h"
  29 #include "mmu-hash64.h"
  30 #include "exec/log.h"
  31
  32 //#define DEBUG_SLB
  33
  34 #ifdef DEBUG_SLB
  35 #  define LOG_SLB(...) qemu_log_mask(CPU_LOG_MMU, __VA_ARGS__)
  36 #else
  37 #  define LOG_SLB(...) do { } while (0)
  38 #endif
  39
  40 /*
  41  * Used to indicate that a CPU has its hash page table (HPT) managed
  42  * within the host kernel
  43  */
  44 #define MMU_HASH64_KVM_MANAGED_HPT      ((void *)-1)
  45
  46 /*
  47  * SLB handling
  48  */
  49
  50 static ppc_slb_t *slb_lookup(PowerPCCPU *cpu, target_ulong eaddr)
  51 {
  52     CPUPPCState *env = &cpu->env;
  53     uint64_t esid_256M, esid_1T;
  54     int n;
  55
  56     LOG_SLB("%s: eaddr " TARGET_FMT_lx "\n", __func__, eaddr);
  57
  58     esid_256M = (eaddr & SEGMENT_MASK_256M) | SLB_ESID_V;
  59     esid_1T = (eaddr & SEGMENT_MASK_1T) | SLB_ESID_V;
  60
  61     for (n = 0; n < env->slb_nr; n++) {
  62         ppc_slb_t *slb = &env->slb[n];
  63
  64         LOG_SLB("%s: slot %d %016" PRIx64 " %016"
  65                     PRIx64 "\n", __func__, n, slb->esid, slb->vsid);
  66         /* We check for 1T matches on all MMUs here - if the MMU
  67          * doesn't have 1T segment support, we will have prevented 1T
  68          * entries from being inserted in the slbmte code. */
  69         if (((slb->esid == esid_256M) &&
  70              ((slb->vsid & SLB_VSID_B) == SLB_VSID_B_256M))
  71             || ((slb->esid == esid_1T) &&
  72                 ((slb->vsid & SLB_VSID_B) == SLB_VSID_B_1T))) {
  73             return slb;
  74         }
  75     }
  76
  77     return NULL;
  78 }
  79
  80 void dump_slb(FILE *f, fprintf_function cpu_fprintf, PowerPCCPU *cpu)
  81 {
  82     CPUPPCState *env = &cpu->env;
  83     int i;
  84     uint64_t slbe, slbv;
  85
  86     cpu_synchronize_state(CPU(cpu));
  87
  88     cpu_fprintf(f, "SLB\tESID\t\t\tVSID\n");
  89     for (i = 0; i < env->slb_nr; i++) {
  90         slbe = env->slb[i].esid;
  91         slbv = env->slb[i].vsid;
  92         if (slbe == 0 && slbv == 0) {
  93             continue;
  94         }
  95         cpu_fprintf(f, "%d\t0x%016" PRIx64 "\t0x%016" PRIx64 "\n",
  96                     i, slbe, slbv);
  97     }
  98 }
  99
 100 void helper_slbia(CPUPPCState *env)
 101 {
 102     int n;
 103
 104     /* XXX: Warning: slbia never invalidates the first segment */
 105     for (n = 1; n < env->slb_nr; n++) {
 106         ppc_slb_t *slb = &env->slb[n];
 107
 108         if (slb->esid & SLB_ESID_V) {
 109             slb->esid &= ~SLB_ESID_V;
 110             /* XXX: given the fact that segment size is 256 MB or 1TB,
 111              *      and we still don't have a tlb_flush_mask(env, n, mask)
 112              *      in QEMU, we just invalidate all TLBs
 113              */
 114             env->tlb_need_flush = 1;
 115         }
 116     }
 117 }
 118
 119 void helper_slbie(CPUPPCState *env, target_ulong addr)
 120 {
 121     PowerPCCPU *cpu = ppc_env_get_cpu(env);
 122     ppc_slb_t *slb;
 123
 124     slb = slb_lookup(cpu, addr);
 125     if (!slb) {
 126         return;
 127     }
 128
 129     if (slb->esid & SLB_ESID_V) {
 130         slb->esid &= ~SLB_ESID_V;
 131
 132         /* XXX: given the fact that segment size is 256 MB or 1TB,
 133          *      and we still don't have a tlb_flush_mask(env, n, mask)
 134          *      in QEMU, we just invalidate all TLBs
 135          */
 136         env->tlb_need_flush = 1;
 137     }
 138 }
 139
 140 int ppc_store_slb(PowerPCCPU *cpu, target_ulong slot,
 141                   target_ulong esid, target_ulong vsid)
 142 {
 143     CPUPPCState *env = &cpu->env;
 144     ppc_slb_t *slb = &env->slb[slot];
 145     const struct ppc_one_seg_page_size *sps = NULL;
 146     int i;
 147
 148     if (slot >= env->slb_nr) {
 149         return -1; /* Bad slot number */
 150     }
 151     if (esid & ~(SLB_ESID_ESID | SLB_ESID_V)) {
 152         return -1; /* Reserved bits set */
 153     }
 154     if (vsid & (SLB_VSID_B & ~SLB_VSID_B_1T)) {
 155         return -1; /* Bad segment size */
 156     }
 157     if ((vsid & SLB_VSID_B) && !(env->mmu_model & POWERPC_MMU_1TSEG)) {
 158         return -1; /* 1T segment on MMU that doesn't support it */
 159     }
 160
 161     for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) {
 162         const struct ppc_one_seg_page_size *sps1 = &env->sps.sps[i];
 163
 164         if (!sps1->page_shift) {
 165             break;
 166         }
 167
 168         if ((vsid & SLB_VSID_LLP_MASK) == sps1->slb_enc) {
 169             sps = sps1;
 170             break;
 171         }
 172     }
 173
 174     if (!sps) {
 175         error_report("Bad page size encoding in SLB store: slot "TARGET_FMT_lu
 176                      " esid 0x"TARGET_FMT_lx" vsid 0x"TARGET_FMT_lx,
 177                      slot, esid, vsid);
 178         return -1;
 179     }
 180
 181     slb->esid = esid;
 182     slb->vsid = vsid;
 183     slb->sps = sps;
 184
 185     LOG_SLB("%s: %d " TARGET_FMT_lx " - " TARGET_FMT_lx " => %016" PRIx64
 186             " %016" PRIx64 "\n", __func__, slot, esid, vsid,
 187             slb->esid, slb->vsid);
 188
 189     return 0;
 190 }
 191
 192 static int ppc_load_slb_esid(PowerPCCPU *cpu, target_ulong rb,
 193                              target_ulong *rt)
 194 {
 195     CPUPPCState *env = &cpu->env;
 196     int slot = rb & 0xfff;
 197     ppc_slb_t *slb = &env->slb[slot];
 198
 199     if (slot >= env->slb_nr) {
 200         return -1;
 201     }
 202
 203     *rt = slb->esid;
 204     return 0;
 205 }
 206
 207 static int ppc_load_slb_vsid(PowerPCCPU *cpu, target_ulong rb,
 208                              target_ulong *rt)
 209 {
 210     CPUPPCState *env = &cpu->env;
 211     int slot = rb & 0xfff;
 212     ppc_slb_t *slb = &env->slb[slot];
 213
 214     if (slot >= env->slb_nr) {
 215         return -1;
 216     }
 217
 218     *rt = slb->vsid;
 219     return 0;
 220 }
 221
 222 static int ppc_find_slb_vsid(PowerPCCPU *cpu, target_ulong rb,
 223                              target_ulong *rt)
 224 {
 225     CPUPPCState *env = &cpu->env;
 226     ppc_slb_t *slb;
 227
 228     if (!msr_is_64bit(env, env->msr)) {
 229         rb &= 0xffffffff;
 230     }
 231     slb = slb_lookup(cpu, rb);
 232     if (slb == NULL) {
 233         *rt = (target_ulong)-1ul;
 234     } else {
 235         *rt = slb->vsid;
 236     }
 237     return 0;
 238 }
 239
 240 void helper_store_slb(CPUPPCState *env, target_ulong rb, target_ulong rs)
 241 {
 242     PowerPCCPU *cpu = ppc_env_get_cpu(env);
 243
 244     if (ppc_store_slb(cpu, rb & 0xfff, rb & ~0xfffULL, rs) < 0) {
 245         helper_raise_exception_err(env, POWERPC_EXCP_PROGRAM,
 246                                    POWERPC_EXCP_INVAL);
 247     }
 248 }
 249
 250 target_ulong helper_load_slb_esid(CPUPPCState *env, target_ulong rb)
 251 {
 252     PowerPCCPU *cpu = ppc_env_get_cpu(env);
 253     target_ulong rt = 0;
 254
 255     if (ppc_load_slb_esid(cpu, rb, &rt) < 0) {
 256         helper_raise_exception_err(env, POWERPC_EXCP_PROGRAM,
 257                                    POWERPC_EXCP_INVAL);
 258     }
 259     return rt;
 260 }
 261
 262 target_ulong helper_find_slb_vsid(CPUPPCState *env, target_ulong rb)
 263 {
 264     PowerPCCPU *cpu = ppc_env_get_cpu(env);
 265     target_ulong rt = 0;
 266
 267     if (ppc_find_slb_vsid(cpu, rb, &rt) < 0) {
 268         helper_raise_exception_err(env, POWERPC_EXCP_PROGRAM,
 269                                    POWERPC_EXCP_INVAL);
 270     }
 271     return rt;
 272 }
 273
 274 target_ulong helper_load_slb_vsid(CPUPPCState *env, target_ulong rb)
 275 {
 276     PowerPCCPU *cpu = ppc_env_get_cpu(env);
 277     target_ulong rt = 0;
 278
 279     if (ppc_load_slb_vsid(cpu, rb, &rt) < 0) {
 280         helper_raise_exception_err(env, POWERPC_EXCP_PROGRAM,
 281                                    POWERPC_EXCP_INVAL);
 282     }
 283     return rt;
 284 }
 285
 286 /*
 287  * 64-bit hash table MMU handling
 288  */
 289 void ppc_hash64_set_sdr1(PowerPCCPU *cpu, target_ulong value,
 290                          Error **errp)
 291 {
 292     CPUPPCState *env = &cpu->env;
 293     target_ulong htabsize = value & SDR_64_HTABSIZE;
 294
 295     env->spr[SPR_SDR1] = value;
 296     if (htabsize > 28) {
 297         error_setg(errp,
 298                    "Invalid HTABSIZE 0x" TARGET_FMT_lx" stored in SDR1",
 299                    htabsize);
 300         htabsize = 28;
 301     }
 302     env->htab_mask = (1ULL << (htabsize + 18 - 7)) - 1;
 303     env->htab_base = value & SDR_64_HTABORG;
 304 }
 305
 306 void ppc_hash64_set_external_hpt(PowerPCCPU *cpu, void *hpt, int shift,
 307                                  Error **errp)
 308 {
 309     CPUPPCState *env = &cpu->env;
 310     Error *local_err = NULL;
 311
 312     if (hpt) {
 313         env->external_htab = hpt;
 314     } else {
 315         env->external_htab = MMU_HASH64_KVM_MANAGED_HPT;
 316     }
 317     ppc_hash64_set_sdr1(cpu, (target_ulong)(uintptr_t)hpt | (shift - 18),
 318                         &local_err);
 319     if (local_err) {
 320         error_propagate(errp, local_err);
 321         return;
 322     }
 323
 324     /* Not strictly necessary, but makes it clearer that an external
 325      * htab is in use when debugging */
 326     env->htab_base = -1;
 327
 328     if (kvm_enabled()) {
 329         if (kvmppc_put_books_sregs(cpu) < 0) {
 330             error_setg(errp, "Unable to update SDR1 in KVM");
 331         }
 332     }
 333 }
 334
 335 static int ppc_hash64_pte_prot(PowerPCCPU *cpu,
 336                                ppc_slb_t *slb, ppc_hash_pte64_t pte)
 337 {
 338     CPUPPCState *env = &cpu->env;
 339     unsigned pp, key;
 340     /* Some pp bit combinations have undefined behaviour, so default
 341      * to no access in those cases */
 342     int prot = 0;
 343
 344     key = !!(msr_pr ? (slb->vsid & SLB_VSID_KP)
 345              : (slb->vsid & SLB_VSID_KS));
 346     pp = (pte.pte1 & HPTE64_R_PP) | ((pte.pte1 & HPTE64_R_PP0) >> 61);
 347
 348     if (key == 0) {
 349         switch (pp) {
 350         case 0x0:
 351         case 0x1:
 352         case 0x2:
 353             prot = PAGE_READ | PAGE_WRITE;
 354             break;
 355
 356         case 0x3:
 357         case 0x6:
 358             prot = PAGE_READ;
 359             break;
 360         }
 361     } else {
 362         switch (pp) {
 363         case 0x0:
 364         case 0x6:
 365             prot = 0;
 366             break;
 367
 368         case 0x1:
 369         case 0x3:
 370             prot = PAGE_READ;
 371             break;
 372
 373         case 0x2:
 374             prot = PAGE_READ | PAGE_WRITE;
 375             break;
 376         }
 377     }
 378
 379     /* No execute if either noexec or guarded bits set */
 380     if (!(pte.pte1 & HPTE64_R_N) || (pte.pte1 & HPTE64_R_G)
 381         || (slb->vsid & SLB_VSID_N)) {
 382         prot |= PAGE_EXEC;
 383     }
 384
 385     return prot;
 386 }
 387
 388 static int ppc_hash64_amr_prot(PowerPCCPU *cpu, ppc_hash_pte64_t pte)
 389 {
 390     CPUPPCState *env = &cpu->env;
 391     int key, amrbits;
 392     int prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
 393
 394     /* Only recent MMUs implement Virtual Page Class Key Protection */
 395     if (!(env->mmu_model & POWERPC_MMU_AMR)) {
 396         return prot;
 397     }
 398
 399     key = HPTE64_R_KEY(pte.pte1);
 400     amrbits = (env->spr[SPR_AMR] >> 2*(31 - key)) & 0x3;
 401
 402     /* fprintf(stderr, "AMR protection: key=%d AMR=0x%" PRIx64 "\n", key, */
 403     /*         env->spr[SPR_AMR]); */
 404
 405     /*
 406      * A store is permitted if the AMR bit is 0. Remove write
 407      * protection if it is set.
 408      */
 409     if (amrbits & 0x2) {
 410         prot &= ~PAGE_WRITE;
 411     }
 412     /*
 413      * A load is permitted if the AMR bit is 0. Remove read
 414      * protection if it is set.
 415      */
 416     if (amrbits & 0x1) {
 417         prot &= ~PAGE_READ;
 418     }
 419
 420     return prot;
 421 }
 422
 423 uint64_t ppc_hash64_start_access(PowerPCCPU *cpu, target_ulong pte_index)
 424 {
 425     uint64_t token = 0;
 426     hwaddr pte_offset;
 427
 428     pte_offset = pte_index * HASH_PTE_SIZE_64;
 429     if (cpu->env.external_htab == MMU_HASH64_KVM_MANAGED_HPT) {
 430         /*
 431          * HTAB is controlled by KVM. Fetch the PTEG into a new buffer.
 432          */
 433         token = kvmppc_hash64_read_pteg(cpu, pte_index);
 434     } else if (cpu->env.external_htab) {
 435         /*
 436          * HTAB is controlled by QEMU. Just point to the internally
 437          * accessible PTEG.
 438          */
 439         token = (uint64_t)(uintptr_t) cpu->env.external_htab + pte_offset;
 440     } else if (cpu->env.htab_base) {
 441         token = cpu->env.htab_base + pte_offset;
 442     }
 443     return token;
 444 }
 445
 446 void ppc_hash64_stop_access(PowerPCCPU *cpu, uint64_t token)
 447 {
 448     if (cpu->env.external_htab == MMU_HASH64_KVM_MANAGED_HPT) {
 449         kvmppc_hash64_free_pteg(token);
 450     }
 451 }
 452
 453 static unsigned hpte_page_shift(const struct ppc_one_seg_page_size *sps,
 454     uint64_t pte0, uint64_t pte1)
 455 {
 456     int i;
 457
 458     if (!(pte0 & HPTE64_V_LARGE)) {
 459         if (sps->page_shift != 12) {
 460             /* 4kiB page in a non 4kiB segment */
 461             return 0;
 462         }
 463         /* Normal 4kiB page */
 464         return 12;
 465     }
 466
 467     for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) {
 468         const struct ppc_one_page_size *ps = &sps->enc[i];
 469         uint64_t mask;
 470
 471         if (!ps->page_shift) {
 472             break;
 473         }
 474
 475         if (ps->page_shift == 12) {
 476             /* L bit is set so this can't be a 4kiB page */
 477             continue;
 478         }
 479
 480         mask = ((1ULL << ps->page_shift) - 1) & HPTE64_R_RPN;
 481
 482         if ((pte1 & mask) == (ps->pte_enc << HPTE64_R_RPN_SHIFT)) {
 483             return ps->page_shift;
 484         }
 485     }
 486
 487     return 0; /* Bad page size encoding */
 488 }
 489
 490 static hwaddr ppc_hash64_pteg_search(PowerPCCPU *cpu, hwaddr hash,
 491                                      ppc_slb_t *slb, target_ulong ptem,
 492                                      ppc_hash_pte64_t *pte, unsigned *pshift)
 493 {
 494     CPUPPCState *env = &cpu->env;
 495     int i;
 496     uint64_t token;
 497     target_ulong pte0, pte1;
 498     target_ulong pte_index;
 499
 500     pte_index = (hash & env->htab_mask) * HPTES_PER_GROUP;
 501     token = ppc_hash64_start_access(cpu, pte_index);
 502     if (!token) {
 503         return -1;
 504     }
 505     for (i = 0; i < HPTES_PER_GROUP; i++) {
 506         pte0 = ppc_hash64_load_hpte0(cpu, token, i);
 507         pte1 = ppc_hash64_load_hpte1(cpu, token, i);
 508
 509         /* This compares V, B, H (secondary) and the AVPN */
 510         if (HPTE64_V_COMPARE(pte0, ptem)) {
 511             *pshift = hpte_page_shift(slb->sps, pte0, pte1);
 512             /*
 513              * If there is no match, ignore the PTE, it could simply
 514              * be for a different segment size encoding and the
 515              * architecture specifies we should not match. Linux will
 516              * potentially leave behind PTEs for the wrong base page
 517              * size when demoting segments.
 518              */
 519             if (*pshift == 0) {
 520                 continue;
 521             }
 522             /* We don't do anything with pshift yet as qemu TLB only deals
 523              * with 4K pages anyway
 524              */
 525             pte->pte0 = pte0;
 526             pte->pte1 = pte1;
 527             ppc_hash64_stop_access(cpu, token);
 528             return (pte_index + i) * HASH_PTE_SIZE_64;
 529         }
 530     }
 531     ppc_hash64_stop_access(cpu, token);
 532     /*
 533      * We didn't find a valid entry.
 534      */
 535     return -1;
 536 }
 537
 538 static hwaddr ppc_hash64_htab_lookup(PowerPCCPU *cpu,
 539                                      ppc_slb_t *slb, target_ulong eaddr,
 540                                      ppc_hash_pte64_t *pte, unsigned *pshift)
 541 {
 542     CPUPPCState *env = &cpu->env;
 543     hwaddr pte_offset;
 544     hwaddr hash;
 545     uint64_t vsid, epnmask, epn, ptem;
 546
 547     /* The SLB store path should prevent any bad page size encodings
 548      * getting in there, so: */
 549     assert(slb->sps);
 550
 551     epnmask = ~((1ULL << slb->sps->page_shift) - 1);
 552
 553     if (slb->vsid & SLB_VSID_B) {
 554         /* 1TB segment */
 555         vsid = (slb->vsid & SLB_VSID_VSID) >> SLB_VSID_SHIFT_1T;
 556         epn = (eaddr & ~SEGMENT_MASK_1T) & epnmask;
 557         hash = vsid ^ (vsid << 25) ^ (epn >> slb->sps->page_shift);
 558     } else {
 559         /* 256M segment */
 560         vsid = (slb->vsid & SLB_VSID_VSID) >> SLB_VSID_SHIFT;
 561         epn = (eaddr & ~SEGMENT_MASK_256M) & epnmask;
 562         hash = vsid ^ (epn >> slb->sps->page_shift);
 563     }
 564     ptem = (slb->vsid & SLB_VSID_PTEM) | ((epn >> 16) & HPTE64_V_AVPN);
 565     ptem |= HPTE64_V_VALID;
 566
 567     /* Page address translation */
 568     qemu_log_mask(CPU_LOG_MMU,
 569             "htab_base " TARGET_FMT_plx " htab_mask " TARGET_FMT_plx
 570             " hash " TARGET_FMT_plx "\n",
 571             env->htab_base, env->htab_mask, hash);
 572
 573     /* Primary PTEG lookup */
 574     qemu_log_mask(CPU_LOG_MMU,
 575             "0 htab=" TARGET_FMT_plx "/" TARGET_FMT_plx
 576             " vsid=" TARGET_FMT_lx " ptem=" TARGET_FMT_lx
 577             " hash=" TARGET_FMT_plx "\n",
 578             env->htab_base, env->htab_mask, vsid, ptem,  hash);
 579     pte_offset = ppc_hash64_pteg_search(cpu, hash, slb, ptem, pte, pshift);
 580
 581     if (pte_offset == -1) {
 582         /* Secondary PTEG lookup */
 583         ptem |= HPTE64_V_SECONDARY;
 584         qemu_log_mask(CPU_LOG_MMU,
 585                 "1 htab=" TARGET_FMT_plx "/" TARGET_FMT_plx
 586                 " vsid=" TARGET_FMT_lx " api=" TARGET_FMT_lx
 587                 " hash=" TARGET_FMT_plx "\n", env->htab_base,
 588                 env->htab_mask, vsid, ptem, ~hash);
 589
 590         pte_offset = ppc_hash64_pteg_search(cpu, ~hash, slb, ptem, pte, pshift);
 591     }
 592
 593     return pte_offset;
 594 }
 595
 596 unsigned ppc_hash64_hpte_page_shift_noslb(PowerPCCPU *cpu,
 597                                           uint64_t pte0, uint64_t pte1)
 598 {
 599     CPUPPCState *env = &cpu->env;
 600     int i;
 601
 602     if (!(pte0 & HPTE64_V_LARGE)) {
 603         return 12;
 604     }
 605
 606     /*
 607      * The encodings in env->sps need to be carefully chosen so that
 608      * this gives an unambiguous result.
 609      */
 610     for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) {
 611         const struct ppc_one_seg_page_size *sps = &env->sps.sps[i];
 612         unsigned shift;
 613
 614         if (!sps->page_shift) {
 615             break;
 616         }
 617
 618         shift = hpte_page_shift(sps, pte0, pte1);
 619         if (shift) {
 620             return shift;
 621         }
 622     }
 623
 624     return 0;
 625 }
 626
 627 static void ppc_hash64_set_isi(CPUState *cs, CPUPPCState *env,
 628                                uint64_t error_code)
 629 {
 630     bool vpm;
 631
 632     if (msr_ir) {
 633         vpm = !!(env->spr[SPR_LPCR] & LPCR_VPM1);
 634     } else {
 635         vpm = !!(env->spr[SPR_LPCR] & LPCR_VPM0);
 636     }
 637     if (vpm && !msr_hv) {
 638         cs->exception_index = POWERPC_EXCP_HISI;
 639     } else {
 640         cs->exception_index = POWERPC_EXCP_ISI;
 641     }
 642     env->error_code = error_code;
 643 }
 644
 645 static void ppc_hash64_set_dsi(CPUState *cs, CPUPPCState *env, uint64_t dar,
 646                                uint64_t dsisr)
 647 {
 648     bool vpm;
 649
 650     if (msr_dr) {
 651         vpm = !!(env->spr[SPR_LPCR] & LPCR_VPM1);
 652     } else {
 653         vpm = !!(env->spr[SPR_LPCR] & LPCR_VPM0);
 654     }
 655     if (vpm && !msr_hv) {
 656         cs->exception_index = POWERPC_EXCP_HDSI;
 657         env->spr[SPR_HDAR] = dar;
 658         env->spr[SPR_HDSISR] = dsisr;
 659     } else {
 660         cs->exception_index = POWERPC_EXCP_DSI;
 661         env->spr[SPR_DAR] = dar;
 662         env->spr[SPR_DSISR] = dsisr;
 663    }
 664     env->error_code = 0;
 665 }
 666
 667
 668 int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr,
 669                                 int rwx, int mmu_idx)
 670 {
 671     CPUState *cs = CPU(cpu);
 672     CPUPPCState *env = &cpu->env;
 673     ppc_slb_t *slb;
 674     unsigned apshift;
 675     hwaddr pte_offset;
 676     ppc_hash_pte64_t pte;
 677     int pp_prot, amr_prot, prot;
 678     uint64_t new_pte1, dsisr;
 679     const int need_prot[] = {PAGE_READ, PAGE_WRITE, PAGE_EXEC};
 680     hwaddr raddr;
 681
 682     assert((rwx == 0) || (rwx == 1) || (rwx == 2));
 683
 684     /* Note on LPCR usage: 970 uses HID4, but our special variant
 685      * of store_spr copies relevant fields into env->spr[SPR_LPCR].
 686      * Similarily we filter unimplemented bits when storing into
 687      * LPCR depending on the MMU version. This code can thus just
 688      * use the LPCR "as-is".
 689      */
 690
 691     /* 1. Handle real mode accesses */
 692     if (((rwx == 2) && (msr_ir == 0)) || ((rwx != 2) && (msr_dr == 0))) {
 693         /* Translation is supposedly "off"  */
 694         /* In real mode the top 4 effective address bits are (mostly) ignored */
 695         raddr = eaddr & 0x0FFFFFFFFFFFFFFFULL;
 696
 697         /* In HV mode, add HRMOR if top EA bit is clear */
 698         if (msr_hv || !env->has_hv_mode) {
 699             if (!(eaddr >> 63)) {
 700                 raddr |= env->spr[SPR_HRMOR];
 701             }
 702         } else {
 703             /* Otherwise, check VPM for RMA vs VRMA */
 704             if (env->spr[SPR_LPCR] & LPCR_VPM0) {
 705                 slb = &env->vrma_slb;
 706                 if (slb->sps) {
 707                     goto skip_slb_search;
 708                 }
 709                 /* Not much else to do here */
 710                 cs->exception_index = POWERPC_EXCP_MCHECK;
 711                 env->error_code = 0;
 712                 return 1;
 713             } else if (raddr < env->rmls) {
 714                 /* RMA. Check bounds in RMLS */
 715                 raddr |= env->spr[SPR_RMOR];
 716             } else {
 717                 /* The access failed, generate the approriate interrupt */
 718                 if (rwx == 2) {
 719                     ppc_hash64_set_isi(cs, env, 0x08000000);
 720                 } else {
 721                     dsisr = 0x08000000;
 722                     if (rwx == 1) {
 723                         dsisr |= 0x02000000;
 724                     }
 725                     ppc_hash64_set_dsi(cs, env, eaddr, dsisr);
 726                 }
 727                 return 1;
 728             }
 729         }
 730         tlb_set_page(cs, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK,
 731                      PAGE_READ | PAGE_WRITE | PAGE_EXEC, mmu_idx,
 732                      TARGET_PAGE_SIZE);
 733         return 0;
 734     }
 735
 736     /* 2. Translation is on, so look up the SLB */
 737     slb = slb_lookup(cpu, eaddr);
 738     if (!slb) {
 739         if (rwx == 2) {
 740             cs->exception_index = POWERPC_EXCP_ISEG;
 741             env->error_code = 0;
 742         } else {
 743             cs->exception_index = POWERPC_EXCP_DSEG;
 744             env->error_code = 0;
 745             env->spr[SPR_DAR] = eaddr;
 746         }
 747         return 1;
 748     }
 749
 750 skip_slb_search:
 751
 752     /* 3. Check for segment level no-execute violation */
 753     if ((rwx == 2) && (slb->vsid & SLB_VSID_N)) {
 754         ppc_hash64_set_isi(cs, env, 0x10000000);
 755         return 1;
 756     }
 757
 758     /* 4. Locate the PTE in the hash table */
 759     pte_offset = ppc_hash64_htab_lookup(cpu, slb, eaddr, &pte, &apshift);
 760     if (pte_offset == -1) {
 761         dsisr = 0x40000000;
 762         if (rwx == 2) {
 763             ppc_hash64_set_isi(cs, env, dsisr);
 764         } else {
 765             if (rwx == 1) {
 766                 dsisr |= 0x02000000;
 767             }
 768             ppc_hash64_set_dsi(cs, env, eaddr, dsisr);
 769         }
 770         return 1;
 771     }
 772     qemu_log_mask(CPU_LOG_MMU,
 773                 "found PTE at offset %08" HWADDR_PRIx "\n", pte_offset);
 774
 775     /* 5. Check access permissions */
 776
 777     pp_prot = ppc_hash64_pte_prot(cpu, slb, pte);
 778     amr_prot = ppc_hash64_amr_prot(cpu, pte);
 779     prot = pp_prot & amr_prot;
 780
 781     if ((need_prot[rwx] & ~prot) != 0) {
 782         /* Access right violation */
 783         qemu_log_mask(CPU_LOG_MMU, "PTE access rejected\n");
 784         if (rwx == 2) {
 785             ppc_hash64_set_isi(cs, env, 0x08000000);
 786         } else {
 787             dsisr = 0;
 788             if (need_prot[rwx] & ~pp_prot) {
 789                 dsisr |= 0x08000000;
 790             }
 791             if (rwx == 1) {
 792                 dsisr |= 0x02000000;
 793             }
 794             if (need_prot[rwx] & ~amr_prot) {
 795                 dsisr |= 0x00200000;
 796             }
 797             ppc_hash64_set_dsi(cs, env, eaddr, dsisr);
 798         }
 799         return 1;
 800     }
 801
 802     qemu_log_mask(CPU_LOG_MMU, "PTE access granted !\n");
 803
 804     /* 6. Update PTE referenced and changed bits if necessary */
 805
 806     new_pte1 = pte.pte1 | HPTE64_R_R; /* set referenced bit */
 807     if (rwx == 1) {
 808         new_pte1 |= HPTE64_R_C; /* set changed (dirty) bit */
 809     } else {
 810         /* Treat the page as read-only for now, so that a later write
 811          * will pass through this function again to set the C bit */
 812         prot &= ~PAGE_WRITE;
 813     }
 814
 815     if (new_pte1 != pte.pte1) {
 816         ppc_hash64_store_hpte(cpu, pte_offset / HASH_PTE_SIZE_64,
 817                               pte.pte0, new_pte1);
 818     }
 819
 820     /* 7. Determine the real address from the PTE */
 821
 822     raddr = deposit64(pte.pte1 & HPTE64_R_RPN, 0, apshift, eaddr);
 823
 824     tlb_set_page(cs, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK,
 825                  prot, mmu_idx, 1ULL << apshift);
 826
 827     return 0;
 828 }
 829
 830 hwaddr ppc_hash64_get_phys_page_debug(PowerPCCPU *cpu, target_ulong addr)
 831 {
 832     CPUPPCState *env = &cpu->env;
 833     ppc_slb_t *slb;
 834     hwaddr pte_offset, raddr;
 835     ppc_hash_pte64_t pte;
 836     unsigned apshift;
 837
 838     /* Handle real mode */
 839     if (msr_dr == 0) {
 840         /* In real mode the top 4 effective address bits are ignored */
 841         raddr = addr & 0x0FFFFFFFFFFFFFFFULL;
 842
 843         /* In HV mode, add HRMOR if top EA bit is clear */
 844         if ((msr_hv || !env->has_hv_mode) && !(addr >> 63)) {
 845             return raddr | env->spr[SPR_HRMOR];
 846         }
 847
 848         /* Otherwise, check VPM for RMA vs VRMA */
 849         if (env->spr[SPR_LPCR] & LPCR_VPM0) {
 850             slb = &env->vrma_slb;
 851             if (!slb->sps) {
 852                 return -1;
 853             }
 854         } else if (raddr < env->rmls) {
 855             /* RMA. Check bounds in RMLS */
 856             return raddr | env->spr[SPR_RMOR];
 857         } else {
 858             return -1;
 859         }
 860     } else {
 861         slb = slb_lookup(cpu, addr);
 862         if (!slb) {
 863             return -1;
 864         }
 865     }
 866
 867     pte_offset = ppc_hash64_htab_lookup(cpu, slb, addr, &pte, &apshift);
 868     if (pte_offset == -1) {
 869         return -1;
 870     }
 871
 872     return deposit64(pte.pte1 & HPTE64_R_RPN, 0, apshift, addr)
 873         & TARGET_PAGE_MASK;
 874 }
 875
 876 void ppc_hash64_store_hpte(PowerPCCPU *cpu,
 877                            target_ulong pte_index,
 878                            target_ulong pte0, target_ulong pte1)
 879 {
 880     CPUPPCState *env = &cpu->env;
 881
 882     if (env->external_htab == MMU_HASH64_KVM_MANAGED_HPT) {
 883         kvmppc_hash64_write_pte(env, pte_index, pte0, pte1);
 884         return;
 885     }
 886
 887     pte_index *= HASH_PTE_SIZE_64;
 888     if (env->external_htab) {
 889         stq_p(env->external_htab + pte_index, pte0);
 890         stq_p(env->external_htab + pte_index + HASH_PTE_SIZE_64 / 2, pte1);
 891     } else {
 892         stq_phys(CPU(cpu)->as, env->htab_base + pte_index, pte0);
 893         stq_phys(CPU(cpu)->as,
 894                  env->htab_base + pte_index + HASH_PTE_SIZE_64 / 2, pte1);
 895     }
 896 }
 897
 898 void ppc_hash64_tlb_flush_hpte(PowerPCCPU *cpu,
 899                                target_ulong pte_index,
 900                                target_ulong pte0, target_ulong pte1)
 901 {
 902     /*
 903      * XXX: given the fact that there are too many segments to
 904      * invalidate, and we still don't have a tlb_flush_mask(env, n,
 905      * mask) in QEMU, we just invalidate all TLBs
 906      */
 907     tlb_flush(CPU(cpu), 1);
 908 }
 909
 910 void ppc_hash64_update_rmls(CPUPPCState *env)
 911 {
 912     uint64_t lpcr = env->spr[SPR_LPCR];
 913
 914     /*
 915      * This is the full 4 bits encoding of POWER8. Previous
 916      * CPUs only support a subset of these but the filtering
 917      * is done when writing LPCR
 918      */
 919     switch ((lpcr & LPCR_RMLS) >> LPCR_RMLS_SHIFT) {
 920     case 0x8: /* 32MB */
 921         env->rmls = 0x2000000ull;
 922         break;
 923     case 0x3: /* 64MB */
 924         env->rmls = 0x4000000ull;
 925         break;
 926     case 0x7: /* 128MB */
 927         env->rmls = 0x8000000ull;
 928         break;
 929     case 0x4: /* 256MB */
 930         env->rmls = 0x10000000ull;
 931         break;
 932     case 0x2: /* 1GB */
 933         env->rmls = 0x40000000ull;
 934         break;
 935     case 0x1: /* 16GB */
 936         env->rmls = 0x400000000ull;
 937         break;
 938     default:
 939         /* What to do here ??? */
 940         env->rmls = 0;
 941     }
 942 }
 943
 944 void ppc_hash64_update_vrma(CPUPPCState *env)
 945 {
 946     const struct ppc_one_seg_page_size *sps = NULL;
 947     target_ulong esid, vsid, lpcr;
 948     ppc_slb_t *slb = &env->vrma_slb;
 949     uint32_t vrmasd;
 950     int i;
 951
 952     /* First clear it */
 953     slb->esid = slb->vsid = 0;
 954     slb->sps = NULL;
 955
 956     /* Is VRMA enabled ? */
 957     lpcr = env->spr[SPR_LPCR];
 958     if (!(lpcr & LPCR_VPM0)) {
 959         return;
 960     }
 961
 962     /* Make one up. Mostly ignore the ESID which will not be
 963      * needed for translation
 964      */
 965     vsid = SLB_VSID_VRMA;
 966     vrmasd = (lpcr & LPCR_VRMASD) >> LPCR_VRMASD_SHIFT;
 967     vsid |= (vrmasd << 4) & (SLB_VSID_L | SLB_VSID_LP);
 968     esid = SLB_ESID_V;
 969
 970    for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) {
 971         const struct ppc_one_seg_page_size *sps1 = &env->sps.sps[i];
 972
 973         if (!sps1->page_shift) {
 974             break;
 975         }
 976
 977         if ((vsid & SLB_VSID_LLP_MASK) == sps1->slb_enc) {
 978             sps = sps1;
 979             break;
 980         }
 981     }
 982
 983     if (!sps) {
 984         error_report("Bad page size encoding esid 0x"TARGET_FMT_lx
 985                      " vsid 0x"TARGET_FMT_lx, esid, vsid);
 986         return;
 987     }
 988
 989     slb->vsid = vsid;
 990     slb->esid = esid;
 991     slb->sps = sps;
 992 }
 993
 994 void helper_store_lpcr(CPUPPCState *env, target_ulong val)
 995 {
 996     uint64_t lpcr = 0;
 997
 998     /* Filter out bits */
 999     switch (env->mmu_model) {
1000     case POWERPC_MMU_64B: /* 970 */
1001         if (val & 0x40) {
1002             lpcr |= LPCR_LPES0;
1003         }
1004         if (val & 0x8000000000000000ull) {
1005             lpcr |= LPCR_LPES1;
1006         }
1007         if (val & 0x20) {
1008             lpcr |= (0x4ull << LPCR_RMLS_SHIFT);
1009         }
1010         if (val & 0x4000000000000000ull) {
1011             lpcr |= (0x2ull << LPCR_RMLS_SHIFT);
1012         }
1013         if (val & 0x2000000000000000ull) {
1014             lpcr |= (0x1ull << LPCR_RMLS_SHIFT);
1015         }
1016         env->spr[SPR_RMOR] = ((lpcr >> 41) & 0xffffull) << 26;
1017
1018         /* XXX We could also write LPID from HID4 here
1019          * but since we don't tag any translation on it
1020          * it doesn't actually matter
1021          */
1022         /* XXX For proper emulation of 970 we also need
1023          * to dig HRMOR out of HID5
1024          */
1025         break;
1026     case POWERPC_MMU_2_03: /* P5p */
1027         lpcr = val & (LPCR_RMLS | LPCR_ILE |
1028                       LPCR_LPES0 | LPCR_LPES1 |
1029                       LPCR_RMI | LPCR_HDICE);
1030         break;
1031     case POWERPC_MMU_2_06: /* P7 */
1032         lpcr = val & (LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_DPFD |
1033                       LPCR_VRMASD | LPCR_RMLS | LPCR_ILE |
1034                       LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2 |
1035                       LPCR_MER | LPCR_TC |
1036                       LPCR_LPES0 | LPCR_LPES1 | LPCR_HDICE);
1037         break;
1038     case POWERPC_MMU_2_07: /* P8 */
1039         lpcr = val & (LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_KBV |
1040                       LPCR_DPFD | LPCR_VRMASD | LPCR_RMLS | LPCR_ILE |
1041                       LPCR_AIL | LPCR_ONL | LPCR_P8_PECE0 | LPCR_P8_PECE1 |
1042                       LPCR_P8_PECE2 | LPCR_P8_PECE3 | LPCR_P8_PECE4 |
1043                       LPCR_MER | LPCR_TC | LPCR_LPES0 | LPCR_HDICE);
1044         break;
1045     default:
1046         ;
1047     }
1048     env->spr[SPR_LPCR] = lpcr;
1049     ppc_hash64_update_rmls(env);
1050     ppc_hash64_update_vrma(env);
1051 }