s390x/pci: introduce S390PCIBus
[qemu.git] / hw / s390x / s390-pci-bus.c
blob0c67c1e7aa209fba1396bec4b738b7ca058a0c57
1 /*
2 * s390 PCI BUS
4 * Copyright 2014 IBM Corp.
5 * Author(s): Frank Blaschka <frank.blaschka@de.ibm.com>
6 * Hong Bo Li <lihbbj@cn.ibm.com>
7 * Yi Min Zhao <zyimin@cn.ibm.com>
9 * This work is licensed under the terms of the GNU GPL, version 2 or (at
10 * your option) any later version. See the COPYING file in the top-level
11 * directory.
14 #include "qemu/osdep.h"
15 #include "qemu-common.h"
16 #include "cpu.h"
17 #include "s390-pci-bus.h"
18 #include "s390-pci-inst.h"
19 #include <hw/pci/pci_bus.h>
20 #include <hw/pci/msi.h>
21 #include <qemu/error-report.h>
23 /* #define DEBUG_S390PCI_BUS */
24 #ifdef DEBUG_S390PCI_BUS
25 #define DPRINTF(fmt, ...) \
26 do { fprintf(stderr, "S390pci-bus: " fmt, ## __VA_ARGS__); } while (0)
27 #else
28 #define DPRINTF(fmt, ...) \
29 do { } while (0)
30 #endif
32 static S390pciState *s390_get_phb(void)
34 static S390pciState *phb;
36 if (!phb) {
37 phb = S390_PCI_HOST_BRIDGE(
38 object_resolve_path(TYPE_S390_PCI_HOST_BRIDGE, NULL));
39 assert(phb != NULL);
42 return phb;
45 int chsc_sei_nt2_get_event(void *res)
47 ChscSeiNt2Res *nt2_res = (ChscSeiNt2Res *)res;
48 PciCcdfAvail *accdf;
49 PciCcdfErr *eccdf;
50 int rc = 1;
51 SeiContainer *sei_cont;
52 S390pciState *s = s390_get_phb();
54 sei_cont = QTAILQ_FIRST(&s->pending_sei);
55 if (sei_cont) {
56 QTAILQ_REMOVE(&s->pending_sei, sei_cont, link);
57 nt2_res->nt = 2;
58 nt2_res->cc = sei_cont->cc;
59 nt2_res->length = cpu_to_be16(sizeof(ChscSeiNt2Res));
60 switch (sei_cont->cc) {
61 case 1: /* error event */
62 eccdf = (PciCcdfErr *)nt2_res->ccdf;
63 eccdf->fid = cpu_to_be32(sei_cont->fid);
64 eccdf->fh = cpu_to_be32(sei_cont->fh);
65 eccdf->e = cpu_to_be32(sei_cont->e);
66 eccdf->faddr = cpu_to_be64(sei_cont->faddr);
67 eccdf->pec = cpu_to_be16(sei_cont->pec);
68 break;
69 case 2: /* availability event */
70 accdf = (PciCcdfAvail *)nt2_res->ccdf;
71 accdf->fid = cpu_to_be32(sei_cont->fid);
72 accdf->fh = cpu_to_be32(sei_cont->fh);
73 accdf->pec = cpu_to_be16(sei_cont->pec);
74 break;
75 default:
76 abort();
78 g_free(sei_cont);
79 rc = 0;
82 return rc;
85 int chsc_sei_nt2_have_event(void)
87 S390pciState *s = s390_get_phb();
89 return !QTAILQ_EMPTY(&s->pending_sei);
92 S390PCIBusDevice *s390_pci_find_dev_by_fid(uint32_t fid)
94 S390PCIBusDevice *pbdev;
95 int i;
96 S390pciState *s = s390_get_phb();
98 for (i = 0; i < PCI_SLOT_MAX; i++) {
99 pbdev = &s->pbdev[i];
100 if ((pbdev->fh != 0) && (pbdev->fid == fid)) {
101 return pbdev;
105 return NULL;
108 void s390_pci_sclp_configure(SCCB *sccb)
110 PciCfgSccb *psccb = (PciCfgSccb *)sccb;
111 S390PCIBusDevice *pbdev = s390_pci_find_dev_by_fid(be32_to_cpu(psccb->aid));
112 uint16_t rc;
114 if (be16_to_cpu(sccb->h.length) < 16) {
115 rc = SCLP_RC_INSUFFICIENT_SCCB_LENGTH;
116 goto out;
119 if (!pbdev) {
120 DPRINTF("sclp config no dev found\n");
121 rc = SCLP_RC_ADAPTER_ID_NOT_RECOGNIZED;
122 goto out;
125 switch (pbdev->state) {
126 case ZPCI_FS_RESERVED:
127 rc = SCLP_RC_ADAPTER_IN_RESERVED_STATE;
128 break;
129 case ZPCI_FS_STANDBY:
130 pbdev->state = ZPCI_FS_DISABLED;
131 rc = SCLP_RC_NORMAL_COMPLETION;
132 break;
133 default:
134 rc = SCLP_RC_NO_ACTION_REQUIRED;
136 out:
137 psccb->header.response_code = cpu_to_be16(rc);
140 void s390_pci_sclp_deconfigure(SCCB *sccb)
142 PciCfgSccb *psccb = (PciCfgSccb *)sccb;
143 S390PCIBusDevice *pbdev = s390_pci_find_dev_by_fid(be32_to_cpu(psccb->aid));
144 uint16_t rc;
146 if (be16_to_cpu(sccb->h.length) < 16) {
147 rc = SCLP_RC_INSUFFICIENT_SCCB_LENGTH;
148 goto out;
151 if (!pbdev) {
152 DPRINTF("sclp deconfig no dev found\n");
153 rc = SCLP_RC_ADAPTER_ID_NOT_RECOGNIZED;
154 goto out;
157 switch (pbdev->state) {
158 case ZPCI_FS_RESERVED:
159 rc = SCLP_RC_ADAPTER_IN_RESERVED_STATE;
160 break;
161 case ZPCI_FS_STANDBY:
162 rc = SCLP_RC_NO_ACTION_REQUIRED;
163 break;
164 default:
165 if (pbdev->summary_ind) {
166 pci_dereg_irqs(pbdev);
168 if (pbdev->iommu_enabled) {
169 pci_dereg_ioat(pbdev);
171 pbdev->state = ZPCI_FS_STANDBY;
172 rc = SCLP_RC_NORMAL_COMPLETION;
174 out:
175 psccb->header.response_code = cpu_to_be16(rc);
178 static uint32_t s390_pci_get_pfid(PCIDevice *pdev)
180 return PCI_SLOT(pdev->devfn);
183 static uint32_t s390_pci_get_pfh(PCIDevice *pdev)
185 return PCI_SLOT(pdev->devfn) | FH_SHM_VFIO;
188 S390PCIBusDevice *s390_pci_find_dev_by_idx(uint32_t idx)
190 S390PCIBusDevice *pbdev;
191 int i;
192 int j = 0;
193 S390pciState *s = s390_get_phb();
195 for (i = 0; i < PCI_SLOT_MAX; i++) {
196 pbdev = &s->pbdev[i];
198 if (pbdev->state == ZPCI_FS_RESERVED) {
199 continue;
202 if (j == idx) {
203 return pbdev;
205 j++;
208 return NULL;
211 S390PCIBusDevice *s390_pci_find_dev_by_fh(uint32_t fh)
213 S390pciState *s = s390_get_phb();
214 S390PCIBusDevice *pbdev;
216 pbdev = &s->pbdev[fh & FH_MASK_INDEX];
217 if (pbdev->fh != 0 && pbdev->fh == fh) {
218 return pbdev;
221 return NULL;
224 static void s390_pci_generate_event(uint8_t cc, uint16_t pec, uint32_t fh,
225 uint32_t fid, uint64_t faddr, uint32_t e)
227 SeiContainer *sei_cont;
228 S390pciState *s = s390_get_phb();
230 sei_cont = g_malloc0(sizeof(SeiContainer));
231 sei_cont->fh = fh;
232 sei_cont->fid = fid;
233 sei_cont->cc = cc;
234 sei_cont->pec = pec;
235 sei_cont->faddr = faddr;
236 sei_cont->e = e;
238 QTAILQ_INSERT_TAIL(&s->pending_sei, sei_cont, link);
239 css_generate_css_crws(0);
242 static void s390_pci_generate_plug_event(uint16_t pec, uint32_t fh,
243 uint32_t fid)
245 s390_pci_generate_event(2, pec, fh, fid, 0, 0);
248 void s390_pci_generate_error_event(uint16_t pec, uint32_t fh, uint32_t fid,
249 uint64_t faddr, uint32_t e)
251 s390_pci_generate_event(1, pec, fh, fid, faddr, e);
254 static void s390_pci_set_irq(void *opaque, int irq, int level)
256 /* nothing to do */
259 static int s390_pci_map_irq(PCIDevice *pci_dev, int irq_num)
261 /* nothing to do */
262 return 0;
265 static uint64_t s390_pci_get_table_origin(uint64_t iota)
267 return iota & ~ZPCI_IOTA_RTTO_FLAG;
270 static unsigned int calc_rtx(dma_addr_t ptr)
272 return ((unsigned long) ptr >> ZPCI_RT_SHIFT) & ZPCI_INDEX_MASK;
275 static unsigned int calc_sx(dma_addr_t ptr)
277 return ((unsigned long) ptr >> ZPCI_ST_SHIFT) & ZPCI_INDEX_MASK;
280 static unsigned int calc_px(dma_addr_t ptr)
282 return ((unsigned long) ptr >> PAGE_SHIFT) & ZPCI_PT_MASK;
285 static uint64_t get_rt_sto(uint64_t entry)
287 return ((entry & ZPCI_TABLE_TYPE_MASK) == ZPCI_TABLE_TYPE_RTX)
288 ? (entry & ZPCI_RTE_ADDR_MASK)
289 : 0;
292 static uint64_t get_st_pto(uint64_t entry)
294 return ((entry & ZPCI_TABLE_TYPE_MASK) == ZPCI_TABLE_TYPE_SX)
295 ? (entry & ZPCI_STE_ADDR_MASK)
296 : 0;
299 static uint64_t s390_guest_io_table_walk(uint64_t guest_iota,
300 uint64_t guest_dma_address)
302 uint64_t sto_a, pto_a, px_a;
303 uint64_t sto, pto, pte;
304 uint32_t rtx, sx, px;
306 rtx = calc_rtx(guest_dma_address);
307 sx = calc_sx(guest_dma_address);
308 px = calc_px(guest_dma_address);
310 sto_a = guest_iota + rtx * sizeof(uint64_t);
311 sto = address_space_ldq(&address_space_memory, sto_a,
312 MEMTXATTRS_UNSPECIFIED, NULL);
313 sto = get_rt_sto(sto);
314 if (!sto) {
315 pte = 0;
316 goto out;
319 pto_a = sto + sx * sizeof(uint64_t);
320 pto = address_space_ldq(&address_space_memory, pto_a,
321 MEMTXATTRS_UNSPECIFIED, NULL);
322 pto = get_st_pto(pto);
323 if (!pto) {
324 pte = 0;
325 goto out;
328 px_a = pto + px * sizeof(uint64_t);
329 pte = address_space_ldq(&address_space_memory, px_a,
330 MEMTXATTRS_UNSPECIFIED, NULL);
332 out:
333 return pte;
336 static IOMMUTLBEntry s390_translate_iommu(MemoryRegion *iommu, hwaddr addr,
337 bool is_write)
339 uint64_t pte;
340 uint32_t flags;
341 S390PCIBusDevice *pbdev = container_of(iommu, S390PCIBusDevice, iommu_mr);
342 S390pciState *s;
343 IOMMUTLBEntry ret = {
344 .target_as = &address_space_memory,
345 .iova = 0,
346 .translated_addr = 0,
347 .addr_mask = ~(hwaddr)0,
348 .perm = IOMMU_NONE,
351 switch (pbdev->state) {
352 case ZPCI_FS_ENABLED:
353 case ZPCI_FS_BLOCKED:
354 if (!pbdev->iommu_enabled) {
355 return ret;
357 break;
358 default:
359 return ret;
362 DPRINTF("iommu trans addr 0x%" PRIx64 "\n", addr);
364 s = S390_PCI_HOST_BRIDGE(pci_device_root_bus(pbdev->pdev)->qbus.parent);
365 /* s390 does not have an APIC mapped to main storage so we use
366 * a separate AddressSpace only for msix notifications
368 if (addr == ZPCI_MSI_ADDR) {
369 ret.target_as = &s->msix_notify_as;
370 ret.iova = addr;
371 ret.translated_addr = addr;
372 ret.addr_mask = 0xfff;
373 ret.perm = IOMMU_RW;
374 return ret;
377 if (addr < pbdev->pba || addr > pbdev->pal) {
378 return ret;
381 pte = s390_guest_io_table_walk(s390_pci_get_table_origin(pbdev->g_iota),
382 addr);
383 if (!pte) {
384 return ret;
387 flags = pte & ZPCI_PTE_FLAG_MASK;
388 ret.iova = addr;
389 ret.translated_addr = pte & ZPCI_PTE_ADDR_MASK;
390 ret.addr_mask = 0xfff;
392 if (flags & ZPCI_PTE_INVALID) {
393 ret.perm = IOMMU_NONE;
394 } else {
395 ret.perm = IOMMU_RW;
398 return ret;
401 static const MemoryRegionIOMMUOps s390_iommu_ops = {
402 .translate = s390_translate_iommu,
405 static AddressSpace *s390_pci_dma_iommu(PCIBus *bus, void *opaque, int devfn)
407 S390pciState *s = opaque;
409 return &s->pbdev[PCI_SLOT(devfn)].as;
412 static uint8_t set_ind_atomic(uint64_t ind_loc, uint8_t to_be_set)
414 uint8_t ind_old, ind_new;
415 hwaddr len = 1;
416 uint8_t *ind_addr;
418 ind_addr = cpu_physical_memory_map(ind_loc, &len, 1);
419 if (!ind_addr) {
420 s390_pci_generate_error_event(ERR_EVENT_AIRERR, 0, 0, 0, 0);
421 return -1;
423 do {
424 ind_old = *ind_addr;
425 ind_new = ind_old | to_be_set;
426 } while (atomic_cmpxchg(ind_addr, ind_old, ind_new) != ind_old);
427 cpu_physical_memory_unmap(ind_addr, len, 1, len);
429 return ind_old;
432 static void s390_msi_ctrl_write(void *opaque, hwaddr addr, uint64_t data,
433 unsigned int size)
435 S390PCIBusDevice *pbdev;
436 uint32_t io_int_word;
437 uint32_t fid = data >> ZPCI_MSI_VEC_BITS;
438 uint32_t vec = data & ZPCI_MSI_VEC_MASK;
439 uint64_t ind_bit;
440 uint32_t sum_bit;
441 uint32_t e = 0;
443 DPRINTF("write_msix data 0x%" PRIx64 " fid %d vec 0x%x\n", data, fid, vec);
445 pbdev = s390_pci_find_dev_by_fid(fid);
446 if (!pbdev) {
447 e |= (vec << ERR_EVENT_MVN_OFFSET);
448 s390_pci_generate_error_event(ERR_EVENT_NOMSI, 0, fid, addr, e);
449 return;
452 if (pbdev->state != ZPCI_FS_ENABLED) {
453 return;
456 ind_bit = pbdev->routes.adapter.ind_offset;
457 sum_bit = pbdev->routes.adapter.summary_offset;
459 set_ind_atomic(pbdev->routes.adapter.ind_addr + (ind_bit + vec) / 8,
460 0x80 >> ((ind_bit + vec) % 8));
461 if (!set_ind_atomic(pbdev->routes.adapter.summary_addr + sum_bit / 8,
462 0x80 >> (sum_bit % 8))) {
463 io_int_word = (pbdev->isc << 27) | IO_INT_WORD_AI;
464 s390_io_interrupt(0, 0, 0, io_int_word);
468 static uint64_t s390_msi_ctrl_read(void *opaque, hwaddr addr, unsigned size)
470 return 0xffffffff;
473 static const MemoryRegionOps s390_msi_ctrl_ops = {
474 .write = s390_msi_ctrl_write,
475 .read = s390_msi_ctrl_read,
476 .endianness = DEVICE_LITTLE_ENDIAN,
479 void s390_pci_iommu_enable(S390PCIBusDevice *pbdev)
481 memory_region_init_iommu(&pbdev->iommu_mr, OBJECT(&pbdev->mr),
482 &s390_iommu_ops, "iommu-s390", pbdev->pal + 1);
483 memory_region_add_subregion(&pbdev->mr, 0, &pbdev->iommu_mr);
484 pbdev->iommu_enabled = true;
487 void s390_pci_iommu_disable(S390PCIBusDevice *pbdev)
489 memory_region_del_subregion(&pbdev->mr, &pbdev->iommu_mr);
490 object_unparent(OBJECT(&pbdev->iommu_mr));
491 pbdev->iommu_enabled = false;
494 static void s390_pcihost_init_as(S390pciState *s)
496 int i;
497 S390PCIBusDevice *pbdev;
499 for (i = 0; i < PCI_SLOT_MAX; i++) {
500 pbdev = &s->pbdev[i];
501 memory_region_init(&pbdev->mr, OBJECT(s),
502 "iommu-root-s390", UINT64_MAX);
503 address_space_init(&pbdev->as, &pbdev->mr, "iommu-pci");
506 memory_region_init_io(&s->msix_notify_mr, OBJECT(s),
507 &s390_msi_ctrl_ops, s, "msix-s390", UINT64_MAX);
508 address_space_init(&s->msix_notify_as, &s->msix_notify_mr, "msix-pci");
511 static int s390_pcihost_init(SysBusDevice *dev)
513 PCIBus *b;
514 BusState *bus;
515 PCIHostState *phb = PCI_HOST_BRIDGE(dev);
516 S390pciState *s = S390_PCI_HOST_BRIDGE(dev);
518 DPRINTF("host_init\n");
520 b = pci_register_bus(DEVICE(dev), NULL,
521 s390_pci_set_irq, s390_pci_map_irq, NULL,
522 get_system_memory(), get_system_io(), 0, 64,
523 TYPE_PCI_BUS);
524 s390_pcihost_init_as(s);
525 pci_setup_iommu(b, s390_pci_dma_iommu, s);
527 bus = BUS(b);
528 qbus_set_hotplug_handler(bus, DEVICE(dev), NULL);
529 phb->bus = b;
531 s->bus = S390_PCI_BUS(qbus_create(TYPE_S390_PCI_BUS, DEVICE(s), NULL));
533 QTAILQ_INIT(&s->pending_sei);
534 return 0;
537 static int s390_pcihost_setup_msix(S390PCIBusDevice *pbdev)
539 uint8_t pos;
540 uint16_t ctrl;
541 uint32_t table, pba;
543 pos = pci_find_capability(pbdev->pdev, PCI_CAP_ID_MSIX);
544 if (!pos) {
545 pbdev->msix.available = false;
546 return 0;
549 ctrl = pci_host_config_read_common(pbdev->pdev, pos + PCI_MSIX_FLAGS,
550 pci_config_size(pbdev->pdev), sizeof(ctrl));
551 table = pci_host_config_read_common(pbdev->pdev, pos + PCI_MSIX_TABLE,
552 pci_config_size(pbdev->pdev), sizeof(table));
553 pba = pci_host_config_read_common(pbdev->pdev, pos + PCI_MSIX_PBA,
554 pci_config_size(pbdev->pdev), sizeof(pba));
556 pbdev->msix.table_bar = table & PCI_MSIX_FLAGS_BIRMASK;
557 pbdev->msix.table_offset = table & ~PCI_MSIX_FLAGS_BIRMASK;
558 pbdev->msix.pba_bar = pba & PCI_MSIX_FLAGS_BIRMASK;
559 pbdev->msix.pba_offset = pba & ~PCI_MSIX_FLAGS_BIRMASK;
560 pbdev->msix.entries = (ctrl & PCI_MSIX_FLAGS_QSIZE) + 1;
561 pbdev->msix.available = true;
562 return 0;
565 static void s390_pcihost_hot_plug(HotplugHandler *hotplug_dev,
566 DeviceState *dev, Error **errp)
568 PCIDevice *pci_dev = PCI_DEVICE(dev);
569 S390PCIBusDevice *pbdev;
570 S390pciState *s = S390_PCI_HOST_BRIDGE(pci_device_root_bus(pci_dev)
571 ->qbus.parent);
573 pbdev = &s->pbdev[PCI_SLOT(pci_dev->devfn)];
575 pbdev->fid = s390_pci_get_pfid(pci_dev);
576 pbdev->pdev = pci_dev;
577 pbdev->state = ZPCI_FS_DISABLED;
578 pbdev->fh = s390_pci_get_pfh(pci_dev);
580 s390_pcihost_setup_msix(pbdev);
582 if (dev->hotplugged) {
583 s390_pci_generate_plug_event(HP_EVENT_RESERVED_TO_STANDBY,
584 pbdev->fh, pbdev->fid);
585 s390_pci_generate_plug_event(HP_EVENT_TO_CONFIGURED,
586 pbdev->fh, pbdev->fid);
590 static void s390_pcihost_hot_unplug(HotplugHandler *hotplug_dev,
591 DeviceState *dev, Error **errp)
593 PCIDevice *pci_dev = PCI_DEVICE(dev);
594 S390pciState *s = S390_PCI_HOST_BRIDGE(pci_device_root_bus(pci_dev)
595 ->qbus.parent);
596 S390PCIBusDevice *pbdev = &s->pbdev[PCI_SLOT(pci_dev->devfn)];
598 switch (pbdev->state) {
599 case ZPCI_FS_RESERVED:
600 goto out;
601 case ZPCI_FS_STANDBY:
602 break;
603 default:
604 s390_pci_generate_plug_event(HP_EVENT_CONFIGURED_TO_STBRES,
605 pbdev->fh, pbdev->fid);
608 s390_pci_generate_plug_event(HP_EVENT_STANDBY_TO_RESERVED,
609 pbdev->fh, pbdev->fid);
610 pbdev->fh = 0;
611 pbdev->fid = 0;
612 pbdev->pdev = NULL;
613 pbdev->state = ZPCI_FS_RESERVED;
614 out:
615 object_unparent(OBJECT(pci_dev));
618 static void s390_pcihost_class_init(ObjectClass *klass, void *data)
620 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
621 DeviceClass *dc = DEVICE_CLASS(klass);
622 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(klass);
624 dc->cannot_instantiate_with_device_add_yet = true;
625 k->init = s390_pcihost_init;
626 hc->plug = s390_pcihost_hot_plug;
627 hc->unplug = s390_pcihost_hot_unplug;
628 msi_nonbroken = true;
631 static const TypeInfo s390_pcihost_info = {
632 .name = TYPE_S390_PCI_HOST_BRIDGE,
633 .parent = TYPE_PCI_HOST_BRIDGE,
634 .instance_size = sizeof(S390pciState),
635 .class_init = s390_pcihost_class_init,
636 .interfaces = (InterfaceInfo[]) {
637 { TYPE_HOTPLUG_HANDLER },
642 static const TypeInfo s390_pcibus_info = {
643 .name = TYPE_S390_PCI_BUS,
644 .parent = TYPE_BUS,
645 .instance_size = sizeof(S390PCIBus),
648 static void s390_pci_register_types(void)
650 type_register_static(&s390_pcihost_info);
651 type_register_static(&s390_pcibus_info);
654 type_init(s390_pci_register_types)