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tests/qemu-iotests: Rework the checks and spots using GNU sed
[qemu.git] / hw / arm / npcm7xx.c
blobd85cc0276511b4ecbeae987fb49dc2d2c6b4738e
1 /*
2 * Nuvoton NPCM7xx SoC family.
3 *
4 * Copyright 2020 Google LLC
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 * for more details.
15 */
16
17 #include "qemu/osdep.h"
18
19 #include "hw/arm/boot.h"
20 #include "hw/arm/npcm7xx.h"
21 #include "hw/char/serial.h"
22 #include "hw/loader.h"
23 #include "hw/misc/unimp.h"
24 #include "hw/qdev-clock.h"
25 #include "hw/qdev-properties.h"
26 #include "qapi/error.h"
27 #include "qemu/units.h"
28 #include "sysemu/sysemu.h"
29
30 /*
31 * This covers the whole MMIO space. We'll use this to catch any MMIO accesses
32 * that aren't handled by any device.
33 */
34 #define NPCM7XX_MMIO_BA (0x80000000)
35 #define NPCM7XX_MMIO_SZ (0x7ffd0000)
36
37 /* OTP key storage and fuse strap array */
38 #define NPCM7XX_OTP1_BA (0xf0189000)
39 #define NPCM7XX_OTP2_BA (0xf018a000)
40
41 /* Core system modules. */
42 #define NPCM7XX_L2C_BA (0xf03fc000)
43 #define NPCM7XX_CPUP_BA (0xf03fe000)
44 #define NPCM7XX_GCR_BA (0xf0800000)
45 #define NPCM7XX_CLK_BA (0xf0801000)
46 #define NPCM7XX_MC_BA (0xf0824000)
47 #define NPCM7XX_RNG_BA (0xf000b000)
48
49 /* USB Host modules */
50 #define NPCM7XX_EHCI_BA (0xf0806000)
51 #define NPCM7XX_OHCI_BA (0xf0807000)
52
53 /* ADC Module */
54 #define NPCM7XX_ADC_BA (0xf000c000)
55
56 /* Internal AHB SRAM */
57 #define NPCM7XX_RAM3_BA (0xc0008000)
58 #define NPCM7XX_RAM3_SZ (4 * KiB)
59
60 /* Memory blocks at the end of the address space */
61 #define NPCM7XX_RAM2_BA (0xfffd0000)
62 #define NPCM7XX_RAM2_SZ (128 * KiB)
63 #define NPCM7XX_ROM_BA (0xffff0000)
64 #define NPCM7XX_ROM_SZ (64 * KiB)
65
66 /* SDHCI Modules */
67 #define NPCM7XX_MMC_BA (0xf0842000)
68
69 /* Clock configuration values to be fixed up when bypassing bootloader */
70
71 /* Run PLL1 at 1600 MHz */
72 #define NPCM7XX_PLLCON1_FIXUP_VAL (0x00402101)
73 /* Run the CPU from PLL1 and UART from PLL2 */
74 #define NPCM7XX_CLKSEL_FIXUP_VAL (0x004aaba9)
75
76 /*
77 * Interrupt lines going into the GIC. This does not include internal Cortex-A9
78 * interrupts.
79 */
80 enum NPCM7xxInterrupt {
81 NPCM7XX_ADC_IRQ = 0,
82 NPCM7XX_UART0_IRQ = 2,
83 NPCM7XX_UART1_IRQ,
84 NPCM7XX_UART2_IRQ,
85 NPCM7XX_UART3_IRQ,
86 NPCM7XX_EMC1RX_IRQ = 15,
87 NPCM7XX_EMC1TX_IRQ,
88 NPCM7XX_MMC_IRQ = 26,
89 NPCM7XX_TIMER0_IRQ = 32, /* Timer Module 0 */
90 NPCM7XX_TIMER1_IRQ,
91 NPCM7XX_TIMER2_IRQ,
92 NPCM7XX_TIMER3_IRQ,
93 NPCM7XX_TIMER4_IRQ,
94 NPCM7XX_TIMER5_IRQ, /* Timer Module 1 */
95 NPCM7XX_TIMER6_IRQ,
96 NPCM7XX_TIMER7_IRQ,
97 NPCM7XX_TIMER8_IRQ,
98 NPCM7XX_TIMER9_IRQ,
99 NPCM7XX_TIMER10_IRQ, /* Timer Module 2 */
100 NPCM7XX_TIMER11_IRQ,
101 NPCM7XX_TIMER12_IRQ,
102 NPCM7XX_TIMER13_IRQ,
103 NPCM7XX_TIMER14_IRQ,
104 NPCM7XX_WDG0_IRQ = 47, /* Timer Module 0 Watchdog */
105 NPCM7XX_WDG1_IRQ, /* Timer Module 1 Watchdog */
106 NPCM7XX_WDG2_IRQ, /* Timer Module 2 Watchdog */
107 NPCM7XX_EHCI_IRQ = 61,
108 NPCM7XX_OHCI_IRQ = 62,
109 NPCM7XX_SMBUS0_IRQ = 64,
110 NPCM7XX_SMBUS1_IRQ,
111 NPCM7XX_SMBUS2_IRQ,
112 NPCM7XX_SMBUS3_IRQ,
113 NPCM7XX_SMBUS4_IRQ,
114 NPCM7XX_SMBUS5_IRQ,
115 NPCM7XX_SMBUS6_IRQ,
116 NPCM7XX_SMBUS7_IRQ,
117 NPCM7XX_SMBUS8_IRQ,
118 NPCM7XX_SMBUS9_IRQ,
119 NPCM7XX_SMBUS10_IRQ,
120 NPCM7XX_SMBUS11_IRQ,
121 NPCM7XX_SMBUS12_IRQ,
122 NPCM7XX_SMBUS13_IRQ,
123 NPCM7XX_SMBUS14_IRQ,
124 NPCM7XX_SMBUS15_IRQ,
125 NPCM7XX_PWM0_IRQ = 93, /* PWM module 0 */
126 NPCM7XX_PWM1_IRQ, /* PWM module 1 */
127 NPCM7XX_MFT0_IRQ = 96, /* MFT module 0 */
128 NPCM7XX_MFT1_IRQ, /* MFT module 1 */
129 NPCM7XX_MFT2_IRQ, /* MFT module 2 */
130 NPCM7XX_MFT3_IRQ, /* MFT module 3 */
131 NPCM7XX_MFT4_IRQ, /* MFT module 4 */
132 NPCM7XX_MFT5_IRQ, /* MFT module 5 */
133 NPCM7XX_MFT6_IRQ, /* MFT module 6 */
134 NPCM7XX_MFT7_IRQ, /* MFT module 7 */
135 NPCM7XX_EMC2RX_IRQ = 114,
136 NPCM7XX_EMC2TX_IRQ,
137 NPCM7XX_GPIO0_IRQ = 116,
138 NPCM7XX_GPIO1_IRQ,
139 NPCM7XX_GPIO2_IRQ,
140 NPCM7XX_GPIO3_IRQ,
141 NPCM7XX_GPIO4_IRQ,
142 NPCM7XX_GPIO5_IRQ,
143 NPCM7XX_GPIO6_IRQ,
144 NPCM7XX_GPIO7_IRQ,
145 };
146
147 /* Total number of GIC interrupts, including internal Cortex-A9 interrupts. */
148 #define NPCM7XX_NUM_IRQ (160)
149
150 /* Register base address for each Timer Module */
151 static const hwaddr npcm7xx_tim_addr[] = {
152 0xf0008000,
153 0xf0009000,
154 0xf000a000,
155 };
156
157 /* Register base address for each 16550 UART */
158 static const hwaddr npcm7xx_uart_addr[] = {
159 0xf0001000,
160 0xf0002000,
161 0xf0003000,
162 0xf0004000,
163 };
164
165 /* Direct memory-mapped access to SPI0 CS0-1. */
166 static const hwaddr npcm7xx_fiu0_flash_addr[] = {
167 0x80000000, /* CS0 */
168 0x88000000, /* CS1 */
169 };
170
171 /* Direct memory-mapped access to SPI3 CS0-3. */
172 static const hwaddr npcm7xx_fiu3_flash_addr[] = {
173 0xa0000000, /* CS0 */
174 0xa8000000, /* CS1 */
175 0xb0000000, /* CS2 */
176 0xb8000000, /* CS3 */
177 };
178
179 /* Register base address for each PWM Module */
180 static const hwaddr npcm7xx_pwm_addr[] = {
181 0xf0103000,
182 0xf0104000,
183 };
184
185 /* Register base address for each MFT Module */
186 static const hwaddr npcm7xx_mft_addr[] = {
187 0xf0180000,
188 0xf0181000,
189 0xf0182000,
190 0xf0183000,
191 0xf0184000,
192 0xf0185000,
193 0xf0186000,
194 0xf0187000,
195 };
196
197 /* Direct memory-mapped access to each SMBus Module. */
198 static const hwaddr npcm7xx_smbus_addr[] = {
199 0xf0080000,
200 0xf0081000,
201 0xf0082000,
202 0xf0083000,
203 0xf0084000,
204 0xf0085000,
205 0xf0086000,
206 0xf0087000,
207 0xf0088000,
208 0xf0089000,
209 0xf008a000,
210 0xf008b000,
211 0xf008c000,
212 0xf008d000,
213 0xf008e000,
214 0xf008f000,
215 };
216
217 /* Register base address for each EMC Module */
218 static const hwaddr npcm7xx_emc_addr[] = {
219 0xf0825000,
220 0xf0826000,
221 };
222
223 static const struct {
224 hwaddr regs_addr;
225 uint32_t unconnected_pins;
226 uint32_t reset_pu;
227 uint32_t reset_pd;
228 uint32_t reset_osrc;
229 uint32_t reset_odsc;
230 } npcm7xx_gpio[] = {
231 {
232 .regs_addr = 0xf0010000,
233 .reset_pu = 0xff03ffff,
234 .reset_pd = 0x00fc0000,
235 }, {
236 .regs_addr = 0xf0011000,
237 .unconnected_pins = 0x0000001e,
238 .reset_pu = 0xfefffe07,
239 .reset_pd = 0x010001e0,
240 }, {
241 .regs_addr = 0xf0012000,
242 .reset_pu = 0x780fffff,
243 .reset_pd = 0x07f00000,
244 .reset_odsc = 0x00700000,
245 }, {
246 .regs_addr = 0xf0013000,
247 .reset_pu = 0x00fc0000,
248 .reset_pd = 0xff000000,
249 }, {
250 .regs_addr = 0xf0014000,
251 .reset_pu = 0xffffffff,
252 }, {
253 .regs_addr = 0xf0015000,
254 .reset_pu = 0xbf83f801,
255 .reset_pd = 0x007c0000,
256 .reset_osrc = 0x000000f1,
257 .reset_odsc = 0x3f9f80f1,
258 }, {
259 .regs_addr = 0xf0016000,
260 .reset_pu = 0xfc00f801,
261 .reset_pd = 0x000007fe,
262 .reset_odsc = 0x00000800,
263 }, {
264 .regs_addr = 0xf0017000,
265 .unconnected_pins = 0xffffff00,
266 .reset_pu = 0x0000007f,
267 .reset_osrc = 0x0000007f,
268 .reset_odsc = 0x0000007f,
269 },
270 };
271
272 static const struct {
273 const char *name;
274 hwaddr regs_addr;
275 int cs_count;
276 const hwaddr *flash_addr;
277 } npcm7xx_fiu[] = {
278 {
279 .name = "fiu0",
280 .regs_addr = 0xfb000000,
281 .cs_count = ARRAY_SIZE(npcm7xx_fiu0_flash_addr),
282 .flash_addr = npcm7xx_fiu0_flash_addr,
283 }, {
284 .name = "fiu3",
285 .regs_addr = 0xc0000000,
286 .cs_count = ARRAY_SIZE(npcm7xx_fiu3_flash_addr),
287 .flash_addr = npcm7xx_fiu3_flash_addr,
288 },
289 };
290
291 static void npcm7xx_write_board_setup(ARMCPU *cpu,
292 const struct arm_boot_info *info)
293 {
294 uint32_t board_setup[] = {
295 0xe59f0010, /* ldr r0, clk_base_addr */
296 0xe59f1010, /* ldr r1, pllcon1_value */
297 0xe5801010, /* str r1, [r0, #16] */
298 0xe59f100c, /* ldr r1, clksel_value */
299 0xe5801004, /* str r1, [r0, #4] */
300 0xe12fff1e, /* bx lr */
301 NPCM7XX_CLK_BA,
302 NPCM7XX_PLLCON1_FIXUP_VAL,
303 NPCM7XX_CLKSEL_FIXUP_VAL,
304 };
305 int i;
306
307 for (i = 0; i < ARRAY_SIZE(board_setup); i++) {
308 board_setup[i] = tswap32(board_setup[i]);
309 }
310 rom_add_blob_fixed("board-setup", board_setup, sizeof(board_setup),
311 info->board_setup_addr);
312 }
313
314 static void npcm7xx_write_secondary_boot(ARMCPU *cpu,
315 const struct arm_boot_info *info)
316 {
317 /*
318 * The default smpboot stub halts the secondary CPU with a 'wfi'
319 * instruction, but the arch/arm/mach-npcm/platsmp.c in the Linux kernel
320 * does not send an IPI to wake it up, so the second CPU fails to boot. So
321 * we need to provide our own smpboot stub that can not use 'wfi', it has
322 * to spin the secondary CPU until the first CPU writes to the SCRPAD reg.
323 */
324 uint32_t smpboot[] = {
325 0xe59f2018, /* ldr r2, bootreg_addr */
326 0xe3a00000, /* mov r0, #0 */
327 0xe5820000, /* str r0, [r2] */
328 0xe320f002, /* wfe */
329 0xe5921000, /* ldr r1, [r2] */
330 0xe1110001, /* tst r1, r1 */
331 0x0afffffb, /* beq <wfe> */
332 0xe12fff11, /* bx r1 */
333 NPCM7XX_SMP_BOOTREG_ADDR,
334 };
335 int i;
336
337 for (i = 0; i < ARRAY_SIZE(smpboot); i++) {
338 smpboot[i] = tswap32(smpboot[i]);
339 }
340
341 rom_add_blob_fixed("smpboot", smpboot, sizeof(smpboot),
342 NPCM7XX_SMP_LOADER_START);
343 }
344
345 static struct arm_boot_info npcm7xx_binfo = {
346 .loader_start = NPCM7XX_LOADER_START,
347 .smp_loader_start = NPCM7XX_SMP_LOADER_START,
348 .smp_bootreg_addr = NPCM7XX_SMP_BOOTREG_ADDR,
349 .gic_cpu_if_addr = NPCM7XX_GIC_CPU_IF_ADDR,
350 .write_secondary_boot = npcm7xx_write_secondary_boot,
351 .board_id = -1,
352 .board_setup_addr = NPCM7XX_BOARD_SETUP_ADDR,
353 .write_board_setup = npcm7xx_write_board_setup,
354 };
355
356 void npcm7xx_load_kernel(MachineState *machine, NPCM7xxState *soc)
357 {
358 npcm7xx_binfo.ram_size = machine->ram_size;
359
360 arm_load_kernel(&soc->cpu[0], machine, &npcm7xx_binfo);
361 }
362
363 static void npcm7xx_init_fuses(NPCM7xxState *s)
364 {
365 NPCM7xxClass *nc = NPCM7XX_GET_CLASS(s);
366 uint32_t value;
367
368 /*
369 * The initial mask of disabled modules indicates the chip derivative (e.g.
370 * NPCM750 or NPCM730).
371 */
372 value = tswap32(nc->disabled_modules);
373 npcm7xx_otp_array_write(&s->fuse_array, &value, NPCM7XX_FUSE_DERIVATIVE,
374 sizeof(value));
375 }
376
377 static void npcm7xx_write_adc_calibration(NPCM7xxState *s)
378 {
379 /* Both ADC and the fuse array must have realized. */
380 QEMU_BUILD_BUG_ON(sizeof(s->adc.calibration_r_values) != 4);
381 npcm7xx_otp_array_write(&s->fuse_array, s->adc.calibration_r_values,
382 NPCM7XX_FUSE_ADC_CALIB, sizeof(s->adc.calibration_r_values));
383 }
384
385 static qemu_irq npcm7xx_irq(NPCM7xxState *s, int n)
386 {
387 return qdev_get_gpio_in(DEVICE(&s->a9mpcore), n);
388 }
389
390 static void npcm7xx_init(Object *obj)
391 {
392 NPCM7xxState *s = NPCM7XX(obj);
393 int i;
394
395 for (i = 0; i < NPCM7XX_MAX_NUM_CPUS; i++) {
396 object_initialize_child(obj, "cpu[*]", &s->cpu[i],
397 ARM_CPU_TYPE_NAME("cortex-a9"));
398 }
399
400 object_initialize_child(obj, "a9mpcore", &s->a9mpcore, TYPE_A9MPCORE_PRIV);
401 object_initialize_child(obj, "gcr", &s->gcr, TYPE_NPCM7XX_GCR);
402 object_property_add_alias(obj, "power-on-straps", OBJECT(&s->gcr),
403 "power-on-straps");
404 object_initialize_child(obj, "clk", &s->clk, TYPE_NPCM7XX_CLK);
405 object_initialize_child(obj, "otp1", &s->key_storage,
406 TYPE_NPCM7XX_KEY_STORAGE);
407 object_initialize_child(obj, "otp2", &s->fuse_array,
408 TYPE_NPCM7XX_FUSE_ARRAY);
409 object_initialize_child(obj, "mc", &s->mc, TYPE_NPCM7XX_MC);
410 object_initialize_child(obj, "rng", &s->rng, TYPE_NPCM7XX_RNG);
411 object_initialize_child(obj, "adc", &s->adc, TYPE_NPCM7XX_ADC);
412
413 for (i = 0; i < ARRAY_SIZE(s->tim); i++) {
414 object_initialize_child(obj, "tim[*]", &s->tim[i], TYPE_NPCM7XX_TIMER);
415 }
416
417 for (i = 0; i < ARRAY_SIZE(s->gpio); i++) {
418 object_initialize_child(obj, "gpio[*]", &s->gpio[i], TYPE_NPCM7XX_GPIO);
419 }
420
421 for (i = 0; i < ARRAY_SIZE(s->smbus); i++) {
422 object_initialize_child(obj, "smbus[*]", &s->smbus[i],
423 TYPE_NPCM7XX_SMBUS);
424 }
425
426 object_initialize_child(obj, "ehci", &s->ehci, TYPE_NPCM7XX_EHCI);
427 object_initialize_child(obj, "ohci", &s->ohci, TYPE_SYSBUS_OHCI);
428
429 QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_fiu) != ARRAY_SIZE(s->fiu));
430 for (i = 0; i < ARRAY_SIZE(s->fiu); i++) {
431 object_initialize_child(obj, npcm7xx_fiu[i].name, &s->fiu[i],
432 TYPE_NPCM7XX_FIU);
433 }
434
435 for (i = 0; i < ARRAY_SIZE(s->pwm); i++) {
436 object_initialize_child(obj, "pwm[*]", &s->pwm[i], TYPE_NPCM7XX_PWM);
437 }
438
439 for (i = 0; i < ARRAY_SIZE(s->mft); i++) {
440 object_initialize_child(obj, "mft[*]", &s->mft[i], TYPE_NPCM7XX_MFT);
441 }
442
443 for (i = 0; i < ARRAY_SIZE(s->emc); i++) {
444 object_initialize_child(obj, "emc[*]", &s->emc[i], TYPE_NPCM7XX_EMC);
445 }
446
447 object_initialize_child(obj, "mmc", &s->mmc, TYPE_NPCM7XX_SDHCI);
448 }
449
450 static void npcm7xx_realize(DeviceState *dev, Error **errp)
451 {
452 NPCM7xxState *s = NPCM7XX(dev);
453 NPCM7xxClass *nc = NPCM7XX_GET_CLASS(s);
454 int i;
455
456 if (memory_region_size(s->dram) > NPCM7XX_DRAM_SZ) {
457 error_setg(errp, "%s: NPCM7xx cannot address more than %" PRIu64
458 " MiB of DRAM", __func__, NPCM7XX_DRAM_SZ / MiB);
459 return;
460 }
461
462 /* CPUs */
463 for (i = 0; i < nc->num_cpus; i++) {
464 object_property_set_int(OBJECT(&s->cpu[i]), "mp-affinity",
465 arm_cpu_mp_affinity(i, NPCM7XX_MAX_NUM_CPUS),
466 &error_abort);
467 object_property_set_int(OBJECT(&s->cpu[i]), "reset-cbar",
468 NPCM7XX_GIC_CPU_IF_ADDR, &error_abort);
469 object_property_set_bool(OBJECT(&s->cpu[i]), "reset-hivecs", true,
470 &error_abort);
471
472 /* Disable security extensions. */
473 object_property_set_bool(OBJECT(&s->cpu[i]), "has_el3", false,
474 &error_abort);
475
476 if (!qdev_realize(DEVICE(&s->cpu[i]), NULL, errp)) {
477 return;
478 }
479 }
480
481 /* A9MPCORE peripherals. Can only fail if we pass bad parameters here. */
482 object_property_set_int(OBJECT(&s->a9mpcore), "num-cpu", nc->num_cpus,
483 &error_abort);
484 object_property_set_int(OBJECT(&s->a9mpcore), "num-irq", NPCM7XX_NUM_IRQ,
485 &error_abort);
486 sysbus_realize(SYS_BUS_DEVICE(&s->a9mpcore), &error_abort);
487 sysbus_mmio_map(SYS_BUS_DEVICE(&s->a9mpcore), 0, NPCM7XX_CPUP_BA);
488
489 for (i = 0; i < nc->num_cpus; i++) {
490 sysbus_connect_irq(SYS_BUS_DEVICE(&s->a9mpcore), i,
491 qdev_get_gpio_in(DEVICE(&s->cpu[i]), ARM_CPU_IRQ));
492 sysbus_connect_irq(SYS_BUS_DEVICE(&s->a9mpcore), i + nc->num_cpus,
493 qdev_get_gpio_in(DEVICE(&s->cpu[i]), ARM_CPU_FIQ));
494 }
495
496 /* L2 cache controller */
497 sysbus_create_simple("l2x0", NPCM7XX_L2C_BA, NULL);
498
499 /* System Global Control Registers (GCR). Can fail due to user input. */
500 object_property_set_int(OBJECT(&s->gcr), "disabled-modules",
501 nc->disabled_modules, &error_abort);
502 object_property_add_const_link(OBJECT(&s->gcr), "dram-mr", OBJECT(s->dram));
503 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gcr), errp)) {
504 return;
505 }
506 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gcr), 0, NPCM7XX_GCR_BA);
507
508 /* Clock Control Registers (CLK). Cannot fail. */
509 sysbus_realize(SYS_BUS_DEVICE(&s->clk), &error_abort);
510 sysbus_mmio_map(SYS_BUS_DEVICE(&s->clk), 0, NPCM7XX_CLK_BA);
511
512 /* OTP key storage and fuse strap array. Cannot fail. */
513 sysbus_realize(SYS_BUS_DEVICE(&s->key_storage), &error_abort);
514 sysbus_mmio_map(SYS_BUS_DEVICE(&s->key_storage), 0, NPCM7XX_OTP1_BA);
515 sysbus_realize(SYS_BUS_DEVICE(&s->fuse_array), &error_abort);
516 sysbus_mmio_map(SYS_BUS_DEVICE(&s->fuse_array), 0, NPCM7XX_OTP2_BA);
517 npcm7xx_init_fuses(s);
518
519 /* Fake Memory Controller (MC). Cannot fail. */
520 sysbus_realize(SYS_BUS_DEVICE(&s->mc), &error_abort);
521 sysbus_mmio_map(SYS_BUS_DEVICE(&s->mc), 0, NPCM7XX_MC_BA);
522
523 /* ADC Modules. Cannot fail. */
524 qdev_connect_clock_in(DEVICE(&s->adc), "clock", qdev_get_clock_out(
525 DEVICE(&s->clk), "adc-clock"));
526 sysbus_realize(SYS_BUS_DEVICE(&s->adc), &error_abort);
527 sysbus_mmio_map(SYS_BUS_DEVICE(&s->adc), 0, NPCM7XX_ADC_BA);
528 sysbus_connect_irq(SYS_BUS_DEVICE(&s->adc), 0,
529 npcm7xx_irq(s, NPCM7XX_ADC_IRQ));
530 npcm7xx_write_adc_calibration(s);
531
532 /* Timer Modules (TIM). Cannot fail. */
533 QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_tim_addr) != ARRAY_SIZE(s->tim));
534 for (i = 0; i < ARRAY_SIZE(s->tim); i++) {
535 SysBusDevice *sbd = SYS_BUS_DEVICE(&s->tim[i]);
536 int first_irq;
537 int j;
538
539 /* Connect the timer clock. */
540 qdev_connect_clock_in(DEVICE(&s->tim[i]), "clock", qdev_get_clock_out(
541 DEVICE(&s->clk), "timer-clock"));
542
543 sysbus_realize(sbd, &error_abort);
544 sysbus_mmio_map(sbd, 0, npcm7xx_tim_addr[i]);
545
546 first_irq = NPCM7XX_TIMER0_IRQ + i * NPCM7XX_TIMERS_PER_CTRL;
547 for (j = 0; j < NPCM7XX_TIMERS_PER_CTRL; j++) {
548 qemu_irq irq = npcm7xx_irq(s, first_irq + j);
549 sysbus_connect_irq(sbd, j, irq);
550 }
551
552 /* IRQ for watchdogs */
553 sysbus_connect_irq(sbd, NPCM7XX_TIMERS_PER_CTRL,
554 npcm7xx_irq(s, NPCM7XX_WDG0_IRQ + i));
555 /* GPIO that connects clk module with watchdog */
556 qdev_connect_gpio_out_named(DEVICE(&s->tim[i]),
557 NPCM7XX_WATCHDOG_RESET_GPIO_OUT, 0,
558 qdev_get_gpio_in_named(DEVICE(&s->clk),
559 NPCM7XX_WATCHDOG_RESET_GPIO_IN, i));
560 }
561
562 /* UART0..3 (16550 compatible) */
563 for (i = 0; i < ARRAY_SIZE(npcm7xx_uart_addr); i++) {
564 serial_mm_init(get_system_memory(), npcm7xx_uart_addr[i], 2,
565 npcm7xx_irq(s, NPCM7XX_UART0_IRQ + i), 115200,
566 serial_hd(i), DEVICE_LITTLE_ENDIAN);
567 }
568
569 /* Random Number Generator. Cannot fail. */
570 sysbus_realize(SYS_BUS_DEVICE(&s->rng), &error_abort);
571 sysbus_mmio_map(SYS_BUS_DEVICE(&s->rng), 0, NPCM7XX_RNG_BA);
572
573 /* GPIO modules. Cannot fail. */
574 QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_gpio) != ARRAY_SIZE(s->gpio));
575 for (i = 0; i < ARRAY_SIZE(s->gpio); i++) {
576 Object *obj = OBJECT(&s->gpio[i]);
577
578 object_property_set_uint(obj, "reset-pullup",
579 npcm7xx_gpio[i].reset_pu, &error_abort);
580 object_property_set_uint(obj, "reset-pulldown",
581 npcm7xx_gpio[i].reset_pd, &error_abort);
582 object_property_set_uint(obj, "reset-osrc",
583 npcm7xx_gpio[i].reset_osrc, &error_abort);
584 object_property_set_uint(obj, "reset-odsc",
585 npcm7xx_gpio[i].reset_odsc, &error_abort);
586 sysbus_realize(SYS_BUS_DEVICE(obj), &error_abort);
587 sysbus_mmio_map(SYS_BUS_DEVICE(obj), 0, npcm7xx_gpio[i].regs_addr);
588 sysbus_connect_irq(SYS_BUS_DEVICE(obj), 0,
589 npcm7xx_irq(s, NPCM7XX_GPIO0_IRQ + i));
590 }
591
592 /* SMBus modules. Cannot fail. */
593 QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_smbus_addr) != ARRAY_SIZE(s->smbus));
594 for (i = 0; i < ARRAY_SIZE(s->smbus); i++) {
595 Object *obj = OBJECT(&s->smbus[i]);
596
597 sysbus_realize(SYS_BUS_DEVICE(obj), &error_abort);
598 sysbus_mmio_map(SYS_BUS_DEVICE(obj), 0, npcm7xx_smbus_addr[i]);
599 sysbus_connect_irq(SYS_BUS_DEVICE(obj), 0,
600 npcm7xx_irq(s, NPCM7XX_SMBUS0_IRQ + i));
601 }
602
603 /* USB Host */
604 object_property_set_bool(OBJECT(&s->ehci), "companion-enable", true,
605 &error_abort);
606 sysbus_realize(SYS_BUS_DEVICE(&s->ehci), &error_abort);
607 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ehci), 0, NPCM7XX_EHCI_BA);
608 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci), 0,
609 npcm7xx_irq(s, NPCM7XX_EHCI_IRQ));
610
611 object_property_set_str(OBJECT(&s->ohci), "masterbus", "usb-bus.0",
612 &error_abort);
613 object_property_set_uint(OBJECT(&s->ohci), "num-ports", 1, &error_abort);
614 sysbus_realize(SYS_BUS_DEVICE(&s->ohci), &error_abort);
615 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ohci), 0, NPCM7XX_OHCI_BA);
616 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ohci), 0,
617 npcm7xx_irq(s, NPCM7XX_OHCI_IRQ));
618
619 /* PWM Modules. Cannot fail. */
620 QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_pwm_addr) != ARRAY_SIZE(s->pwm));
621 for (i = 0; i < ARRAY_SIZE(s->pwm); i++) {
622 SysBusDevice *sbd = SYS_BUS_DEVICE(&s->pwm[i]);
623
624 qdev_connect_clock_in(DEVICE(&s->pwm[i]), "clock", qdev_get_clock_out(
625 DEVICE(&s->clk), "apb3-clock"));
626 sysbus_realize(sbd, &error_abort);
627 sysbus_mmio_map(sbd, 0, npcm7xx_pwm_addr[i]);
628 sysbus_connect_irq(sbd, i, npcm7xx_irq(s, NPCM7XX_PWM0_IRQ + i));
629 }
630
631 /* MFT Modules. Cannot fail. */
632 QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_mft_addr) != ARRAY_SIZE(s->mft));
633 for (i = 0; i < ARRAY_SIZE(s->mft); i++) {
634 SysBusDevice *sbd = SYS_BUS_DEVICE(&s->mft[i]);
635
636 qdev_connect_clock_in(DEVICE(&s->mft[i]), "clock-in",
637 qdev_get_clock_out(DEVICE(&s->clk),
638 "apb4-clock"));
639 sysbus_realize(sbd, &error_abort);
640 sysbus_mmio_map(sbd, 0, npcm7xx_mft_addr[i]);
641 sysbus_connect_irq(sbd, 0, npcm7xx_irq(s, NPCM7XX_MFT0_IRQ + i));
642 }
643
644 /*
645 * EMC Modules. Cannot fail.
646 * The mapping of the device to its netdev backend works as follows:
647 * emc[i] = nd_table[i]
648 * This works around the inability to specify the netdev property for the
649 * emc device: it's not pluggable and thus the -device option can't be
650 * used.
651 */
652 QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_emc_addr) != ARRAY_SIZE(s->emc));
653 QEMU_BUILD_BUG_ON(ARRAY_SIZE(s->emc) != 2);
654 for (i = 0; i < ARRAY_SIZE(s->emc); i++) {
655 s->emc[i].emc_num = i;
656 SysBusDevice *sbd = SYS_BUS_DEVICE(&s->emc[i]);
657 if (nd_table[i].used) {
658 qemu_check_nic_model(&nd_table[i], TYPE_NPCM7XX_EMC);
659 qdev_set_nic_properties(DEVICE(sbd), &nd_table[i]);
660 }
661 /*
662 * The device exists regardless of whether it's connected to a QEMU
663 * netdev backend. So always instantiate it even if there is no
664 * backend.
665 */
666 sysbus_realize(sbd, &error_abort);
667 sysbus_mmio_map(sbd, 0, npcm7xx_emc_addr[i]);
668 int tx_irq = i == 0 ? NPCM7XX_EMC1TX_IRQ : NPCM7XX_EMC2TX_IRQ;
669 int rx_irq = i == 0 ? NPCM7XX_EMC1RX_IRQ : NPCM7XX_EMC2RX_IRQ;
670 /*
671 * N.B. The values for the second argument sysbus_connect_irq are
672 * chosen to match the registration order in npcm7xx_emc_realize.
673 */
674 sysbus_connect_irq(sbd, 0, npcm7xx_irq(s, tx_irq));
675 sysbus_connect_irq(sbd, 1, npcm7xx_irq(s, rx_irq));
676 }
677
678 /*
679 * Flash Interface Unit (FIU). Can fail if incorrect number of chip selects
680 * specified, but this is a programming error.
681 */
682 QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_fiu) != ARRAY_SIZE(s->fiu));
683 for (i = 0; i < ARRAY_SIZE(s->fiu); i++) {
684 SysBusDevice *sbd = SYS_BUS_DEVICE(&s->fiu[i]);
685 int j;
686
687 object_property_set_int(OBJECT(sbd), "cs-count",
688 npcm7xx_fiu[i].cs_count, &error_abort);
689 sysbus_realize(sbd, &error_abort);
690
691 sysbus_mmio_map(sbd, 0, npcm7xx_fiu[i].regs_addr);
692 for (j = 0; j < npcm7xx_fiu[i].cs_count; j++) {
693 sysbus_mmio_map(sbd, j + 1, npcm7xx_fiu[i].flash_addr[j]);
694 }
695 }
696
697 /* RAM2 (SRAM) */
698 memory_region_init_ram(&s->sram, OBJECT(dev), "ram2",
699 NPCM7XX_RAM2_SZ, &error_abort);
700 memory_region_add_subregion(get_system_memory(), NPCM7XX_RAM2_BA, &s->sram);
701
702 /* RAM3 (SRAM) */
703 memory_region_init_ram(&s->ram3, OBJECT(dev), "ram3",
704 NPCM7XX_RAM3_SZ, &error_abort);
705 memory_region_add_subregion(get_system_memory(), NPCM7XX_RAM3_BA, &s->ram3);
706
707 /* Internal ROM */
708 memory_region_init_rom(&s->irom, OBJECT(dev), "irom", NPCM7XX_ROM_SZ,
709 &error_abort);
710 memory_region_add_subregion(get_system_memory(), NPCM7XX_ROM_BA, &s->irom);
711
712 /* SDHCI */
713 sysbus_realize(SYS_BUS_DEVICE(&s->mmc), &error_abort);
714 sysbus_mmio_map(SYS_BUS_DEVICE(&s->mmc), 0, NPCM7XX_MMC_BA);
715 sysbus_connect_irq(SYS_BUS_DEVICE(&s->mmc), 0,
716 npcm7xx_irq(s, NPCM7XX_MMC_IRQ));
717
718 create_unimplemented_device("npcm7xx.shm", 0xc0001000, 4 * KiB);
719 create_unimplemented_device("npcm7xx.vdmx", 0xe0800000, 4 * KiB);
720 create_unimplemented_device("npcm7xx.pcierc", 0xe1000000, 64 * KiB);
721 create_unimplemented_device("npcm7xx.kcs", 0xf0007000, 4 * KiB);
722 create_unimplemented_device("npcm7xx.gfxi", 0xf000e000, 4 * KiB);
723 create_unimplemented_device("npcm7xx.espi", 0xf009f000, 4 * KiB);
724 create_unimplemented_device("npcm7xx.peci", 0xf0100000, 4 * KiB);
725 create_unimplemented_device("npcm7xx.siox[1]", 0xf0101000, 4 * KiB);
726 create_unimplemented_device("npcm7xx.siox[2]", 0xf0102000, 4 * KiB);
727 create_unimplemented_device("npcm7xx.pspi1", 0xf0200000, 4 * KiB);
728 create_unimplemented_device("npcm7xx.pspi2", 0xf0201000, 4 * KiB);
729 create_unimplemented_device("npcm7xx.ahbpci", 0xf0400000, 1 * MiB);
730 create_unimplemented_device("npcm7xx.mcphy", 0xf05f0000, 64 * KiB);
731 create_unimplemented_device("npcm7xx.gmac1", 0xf0802000, 8 * KiB);
732 create_unimplemented_device("npcm7xx.gmac2", 0xf0804000, 8 * KiB);
733 create_unimplemented_device("npcm7xx.vcd", 0xf0810000, 64 * KiB);
734 create_unimplemented_device("npcm7xx.ece", 0xf0820000, 8 * KiB);
735 create_unimplemented_device("npcm7xx.vdma", 0xf0822000, 8 * KiB);
736 create_unimplemented_device("npcm7xx.usbd[0]", 0xf0830000, 4 * KiB);
737 create_unimplemented_device("npcm7xx.usbd[1]", 0xf0831000, 4 * KiB);
738 create_unimplemented_device("npcm7xx.usbd[2]", 0xf0832000, 4 * KiB);
739 create_unimplemented_device("npcm7xx.usbd[3]", 0xf0833000, 4 * KiB);
740 create_unimplemented_device("npcm7xx.usbd[4]", 0xf0834000, 4 * KiB);
741 create_unimplemented_device("npcm7xx.usbd[5]", 0xf0835000, 4 * KiB);
742 create_unimplemented_device("npcm7xx.usbd[6]", 0xf0836000, 4 * KiB);
743 create_unimplemented_device("npcm7xx.usbd[7]", 0xf0837000, 4 * KiB);
744 create_unimplemented_device("npcm7xx.usbd[8]", 0xf0838000, 4 * KiB);
745 create_unimplemented_device("npcm7xx.usbd[9]", 0xf0839000, 4 * KiB);
746 create_unimplemented_device("npcm7xx.sd", 0xf0840000, 8 * KiB);
747 create_unimplemented_device("npcm7xx.pcimbx", 0xf0848000, 512 * KiB);
748 create_unimplemented_device("npcm7xx.aes", 0xf0858000, 4 * KiB);
749 create_unimplemented_device("npcm7xx.des", 0xf0859000, 4 * KiB);
750 create_unimplemented_device("npcm7xx.sha", 0xf085a000, 4 * KiB);
751 create_unimplemented_device("npcm7xx.secacc", 0xf085b000, 4 * KiB);
752 create_unimplemented_device("npcm7xx.spixcs0", 0xf8000000, 16 * MiB);
753 create_unimplemented_device("npcm7xx.spixcs1", 0xf9000000, 16 * MiB);
754 create_unimplemented_device("npcm7xx.spix", 0xfb001000, 4 * KiB);
755 }
756
757 static Property npcm7xx_properties[] = {
758 DEFINE_PROP_LINK("dram-mr", NPCM7xxState, dram, TYPE_MEMORY_REGION,
759 MemoryRegion *),
760 DEFINE_PROP_END_OF_LIST(),
761 };
762
763 static void npcm7xx_class_init(ObjectClass *oc, void *data)
764 {
765 DeviceClass *dc = DEVICE_CLASS(oc);
766
767 dc->realize = npcm7xx_realize;
768 dc->user_creatable = false;
769 device_class_set_props(dc, npcm7xx_properties);
770 }
771
772 static void npcm730_class_init(ObjectClass *oc, void *data)
773 {
774 NPCM7xxClass *nc = NPCM7XX_CLASS(oc);
775
776 /* NPCM730 is optimized for data center use, so no graphics, etc. */
777 nc->disabled_modules = 0x00300395;
778 nc->num_cpus = 2;
779 }
780
781 static void npcm750_class_init(ObjectClass *oc, void *data)
782 {
783 NPCM7xxClass *nc = NPCM7XX_CLASS(oc);
784
785 /* NPCM750 has 2 cores and a full set of peripherals */
786 nc->disabled_modules = 0x00000000;
787 nc->num_cpus = 2;
788 }
789
790 static const TypeInfo npcm7xx_soc_types[] = {
791 {
792 .name = TYPE_NPCM7XX,
793 .parent = TYPE_DEVICE,
794 .instance_size = sizeof(NPCM7xxState),
795 .instance_init = npcm7xx_init,
796 .class_size = sizeof(NPCM7xxClass),
797 .class_init = npcm7xx_class_init,
798 .abstract = true,
799 }, {
800 .name = TYPE_NPCM730,
801 .parent = TYPE_NPCM7XX,
802 .class_init = npcm730_class_init,
803 }, {
804 .name = TYPE_NPCM750,
805 .parent = TYPE_NPCM7XX,
806 .class_init = npcm750_class_init,
807 },
808 };
809
810 DEFINE_TYPES(npcm7xx_soc_types);
QEmu