2 * QEMU Cirrus CLGD 54xx VGA Emulator.
4 * Copyright (c) 2004 Fabrice Bellard
5 * Copyright (c) 2004 Makoto Suzuki (suzu)
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
26 * Reference: Finn Thogersons' VGADOC4b
27 * available at http://home.worldonline.dk/~finth/
35 #include "exec-memory.h"
39 * - destination write mask support not complete (bits 5..7)
40 * - optimize linear mappings
41 * - optimize bitblt functions
44 //#define DEBUG_CIRRUS
45 //#define DEBUG_BITBLT
47 /***************************************
51 ***************************************/
54 #define CIRRUS_ID_CLGD5422 (0x23<<2)
55 #define CIRRUS_ID_CLGD5426 (0x24<<2)
56 #define CIRRUS_ID_CLGD5424 (0x25<<2)
57 #define CIRRUS_ID_CLGD5428 (0x26<<2)
58 #define CIRRUS_ID_CLGD5430 (0x28<<2)
59 #define CIRRUS_ID_CLGD5434 (0x2A<<2)
60 #define CIRRUS_ID_CLGD5436 (0x2B<<2)
61 #define CIRRUS_ID_CLGD5446 (0x2E<<2)
64 #define CIRRUS_SR7_BPP_VGA 0x00
65 #define CIRRUS_SR7_BPP_SVGA 0x01
66 #define CIRRUS_SR7_BPP_MASK 0x0e
67 #define CIRRUS_SR7_BPP_8 0x00
68 #define CIRRUS_SR7_BPP_16_DOUBLEVCLK 0x02
69 #define CIRRUS_SR7_BPP_24 0x04
70 #define CIRRUS_SR7_BPP_16 0x06
71 #define CIRRUS_SR7_BPP_32 0x08
72 #define CIRRUS_SR7_ISAADDR_MASK 0xe0
75 #define CIRRUS_MEMSIZE_512k 0x08
76 #define CIRRUS_MEMSIZE_1M 0x10
77 #define CIRRUS_MEMSIZE_2M 0x18
78 #define CIRRUS_MEMFLAGS_BANKSWITCH 0x80 // bank switching is enabled.
81 #define CIRRUS_CURSOR_SHOW 0x01
82 #define CIRRUS_CURSOR_HIDDENPEL 0x02
83 #define CIRRUS_CURSOR_LARGE 0x04 // 64x64 if set, 32x32 if clear
86 #define CIRRUS_BUSTYPE_VLBFAST 0x10
87 #define CIRRUS_BUSTYPE_PCI 0x20
88 #define CIRRUS_BUSTYPE_VLBSLOW 0x30
89 #define CIRRUS_BUSTYPE_ISA 0x38
90 #define CIRRUS_MMIO_ENABLE 0x04
91 #define CIRRUS_MMIO_USE_PCIADDR 0x40 // 0xb8000 if cleared.
92 #define CIRRUS_MEMSIZEEXT_DOUBLE 0x80
95 #define CIRRUS_BANKING_DUAL 0x01
96 #define CIRRUS_BANKING_GRANULARITY_16K 0x20 // set:16k, clear:4k
99 #define CIRRUS_BLTMODE_BACKWARDS 0x01
100 #define CIRRUS_BLTMODE_MEMSYSDEST 0x02
101 #define CIRRUS_BLTMODE_MEMSYSSRC 0x04
102 #define CIRRUS_BLTMODE_TRANSPARENTCOMP 0x08
103 #define CIRRUS_BLTMODE_PATTERNCOPY 0x40
104 #define CIRRUS_BLTMODE_COLOREXPAND 0x80
105 #define CIRRUS_BLTMODE_PIXELWIDTHMASK 0x30
106 #define CIRRUS_BLTMODE_PIXELWIDTH8 0x00
107 #define CIRRUS_BLTMODE_PIXELWIDTH16 0x10
108 #define CIRRUS_BLTMODE_PIXELWIDTH24 0x20
109 #define CIRRUS_BLTMODE_PIXELWIDTH32 0x30
112 #define CIRRUS_BLT_BUSY 0x01
113 #define CIRRUS_BLT_START 0x02
114 #define CIRRUS_BLT_RESET 0x04
115 #define CIRRUS_BLT_FIFOUSED 0x10
116 #define CIRRUS_BLT_AUTOSTART 0x80
119 #define CIRRUS_ROP_0 0x00
120 #define CIRRUS_ROP_SRC_AND_DST 0x05
121 #define CIRRUS_ROP_NOP 0x06
122 #define CIRRUS_ROP_SRC_AND_NOTDST 0x09
123 #define CIRRUS_ROP_NOTDST 0x0b
124 #define CIRRUS_ROP_SRC 0x0d
125 #define CIRRUS_ROP_1 0x0e
126 #define CIRRUS_ROP_NOTSRC_AND_DST 0x50
127 #define CIRRUS_ROP_SRC_XOR_DST 0x59
128 #define CIRRUS_ROP_SRC_OR_DST 0x6d
129 #define CIRRUS_ROP_NOTSRC_OR_NOTDST 0x90
130 #define CIRRUS_ROP_SRC_NOTXOR_DST 0x95
131 #define CIRRUS_ROP_SRC_OR_NOTDST 0xad
132 #define CIRRUS_ROP_NOTSRC 0xd0
133 #define CIRRUS_ROP_NOTSRC_OR_DST 0xd6
134 #define CIRRUS_ROP_NOTSRC_AND_NOTDST 0xda
136 #define CIRRUS_ROP_NOP_INDEX 2
137 #define CIRRUS_ROP_SRC_INDEX 5
140 #define CIRRUS_BLTMODEEXT_SOLIDFILL 0x04
141 #define CIRRUS_BLTMODEEXT_COLOREXPINV 0x02
142 #define CIRRUS_BLTMODEEXT_DWORDGRANULARITY 0x01
145 #define CIRRUS_MMIO_BLTBGCOLOR 0x00 // dword
146 #define CIRRUS_MMIO_BLTFGCOLOR 0x04 // dword
147 #define CIRRUS_MMIO_BLTWIDTH 0x08 // word
148 #define CIRRUS_MMIO_BLTHEIGHT 0x0a // word
149 #define CIRRUS_MMIO_BLTDESTPITCH 0x0c // word
150 #define CIRRUS_MMIO_BLTSRCPITCH 0x0e // word
151 #define CIRRUS_MMIO_BLTDESTADDR 0x10 // dword
152 #define CIRRUS_MMIO_BLTSRCADDR 0x14 // dword
153 #define CIRRUS_MMIO_BLTWRITEMASK 0x17 // byte
154 #define CIRRUS_MMIO_BLTMODE 0x18 // byte
155 #define CIRRUS_MMIO_BLTROP 0x1a // byte
156 #define CIRRUS_MMIO_BLTMODEEXT 0x1b // byte
157 #define CIRRUS_MMIO_BLTTRANSPARENTCOLOR 0x1c // word?
158 #define CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK 0x20 // word?
159 #define CIRRUS_MMIO_LINEARDRAW_START_X 0x24 // word
160 #define CIRRUS_MMIO_LINEARDRAW_START_Y 0x26 // word
161 #define CIRRUS_MMIO_LINEARDRAW_END_X 0x28 // word
162 #define CIRRUS_MMIO_LINEARDRAW_END_Y 0x2a // word
163 #define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_INC 0x2c // byte
164 #define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_ROLLOVER 0x2d // byte
165 #define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_MASK 0x2e // byte
166 #define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_ACCUM 0x2f // byte
167 #define CIRRUS_MMIO_BRESENHAM_K1 0x30 // word
168 #define CIRRUS_MMIO_BRESENHAM_K3 0x32 // word
169 #define CIRRUS_MMIO_BRESENHAM_ERROR 0x34 // word
170 #define CIRRUS_MMIO_BRESENHAM_DELTA_MAJOR 0x36 // word
171 #define CIRRUS_MMIO_BRESENHAM_DIRECTION 0x38 // byte
172 #define CIRRUS_MMIO_LINEDRAW_MODE 0x39 // byte
173 #define CIRRUS_MMIO_BLTSTATUS 0x40 // byte
175 #define CIRRUS_PNPMMIO_SIZE 0x1000
177 #define BLTUNSAFE(s) \
179 ( /* check dst is within bounds */ \
180 (s)->cirrus_blt_height * ABS((s)->cirrus_blt_dstpitch) \
181 + ((s)->cirrus_blt_dstaddr & (s)->cirrus_addr_mask) > \
184 ( /* check src is within bounds */ \
185 (s)->cirrus_blt_height * ABS((s)->cirrus_blt_srcpitch) \
186 + ((s)->cirrus_blt_srcaddr & (s)->cirrus_addr_mask) > \
191 struct CirrusVGAState
;
192 typedef void (*cirrus_bitblt_rop_t
) (struct CirrusVGAState
*s
,
193 uint8_t * dst
, const uint8_t * src
,
194 int dstpitch
, int srcpitch
,
195 int bltwidth
, int bltheight
);
196 typedef void (*cirrus_fill_t
)(struct CirrusVGAState
*s
,
197 uint8_t *dst
, int dst_pitch
, int width
, int height
);
199 typedef struct CirrusVGAState
{
202 MemoryRegion cirrus_linear_io
;
203 MemoryRegion cirrus_linear_bitblt_io
;
204 MemoryRegion cirrus_mmio_io
;
205 MemoryRegion pci_bar
;
206 bool linear_vram
; /* vga.vram mapped over cirrus_linear_io */
207 MemoryRegion low_mem_container
; /* container for 0xa0000-0xc0000 */
208 MemoryRegion low_mem
; /* always mapped, overridden by: */
209 MemoryRegion
*cirrus_bank
[2]; /* aliases at 0xa0000-0xb0000 */
210 uint32_t cirrus_addr_mask
;
211 uint32_t linear_mmio_mask
;
212 uint8_t cirrus_shadow_gr0
;
213 uint8_t cirrus_shadow_gr1
;
214 uint8_t cirrus_hidden_dac_lockindex
;
215 uint8_t cirrus_hidden_dac_data
;
216 uint32_t cirrus_bank_base
[2];
217 uint32_t cirrus_bank_limit
[2];
218 uint8_t cirrus_hidden_palette
[48];
219 uint32_t hw_cursor_x
;
220 uint32_t hw_cursor_y
;
221 int cirrus_blt_pixelwidth
;
222 int cirrus_blt_width
;
223 int cirrus_blt_height
;
224 int cirrus_blt_dstpitch
;
225 int cirrus_blt_srcpitch
;
226 uint32_t cirrus_blt_fgcol
;
227 uint32_t cirrus_blt_bgcol
;
228 uint32_t cirrus_blt_dstaddr
;
229 uint32_t cirrus_blt_srcaddr
;
230 uint8_t cirrus_blt_mode
;
231 uint8_t cirrus_blt_modeext
;
232 cirrus_bitblt_rop_t cirrus_rop
;
233 #define CIRRUS_BLTBUFSIZE (2048 * 4) /* one line width */
234 uint8_t cirrus_bltbuf
[CIRRUS_BLTBUFSIZE
];
235 uint8_t *cirrus_srcptr
;
236 uint8_t *cirrus_srcptr_end
;
237 uint32_t cirrus_srccounter
;
238 /* hwcursor display state */
239 int last_hw_cursor_size
;
240 int last_hw_cursor_x
;
241 int last_hw_cursor_y
;
242 int last_hw_cursor_y_start
;
243 int last_hw_cursor_y_end
;
244 int real_vram_size
; /* XXX: suppress that */
249 typedef struct PCICirrusVGAState
{
251 CirrusVGAState cirrus_vga
;
254 static uint8_t rop_to_index
[256];
256 /***************************************
260 ***************************************/
263 static void cirrus_bitblt_reset(CirrusVGAState
*s
);
264 static void cirrus_update_memory_access(CirrusVGAState
*s
);
266 /***************************************
270 ***************************************/
272 static void cirrus_bitblt_rop_nop(CirrusVGAState
*s
,
273 uint8_t *dst
,const uint8_t *src
,
274 int dstpitch
,int srcpitch
,
275 int bltwidth
,int bltheight
)
279 static void cirrus_bitblt_fill_nop(CirrusVGAState
*s
,
281 int dstpitch
, int bltwidth
,int bltheight
)
286 #define ROP_FN(d, s) 0
287 #include "cirrus_vga_rop.h"
289 #define ROP_NAME src_and_dst
290 #define ROP_FN(d, s) (s) & (d)
291 #include "cirrus_vga_rop.h"
293 #define ROP_NAME src_and_notdst
294 #define ROP_FN(d, s) (s) & (~(d))
295 #include "cirrus_vga_rop.h"
297 #define ROP_NAME notdst
298 #define ROP_FN(d, s) ~(d)
299 #include "cirrus_vga_rop.h"
302 #define ROP_FN(d, s) s
303 #include "cirrus_vga_rop.h"
306 #define ROP_FN(d, s) ~0
307 #include "cirrus_vga_rop.h"
309 #define ROP_NAME notsrc_and_dst
310 #define ROP_FN(d, s) (~(s)) & (d)
311 #include "cirrus_vga_rop.h"
313 #define ROP_NAME src_xor_dst
314 #define ROP_FN(d, s) (s) ^ (d)
315 #include "cirrus_vga_rop.h"
317 #define ROP_NAME src_or_dst
318 #define ROP_FN(d, s) (s) | (d)
319 #include "cirrus_vga_rop.h"
321 #define ROP_NAME notsrc_or_notdst
322 #define ROP_FN(d, s) (~(s)) | (~(d))
323 #include "cirrus_vga_rop.h"
325 #define ROP_NAME src_notxor_dst
326 #define ROP_FN(d, s) ~((s) ^ (d))
327 #include "cirrus_vga_rop.h"
329 #define ROP_NAME src_or_notdst
330 #define ROP_FN(d, s) (s) | (~(d))
331 #include "cirrus_vga_rop.h"
333 #define ROP_NAME notsrc
334 #define ROP_FN(d, s) (~(s))
335 #include "cirrus_vga_rop.h"
337 #define ROP_NAME notsrc_or_dst
338 #define ROP_FN(d, s) (~(s)) | (d)
339 #include "cirrus_vga_rop.h"
341 #define ROP_NAME notsrc_and_notdst
342 #define ROP_FN(d, s) (~(s)) & (~(d))
343 #include "cirrus_vga_rop.h"
345 static const cirrus_bitblt_rop_t cirrus_fwd_rop
[16] = {
346 cirrus_bitblt_rop_fwd_0
,
347 cirrus_bitblt_rop_fwd_src_and_dst
,
348 cirrus_bitblt_rop_nop
,
349 cirrus_bitblt_rop_fwd_src_and_notdst
,
350 cirrus_bitblt_rop_fwd_notdst
,
351 cirrus_bitblt_rop_fwd_src
,
352 cirrus_bitblt_rop_fwd_1
,
353 cirrus_bitblt_rop_fwd_notsrc_and_dst
,
354 cirrus_bitblt_rop_fwd_src_xor_dst
,
355 cirrus_bitblt_rop_fwd_src_or_dst
,
356 cirrus_bitblt_rop_fwd_notsrc_or_notdst
,
357 cirrus_bitblt_rop_fwd_src_notxor_dst
,
358 cirrus_bitblt_rop_fwd_src_or_notdst
,
359 cirrus_bitblt_rop_fwd_notsrc
,
360 cirrus_bitblt_rop_fwd_notsrc_or_dst
,
361 cirrus_bitblt_rop_fwd_notsrc_and_notdst
,
364 static const cirrus_bitblt_rop_t cirrus_bkwd_rop
[16] = {
365 cirrus_bitblt_rop_bkwd_0
,
366 cirrus_bitblt_rop_bkwd_src_and_dst
,
367 cirrus_bitblt_rop_nop
,
368 cirrus_bitblt_rop_bkwd_src_and_notdst
,
369 cirrus_bitblt_rop_bkwd_notdst
,
370 cirrus_bitblt_rop_bkwd_src
,
371 cirrus_bitblt_rop_bkwd_1
,
372 cirrus_bitblt_rop_bkwd_notsrc_and_dst
,
373 cirrus_bitblt_rop_bkwd_src_xor_dst
,
374 cirrus_bitblt_rop_bkwd_src_or_dst
,
375 cirrus_bitblt_rop_bkwd_notsrc_or_notdst
,
376 cirrus_bitblt_rop_bkwd_src_notxor_dst
,
377 cirrus_bitblt_rop_bkwd_src_or_notdst
,
378 cirrus_bitblt_rop_bkwd_notsrc
,
379 cirrus_bitblt_rop_bkwd_notsrc_or_dst
,
380 cirrus_bitblt_rop_bkwd_notsrc_and_notdst
,
383 #define TRANSP_ROP(name) {\
387 #define TRANSP_NOP(func) {\
392 static const cirrus_bitblt_rop_t cirrus_fwd_transp_rop
[16][2] = {
393 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_0
),
394 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_and_dst
),
395 TRANSP_NOP(cirrus_bitblt_rop_nop
),
396 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_and_notdst
),
397 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notdst
),
398 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src
),
399 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_1
),
400 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_and_dst
),
401 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_xor_dst
),
402 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_or_dst
),
403 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_or_notdst
),
404 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_notxor_dst
),
405 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_or_notdst
),
406 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc
),
407 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_or_dst
),
408 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_and_notdst
),
411 static const cirrus_bitblt_rop_t cirrus_bkwd_transp_rop
[16][2] = {
412 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_0
),
413 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_and_dst
),
414 TRANSP_NOP(cirrus_bitblt_rop_nop
),
415 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_and_notdst
),
416 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notdst
),
417 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src
),
418 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_1
),
419 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_and_dst
),
420 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_xor_dst
),
421 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_or_dst
),
422 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_or_notdst
),
423 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_notxor_dst
),
424 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_or_notdst
),
425 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc
),
426 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_or_dst
),
427 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_and_notdst
),
430 #define ROP2(name) {\
437 #define ROP_NOP2(func) {\
444 static const cirrus_bitblt_rop_t cirrus_patternfill
[16][4] = {
445 ROP2(cirrus_patternfill_0
),
446 ROP2(cirrus_patternfill_src_and_dst
),
447 ROP_NOP2(cirrus_bitblt_rop_nop
),
448 ROP2(cirrus_patternfill_src_and_notdst
),
449 ROP2(cirrus_patternfill_notdst
),
450 ROP2(cirrus_patternfill_src
),
451 ROP2(cirrus_patternfill_1
),
452 ROP2(cirrus_patternfill_notsrc_and_dst
),
453 ROP2(cirrus_patternfill_src_xor_dst
),
454 ROP2(cirrus_patternfill_src_or_dst
),
455 ROP2(cirrus_patternfill_notsrc_or_notdst
),
456 ROP2(cirrus_patternfill_src_notxor_dst
),
457 ROP2(cirrus_patternfill_src_or_notdst
),
458 ROP2(cirrus_patternfill_notsrc
),
459 ROP2(cirrus_patternfill_notsrc_or_dst
),
460 ROP2(cirrus_patternfill_notsrc_and_notdst
),
463 static const cirrus_bitblt_rop_t cirrus_colorexpand_transp
[16][4] = {
464 ROP2(cirrus_colorexpand_transp_0
),
465 ROP2(cirrus_colorexpand_transp_src_and_dst
),
466 ROP_NOP2(cirrus_bitblt_rop_nop
),
467 ROP2(cirrus_colorexpand_transp_src_and_notdst
),
468 ROP2(cirrus_colorexpand_transp_notdst
),
469 ROP2(cirrus_colorexpand_transp_src
),
470 ROP2(cirrus_colorexpand_transp_1
),
471 ROP2(cirrus_colorexpand_transp_notsrc_and_dst
),
472 ROP2(cirrus_colorexpand_transp_src_xor_dst
),
473 ROP2(cirrus_colorexpand_transp_src_or_dst
),
474 ROP2(cirrus_colorexpand_transp_notsrc_or_notdst
),
475 ROP2(cirrus_colorexpand_transp_src_notxor_dst
),
476 ROP2(cirrus_colorexpand_transp_src_or_notdst
),
477 ROP2(cirrus_colorexpand_transp_notsrc
),
478 ROP2(cirrus_colorexpand_transp_notsrc_or_dst
),
479 ROP2(cirrus_colorexpand_transp_notsrc_and_notdst
),
482 static const cirrus_bitblt_rop_t cirrus_colorexpand
[16][4] = {
483 ROP2(cirrus_colorexpand_0
),
484 ROP2(cirrus_colorexpand_src_and_dst
),
485 ROP_NOP2(cirrus_bitblt_rop_nop
),
486 ROP2(cirrus_colorexpand_src_and_notdst
),
487 ROP2(cirrus_colorexpand_notdst
),
488 ROP2(cirrus_colorexpand_src
),
489 ROP2(cirrus_colorexpand_1
),
490 ROP2(cirrus_colorexpand_notsrc_and_dst
),
491 ROP2(cirrus_colorexpand_src_xor_dst
),
492 ROP2(cirrus_colorexpand_src_or_dst
),
493 ROP2(cirrus_colorexpand_notsrc_or_notdst
),
494 ROP2(cirrus_colorexpand_src_notxor_dst
),
495 ROP2(cirrus_colorexpand_src_or_notdst
),
496 ROP2(cirrus_colorexpand_notsrc
),
497 ROP2(cirrus_colorexpand_notsrc_or_dst
),
498 ROP2(cirrus_colorexpand_notsrc_and_notdst
),
501 static const cirrus_bitblt_rop_t cirrus_colorexpand_pattern_transp
[16][4] = {
502 ROP2(cirrus_colorexpand_pattern_transp_0
),
503 ROP2(cirrus_colorexpand_pattern_transp_src_and_dst
),
504 ROP_NOP2(cirrus_bitblt_rop_nop
),
505 ROP2(cirrus_colorexpand_pattern_transp_src_and_notdst
),
506 ROP2(cirrus_colorexpand_pattern_transp_notdst
),
507 ROP2(cirrus_colorexpand_pattern_transp_src
),
508 ROP2(cirrus_colorexpand_pattern_transp_1
),
509 ROP2(cirrus_colorexpand_pattern_transp_notsrc_and_dst
),
510 ROP2(cirrus_colorexpand_pattern_transp_src_xor_dst
),
511 ROP2(cirrus_colorexpand_pattern_transp_src_or_dst
),
512 ROP2(cirrus_colorexpand_pattern_transp_notsrc_or_notdst
),
513 ROP2(cirrus_colorexpand_pattern_transp_src_notxor_dst
),
514 ROP2(cirrus_colorexpand_pattern_transp_src_or_notdst
),
515 ROP2(cirrus_colorexpand_pattern_transp_notsrc
),
516 ROP2(cirrus_colorexpand_pattern_transp_notsrc_or_dst
),
517 ROP2(cirrus_colorexpand_pattern_transp_notsrc_and_notdst
),
520 static const cirrus_bitblt_rop_t cirrus_colorexpand_pattern
[16][4] = {
521 ROP2(cirrus_colorexpand_pattern_0
),
522 ROP2(cirrus_colorexpand_pattern_src_and_dst
),
523 ROP_NOP2(cirrus_bitblt_rop_nop
),
524 ROP2(cirrus_colorexpand_pattern_src_and_notdst
),
525 ROP2(cirrus_colorexpand_pattern_notdst
),
526 ROP2(cirrus_colorexpand_pattern_src
),
527 ROP2(cirrus_colorexpand_pattern_1
),
528 ROP2(cirrus_colorexpand_pattern_notsrc_and_dst
),
529 ROP2(cirrus_colorexpand_pattern_src_xor_dst
),
530 ROP2(cirrus_colorexpand_pattern_src_or_dst
),
531 ROP2(cirrus_colorexpand_pattern_notsrc_or_notdst
),
532 ROP2(cirrus_colorexpand_pattern_src_notxor_dst
),
533 ROP2(cirrus_colorexpand_pattern_src_or_notdst
),
534 ROP2(cirrus_colorexpand_pattern_notsrc
),
535 ROP2(cirrus_colorexpand_pattern_notsrc_or_dst
),
536 ROP2(cirrus_colorexpand_pattern_notsrc_and_notdst
),
539 static const cirrus_fill_t cirrus_fill
[16][4] = {
541 ROP2(cirrus_fill_src_and_dst
),
542 ROP_NOP2(cirrus_bitblt_fill_nop
),
543 ROP2(cirrus_fill_src_and_notdst
),
544 ROP2(cirrus_fill_notdst
),
545 ROP2(cirrus_fill_src
),
547 ROP2(cirrus_fill_notsrc_and_dst
),
548 ROP2(cirrus_fill_src_xor_dst
),
549 ROP2(cirrus_fill_src_or_dst
),
550 ROP2(cirrus_fill_notsrc_or_notdst
),
551 ROP2(cirrus_fill_src_notxor_dst
),
552 ROP2(cirrus_fill_src_or_notdst
),
553 ROP2(cirrus_fill_notsrc
),
554 ROP2(cirrus_fill_notsrc_or_dst
),
555 ROP2(cirrus_fill_notsrc_and_notdst
),
558 static inline void cirrus_bitblt_fgcol(CirrusVGAState
*s
)
561 switch (s
->cirrus_blt_pixelwidth
) {
563 s
->cirrus_blt_fgcol
= s
->cirrus_shadow_gr1
;
566 color
= s
->cirrus_shadow_gr1
| (s
->vga
.gr
[0x11] << 8);
567 s
->cirrus_blt_fgcol
= le16_to_cpu(color
);
570 s
->cirrus_blt_fgcol
= s
->cirrus_shadow_gr1
|
571 (s
->vga
.gr
[0x11] << 8) | (s
->vga
.gr
[0x13] << 16);
575 color
= s
->cirrus_shadow_gr1
| (s
->vga
.gr
[0x11] << 8) |
576 (s
->vga
.gr
[0x13] << 16) | (s
->vga
.gr
[0x15] << 24);
577 s
->cirrus_blt_fgcol
= le32_to_cpu(color
);
582 static inline void cirrus_bitblt_bgcol(CirrusVGAState
*s
)
585 switch (s
->cirrus_blt_pixelwidth
) {
587 s
->cirrus_blt_bgcol
= s
->cirrus_shadow_gr0
;
590 color
= s
->cirrus_shadow_gr0
| (s
->vga
.gr
[0x10] << 8);
591 s
->cirrus_blt_bgcol
= le16_to_cpu(color
);
594 s
->cirrus_blt_bgcol
= s
->cirrus_shadow_gr0
|
595 (s
->vga
.gr
[0x10] << 8) | (s
->vga
.gr
[0x12] << 16);
599 color
= s
->cirrus_shadow_gr0
| (s
->vga
.gr
[0x10] << 8) |
600 (s
->vga
.gr
[0x12] << 16) | (s
->vga
.gr
[0x14] << 24);
601 s
->cirrus_blt_bgcol
= le32_to_cpu(color
);
606 static void cirrus_invalidate_region(CirrusVGAState
* s
, int off_begin
,
607 int off_pitch
, int bytesperline
,
614 for (y
= 0; y
< lines
; y
++) {
616 off_cur_end
= (off_cur
+ bytesperline
) & s
->cirrus_addr_mask
;
617 off_cur
&= TARGET_PAGE_MASK
;
618 while (off_cur
< off_cur_end
) {
619 memory_region_set_dirty(&s
->vga
.vram
, off_cur
);
620 off_cur
+= TARGET_PAGE_SIZE
;
622 off_begin
+= off_pitch
;
626 static int cirrus_bitblt_common_patterncopy(CirrusVGAState
* s
,
631 dst
= s
->vga
.vram_ptr
+ (s
->cirrus_blt_dstaddr
& s
->cirrus_addr_mask
);
636 (*s
->cirrus_rop
) (s
, dst
, src
,
637 s
->cirrus_blt_dstpitch
, 0,
638 s
->cirrus_blt_width
, s
->cirrus_blt_height
);
639 cirrus_invalidate_region(s
, s
->cirrus_blt_dstaddr
,
640 s
->cirrus_blt_dstpitch
, s
->cirrus_blt_width
,
641 s
->cirrus_blt_height
);
647 static int cirrus_bitblt_solidfill(CirrusVGAState
*s
, int blt_rop
)
649 cirrus_fill_t rop_func
;
653 rop_func
= cirrus_fill
[rop_to_index
[blt_rop
]][s
->cirrus_blt_pixelwidth
- 1];
654 rop_func(s
, s
->vga
.vram_ptr
+ (s
->cirrus_blt_dstaddr
& s
->cirrus_addr_mask
),
655 s
->cirrus_blt_dstpitch
,
656 s
->cirrus_blt_width
, s
->cirrus_blt_height
);
657 cirrus_invalidate_region(s
, s
->cirrus_blt_dstaddr
,
658 s
->cirrus_blt_dstpitch
, s
->cirrus_blt_width
,
659 s
->cirrus_blt_height
);
660 cirrus_bitblt_reset(s
);
664 /***************************************
666 * bitblt (video-to-video)
668 ***************************************/
670 static int cirrus_bitblt_videotovideo_patterncopy(CirrusVGAState
* s
)
672 return cirrus_bitblt_common_patterncopy(s
,
673 s
->vga
.vram_ptr
+ ((s
->cirrus_blt_srcaddr
& ~7) &
674 s
->cirrus_addr_mask
));
677 static void cirrus_do_copy(CirrusVGAState
*s
, int dst
, int src
, int w
, int h
)
684 /* make sure to only copy if it's a plain copy ROP */
685 if (*s
->cirrus_rop
== cirrus_bitblt_rop_fwd_src
||
686 *s
->cirrus_rop
== cirrus_bitblt_rop_bkwd_src
) {
690 depth
= s
->vga
.get_bpp(&s
->vga
) / 8;
691 s
->vga
.get_resolution(&s
->vga
, &width
, &height
);
694 sx
= (src
% ABS(s
->cirrus_blt_srcpitch
)) / depth
;
695 sy
= (src
/ ABS(s
->cirrus_blt_srcpitch
));
696 dx
= (dst
% ABS(s
->cirrus_blt_dstpitch
)) / depth
;
697 dy
= (dst
/ ABS(s
->cirrus_blt_dstpitch
));
699 /* normalize width */
702 /* if we're doing a backward copy, we have to adjust
703 our x/y to be the upper left corner (instead of the lower
705 if (s
->cirrus_blt_dstpitch
< 0) {
706 sx
-= (s
->cirrus_blt_width
/ depth
) - 1;
707 dx
-= (s
->cirrus_blt_width
/ depth
) - 1;
708 sy
-= s
->cirrus_blt_height
- 1;
709 dy
-= s
->cirrus_blt_height
- 1;
712 /* are we in the visible portion of memory? */
713 if (sx
>= 0 && sy
>= 0 && dx
>= 0 && dy
>= 0 &&
714 (sx
+ w
) <= width
&& (sy
+ h
) <= height
&&
715 (dx
+ w
) <= width
&& (dy
+ h
) <= height
) {
720 /* we have to flush all pending changes so that the copy
721 is generated at the appropriate moment in time */
725 (*s
->cirrus_rop
) (s
, s
->vga
.vram_ptr
+
726 (s
->cirrus_blt_dstaddr
& s
->cirrus_addr_mask
),
728 (s
->cirrus_blt_srcaddr
& s
->cirrus_addr_mask
),
729 s
->cirrus_blt_dstpitch
, s
->cirrus_blt_srcpitch
,
730 s
->cirrus_blt_width
, s
->cirrus_blt_height
);
733 qemu_console_copy(s
->vga
.ds
,
735 s
->cirrus_blt_width
/ depth
,
736 s
->cirrus_blt_height
);
738 /* we don't have to notify the display that this portion has
739 changed since qemu_console_copy implies this */
741 cirrus_invalidate_region(s
, s
->cirrus_blt_dstaddr
,
742 s
->cirrus_blt_dstpitch
, s
->cirrus_blt_width
,
743 s
->cirrus_blt_height
);
746 static int cirrus_bitblt_videotovideo_copy(CirrusVGAState
* s
)
751 cirrus_do_copy(s
, s
->cirrus_blt_dstaddr
- s
->vga
.start_addr
,
752 s
->cirrus_blt_srcaddr
- s
->vga
.start_addr
,
753 s
->cirrus_blt_width
, s
->cirrus_blt_height
);
758 /***************************************
760 * bitblt (cpu-to-video)
762 ***************************************/
764 static void cirrus_bitblt_cputovideo_next(CirrusVGAState
* s
)
769 if (s
->cirrus_srccounter
> 0) {
770 if (s
->cirrus_blt_mode
& CIRRUS_BLTMODE_PATTERNCOPY
) {
771 cirrus_bitblt_common_patterncopy(s
, s
->cirrus_bltbuf
);
773 s
->cirrus_srccounter
= 0;
774 cirrus_bitblt_reset(s
);
776 /* at least one scan line */
778 (*s
->cirrus_rop
)(s
, s
->vga
.vram_ptr
+
779 (s
->cirrus_blt_dstaddr
& s
->cirrus_addr_mask
),
780 s
->cirrus_bltbuf
, 0, 0, s
->cirrus_blt_width
, 1);
781 cirrus_invalidate_region(s
, s
->cirrus_blt_dstaddr
, 0,
782 s
->cirrus_blt_width
, 1);
783 s
->cirrus_blt_dstaddr
+= s
->cirrus_blt_dstpitch
;
784 s
->cirrus_srccounter
-= s
->cirrus_blt_srcpitch
;
785 if (s
->cirrus_srccounter
<= 0)
787 /* more bytes than needed can be transfered because of
788 word alignment, so we keep them for the next line */
789 /* XXX: keep alignment to speed up transfer */
790 end_ptr
= s
->cirrus_bltbuf
+ s
->cirrus_blt_srcpitch
;
791 copy_count
= s
->cirrus_srcptr_end
- end_ptr
;
792 memmove(s
->cirrus_bltbuf
, end_ptr
, copy_count
);
793 s
->cirrus_srcptr
= s
->cirrus_bltbuf
+ copy_count
;
794 s
->cirrus_srcptr_end
= s
->cirrus_bltbuf
+ s
->cirrus_blt_srcpitch
;
795 } while (s
->cirrus_srcptr
>= s
->cirrus_srcptr_end
);
800 /***************************************
804 ***************************************/
806 static void cirrus_bitblt_reset(CirrusVGAState
* s
)
811 ~(CIRRUS_BLT_START
| CIRRUS_BLT_BUSY
| CIRRUS_BLT_FIFOUSED
);
812 need_update
= s
->cirrus_srcptr
!= &s
->cirrus_bltbuf
[0]
813 || s
->cirrus_srcptr_end
!= &s
->cirrus_bltbuf
[0];
814 s
->cirrus_srcptr
= &s
->cirrus_bltbuf
[0];
815 s
->cirrus_srcptr_end
= &s
->cirrus_bltbuf
[0];
816 s
->cirrus_srccounter
= 0;
819 cirrus_update_memory_access(s
);
822 static int cirrus_bitblt_cputovideo(CirrusVGAState
* s
)
826 s
->cirrus_blt_mode
&= ~CIRRUS_BLTMODE_MEMSYSSRC
;
827 s
->cirrus_srcptr
= &s
->cirrus_bltbuf
[0];
828 s
->cirrus_srcptr_end
= &s
->cirrus_bltbuf
[0];
830 if (s
->cirrus_blt_mode
& CIRRUS_BLTMODE_PATTERNCOPY
) {
831 if (s
->cirrus_blt_mode
& CIRRUS_BLTMODE_COLOREXPAND
) {
832 s
->cirrus_blt_srcpitch
= 8;
834 /* XXX: check for 24 bpp */
835 s
->cirrus_blt_srcpitch
= 8 * 8 * s
->cirrus_blt_pixelwidth
;
837 s
->cirrus_srccounter
= s
->cirrus_blt_srcpitch
;
839 if (s
->cirrus_blt_mode
& CIRRUS_BLTMODE_COLOREXPAND
) {
840 w
= s
->cirrus_blt_width
/ s
->cirrus_blt_pixelwidth
;
841 if (s
->cirrus_blt_modeext
& CIRRUS_BLTMODEEXT_DWORDGRANULARITY
)
842 s
->cirrus_blt_srcpitch
= ((w
+ 31) >> 5);
844 s
->cirrus_blt_srcpitch
= ((w
+ 7) >> 3);
846 /* always align input size to 32 bits */
847 s
->cirrus_blt_srcpitch
= (s
->cirrus_blt_width
+ 3) & ~3;
849 s
->cirrus_srccounter
= s
->cirrus_blt_srcpitch
* s
->cirrus_blt_height
;
851 s
->cirrus_srcptr
= s
->cirrus_bltbuf
;
852 s
->cirrus_srcptr_end
= s
->cirrus_bltbuf
+ s
->cirrus_blt_srcpitch
;
853 cirrus_update_memory_access(s
);
857 static int cirrus_bitblt_videotocpu(CirrusVGAState
* s
)
861 printf("cirrus: bitblt (video to cpu) is not implemented yet\n");
866 static int cirrus_bitblt_videotovideo(CirrusVGAState
* s
)
870 if (s
->cirrus_blt_mode
& CIRRUS_BLTMODE_PATTERNCOPY
) {
871 ret
= cirrus_bitblt_videotovideo_patterncopy(s
);
873 ret
= cirrus_bitblt_videotovideo_copy(s
);
876 cirrus_bitblt_reset(s
);
880 static void cirrus_bitblt_start(CirrusVGAState
* s
)
884 s
->vga
.gr
[0x31] |= CIRRUS_BLT_BUSY
;
886 s
->cirrus_blt_width
= (s
->vga
.gr
[0x20] | (s
->vga
.gr
[0x21] << 8)) + 1;
887 s
->cirrus_blt_height
= (s
->vga
.gr
[0x22] | (s
->vga
.gr
[0x23] << 8)) + 1;
888 s
->cirrus_blt_dstpitch
= (s
->vga
.gr
[0x24] | (s
->vga
.gr
[0x25] << 8));
889 s
->cirrus_blt_srcpitch
= (s
->vga
.gr
[0x26] | (s
->vga
.gr
[0x27] << 8));
890 s
->cirrus_blt_dstaddr
=
891 (s
->vga
.gr
[0x28] | (s
->vga
.gr
[0x29] << 8) | (s
->vga
.gr
[0x2a] << 16));
892 s
->cirrus_blt_srcaddr
=
893 (s
->vga
.gr
[0x2c] | (s
->vga
.gr
[0x2d] << 8) | (s
->vga
.gr
[0x2e] << 16));
894 s
->cirrus_blt_mode
= s
->vga
.gr
[0x30];
895 s
->cirrus_blt_modeext
= s
->vga
.gr
[0x33];
896 blt_rop
= s
->vga
.gr
[0x32];
899 printf("rop=0x%02x mode=0x%02x modeext=0x%02x w=%d h=%d dpitch=%d spitch=%d daddr=0x%08x saddr=0x%08x writemask=0x%02x\n",
902 s
->cirrus_blt_modeext
,
904 s
->cirrus_blt_height
,
905 s
->cirrus_blt_dstpitch
,
906 s
->cirrus_blt_srcpitch
,
907 s
->cirrus_blt_dstaddr
,
908 s
->cirrus_blt_srcaddr
,
912 switch (s
->cirrus_blt_mode
& CIRRUS_BLTMODE_PIXELWIDTHMASK
) {
913 case CIRRUS_BLTMODE_PIXELWIDTH8
:
914 s
->cirrus_blt_pixelwidth
= 1;
916 case CIRRUS_BLTMODE_PIXELWIDTH16
:
917 s
->cirrus_blt_pixelwidth
= 2;
919 case CIRRUS_BLTMODE_PIXELWIDTH24
:
920 s
->cirrus_blt_pixelwidth
= 3;
922 case CIRRUS_BLTMODE_PIXELWIDTH32
:
923 s
->cirrus_blt_pixelwidth
= 4;
927 printf("cirrus: bitblt - pixel width is unknown\n");
931 s
->cirrus_blt_mode
&= ~CIRRUS_BLTMODE_PIXELWIDTHMASK
;
934 cirrus_blt_mode
& (CIRRUS_BLTMODE_MEMSYSSRC
|
935 CIRRUS_BLTMODE_MEMSYSDEST
))
936 == (CIRRUS_BLTMODE_MEMSYSSRC
| CIRRUS_BLTMODE_MEMSYSDEST
)) {
938 printf("cirrus: bitblt - memory-to-memory copy is requested\n");
943 if ((s
->cirrus_blt_modeext
& CIRRUS_BLTMODEEXT_SOLIDFILL
) &&
944 (s
->cirrus_blt_mode
& (CIRRUS_BLTMODE_MEMSYSDEST
|
945 CIRRUS_BLTMODE_TRANSPARENTCOMP
|
946 CIRRUS_BLTMODE_PATTERNCOPY
|
947 CIRRUS_BLTMODE_COLOREXPAND
)) ==
948 (CIRRUS_BLTMODE_PATTERNCOPY
| CIRRUS_BLTMODE_COLOREXPAND
)) {
949 cirrus_bitblt_fgcol(s
);
950 cirrus_bitblt_solidfill(s
, blt_rop
);
952 if ((s
->cirrus_blt_mode
& (CIRRUS_BLTMODE_COLOREXPAND
|
953 CIRRUS_BLTMODE_PATTERNCOPY
)) ==
954 CIRRUS_BLTMODE_COLOREXPAND
) {
956 if (s
->cirrus_blt_mode
& CIRRUS_BLTMODE_TRANSPARENTCOMP
) {
957 if (s
->cirrus_blt_modeext
& CIRRUS_BLTMODEEXT_COLOREXPINV
)
958 cirrus_bitblt_bgcol(s
);
960 cirrus_bitblt_fgcol(s
);
961 s
->cirrus_rop
= cirrus_colorexpand_transp
[rop_to_index
[blt_rop
]][s
->cirrus_blt_pixelwidth
- 1];
963 cirrus_bitblt_fgcol(s
);
964 cirrus_bitblt_bgcol(s
);
965 s
->cirrus_rop
= cirrus_colorexpand
[rop_to_index
[blt_rop
]][s
->cirrus_blt_pixelwidth
- 1];
967 } else if (s
->cirrus_blt_mode
& CIRRUS_BLTMODE_PATTERNCOPY
) {
968 if (s
->cirrus_blt_mode
& CIRRUS_BLTMODE_COLOREXPAND
) {
969 if (s
->cirrus_blt_mode
& CIRRUS_BLTMODE_TRANSPARENTCOMP
) {
970 if (s
->cirrus_blt_modeext
& CIRRUS_BLTMODEEXT_COLOREXPINV
)
971 cirrus_bitblt_bgcol(s
);
973 cirrus_bitblt_fgcol(s
);
974 s
->cirrus_rop
= cirrus_colorexpand_pattern_transp
[rop_to_index
[blt_rop
]][s
->cirrus_blt_pixelwidth
- 1];
976 cirrus_bitblt_fgcol(s
);
977 cirrus_bitblt_bgcol(s
);
978 s
->cirrus_rop
= cirrus_colorexpand_pattern
[rop_to_index
[blt_rop
]][s
->cirrus_blt_pixelwidth
- 1];
981 s
->cirrus_rop
= cirrus_patternfill
[rop_to_index
[blt_rop
]][s
->cirrus_blt_pixelwidth
- 1];
984 if (s
->cirrus_blt_mode
& CIRRUS_BLTMODE_TRANSPARENTCOMP
) {
985 if (s
->cirrus_blt_pixelwidth
> 2) {
986 printf("src transparent without colorexpand must be 8bpp or 16bpp\n");
989 if (s
->cirrus_blt_mode
& CIRRUS_BLTMODE_BACKWARDS
) {
990 s
->cirrus_blt_dstpitch
= -s
->cirrus_blt_dstpitch
;
991 s
->cirrus_blt_srcpitch
= -s
->cirrus_blt_srcpitch
;
992 s
->cirrus_rop
= cirrus_bkwd_transp_rop
[rop_to_index
[blt_rop
]][s
->cirrus_blt_pixelwidth
- 1];
994 s
->cirrus_rop
= cirrus_fwd_transp_rop
[rop_to_index
[blt_rop
]][s
->cirrus_blt_pixelwidth
- 1];
997 if (s
->cirrus_blt_mode
& CIRRUS_BLTMODE_BACKWARDS
) {
998 s
->cirrus_blt_dstpitch
= -s
->cirrus_blt_dstpitch
;
999 s
->cirrus_blt_srcpitch
= -s
->cirrus_blt_srcpitch
;
1000 s
->cirrus_rop
= cirrus_bkwd_rop
[rop_to_index
[blt_rop
]];
1002 s
->cirrus_rop
= cirrus_fwd_rop
[rop_to_index
[blt_rop
]];
1006 // setup bitblt engine.
1007 if (s
->cirrus_blt_mode
& CIRRUS_BLTMODE_MEMSYSSRC
) {
1008 if (!cirrus_bitblt_cputovideo(s
))
1010 } else if (s
->cirrus_blt_mode
& CIRRUS_BLTMODE_MEMSYSDEST
) {
1011 if (!cirrus_bitblt_videotocpu(s
))
1014 if (!cirrus_bitblt_videotovideo(s
))
1020 cirrus_bitblt_reset(s
);
1023 static void cirrus_write_bitblt(CirrusVGAState
* s
, unsigned reg_value
)
1027 old_value
= s
->vga
.gr
[0x31];
1028 s
->vga
.gr
[0x31] = reg_value
;
1030 if (((old_value
& CIRRUS_BLT_RESET
) != 0) &&
1031 ((reg_value
& CIRRUS_BLT_RESET
) == 0)) {
1032 cirrus_bitblt_reset(s
);
1033 } else if (((old_value
& CIRRUS_BLT_START
) == 0) &&
1034 ((reg_value
& CIRRUS_BLT_START
) != 0)) {
1035 cirrus_bitblt_start(s
);
1040 /***************************************
1044 ***************************************/
1046 static void cirrus_get_offsets(VGACommonState
*s1
,
1047 uint32_t *pline_offset
,
1048 uint32_t *pstart_addr
,
1049 uint32_t *pline_compare
)
1051 CirrusVGAState
* s
= container_of(s1
, CirrusVGAState
, vga
);
1052 uint32_t start_addr
, line_offset
, line_compare
;
1054 line_offset
= s
->vga
.cr
[0x13]
1055 | ((s
->vga
.cr
[0x1b] & 0x10) << 4);
1057 *pline_offset
= line_offset
;
1059 start_addr
= (s
->vga
.cr
[0x0c] << 8)
1061 | ((s
->vga
.cr
[0x1b] & 0x01) << 16)
1062 | ((s
->vga
.cr
[0x1b] & 0x0c) << 15)
1063 | ((s
->vga
.cr
[0x1d] & 0x80) << 12);
1064 *pstart_addr
= start_addr
;
1066 line_compare
= s
->vga
.cr
[0x18] |
1067 ((s
->vga
.cr
[0x07] & 0x10) << 4) |
1068 ((s
->vga
.cr
[0x09] & 0x40) << 3);
1069 *pline_compare
= line_compare
;
1072 static uint32_t cirrus_get_bpp16_depth(CirrusVGAState
* s
)
1076 switch (s
->cirrus_hidden_dac_data
& 0xf) {
1079 break; /* Sierra HiColor */
1082 break; /* XGA HiColor */
1085 printf("cirrus: invalid DAC value %x in 16bpp\n",
1086 (s
->cirrus_hidden_dac_data
& 0xf));
1094 static int cirrus_get_bpp(VGACommonState
*s1
)
1096 CirrusVGAState
* s
= container_of(s1
, CirrusVGAState
, vga
);
1099 if ((s
->vga
.sr
[0x07] & 0x01) != 0) {
1101 switch (s
->vga
.sr
[0x07] & CIRRUS_SR7_BPP_MASK
) {
1102 case CIRRUS_SR7_BPP_8
:
1105 case CIRRUS_SR7_BPP_16_DOUBLEVCLK
:
1106 ret
= cirrus_get_bpp16_depth(s
);
1108 case CIRRUS_SR7_BPP_24
:
1111 case CIRRUS_SR7_BPP_16
:
1112 ret
= cirrus_get_bpp16_depth(s
);
1114 case CIRRUS_SR7_BPP_32
:
1119 printf("cirrus: unknown bpp - sr7=%x\n", s
->vga
.sr
[0x7]);
1132 static void cirrus_get_resolution(VGACommonState
*s
, int *pwidth
, int *pheight
)
1136 width
= (s
->cr
[0x01] + 1) * 8;
1137 height
= s
->cr
[0x12] |
1138 ((s
->cr
[0x07] & 0x02) << 7) |
1139 ((s
->cr
[0x07] & 0x40) << 3);
1140 height
= (height
+ 1);
1141 /* interlace support */
1142 if (s
->cr
[0x1a] & 0x01)
1143 height
= height
* 2;
1148 /***************************************
1152 ***************************************/
1154 static void cirrus_update_bank_ptr(CirrusVGAState
* s
, unsigned bank_index
)
1159 if ((s
->vga
.gr
[0x0b] & 0x01) != 0) /* dual bank */
1160 offset
= s
->vga
.gr
[0x09 + bank_index
];
1161 else /* single bank */
1162 offset
= s
->vga
.gr
[0x09];
1164 if ((s
->vga
.gr
[0x0b] & 0x20) != 0)
1169 if (s
->real_vram_size
<= offset
)
1172 limit
= s
->real_vram_size
- offset
;
1174 if (((s
->vga
.gr
[0x0b] & 0x01) == 0) && (bank_index
!= 0)) {
1175 if (limit
> 0x8000) {
1184 s
->cirrus_bank_base
[bank_index
] = offset
;
1185 s
->cirrus_bank_limit
[bank_index
] = limit
;
1187 s
->cirrus_bank_base
[bank_index
] = 0;
1188 s
->cirrus_bank_limit
[bank_index
] = 0;
1192 /***************************************
1194 * I/O access between 0x3c4-0x3c5
1196 ***************************************/
1198 static int cirrus_vga_read_sr(CirrusVGAState
* s
)
1200 switch (s
->vga
.sr_index
) {
1201 case 0x00: // Standard VGA
1202 case 0x01: // Standard VGA
1203 case 0x02: // Standard VGA
1204 case 0x03: // Standard VGA
1205 case 0x04: // Standard VGA
1206 return s
->vga
.sr
[s
->vga
.sr_index
];
1207 case 0x06: // Unlock Cirrus extensions
1208 return s
->vga
.sr
[s
->vga
.sr_index
];
1212 case 0x70: // Graphics Cursor X
1216 case 0xf0: // Graphics Cursor X
1217 return s
->vga
.sr
[0x10];
1221 case 0x71: // Graphics Cursor Y
1225 case 0xf1: // Graphics Cursor Y
1226 return s
->vga
.sr
[0x11];
1228 case 0x07: // Extended Sequencer Mode
1229 case 0x08: // EEPROM Control
1230 case 0x09: // Scratch Register 0
1231 case 0x0a: // Scratch Register 1
1232 case 0x0b: // VCLK 0
1233 case 0x0c: // VCLK 1
1234 case 0x0d: // VCLK 2
1235 case 0x0e: // VCLK 3
1236 case 0x0f: // DRAM Control
1237 case 0x12: // Graphics Cursor Attribute
1238 case 0x13: // Graphics Cursor Pattern Address
1239 case 0x14: // Scratch Register 2
1240 case 0x15: // Scratch Register 3
1241 case 0x16: // Performance Tuning Register
1242 case 0x17: // Configuration Readback and Extended Control
1243 case 0x18: // Signature Generator Control
1244 case 0x19: // Signal Generator Result
1245 case 0x1a: // Signal Generator Result
1246 case 0x1b: // VCLK 0 Denominator & Post
1247 case 0x1c: // VCLK 1 Denominator & Post
1248 case 0x1d: // VCLK 2 Denominator & Post
1249 case 0x1e: // VCLK 3 Denominator & Post
1250 case 0x1f: // BIOS Write Enable and MCLK select
1252 printf("cirrus: handled inport sr_index %02x\n", s
->vga
.sr_index
);
1254 return s
->vga
.sr
[s
->vga
.sr_index
];
1257 printf("cirrus: inport sr_index %02x\n", s
->vga
.sr_index
);
1264 static void cirrus_vga_write_sr(CirrusVGAState
* s
, uint32_t val
)
1266 switch (s
->vga
.sr_index
) {
1267 case 0x00: // Standard VGA
1268 case 0x01: // Standard VGA
1269 case 0x02: // Standard VGA
1270 case 0x03: // Standard VGA
1271 case 0x04: // Standard VGA
1272 s
->vga
.sr
[s
->vga
.sr_index
] = val
& sr_mask
[s
->vga
.sr_index
];
1273 if (s
->vga
.sr_index
== 1)
1274 s
->vga
.update_retrace_info(&s
->vga
);
1276 case 0x06: // Unlock Cirrus extensions
1279 s
->vga
.sr
[s
->vga
.sr_index
] = 0x12;
1281 s
->vga
.sr
[s
->vga
.sr_index
] = 0x0f;
1287 case 0x70: // Graphics Cursor X
1291 case 0xf0: // Graphics Cursor X
1292 s
->vga
.sr
[0x10] = val
;
1293 s
->hw_cursor_x
= (val
<< 3) | (s
->vga
.sr_index
>> 5);
1298 case 0x71: // Graphics Cursor Y
1302 case 0xf1: // Graphics Cursor Y
1303 s
->vga
.sr
[0x11] = val
;
1304 s
->hw_cursor_y
= (val
<< 3) | (s
->vga
.sr_index
>> 5);
1306 case 0x07: // Extended Sequencer Mode
1307 cirrus_update_memory_access(s
);
1308 case 0x08: // EEPROM Control
1309 case 0x09: // Scratch Register 0
1310 case 0x0a: // Scratch Register 1
1311 case 0x0b: // VCLK 0
1312 case 0x0c: // VCLK 1
1313 case 0x0d: // VCLK 2
1314 case 0x0e: // VCLK 3
1315 case 0x0f: // DRAM Control
1316 case 0x12: // Graphics Cursor Attribute
1317 case 0x13: // Graphics Cursor Pattern Address
1318 case 0x14: // Scratch Register 2
1319 case 0x15: // Scratch Register 3
1320 case 0x16: // Performance Tuning Register
1321 case 0x18: // Signature Generator Control
1322 case 0x19: // Signature Generator Result
1323 case 0x1a: // Signature Generator Result
1324 case 0x1b: // VCLK 0 Denominator & Post
1325 case 0x1c: // VCLK 1 Denominator & Post
1326 case 0x1d: // VCLK 2 Denominator & Post
1327 case 0x1e: // VCLK 3 Denominator & Post
1328 case 0x1f: // BIOS Write Enable and MCLK select
1329 s
->vga
.sr
[s
->vga
.sr_index
] = val
;
1331 printf("cirrus: handled outport sr_index %02x, sr_value %02x\n",
1332 s
->vga
.sr_index
, val
);
1335 case 0x17: // Configuration Readback and Extended Control
1336 s
->vga
.sr
[s
->vga
.sr_index
] = (s
->vga
.sr
[s
->vga
.sr_index
] & 0x38)
1338 cirrus_update_memory_access(s
);
1342 printf("cirrus: outport sr_index %02x, sr_value %02x\n",
1343 s
->vga
.sr_index
, val
);
1349 /***************************************
1351 * I/O access at 0x3c6
1353 ***************************************/
1355 static int cirrus_read_hidden_dac(CirrusVGAState
* s
)
1357 if (++s
->cirrus_hidden_dac_lockindex
== 5) {
1358 s
->cirrus_hidden_dac_lockindex
= 0;
1359 return s
->cirrus_hidden_dac_data
;
1364 static void cirrus_write_hidden_dac(CirrusVGAState
* s
, int reg_value
)
1366 if (s
->cirrus_hidden_dac_lockindex
== 4) {
1367 s
->cirrus_hidden_dac_data
= reg_value
;
1368 #if defined(DEBUG_CIRRUS)
1369 printf("cirrus: outport hidden DAC, value %02x\n", reg_value
);
1372 s
->cirrus_hidden_dac_lockindex
= 0;
1375 /***************************************
1377 * I/O access at 0x3c9
1379 ***************************************/
1381 static int cirrus_vga_read_palette(CirrusVGAState
* s
)
1385 if ((s
->vga
.sr
[0x12] & CIRRUS_CURSOR_HIDDENPEL
)) {
1386 val
= s
->cirrus_hidden_palette
[(s
->vga
.dac_read_index
& 0x0f) * 3 +
1387 s
->vga
.dac_sub_index
];
1389 val
= s
->vga
.palette
[s
->vga
.dac_read_index
* 3 + s
->vga
.dac_sub_index
];
1391 if (++s
->vga
.dac_sub_index
== 3) {
1392 s
->vga
.dac_sub_index
= 0;
1393 s
->vga
.dac_read_index
++;
1398 static void cirrus_vga_write_palette(CirrusVGAState
* s
, int reg_value
)
1400 s
->vga
.dac_cache
[s
->vga
.dac_sub_index
] = reg_value
;
1401 if (++s
->vga
.dac_sub_index
== 3) {
1402 if ((s
->vga
.sr
[0x12] & CIRRUS_CURSOR_HIDDENPEL
)) {
1403 memcpy(&s
->cirrus_hidden_palette
[(s
->vga
.dac_write_index
& 0x0f) * 3],
1404 s
->vga
.dac_cache
, 3);
1406 memcpy(&s
->vga
.palette
[s
->vga
.dac_write_index
* 3], s
->vga
.dac_cache
, 3);
1408 /* XXX update cursor */
1409 s
->vga
.dac_sub_index
= 0;
1410 s
->vga
.dac_write_index
++;
1414 /***************************************
1416 * I/O access between 0x3ce-0x3cf
1418 ***************************************/
1420 static int cirrus_vga_read_gr(CirrusVGAState
* s
, unsigned reg_index
)
1422 switch (reg_index
) {
1423 case 0x00: // Standard VGA, BGCOLOR 0x000000ff
1424 return s
->cirrus_shadow_gr0
;
1425 case 0x01: // Standard VGA, FGCOLOR 0x000000ff
1426 return s
->cirrus_shadow_gr1
;
1427 case 0x02: // Standard VGA
1428 case 0x03: // Standard VGA
1429 case 0x04: // Standard VGA
1430 case 0x06: // Standard VGA
1431 case 0x07: // Standard VGA
1432 case 0x08: // Standard VGA
1433 return s
->vga
.gr
[s
->vga
.gr_index
];
1434 case 0x05: // Standard VGA, Cirrus extended mode
1439 if (reg_index
< 0x3a) {
1440 return s
->vga
.gr
[reg_index
];
1443 printf("cirrus: inport gr_index %02x\n", reg_index
);
1450 cirrus_vga_write_gr(CirrusVGAState
* s
, unsigned reg_index
, int reg_value
)
1452 #if defined(DEBUG_BITBLT) && 0
1453 printf("gr%02x: %02x\n", reg_index
, reg_value
);
1455 switch (reg_index
) {
1456 case 0x00: // Standard VGA, BGCOLOR 0x000000ff
1457 s
->vga
.gr
[reg_index
] = reg_value
& gr_mask
[reg_index
];
1458 s
->cirrus_shadow_gr0
= reg_value
;
1460 case 0x01: // Standard VGA, FGCOLOR 0x000000ff
1461 s
->vga
.gr
[reg_index
] = reg_value
& gr_mask
[reg_index
];
1462 s
->cirrus_shadow_gr1
= reg_value
;
1464 case 0x02: // Standard VGA
1465 case 0x03: // Standard VGA
1466 case 0x04: // Standard VGA
1467 case 0x06: // Standard VGA
1468 case 0x07: // Standard VGA
1469 case 0x08: // Standard VGA
1470 s
->vga
.gr
[reg_index
] = reg_value
& gr_mask
[reg_index
];
1472 case 0x05: // Standard VGA, Cirrus extended mode
1473 s
->vga
.gr
[reg_index
] = reg_value
& 0x7f;
1474 cirrus_update_memory_access(s
);
1476 case 0x09: // bank offset #0
1477 case 0x0A: // bank offset #1
1478 s
->vga
.gr
[reg_index
] = reg_value
;
1479 cirrus_update_bank_ptr(s
, 0);
1480 cirrus_update_bank_ptr(s
, 1);
1481 cirrus_update_memory_access(s
);
1484 s
->vga
.gr
[reg_index
] = reg_value
;
1485 cirrus_update_bank_ptr(s
, 0);
1486 cirrus_update_bank_ptr(s
, 1);
1487 cirrus_update_memory_access(s
);
1489 case 0x10: // BGCOLOR 0x0000ff00
1490 case 0x11: // FGCOLOR 0x0000ff00
1491 case 0x12: // BGCOLOR 0x00ff0000
1492 case 0x13: // FGCOLOR 0x00ff0000
1493 case 0x14: // BGCOLOR 0xff000000
1494 case 0x15: // FGCOLOR 0xff000000
1495 case 0x20: // BLT WIDTH 0x0000ff
1496 case 0x22: // BLT HEIGHT 0x0000ff
1497 case 0x24: // BLT DEST PITCH 0x0000ff
1498 case 0x26: // BLT SRC PITCH 0x0000ff
1499 case 0x28: // BLT DEST ADDR 0x0000ff
1500 case 0x29: // BLT DEST ADDR 0x00ff00
1501 case 0x2c: // BLT SRC ADDR 0x0000ff
1502 case 0x2d: // BLT SRC ADDR 0x00ff00
1503 case 0x2f: // BLT WRITEMASK
1504 case 0x30: // BLT MODE
1505 case 0x32: // RASTER OP
1506 case 0x33: // BLT MODEEXT
1507 case 0x34: // BLT TRANSPARENT COLOR 0x00ff
1508 case 0x35: // BLT TRANSPARENT COLOR 0xff00
1509 case 0x38: // BLT TRANSPARENT COLOR MASK 0x00ff
1510 case 0x39: // BLT TRANSPARENT COLOR MASK 0xff00
1511 s
->vga
.gr
[reg_index
] = reg_value
;
1513 case 0x21: // BLT WIDTH 0x001f00
1514 case 0x23: // BLT HEIGHT 0x001f00
1515 case 0x25: // BLT DEST PITCH 0x001f00
1516 case 0x27: // BLT SRC PITCH 0x001f00
1517 s
->vga
.gr
[reg_index
] = reg_value
& 0x1f;
1519 case 0x2a: // BLT DEST ADDR 0x3f0000
1520 s
->vga
.gr
[reg_index
] = reg_value
& 0x3f;
1521 /* if auto start mode, starts bit blt now */
1522 if (s
->vga
.gr
[0x31] & CIRRUS_BLT_AUTOSTART
) {
1523 cirrus_bitblt_start(s
);
1526 case 0x2e: // BLT SRC ADDR 0x3f0000
1527 s
->vga
.gr
[reg_index
] = reg_value
& 0x3f;
1529 case 0x31: // BLT STATUS/START
1530 cirrus_write_bitblt(s
, reg_value
);
1534 printf("cirrus: outport gr_index %02x, gr_value %02x\n", reg_index
,
1541 /***************************************
1543 * I/O access between 0x3d4-0x3d5
1545 ***************************************/
1547 static int cirrus_vga_read_cr(CirrusVGAState
* s
, unsigned reg_index
)
1549 switch (reg_index
) {
1550 case 0x00: // Standard VGA
1551 case 0x01: // Standard VGA
1552 case 0x02: // Standard VGA
1553 case 0x03: // Standard VGA
1554 case 0x04: // Standard VGA
1555 case 0x05: // Standard VGA
1556 case 0x06: // Standard VGA
1557 case 0x07: // Standard VGA
1558 case 0x08: // Standard VGA
1559 case 0x09: // Standard VGA
1560 case 0x0a: // Standard VGA
1561 case 0x0b: // Standard VGA
1562 case 0x0c: // Standard VGA
1563 case 0x0d: // Standard VGA
1564 case 0x0e: // Standard VGA
1565 case 0x0f: // Standard VGA
1566 case 0x10: // Standard VGA
1567 case 0x11: // Standard VGA
1568 case 0x12: // Standard VGA
1569 case 0x13: // Standard VGA
1570 case 0x14: // Standard VGA
1571 case 0x15: // Standard VGA
1572 case 0x16: // Standard VGA
1573 case 0x17: // Standard VGA
1574 case 0x18: // Standard VGA
1575 return s
->vga
.cr
[s
->vga
.cr_index
];
1576 case 0x24: // Attribute Controller Toggle Readback (R)
1577 return (s
->vga
.ar_flip_flop
<< 7);
1578 case 0x19: // Interlace End
1579 case 0x1a: // Miscellaneous Control
1580 case 0x1b: // Extended Display Control
1581 case 0x1c: // Sync Adjust and Genlock
1582 case 0x1d: // Overlay Extended Control
1583 case 0x22: // Graphics Data Latches Readback (R)
1584 case 0x25: // Part Status
1585 case 0x27: // Part ID (R)
1586 return s
->vga
.cr
[s
->vga
.cr_index
];
1587 case 0x26: // Attribute Controller Index Readback (R)
1588 return s
->vga
.ar_index
& 0x3f;
1592 printf("cirrus: inport cr_index %02x\n", reg_index
);
1598 static void cirrus_vga_write_cr(CirrusVGAState
* s
, int reg_value
)
1600 switch (s
->vga
.cr_index
) {
1601 case 0x00: // Standard VGA
1602 case 0x01: // Standard VGA
1603 case 0x02: // Standard VGA
1604 case 0x03: // Standard VGA
1605 case 0x04: // Standard VGA
1606 case 0x05: // Standard VGA
1607 case 0x06: // Standard VGA
1608 case 0x07: // Standard VGA
1609 case 0x08: // Standard VGA
1610 case 0x09: // Standard VGA
1611 case 0x0a: // Standard VGA
1612 case 0x0b: // Standard VGA
1613 case 0x0c: // Standard VGA
1614 case 0x0d: // Standard VGA
1615 case 0x0e: // Standard VGA
1616 case 0x0f: // Standard VGA
1617 case 0x10: // Standard VGA
1618 case 0x11: // Standard VGA
1619 case 0x12: // Standard VGA
1620 case 0x13: // Standard VGA
1621 case 0x14: // Standard VGA
1622 case 0x15: // Standard VGA
1623 case 0x16: // Standard VGA
1624 case 0x17: // Standard VGA
1625 case 0x18: // Standard VGA
1626 /* handle CR0-7 protection */
1627 if ((s
->vga
.cr
[0x11] & 0x80) && s
->vga
.cr_index
<= 7) {
1628 /* can always write bit 4 of CR7 */
1629 if (s
->vga
.cr_index
== 7)
1630 s
->vga
.cr
[7] = (s
->vga
.cr
[7] & ~0x10) | (reg_value
& 0x10);
1633 s
->vga
.cr
[s
->vga
.cr_index
] = reg_value
;
1634 switch(s
->vga
.cr_index
) {
1642 s
->vga
.update_retrace_info(&s
->vga
);
1646 case 0x19: // Interlace End
1647 case 0x1a: // Miscellaneous Control
1648 case 0x1b: // Extended Display Control
1649 case 0x1c: // Sync Adjust and Genlock
1650 case 0x1d: // Overlay Extended Control
1651 s
->vga
.cr
[s
->vga
.cr_index
] = reg_value
;
1653 printf("cirrus: handled outport cr_index %02x, cr_value %02x\n",
1654 s
->vga
.cr_index
, reg_value
);
1657 case 0x22: // Graphics Data Latches Readback (R)
1658 case 0x24: // Attribute Controller Toggle Readback (R)
1659 case 0x26: // Attribute Controller Index Readback (R)
1660 case 0x27: // Part ID (R)
1662 case 0x25: // Part Status
1665 printf("cirrus: outport cr_index %02x, cr_value %02x\n",
1666 s
->vga
.cr_index
, reg_value
);
1672 /***************************************
1674 * memory-mapped I/O (bitblt)
1676 ***************************************/
1678 static uint8_t cirrus_mmio_blt_read(CirrusVGAState
* s
, unsigned address
)
1683 case (CIRRUS_MMIO_BLTBGCOLOR
+ 0):
1684 value
= cirrus_vga_read_gr(s
, 0x00);
1686 case (CIRRUS_MMIO_BLTBGCOLOR
+ 1):
1687 value
= cirrus_vga_read_gr(s
, 0x10);
1689 case (CIRRUS_MMIO_BLTBGCOLOR
+ 2):
1690 value
= cirrus_vga_read_gr(s
, 0x12);
1692 case (CIRRUS_MMIO_BLTBGCOLOR
+ 3):
1693 value
= cirrus_vga_read_gr(s
, 0x14);
1695 case (CIRRUS_MMIO_BLTFGCOLOR
+ 0):
1696 value
= cirrus_vga_read_gr(s
, 0x01);
1698 case (CIRRUS_MMIO_BLTFGCOLOR
+ 1):
1699 value
= cirrus_vga_read_gr(s
, 0x11);
1701 case (CIRRUS_MMIO_BLTFGCOLOR
+ 2):
1702 value
= cirrus_vga_read_gr(s
, 0x13);
1704 case (CIRRUS_MMIO_BLTFGCOLOR
+ 3):
1705 value
= cirrus_vga_read_gr(s
, 0x15);
1707 case (CIRRUS_MMIO_BLTWIDTH
+ 0):
1708 value
= cirrus_vga_read_gr(s
, 0x20);
1710 case (CIRRUS_MMIO_BLTWIDTH
+ 1):
1711 value
= cirrus_vga_read_gr(s
, 0x21);
1713 case (CIRRUS_MMIO_BLTHEIGHT
+ 0):
1714 value
= cirrus_vga_read_gr(s
, 0x22);
1716 case (CIRRUS_MMIO_BLTHEIGHT
+ 1):
1717 value
= cirrus_vga_read_gr(s
, 0x23);
1719 case (CIRRUS_MMIO_BLTDESTPITCH
+ 0):
1720 value
= cirrus_vga_read_gr(s
, 0x24);
1722 case (CIRRUS_MMIO_BLTDESTPITCH
+ 1):
1723 value
= cirrus_vga_read_gr(s
, 0x25);
1725 case (CIRRUS_MMIO_BLTSRCPITCH
+ 0):
1726 value
= cirrus_vga_read_gr(s
, 0x26);
1728 case (CIRRUS_MMIO_BLTSRCPITCH
+ 1):
1729 value
= cirrus_vga_read_gr(s
, 0x27);
1731 case (CIRRUS_MMIO_BLTDESTADDR
+ 0):
1732 value
= cirrus_vga_read_gr(s
, 0x28);
1734 case (CIRRUS_MMIO_BLTDESTADDR
+ 1):
1735 value
= cirrus_vga_read_gr(s
, 0x29);
1737 case (CIRRUS_MMIO_BLTDESTADDR
+ 2):
1738 value
= cirrus_vga_read_gr(s
, 0x2a);
1740 case (CIRRUS_MMIO_BLTSRCADDR
+ 0):
1741 value
= cirrus_vga_read_gr(s
, 0x2c);
1743 case (CIRRUS_MMIO_BLTSRCADDR
+ 1):
1744 value
= cirrus_vga_read_gr(s
, 0x2d);
1746 case (CIRRUS_MMIO_BLTSRCADDR
+ 2):
1747 value
= cirrus_vga_read_gr(s
, 0x2e);
1749 case CIRRUS_MMIO_BLTWRITEMASK
:
1750 value
= cirrus_vga_read_gr(s
, 0x2f);
1752 case CIRRUS_MMIO_BLTMODE
:
1753 value
= cirrus_vga_read_gr(s
, 0x30);
1755 case CIRRUS_MMIO_BLTROP
:
1756 value
= cirrus_vga_read_gr(s
, 0x32);
1758 case CIRRUS_MMIO_BLTMODEEXT
:
1759 value
= cirrus_vga_read_gr(s
, 0x33);
1761 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR
+ 0):
1762 value
= cirrus_vga_read_gr(s
, 0x34);
1764 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR
+ 1):
1765 value
= cirrus_vga_read_gr(s
, 0x35);
1767 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK
+ 0):
1768 value
= cirrus_vga_read_gr(s
, 0x38);
1770 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK
+ 1):
1771 value
= cirrus_vga_read_gr(s
, 0x39);
1773 case CIRRUS_MMIO_BLTSTATUS
:
1774 value
= cirrus_vga_read_gr(s
, 0x31);
1778 printf("cirrus: mmio read - address 0x%04x\n", address
);
1783 return (uint8_t) value
;
1786 static void cirrus_mmio_blt_write(CirrusVGAState
* s
, unsigned address
,
1790 case (CIRRUS_MMIO_BLTBGCOLOR
+ 0):
1791 cirrus_vga_write_gr(s
, 0x00, value
);
1793 case (CIRRUS_MMIO_BLTBGCOLOR
+ 1):
1794 cirrus_vga_write_gr(s
, 0x10, value
);
1796 case (CIRRUS_MMIO_BLTBGCOLOR
+ 2):
1797 cirrus_vga_write_gr(s
, 0x12, value
);
1799 case (CIRRUS_MMIO_BLTBGCOLOR
+ 3):
1800 cirrus_vga_write_gr(s
, 0x14, value
);
1802 case (CIRRUS_MMIO_BLTFGCOLOR
+ 0):
1803 cirrus_vga_write_gr(s
, 0x01, value
);
1805 case (CIRRUS_MMIO_BLTFGCOLOR
+ 1):
1806 cirrus_vga_write_gr(s
, 0x11, value
);
1808 case (CIRRUS_MMIO_BLTFGCOLOR
+ 2):
1809 cirrus_vga_write_gr(s
, 0x13, value
);
1811 case (CIRRUS_MMIO_BLTFGCOLOR
+ 3):
1812 cirrus_vga_write_gr(s
, 0x15, value
);
1814 case (CIRRUS_MMIO_BLTWIDTH
+ 0):
1815 cirrus_vga_write_gr(s
, 0x20, value
);
1817 case (CIRRUS_MMIO_BLTWIDTH
+ 1):
1818 cirrus_vga_write_gr(s
, 0x21, value
);
1820 case (CIRRUS_MMIO_BLTHEIGHT
+ 0):
1821 cirrus_vga_write_gr(s
, 0x22, value
);
1823 case (CIRRUS_MMIO_BLTHEIGHT
+ 1):
1824 cirrus_vga_write_gr(s
, 0x23, value
);
1826 case (CIRRUS_MMIO_BLTDESTPITCH
+ 0):
1827 cirrus_vga_write_gr(s
, 0x24, value
);
1829 case (CIRRUS_MMIO_BLTDESTPITCH
+ 1):
1830 cirrus_vga_write_gr(s
, 0x25, value
);
1832 case (CIRRUS_MMIO_BLTSRCPITCH
+ 0):
1833 cirrus_vga_write_gr(s
, 0x26, value
);
1835 case (CIRRUS_MMIO_BLTSRCPITCH
+ 1):
1836 cirrus_vga_write_gr(s
, 0x27, value
);
1838 case (CIRRUS_MMIO_BLTDESTADDR
+ 0):
1839 cirrus_vga_write_gr(s
, 0x28, value
);
1841 case (CIRRUS_MMIO_BLTDESTADDR
+ 1):
1842 cirrus_vga_write_gr(s
, 0x29, value
);
1844 case (CIRRUS_MMIO_BLTDESTADDR
+ 2):
1845 cirrus_vga_write_gr(s
, 0x2a, value
);
1847 case (CIRRUS_MMIO_BLTDESTADDR
+ 3):
1850 case (CIRRUS_MMIO_BLTSRCADDR
+ 0):
1851 cirrus_vga_write_gr(s
, 0x2c, value
);
1853 case (CIRRUS_MMIO_BLTSRCADDR
+ 1):
1854 cirrus_vga_write_gr(s
, 0x2d, value
);
1856 case (CIRRUS_MMIO_BLTSRCADDR
+ 2):
1857 cirrus_vga_write_gr(s
, 0x2e, value
);
1859 case CIRRUS_MMIO_BLTWRITEMASK
:
1860 cirrus_vga_write_gr(s
, 0x2f, value
);
1862 case CIRRUS_MMIO_BLTMODE
:
1863 cirrus_vga_write_gr(s
, 0x30, value
);
1865 case CIRRUS_MMIO_BLTROP
:
1866 cirrus_vga_write_gr(s
, 0x32, value
);
1868 case CIRRUS_MMIO_BLTMODEEXT
:
1869 cirrus_vga_write_gr(s
, 0x33, value
);
1871 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR
+ 0):
1872 cirrus_vga_write_gr(s
, 0x34, value
);
1874 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR
+ 1):
1875 cirrus_vga_write_gr(s
, 0x35, value
);
1877 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK
+ 0):
1878 cirrus_vga_write_gr(s
, 0x38, value
);
1880 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK
+ 1):
1881 cirrus_vga_write_gr(s
, 0x39, value
);
1883 case CIRRUS_MMIO_BLTSTATUS
:
1884 cirrus_vga_write_gr(s
, 0x31, value
);
1888 printf("cirrus: mmio write - addr 0x%04x val 0x%02x (ignored)\n",
1895 /***************************************
1899 * assume TARGET_PAGE_SIZE >= 16
1901 ***************************************/
1903 static void cirrus_mem_writeb_mode4and5_8bpp(CirrusVGAState
* s
,
1909 unsigned val
= mem_value
;
1912 dst
= s
->vga
.vram_ptr
+ (offset
&= s
->cirrus_addr_mask
);
1913 for (x
= 0; x
< 8; x
++) {
1915 *dst
= s
->cirrus_shadow_gr1
;
1916 } else if (mode
== 5) {
1917 *dst
= s
->cirrus_shadow_gr0
;
1922 memory_region_set_dirty(&s
->vga
.vram
, offset
);
1923 memory_region_set_dirty(&s
->vga
.vram
, offset
+ 7);
1926 static void cirrus_mem_writeb_mode4and5_16bpp(CirrusVGAState
* s
,
1932 unsigned val
= mem_value
;
1935 dst
= s
->vga
.vram_ptr
+ (offset
&= s
->cirrus_addr_mask
);
1936 for (x
= 0; x
< 8; x
++) {
1938 *dst
= s
->cirrus_shadow_gr1
;
1939 *(dst
+ 1) = s
->vga
.gr
[0x11];
1940 } else if (mode
== 5) {
1941 *dst
= s
->cirrus_shadow_gr0
;
1942 *(dst
+ 1) = s
->vga
.gr
[0x10];
1947 memory_region_set_dirty(&s
->vga
.vram
, offset
);
1948 memory_region_set_dirty(&s
->vga
.vram
, offset
+ 15);
1951 /***************************************
1953 * memory access between 0xa0000-0xbffff
1955 ***************************************/
1957 static uint64_t cirrus_vga_mem_read(void *opaque
,
1958 target_phys_addr_t addr
,
1961 CirrusVGAState
*s
= opaque
;
1962 unsigned bank_index
;
1963 unsigned bank_offset
;
1966 if ((s
->vga
.sr
[0x07] & 0x01) == 0) {
1967 return vga_mem_readb(&s
->vga
, addr
);
1970 if (addr
< 0x10000) {
1971 /* XXX handle bitblt */
1973 bank_index
= addr
>> 15;
1974 bank_offset
= addr
& 0x7fff;
1975 if (bank_offset
< s
->cirrus_bank_limit
[bank_index
]) {
1976 bank_offset
+= s
->cirrus_bank_base
[bank_index
];
1977 if ((s
->vga
.gr
[0x0B] & 0x14) == 0x14) {
1979 } else if (s
->vga
.gr
[0x0B] & 0x02) {
1982 bank_offset
&= s
->cirrus_addr_mask
;
1983 val
= *(s
->vga
.vram_ptr
+ bank_offset
);
1986 } else if (addr
>= 0x18000 && addr
< 0x18100) {
1987 /* memory-mapped I/O */
1989 if ((s
->vga
.sr
[0x17] & 0x44) == 0x04) {
1990 val
= cirrus_mmio_blt_read(s
, addr
& 0xff);
1995 printf("cirrus: mem_readb " TARGET_FMT_plx
"\n", addr
);
2001 static void cirrus_vga_mem_write(void *opaque
,
2002 target_phys_addr_t addr
,
2006 CirrusVGAState
*s
= opaque
;
2007 unsigned bank_index
;
2008 unsigned bank_offset
;
2011 if ((s
->vga
.sr
[0x07] & 0x01) == 0) {
2012 vga_mem_writeb(&s
->vga
, addr
, mem_value
);
2016 if (addr
< 0x10000) {
2017 if (s
->cirrus_srcptr
!= s
->cirrus_srcptr_end
) {
2019 *s
->cirrus_srcptr
++ = (uint8_t) mem_value
;
2020 if (s
->cirrus_srcptr
>= s
->cirrus_srcptr_end
) {
2021 cirrus_bitblt_cputovideo_next(s
);
2025 bank_index
= addr
>> 15;
2026 bank_offset
= addr
& 0x7fff;
2027 if (bank_offset
< s
->cirrus_bank_limit
[bank_index
]) {
2028 bank_offset
+= s
->cirrus_bank_base
[bank_index
];
2029 if ((s
->vga
.gr
[0x0B] & 0x14) == 0x14) {
2031 } else if (s
->vga
.gr
[0x0B] & 0x02) {
2034 bank_offset
&= s
->cirrus_addr_mask
;
2035 mode
= s
->vga
.gr
[0x05] & 0x7;
2036 if (mode
< 4 || mode
> 5 || ((s
->vga
.gr
[0x0B] & 0x4) == 0)) {
2037 *(s
->vga
.vram_ptr
+ bank_offset
) = mem_value
;
2038 memory_region_set_dirty(&s
->vga
.vram
, bank_offset
);
2040 if ((s
->vga
.gr
[0x0B] & 0x14) != 0x14) {
2041 cirrus_mem_writeb_mode4and5_8bpp(s
, mode
,
2045 cirrus_mem_writeb_mode4and5_16bpp(s
, mode
,
2052 } else if (addr
>= 0x18000 && addr
< 0x18100) {
2053 /* memory-mapped I/O */
2054 if ((s
->vga
.sr
[0x17] & 0x44) == 0x04) {
2055 cirrus_mmio_blt_write(s
, addr
& 0xff, mem_value
);
2059 printf("cirrus: mem_writeb " TARGET_FMT_plx
" value %02x\n", addr
,
2065 static const MemoryRegionOps cirrus_vga_mem_ops
= {
2066 .read
= cirrus_vga_mem_read
,
2067 .write
= cirrus_vga_mem_write
,
2068 .endianness
= DEVICE_LITTLE_ENDIAN
,
2070 .min_access_size
= 1,
2071 .max_access_size
= 1,
2075 /***************************************
2079 ***************************************/
2081 static inline void invalidate_cursor1(CirrusVGAState
*s
)
2083 if (s
->last_hw_cursor_size
) {
2084 vga_invalidate_scanlines(&s
->vga
,
2085 s
->last_hw_cursor_y
+ s
->last_hw_cursor_y_start
,
2086 s
->last_hw_cursor_y
+ s
->last_hw_cursor_y_end
);
2090 static inline void cirrus_cursor_compute_yrange(CirrusVGAState
*s
)
2094 int y
, y_min
, y_max
;
2096 src
= s
->vga
.vram_ptr
+ s
->real_vram_size
- 16 * 1024;
2097 if (s
->vga
.sr
[0x12] & CIRRUS_CURSOR_LARGE
) {
2098 src
+= (s
->vga
.sr
[0x13] & 0x3c) * 256;
2101 for(y
= 0; y
< 64; y
++) {
2102 content
= ((uint32_t *)src
)[0] |
2103 ((uint32_t *)src
)[1] |
2104 ((uint32_t *)src
)[2] |
2105 ((uint32_t *)src
)[3];
2115 src
+= (s
->vga
.sr
[0x13] & 0x3f) * 256;
2118 for(y
= 0; y
< 32; y
++) {
2119 content
= ((uint32_t *)src
)[0] |
2120 ((uint32_t *)(src
+ 128))[0];
2130 if (y_min
> y_max
) {
2131 s
->last_hw_cursor_y_start
= 0;
2132 s
->last_hw_cursor_y_end
= 0;
2134 s
->last_hw_cursor_y_start
= y_min
;
2135 s
->last_hw_cursor_y_end
= y_max
+ 1;
2139 /* NOTE: we do not currently handle the cursor bitmap change, so we
2140 update the cursor only if it moves. */
2141 static void cirrus_cursor_invalidate(VGACommonState
*s1
)
2143 CirrusVGAState
*s
= container_of(s1
, CirrusVGAState
, vga
);
2146 if (!(s
->vga
.sr
[0x12] & CIRRUS_CURSOR_SHOW
)) {
2149 if (s
->vga
.sr
[0x12] & CIRRUS_CURSOR_LARGE
)
2154 /* invalidate last cursor and new cursor if any change */
2155 if (s
->last_hw_cursor_size
!= size
||
2156 s
->last_hw_cursor_x
!= s
->hw_cursor_x
||
2157 s
->last_hw_cursor_y
!= s
->hw_cursor_y
) {
2159 invalidate_cursor1(s
);
2161 s
->last_hw_cursor_size
= size
;
2162 s
->last_hw_cursor_x
= s
->hw_cursor_x
;
2163 s
->last_hw_cursor_y
= s
->hw_cursor_y
;
2164 /* compute the real cursor min and max y */
2165 cirrus_cursor_compute_yrange(s
);
2166 invalidate_cursor1(s
);
2170 static void cirrus_cursor_draw_line(VGACommonState
*s1
, uint8_t *d1
, int scr_y
)
2172 CirrusVGAState
*s
= container_of(s1
, CirrusVGAState
, vga
);
2173 int w
, h
, bpp
, x1
, x2
, poffset
;
2174 unsigned int color0
, color1
;
2175 const uint8_t *palette
, *src
;
2178 if (!(s
->vga
.sr
[0x12] & CIRRUS_CURSOR_SHOW
))
2180 /* fast test to see if the cursor intersects with the scan line */
2181 if (s
->vga
.sr
[0x12] & CIRRUS_CURSOR_LARGE
) {
2186 if (scr_y
< s
->hw_cursor_y
||
2187 scr_y
>= (s
->hw_cursor_y
+ h
))
2190 src
= s
->vga
.vram_ptr
+ s
->real_vram_size
- 16 * 1024;
2191 if (s
->vga
.sr
[0x12] & CIRRUS_CURSOR_LARGE
) {
2192 src
+= (s
->vga
.sr
[0x13] & 0x3c) * 256;
2193 src
+= (scr_y
- s
->hw_cursor_y
) * 16;
2195 content
= ((uint32_t *)src
)[0] |
2196 ((uint32_t *)src
)[1] |
2197 ((uint32_t *)src
)[2] |
2198 ((uint32_t *)src
)[3];
2200 src
+= (s
->vga
.sr
[0x13] & 0x3f) * 256;
2201 src
+= (scr_y
- s
->hw_cursor_y
) * 4;
2203 content
= ((uint32_t *)src
)[0] |
2204 ((uint32_t *)(src
+ 128))[0];
2206 /* if nothing to draw, no need to continue */
2211 x1
= s
->hw_cursor_x
;
2212 if (x1
>= s
->vga
.last_scr_width
)
2214 x2
= s
->hw_cursor_x
+ w
;
2215 if (x2
> s
->vga
.last_scr_width
)
2216 x2
= s
->vga
.last_scr_width
;
2218 palette
= s
->cirrus_hidden_palette
;
2219 color0
= s
->vga
.rgb_to_pixel(c6_to_8(palette
[0x0 * 3]),
2220 c6_to_8(palette
[0x0 * 3 + 1]),
2221 c6_to_8(palette
[0x0 * 3 + 2]));
2222 color1
= s
->vga
.rgb_to_pixel(c6_to_8(palette
[0xf * 3]),
2223 c6_to_8(palette
[0xf * 3 + 1]),
2224 c6_to_8(palette
[0xf * 3 + 2]));
2225 bpp
= ((ds_get_bits_per_pixel(s
->vga
.ds
) + 7) >> 3);
2227 switch(ds_get_bits_per_pixel(s
->vga
.ds
)) {
2231 vga_draw_cursor_line_8(d1
, src
, poffset
, w
, color0
, color1
, 0xff);
2234 vga_draw_cursor_line_16(d1
, src
, poffset
, w
, color0
, color1
, 0x7fff);
2237 vga_draw_cursor_line_16(d1
, src
, poffset
, w
, color0
, color1
, 0xffff);
2240 vga_draw_cursor_line_32(d1
, src
, poffset
, w
, color0
, color1
, 0xffffff);
2245 /***************************************
2249 ***************************************/
2251 static uint64_t cirrus_linear_read(void *opaque
, target_phys_addr_t addr
,
2254 CirrusVGAState
*s
= opaque
;
2257 addr
&= s
->cirrus_addr_mask
;
2259 if (((s
->vga
.sr
[0x17] & 0x44) == 0x44) &&
2260 ((addr
& s
->linear_mmio_mask
) == s
->linear_mmio_mask
)) {
2261 /* memory-mapped I/O */
2262 ret
= cirrus_mmio_blt_read(s
, addr
& 0xff);
2264 /* XXX handle bitblt */
2268 if ((s
->vga
.gr
[0x0B] & 0x14) == 0x14) {
2270 } else if (s
->vga
.gr
[0x0B] & 0x02) {
2273 addr
&= s
->cirrus_addr_mask
;
2274 ret
= *(s
->vga
.vram_ptr
+ addr
);
2280 static void cirrus_linear_write(void *opaque
, target_phys_addr_t addr
,
2281 uint64_t val
, unsigned size
)
2283 CirrusVGAState
*s
= opaque
;
2286 addr
&= s
->cirrus_addr_mask
;
2288 if (((s
->vga
.sr
[0x17] & 0x44) == 0x44) &&
2289 ((addr
& s
->linear_mmio_mask
) == s
->linear_mmio_mask
)) {
2290 /* memory-mapped I/O */
2291 cirrus_mmio_blt_write(s
, addr
& 0xff, val
);
2292 } else if (s
->cirrus_srcptr
!= s
->cirrus_srcptr_end
) {
2294 *s
->cirrus_srcptr
++ = (uint8_t) val
;
2295 if (s
->cirrus_srcptr
>= s
->cirrus_srcptr_end
) {
2296 cirrus_bitblt_cputovideo_next(s
);
2300 if ((s
->vga
.gr
[0x0B] & 0x14) == 0x14) {
2302 } else if (s
->vga
.gr
[0x0B] & 0x02) {
2305 addr
&= s
->cirrus_addr_mask
;
2307 mode
= s
->vga
.gr
[0x05] & 0x7;
2308 if (mode
< 4 || mode
> 5 || ((s
->vga
.gr
[0x0B] & 0x4) == 0)) {
2309 *(s
->vga
.vram_ptr
+ addr
) = (uint8_t) val
;
2310 memory_region_set_dirty(&s
->vga
.vram
, addr
);
2312 if ((s
->vga
.gr
[0x0B] & 0x14) != 0x14) {
2313 cirrus_mem_writeb_mode4and5_8bpp(s
, mode
, addr
, val
);
2315 cirrus_mem_writeb_mode4and5_16bpp(s
, mode
, addr
, val
);
2321 /***************************************
2323 * system to screen memory access
2325 ***************************************/
2328 static uint64_t cirrus_linear_bitblt_read(void *opaque
,
2329 target_phys_addr_t addr
,
2332 CirrusVGAState
*s
= opaque
;
2335 /* XXX handle bitblt */
2341 static void cirrus_linear_bitblt_write(void *opaque
,
2342 target_phys_addr_t addr
,
2346 CirrusVGAState
*s
= opaque
;
2348 if (s
->cirrus_srcptr
!= s
->cirrus_srcptr_end
) {
2350 *s
->cirrus_srcptr
++ = (uint8_t) val
;
2351 if (s
->cirrus_srcptr
>= s
->cirrus_srcptr_end
) {
2352 cirrus_bitblt_cputovideo_next(s
);
2357 static const MemoryRegionOps cirrus_linear_bitblt_io_ops
= {
2358 .read
= cirrus_linear_bitblt_read
,
2359 .write
= cirrus_linear_bitblt_write
,
2360 .endianness
= DEVICE_LITTLE_ENDIAN
,
2362 .min_access_size
= 1,
2363 .max_access_size
= 1,
2367 static void unmap_bank(CirrusVGAState
*s
, unsigned bank
)
2369 if (s
->cirrus_bank
[bank
]) {
2370 memory_region_del_subregion(&s
->low_mem_container
,
2371 s
->cirrus_bank
[bank
]);
2372 memory_region_destroy(s
->cirrus_bank
[bank
]);
2373 g_free(s
->cirrus_bank
[bank
]);
2374 s
->cirrus_bank
[bank
] = NULL
;
2378 static void map_linear_vram_bank(CirrusVGAState
*s
, unsigned bank
)
2381 static const char *names
[] = { "vga.bank0", "vga.bank1" };
2383 if (!(s
->cirrus_srcptr
!= s
->cirrus_srcptr_end
)
2384 && !((s
->vga
.sr
[0x07] & 0x01) == 0)
2385 && !((s
->vga
.gr
[0x0B] & 0x14) == 0x14)
2386 && !(s
->vga
.gr
[0x0B] & 0x02)) {
2388 mr
= g_malloc(sizeof(*mr
));
2389 memory_region_init_alias(mr
, names
[bank
], &s
->vga
.vram
,
2390 s
->cirrus_bank_base
[bank
], 0x8000);
2391 memory_region_add_subregion_overlap(
2392 &s
->low_mem_container
,
2396 unmap_bank(s
, bank
);
2397 s
->cirrus_bank
[bank
] = mr
;
2399 unmap_bank(s
, bank
);
2403 static void map_linear_vram(CirrusVGAState
*s
)
2405 if (!s
->linear_vram
) {
2406 s
->linear_vram
= true;
2407 memory_region_add_subregion_overlap(&s
->pci_bar
, 0, &s
->vga
.vram
, 1);
2409 map_linear_vram_bank(s
, 0);
2410 map_linear_vram_bank(s
, 1);
2413 static void unmap_linear_vram(CirrusVGAState
*s
)
2415 if (s
->linear_vram
) {
2416 s
->linear_vram
= false;
2417 memory_region_del_subregion(&s
->pci_bar
, &s
->vga
.vram
);
2423 /* Compute the memory access functions */
2424 static void cirrus_update_memory_access(CirrusVGAState
*s
)
2428 if ((s
->vga
.sr
[0x17] & 0x44) == 0x44) {
2430 } else if (s
->cirrus_srcptr
!= s
->cirrus_srcptr_end
) {
2433 if ((s
->vga
.gr
[0x0B] & 0x14) == 0x14) {
2435 } else if (s
->vga
.gr
[0x0B] & 0x02) {
2439 mode
= s
->vga
.gr
[0x05] & 0x7;
2440 if (mode
< 4 || mode
> 5 || ((s
->vga
.gr
[0x0B] & 0x4) == 0)) {
2444 unmap_linear_vram(s
);
2452 static uint32_t cirrus_vga_ioport_read(void *opaque
, uint32_t addr
)
2454 CirrusVGAState
*c
= opaque
;
2455 VGACommonState
*s
= &c
->vga
;
2458 if (vga_ioport_invalid(s
, addr
)) {
2463 if (s
->ar_flip_flop
== 0) {
2470 index
= s
->ar_index
& 0x1f;
2483 val
= cirrus_vga_read_sr(c
);
2485 #ifdef DEBUG_VGA_REG
2486 printf("vga: read SR%x = 0x%02x\n", s
->sr_index
, val
);
2490 val
= cirrus_read_hidden_dac(c
);
2496 val
= s
->dac_write_index
;
2497 c
->cirrus_hidden_dac_lockindex
= 0;
2500 val
= cirrus_vga_read_palette(c
);
2512 val
= cirrus_vga_read_gr(c
, s
->gr_index
);
2513 #ifdef DEBUG_VGA_REG
2514 printf("vga: read GR%x = 0x%02x\n", s
->gr_index
, val
);
2523 val
= cirrus_vga_read_cr(c
, s
->cr_index
);
2524 #ifdef DEBUG_VGA_REG
2525 printf("vga: read CR%x = 0x%02x\n", s
->cr_index
, val
);
2530 /* just toggle to fool polling */
2531 val
= s
->st01
= s
->retrace(s
);
2532 s
->ar_flip_flop
= 0;
2539 #if defined(DEBUG_VGA)
2540 printf("VGA: read addr=0x%04x data=0x%02x\n", addr
, val
);
2545 static void cirrus_vga_ioport_write(void *opaque
, uint32_t addr
, uint32_t val
)
2547 CirrusVGAState
*c
= opaque
;
2548 VGACommonState
*s
= &c
->vga
;
2551 /* check port range access depending on color/monochrome mode */
2552 if (vga_ioport_invalid(s
, addr
)) {
2556 printf("VGA: write addr=0x%04x data=0x%02x\n", addr
, val
);
2561 if (s
->ar_flip_flop
== 0) {
2565 index
= s
->ar_index
& 0x1f;
2568 s
->ar
[index
] = val
& 0x3f;
2571 s
->ar
[index
] = val
& ~0x10;
2577 s
->ar
[index
] = val
& ~0xc0;
2580 s
->ar
[index
] = val
& ~0xf0;
2583 s
->ar
[index
] = val
& ~0xf0;
2589 s
->ar_flip_flop
^= 1;
2592 s
->msr
= val
& ~0x10;
2593 s
->update_retrace_info(s
);
2599 #ifdef DEBUG_VGA_REG
2600 printf("vga: write SR%x = 0x%02x\n", s
->sr_index
, val
);
2602 cirrus_vga_write_sr(c
, val
);
2606 cirrus_write_hidden_dac(c
, val
);
2609 s
->dac_read_index
= val
;
2610 s
->dac_sub_index
= 0;
2614 s
->dac_write_index
= val
;
2615 s
->dac_sub_index
= 0;
2619 cirrus_vga_write_palette(c
, val
);
2625 #ifdef DEBUG_VGA_REG
2626 printf("vga: write GR%x = 0x%02x\n", s
->gr_index
, val
);
2628 cirrus_vga_write_gr(c
, s
->gr_index
, val
);
2636 #ifdef DEBUG_VGA_REG
2637 printf("vga: write CR%x = 0x%02x\n", s
->cr_index
, val
);
2639 cirrus_vga_write_cr(c
, val
);
2643 s
->fcr
= val
& 0x10;
2648 /***************************************
2650 * memory-mapped I/O access
2652 ***************************************/
2654 static uint64_t cirrus_mmio_read(void *opaque
, target_phys_addr_t addr
,
2657 CirrusVGAState
*s
= opaque
;
2659 if (addr
>= 0x100) {
2660 return cirrus_mmio_blt_read(s
, addr
- 0x100);
2662 return cirrus_vga_ioport_read(s
, addr
+ 0x3c0);
2666 static void cirrus_mmio_write(void *opaque
, target_phys_addr_t addr
,
2667 uint64_t val
, unsigned size
)
2669 CirrusVGAState
*s
= opaque
;
2671 if (addr
>= 0x100) {
2672 cirrus_mmio_blt_write(s
, addr
- 0x100, val
);
2674 cirrus_vga_ioport_write(s
, addr
+ 0x3c0, val
);
2678 static const MemoryRegionOps cirrus_mmio_io_ops
= {
2679 .read
= cirrus_mmio_read
,
2680 .write
= cirrus_mmio_write
,
2681 .endianness
= DEVICE_LITTLE_ENDIAN
,
2683 .min_access_size
= 1,
2684 .max_access_size
= 1,
2688 /* load/save state */
2690 static int cirrus_post_load(void *opaque
, int version_id
)
2692 CirrusVGAState
*s
= opaque
;
2694 s
->vga
.gr
[0x00] = s
->cirrus_shadow_gr0
& 0x0f;
2695 s
->vga
.gr
[0x01] = s
->cirrus_shadow_gr1
& 0x0f;
2697 cirrus_update_memory_access(s
);
2699 s
->vga
.graphic_mode
= -1;
2700 cirrus_update_bank_ptr(s
, 0);
2701 cirrus_update_bank_ptr(s
, 1);
2705 static const VMStateDescription vmstate_cirrus_vga
= {
2706 .name
= "cirrus_vga",
2708 .minimum_version_id
= 1,
2709 .minimum_version_id_old
= 1,
2710 .post_load
= cirrus_post_load
,
2711 .fields
= (VMStateField
[]) {
2712 VMSTATE_UINT32(vga
.latch
, CirrusVGAState
),
2713 VMSTATE_UINT8(vga
.sr_index
, CirrusVGAState
),
2714 VMSTATE_BUFFER(vga
.sr
, CirrusVGAState
),
2715 VMSTATE_UINT8(vga
.gr_index
, CirrusVGAState
),
2716 VMSTATE_UINT8(cirrus_shadow_gr0
, CirrusVGAState
),
2717 VMSTATE_UINT8(cirrus_shadow_gr1
, CirrusVGAState
),
2718 VMSTATE_BUFFER_START_MIDDLE(vga
.gr
, CirrusVGAState
, 2),
2719 VMSTATE_UINT8(vga
.ar_index
, CirrusVGAState
),
2720 VMSTATE_BUFFER(vga
.ar
, CirrusVGAState
),
2721 VMSTATE_INT32(vga
.ar_flip_flop
, CirrusVGAState
),
2722 VMSTATE_UINT8(vga
.cr_index
, CirrusVGAState
),
2723 VMSTATE_BUFFER(vga
.cr
, CirrusVGAState
),
2724 VMSTATE_UINT8(vga
.msr
, CirrusVGAState
),
2725 VMSTATE_UINT8(vga
.fcr
, CirrusVGAState
),
2726 VMSTATE_UINT8(vga
.st00
, CirrusVGAState
),
2727 VMSTATE_UINT8(vga
.st01
, CirrusVGAState
),
2728 VMSTATE_UINT8(vga
.dac_state
, CirrusVGAState
),
2729 VMSTATE_UINT8(vga
.dac_sub_index
, CirrusVGAState
),
2730 VMSTATE_UINT8(vga
.dac_read_index
, CirrusVGAState
),
2731 VMSTATE_UINT8(vga
.dac_write_index
, CirrusVGAState
),
2732 VMSTATE_BUFFER(vga
.dac_cache
, CirrusVGAState
),
2733 VMSTATE_BUFFER(vga
.palette
, CirrusVGAState
),
2734 VMSTATE_INT32(vga
.bank_offset
, CirrusVGAState
),
2735 VMSTATE_UINT8(cirrus_hidden_dac_lockindex
, CirrusVGAState
),
2736 VMSTATE_UINT8(cirrus_hidden_dac_data
, CirrusVGAState
),
2737 VMSTATE_UINT32(hw_cursor_x
, CirrusVGAState
),
2738 VMSTATE_UINT32(hw_cursor_y
, CirrusVGAState
),
2739 /* XXX: we do not save the bitblt state - we assume we do not save
2740 the state when the blitter is active */
2741 VMSTATE_END_OF_LIST()
2745 static const VMStateDescription vmstate_pci_cirrus_vga
= {
2746 .name
= "cirrus_vga",
2748 .minimum_version_id
= 2,
2749 .minimum_version_id_old
= 2,
2750 .fields
= (VMStateField
[]) {
2751 VMSTATE_PCI_DEVICE(dev
, PCICirrusVGAState
),
2752 VMSTATE_STRUCT(cirrus_vga
, PCICirrusVGAState
, 0,
2753 vmstate_cirrus_vga
, CirrusVGAState
),
2754 VMSTATE_END_OF_LIST()
2758 /***************************************
2762 ***************************************/
2764 static void cirrus_reset(void *opaque
)
2766 CirrusVGAState
*s
= opaque
;
2768 vga_common_reset(&s
->vga
);
2769 unmap_linear_vram(s
);
2770 s
->vga
.sr
[0x06] = 0x0f;
2771 if (s
->device_id
== CIRRUS_ID_CLGD5446
) {
2772 /* 4MB 64 bit memory config, always PCI */
2773 s
->vga
.sr
[0x1F] = 0x2d; // MemClock
2774 s
->vga
.gr
[0x18] = 0x0f; // fastest memory configuration
2775 s
->vga
.sr
[0x0f] = 0x98;
2776 s
->vga
.sr
[0x17] = 0x20;
2777 s
->vga
.sr
[0x15] = 0x04; /* memory size, 3=2MB, 4=4MB */
2779 s
->vga
.sr
[0x1F] = 0x22; // MemClock
2780 s
->vga
.sr
[0x0F] = CIRRUS_MEMSIZE_2M
;
2781 s
->vga
.sr
[0x17] = s
->bustype
;
2782 s
->vga
.sr
[0x15] = 0x03; /* memory size, 3=2MB, 4=4MB */
2784 s
->vga
.cr
[0x27] = s
->device_id
;
2786 /* Win2K seems to assume that the pattern buffer is at 0xff
2788 memset(s
->vga
.vram_ptr
, 0xff, s
->real_vram_size
);
2790 s
->cirrus_hidden_dac_lockindex
= 5;
2791 s
->cirrus_hidden_dac_data
= 0;
2794 static const MemoryRegionOps cirrus_linear_io_ops
= {
2795 .read
= cirrus_linear_read
,
2796 .write
= cirrus_linear_write
,
2797 .endianness
= DEVICE_LITTLE_ENDIAN
,
2799 .min_access_size
= 1,
2800 .max_access_size
= 1,
2804 static void cirrus_init_common(CirrusVGAState
* s
, int device_id
, int is_pci
)
2811 for(i
= 0;i
< 256; i
++)
2812 rop_to_index
[i
] = CIRRUS_ROP_NOP_INDEX
; /* nop rop */
2813 rop_to_index
[CIRRUS_ROP_0
] = 0;
2814 rop_to_index
[CIRRUS_ROP_SRC_AND_DST
] = 1;
2815 rop_to_index
[CIRRUS_ROP_NOP
] = 2;
2816 rop_to_index
[CIRRUS_ROP_SRC_AND_NOTDST
] = 3;
2817 rop_to_index
[CIRRUS_ROP_NOTDST
] = 4;
2818 rop_to_index
[CIRRUS_ROP_SRC
] = 5;
2819 rop_to_index
[CIRRUS_ROP_1
] = 6;
2820 rop_to_index
[CIRRUS_ROP_NOTSRC_AND_DST
] = 7;
2821 rop_to_index
[CIRRUS_ROP_SRC_XOR_DST
] = 8;
2822 rop_to_index
[CIRRUS_ROP_SRC_OR_DST
] = 9;
2823 rop_to_index
[CIRRUS_ROP_NOTSRC_OR_NOTDST
] = 10;
2824 rop_to_index
[CIRRUS_ROP_SRC_NOTXOR_DST
] = 11;
2825 rop_to_index
[CIRRUS_ROP_SRC_OR_NOTDST
] = 12;
2826 rop_to_index
[CIRRUS_ROP_NOTSRC
] = 13;
2827 rop_to_index
[CIRRUS_ROP_NOTSRC_OR_DST
] = 14;
2828 rop_to_index
[CIRRUS_ROP_NOTSRC_AND_NOTDST
] = 15;
2829 s
->device_id
= device_id
;
2831 s
->bustype
= CIRRUS_BUSTYPE_PCI
;
2833 s
->bustype
= CIRRUS_BUSTYPE_ISA
;
2836 register_ioport_write(0x3c0, 16, 1, cirrus_vga_ioport_write
, s
);
2838 register_ioport_write(0x3b4, 2, 1, cirrus_vga_ioport_write
, s
);
2839 register_ioport_write(0x3d4, 2, 1, cirrus_vga_ioport_write
, s
);
2840 register_ioport_write(0x3ba, 1, 1, cirrus_vga_ioport_write
, s
);
2841 register_ioport_write(0x3da, 1, 1, cirrus_vga_ioport_write
, s
);
2843 register_ioport_read(0x3c0, 16, 1, cirrus_vga_ioport_read
, s
);
2845 register_ioport_read(0x3b4, 2, 1, cirrus_vga_ioport_read
, s
);
2846 register_ioport_read(0x3d4, 2, 1, cirrus_vga_ioport_read
, s
);
2847 register_ioport_read(0x3ba, 1, 1, cirrus_vga_ioport_read
, s
);
2848 register_ioport_read(0x3da, 1, 1, cirrus_vga_ioport_read
, s
);
2850 memory_region_init(&s
->low_mem_container
,
2851 "cirrus-lowmem-container",
2854 memory_region_init_io(&s
->low_mem
, &cirrus_vga_mem_ops
, s
,
2855 "cirrus-low-memory", 0x20000);
2856 memory_region_add_subregion(&s
->low_mem_container
, 0, &s
->low_mem
);
2857 memory_region_add_subregion_overlap(get_system_memory(),
2858 isa_mem_base
+ 0x000a0000,
2859 &s
->low_mem_container
,
2861 memory_region_set_coalescing(&s
->low_mem
);
2863 /* I/O handler for LFB */
2864 memory_region_init_io(&s
->cirrus_linear_io
, &cirrus_linear_io_ops
, s
,
2865 "cirrus-linear-io", VGA_RAM_SIZE
);
2867 /* I/O handler for LFB */
2868 memory_region_init_io(&s
->cirrus_linear_bitblt_io
,
2869 &cirrus_linear_bitblt_io_ops
,
2871 "cirrus-bitblt-mmio",
2874 /* I/O handler for memory-mapped I/O */
2875 memory_region_init_io(&s
->cirrus_mmio_io
, &cirrus_mmio_io_ops
, s
,
2876 "cirrus-mmio", CIRRUS_PNPMMIO_SIZE
);
2879 (s
->device_id
== CIRRUS_ID_CLGD5446
) ? 4096 * 1024 : 2048 * 1024;
2881 /* XXX: s->vga.vram_size must be a power of two */
2882 s
->cirrus_addr_mask
= s
->real_vram_size
- 1;
2883 s
->linear_mmio_mask
= s
->real_vram_size
- 256;
2885 s
->vga
.get_bpp
= cirrus_get_bpp
;
2886 s
->vga
.get_offsets
= cirrus_get_offsets
;
2887 s
->vga
.get_resolution
= cirrus_get_resolution
;
2888 s
->vga
.cursor_invalidate
= cirrus_cursor_invalidate
;
2889 s
->vga
.cursor_draw_line
= cirrus_cursor_draw_line
;
2891 qemu_register_reset(cirrus_reset
, s
);
2894 /***************************************
2898 ***************************************/
2900 void isa_cirrus_vga_init(void)
2904 s
= g_malloc0(sizeof(CirrusVGAState
));
2906 vga_common_init(&s
->vga
, VGA_RAM_SIZE
);
2907 cirrus_init_common(s
, CIRRUS_ID_CLGD5430
, 0);
2908 s
->vga
.ds
= graphic_console_init(s
->vga
.update
, s
->vga
.invalidate
,
2909 s
->vga
.screen_dump
, s
->vga
.text_update
,
2911 vmstate_register(NULL
, 0, &vmstate_cirrus_vga
, s
);
2912 rom_add_vga(VGABIOS_CIRRUS_FILENAME
);
2913 /* XXX ISA-LFB support */
2916 /***************************************
2920 ***************************************/
2922 static int pci_cirrus_vga_initfn(PCIDevice
*dev
)
2924 PCICirrusVGAState
*d
= DO_UPCAST(PCICirrusVGAState
, dev
, dev
);
2925 CirrusVGAState
*s
= &d
->cirrus_vga
;
2926 PCIDeviceInfo
*info
= DO_UPCAST(PCIDeviceInfo
, qdev
, dev
->qdev
.info
);
2927 int16_t device_id
= info
->device_id
;
2930 vga_common_init(&s
->vga
, VGA_RAM_SIZE
);
2931 cirrus_init_common(s
, device_id
, 1);
2932 s
->vga
.ds
= graphic_console_init(s
->vga
.update
, s
->vga
.invalidate
,
2933 s
->vga
.screen_dump
, s
->vga
.text_update
,
2938 memory_region_init(&s
->pci_bar
, "cirrus-pci-bar0", 0x2000000);
2940 /* XXX: add byte swapping apertures */
2941 memory_region_add_subregion(&s
->pci_bar
, 0, &s
->cirrus_linear_io
);
2942 memory_region_add_subregion(&s
->pci_bar
, 0x1000000,
2943 &s
->cirrus_linear_bitblt_io
);
2945 /* setup memory space */
2947 /* memory #1 memory-mapped I/O */
2948 /* XXX: s->vga.vram_size must be a power of two */
2949 pci_register_bar(&d
->dev
, 0, PCI_BASE_ADDRESS_MEM_PREFETCH
, &s
->pci_bar
);
2950 if (device_id
== CIRRUS_ID_CLGD5446
) {
2951 pci_register_bar(&d
->dev
, 1, 0, &s
->cirrus_mmio_io
);
2956 void pci_cirrus_vga_init(PCIBus
*bus
)
2958 pci_create_simple(bus
, -1, "cirrus-vga");
2961 static PCIDeviceInfo cirrus_vga_info
= {
2962 .qdev
.name
= "cirrus-vga",
2963 .qdev
.desc
= "Cirrus CLGD 54xx VGA",
2964 .qdev
.size
= sizeof(PCICirrusVGAState
),
2965 .qdev
.vmsd
= &vmstate_pci_cirrus_vga
,
2967 .init
= pci_cirrus_vga_initfn
,
2968 .romfile
= VGABIOS_CIRRUS_FILENAME
,
2969 .vendor_id
= PCI_VENDOR_ID_CIRRUS
,
2970 .device_id
= CIRRUS_ID_CLGD5446
,
2971 .class_id
= PCI_CLASS_DISPLAY_VGA
,
2974 static void cirrus_vga_register(void)
2976 pci_qdev_register(&cirrus_vga_info
);
2978 device_init(cirrus_vga_register
);