4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 #include "qemu/osdep.h"
20 #include "qapi/error.h"
22 #include "qemu/cutils.h"
24 #include "exec/exec-all.h"
25 #include "exec/target_page.h"
27 #include "hw/qdev-core.h"
28 #include "hw/qdev-properties.h"
29 #if !defined(CONFIG_USER_ONLY)
30 #include "hw/boards.h"
31 #include "hw/xen/xen.h"
33 #include "sysemu/kvm.h"
34 #include "sysemu/sysemu.h"
35 #include "qemu/timer.h"
36 #include "qemu/config-file.h"
37 #include "qemu/error-report.h"
38 #include "qemu/qemu-print.h"
39 #if defined(CONFIG_USER_ONLY)
41 #else /* !CONFIG_USER_ONLY */
43 #include "exec/memory.h"
44 #include "exec/ioport.h"
45 #include "sysemu/dma.h"
46 #include "sysemu/numa.h"
47 #include "sysemu/hw_accel.h"
48 #include "exec/address-spaces.h"
49 #include "sysemu/xen-mapcache.h"
50 #include "trace-root.h"
52 #ifdef CONFIG_FALLOCATE_PUNCH_HOLE
53 #include <linux/falloc.h>
57 #include "qemu/rcu_queue.h"
58 #include "qemu/main-loop.h"
59 #include "translate-all.h"
60 #include "sysemu/replay.h"
62 #include "exec/memory-internal.h"
63 #include "exec/ram_addr.h"
66 #include "migration/vmstate.h"
68 #include "qemu/range.h"
70 #include "qemu/mmap-alloc.h"
73 #include "monitor/monitor.h"
75 //#define DEBUG_SUBPAGE
77 #if !defined(CONFIG_USER_ONLY)
78 /* ram_list is read under rcu_read_lock()/rcu_read_unlock(). Writes
79 * are protected by the ramlist lock.
81 RAMList ram_list
= { .blocks
= QLIST_HEAD_INITIALIZER(ram_list
.blocks
) };
83 static MemoryRegion
*system_memory
;
84 static MemoryRegion
*system_io
;
86 AddressSpace address_space_io
;
87 AddressSpace address_space_memory
;
89 MemoryRegion io_mem_rom
, io_mem_notdirty
;
90 static MemoryRegion io_mem_unassigned
;
93 #ifdef TARGET_PAGE_BITS_VARY
95 bool target_page_bits_decided
;
98 CPUTailQ cpus
= QTAILQ_HEAD_INITIALIZER(cpus
);
100 /* current CPU in the current thread. It is only valid inside
102 __thread CPUState
*current_cpu
;
103 /* 0 = Do not count executed instructions.
104 1 = Precise instruction counting.
105 2 = Adaptive rate instruction counting. */
108 uintptr_t qemu_host_page_size
;
109 intptr_t qemu_host_page_mask
;
111 bool set_preferred_target_page_bits(int bits
)
113 /* The target page size is the lowest common denominator for all
114 * the CPUs in the system, so we can only make it smaller, never
115 * larger. And we can't make it smaller once we've committed to
118 #ifdef TARGET_PAGE_BITS_VARY
119 assert(bits
>= TARGET_PAGE_BITS_MIN
);
120 if (target_page_bits
== 0 || target_page_bits
> bits
) {
121 if (target_page_bits_decided
) {
124 target_page_bits
= bits
;
130 #if !defined(CONFIG_USER_ONLY)
132 static void finalize_target_page_bits(void)
134 #ifdef TARGET_PAGE_BITS_VARY
135 if (target_page_bits
== 0) {
136 target_page_bits
= TARGET_PAGE_BITS_MIN
;
138 target_page_bits_decided
= true;
142 typedef struct PhysPageEntry PhysPageEntry
;
144 struct PhysPageEntry
{
145 /* How many bits skip to next level (in units of L2_SIZE). 0 for a leaf. */
147 /* index into phys_sections (!skip) or phys_map_nodes (skip) */
151 #define PHYS_MAP_NODE_NIL (((uint32_t)~0) >> 6)
153 /* Size of the L2 (and L3, etc) page tables. */
154 #define ADDR_SPACE_BITS 64
157 #define P_L2_SIZE (1 << P_L2_BITS)
159 #define P_L2_LEVELS (((ADDR_SPACE_BITS - TARGET_PAGE_BITS - 1) / P_L2_BITS) + 1)
161 typedef PhysPageEntry Node
[P_L2_SIZE
];
163 typedef struct PhysPageMap
{
166 unsigned sections_nb
;
167 unsigned sections_nb_alloc
;
169 unsigned nodes_nb_alloc
;
171 MemoryRegionSection
*sections
;
174 struct AddressSpaceDispatch
{
175 MemoryRegionSection
*mru_section
;
176 /* This is a multi-level map on the physical address space.
177 * The bottom level has pointers to MemoryRegionSections.
179 PhysPageEntry phys_map
;
183 #define SUBPAGE_IDX(addr) ((addr) & ~TARGET_PAGE_MASK)
184 typedef struct subpage_t
{
188 uint16_t sub_section
[];
191 #define PHYS_SECTION_UNASSIGNED 0
192 #define PHYS_SECTION_NOTDIRTY 1
193 #define PHYS_SECTION_ROM 2
194 #define PHYS_SECTION_WATCH 3
196 static void io_mem_init(void);
197 static void memory_map_init(void);
198 static void tcg_commit(MemoryListener
*listener
);
200 static MemoryRegion io_mem_watch
;
203 * CPUAddressSpace: all the information a CPU needs about an AddressSpace
204 * @cpu: the CPU whose AddressSpace this is
205 * @as: the AddressSpace itself
206 * @memory_dispatch: its dispatch pointer (cached, RCU protected)
207 * @tcg_as_listener: listener for tracking changes to the AddressSpace
209 struct CPUAddressSpace
{
212 struct AddressSpaceDispatch
*memory_dispatch
;
213 MemoryListener tcg_as_listener
;
216 struct DirtyBitmapSnapshot
{
219 unsigned long dirty
[];
224 #if !defined(CONFIG_USER_ONLY)
226 static void phys_map_node_reserve(PhysPageMap
*map
, unsigned nodes
)
228 static unsigned alloc_hint
= 16;
229 if (map
->nodes_nb
+ nodes
> map
->nodes_nb_alloc
) {
230 map
->nodes_nb_alloc
= MAX(map
->nodes_nb_alloc
, alloc_hint
);
231 map
->nodes_nb_alloc
= MAX(map
->nodes_nb_alloc
, map
->nodes_nb
+ nodes
);
232 map
->nodes
= g_renew(Node
, map
->nodes
, map
->nodes_nb_alloc
);
233 alloc_hint
= map
->nodes_nb_alloc
;
237 static uint32_t phys_map_node_alloc(PhysPageMap
*map
, bool leaf
)
244 ret
= map
->nodes_nb
++;
246 assert(ret
!= PHYS_MAP_NODE_NIL
);
247 assert(ret
!= map
->nodes_nb_alloc
);
249 e
.skip
= leaf
? 0 : 1;
250 e
.ptr
= leaf
? PHYS_SECTION_UNASSIGNED
: PHYS_MAP_NODE_NIL
;
251 for (i
= 0; i
< P_L2_SIZE
; ++i
) {
252 memcpy(&p
[i
], &e
, sizeof(e
));
257 static void phys_page_set_level(PhysPageMap
*map
, PhysPageEntry
*lp
,
258 hwaddr
*index
, hwaddr
*nb
, uint16_t leaf
,
262 hwaddr step
= (hwaddr
)1 << (level
* P_L2_BITS
);
264 if (lp
->skip
&& lp
->ptr
== PHYS_MAP_NODE_NIL
) {
265 lp
->ptr
= phys_map_node_alloc(map
, level
== 0);
267 p
= map
->nodes
[lp
->ptr
];
268 lp
= &p
[(*index
>> (level
* P_L2_BITS
)) & (P_L2_SIZE
- 1)];
270 while (*nb
&& lp
< &p
[P_L2_SIZE
]) {
271 if ((*index
& (step
- 1)) == 0 && *nb
>= step
) {
277 phys_page_set_level(map
, lp
, index
, nb
, leaf
, level
- 1);
283 static void phys_page_set(AddressSpaceDispatch
*d
,
284 hwaddr index
, hwaddr nb
,
287 /* Wildly overreserve - it doesn't matter much. */
288 phys_map_node_reserve(&d
->map
, 3 * P_L2_LEVELS
);
290 phys_page_set_level(&d
->map
, &d
->phys_map
, &index
, &nb
, leaf
, P_L2_LEVELS
- 1);
293 /* Compact a non leaf page entry. Simply detect that the entry has a single child,
294 * and update our entry so we can skip it and go directly to the destination.
296 static void phys_page_compact(PhysPageEntry
*lp
, Node
*nodes
)
298 unsigned valid_ptr
= P_L2_SIZE
;
303 if (lp
->ptr
== PHYS_MAP_NODE_NIL
) {
308 for (i
= 0; i
< P_L2_SIZE
; i
++) {
309 if (p
[i
].ptr
== PHYS_MAP_NODE_NIL
) {
316 phys_page_compact(&p
[i
], nodes
);
320 /* We can only compress if there's only one child. */
325 assert(valid_ptr
< P_L2_SIZE
);
327 /* Don't compress if it won't fit in the # of bits we have. */
328 if (lp
->skip
+ p
[valid_ptr
].skip
>= (1 << 3)) {
332 lp
->ptr
= p
[valid_ptr
].ptr
;
333 if (!p
[valid_ptr
].skip
) {
334 /* If our only child is a leaf, make this a leaf. */
335 /* By design, we should have made this node a leaf to begin with so we
336 * should never reach here.
337 * But since it's so simple to handle this, let's do it just in case we
342 lp
->skip
+= p
[valid_ptr
].skip
;
346 void address_space_dispatch_compact(AddressSpaceDispatch
*d
)
348 if (d
->phys_map
.skip
) {
349 phys_page_compact(&d
->phys_map
, d
->map
.nodes
);
353 static inline bool section_covers_addr(const MemoryRegionSection
*section
,
356 /* Memory topology clips a memory region to [0, 2^64); size.hi > 0 means
357 * the section must cover the entire address space.
359 return int128_gethi(section
->size
) ||
360 range_covers_byte(section
->offset_within_address_space
,
361 int128_getlo(section
->size
), addr
);
364 static MemoryRegionSection
*phys_page_find(AddressSpaceDispatch
*d
, hwaddr addr
)
366 PhysPageEntry lp
= d
->phys_map
, *p
;
367 Node
*nodes
= d
->map
.nodes
;
368 MemoryRegionSection
*sections
= d
->map
.sections
;
369 hwaddr index
= addr
>> TARGET_PAGE_BITS
;
372 for (i
= P_L2_LEVELS
; lp
.skip
&& (i
-= lp
.skip
) >= 0;) {
373 if (lp
.ptr
== PHYS_MAP_NODE_NIL
) {
374 return §ions
[PHYS_SECTION_UNASSIGNED
];
377 lp
= p
[(index
>> (i
* P_L2_BITS
)) & (P_L2_SIZE
- 1)];
380 if (section_covers_addr(§ions
[lp
.ptr
], addr
)) {
381 return §ions
[lp
.ptr
];
383 return §ions
[PHYS_SECTION_UNASSIGNED
];
387 /* Called from RCU critical section */
388 static MemoryRegionSection
*address_space_lookup_region(AddressSpaceDispatch
*d
,
390 bool resolve_subpage
)
392 MemoryRegionSection
*section
= atomic_read(&d
->mru_section
);
395 if (!section
|| section
== &d
->map
.sections
[PHYS_SECTION_UNASSIGNED
] ||
396 !section_covers_addr(section
, addr
)) {
397 section
= phys_page_find(d
, addr
);
398 atomic_set(&d
->mru_section
, section
);
400 if (resolve_subpage
&& section
->mr
->subpage
) {
401 subpage
= container_of(section
->mr
, subpage_t
, iomem
);
402 section
= &d
->map
.sections
[subpage
->sub_section
[SUBPAGE_IDX(addr
)]];
407 /* Called from RCU critical section */
408 static MemoryRegionSection
*
409 address_space_translate_internal(AddressSpaceDispatch
*d
, hwaddr addr
, hwaddr
*xlat
,
410 hwaddr
*plen
, bool resolve_subpage
)
412 MemoryRegionSection
*section
;
416 section
= address_space_lookup_region(d
, addr
, resolve_subpage
);
417 /* Compute offset within MemoryRegionSection */
418 addr
-= section
->offset_within_address_space
;
420 /* Compute offset within MemoryRegion */
421 *xlat
= addr
+ section
->offset_within_region
;
425 /* MMIO registers can be expected to perform full-width accesses based only
426 * on their address, without considering adjacent registers that could
427 * decode to completely different MemoryRegions. When such registers
428 * exist (e.g. I/O ports 0xcf8 and 0xcf9 on most PC chipsets), MMIO
429 * regions overlap wildly. For this reason we cannot clamp the accesses
432 * If the length is small (as is the case for address_space_ldl/stl),
433 * everything works fine. If the incoming length is large, however,
434 * the caller really has to do the clamping through memory_access_size.
436 if (memory_region_is_ram(mr
)) {
437 diff
= int128_sub(section
->size
, int128_make64(addr
));
438 *plen
= int128_get64(int128_min(diff
, int128_make64(*plen
)));
444 * address_space_translate_iommu - translate an address through an IOMMU
445 * memory region and then through the target address space.
447 * @iommu_mr: the IOMMU memory region that we start the translation from
448 * @addr: the address to be translated through the MMU
449 * @xlat: the translated address offset within the destination memory region.
450 * It cannot be %NULL.
451 * @plen_out: valid read/write length of the translated address. It
453 * @page_mask_out: page mask for the translated address. This
454 * should only be meaningful for IOMMU translated
455 * addresses, since there may be huge pages that this bit
456 * would tell. It can be %NULL if we don't care about it.
457 * @is_write: whether the translation operation is for write
458 * @is_mmio: whether this can be MMIO, set true if it can
459 * @target_as: the address space targeted by the IOMMU
460 * @attrs: transaction attributes
462 * This function is called from RCU critical section. It is the common
463 * part of flatview_do_translate and address_space_translate_cached.
465 static MemoryRegionSection
address_space_translate_iommu(IOMMUMemoryRegion
*iommu_mr
,
468 hwaddr
*page_mask_out
,
471 AddressSpace
**target_as
,
474 MemoryRegionSection
*section
;
475 hwaddr page_mask
= (hwaddr
)-1;
479 IOMMUMemoryRegionClass
*imrc
= memory_region_get_iommu_class_nocheck(iommu_mr
);
483 if (imrc
->attrs_to_index
) {
484 iommu_idx
= imrc
->attrs_to_index(iommu_mr
, attrs
);
487 iotlb
= imrc
->translate(iommu_mr
, addr
, is_write
?
488 IOMMU_WO
: IOMMU_RO
, iommu_idx
);
490 if (!(iotlb
.perm
& (1 << is_write
))) {
494 addr
= ((iotlb
.translated_addr
& ~iotlb
.addr_mask
)
495 | (addr
& iotlb
.addr_mask
));
496 page_mask
&= iotlb
.addr_mask
;
497 *plen_out
= MIN(*plen_out
, (addr
| iotlb
.addr_mask
) - addr
+ 1);
498 *target_as
= iotlb
.target_as
;
500 section
= address_space_translate_internal(
501 address_space_to_dispatch(iotlb
.target_as
), addr
, xlat
,
504 iommu_mr
= memory_region_get_iommu(section
->mr
);
505 } while (unlikely(iommu_mr
));
508 *page_mask_out
= page_mask
;
513 return (MemoryRegionSection
) { .mr
= &io_mem_unassigned
};
517 * flatview_do_translate - translate an address in FlatView
519 * @fv: the flat view that we want to translate on
520 * @addr: the address to be translated in above address space
521 * @xlat: the translated address offset within memory region. It
523 * @plen_out: valid read/write length of the translated address. It
524 * can be @NULL when we don't care about it.
525 * @page_mask_out: page mask for the translated address. This
526 * should only be meaningful for IOMMU translated
527 * addresses, since there may be huge pages that this bit
528 * would tell. It can be @NULL if we don't care about it.
529 * @is_write: whether the translation operation is for write
530 * @is_mmio: whether this can be MMIO, set true if it can
531 * @target_as: the address space targeted by the IOMMU
532 * @attrs: memory transaction attributes
534 * This function is called from RCU critical section
536 static MemoryRegionSection
flatview_do_translate(FlatView
*fv
,
540 hwaddr
*page_mask_out
,
543 AddressSpace
**target_as
,
546 MemoryRegionSection
*section
;
547 IOMMUMemoryRegion
*iommu_mr
;
548 hwaddr plen
= (hwaddr
)(-1);
554 section
= address_space_translate_internal(
555 flatview_to_dispatch(fv
), addr
, xlat
,
558 iommu_mr
= memory_region_get_iommu(section
->mr
);
559 if (unlikely(iommu_mr
)) {
560 return address_space_translate_iommu(iommu_mr
, xlat
,
561 plen_out
, page_mask_out
,
566 /* Not behind an IOMMU, use default page size. */
567 *page_mask_out
= ~TARGET_PAGE_MASK
;
573 /* Called from RCU critical section */
574 IOMMUTLBEntry
address_space_get_iotlb_entry(AddressSpace
*as
, hwaddr addr
,
575 bool is_write
, MemTxAttrs attrs
)
577 MemoryRegionSection section
;
578 hwaddr xlat
, page_mask
;
581 * This can never be MMIO, and we don't really care about plen,
584 section
= flatview_do_translate(address_space_to_flatview(as
), addr
, &xlat
,
585 NULL
, &page_mask
, is_write
, false, &as
,
588 /* Illegal translation */
589 if (section
.mr
== &io_mem_unassigned
) {
593 /* Convert memory region offset into address space offset */
594 xlat
+= section
.offset_within_address_space
-
595 section
.offset_within_region
;
597 return (IOMMUTLBEntry
) {
599 .iova
= addr
& ~page_mask
,
600 .translated_addr
= xlat
& ~page_mask
,
601 .addr_mask
= page_mask
,
602 /* IOTLBs are for DMAs, and DMA only allows on RAMs. */
607 return (IOMMUTLBEntry
) {0};
610 /* Called from RCU critical section */
611 MemoryRegion
*flatview_translate(FlatView
*fv
, hwaddr addr
, hwaddr
*xlat
,
612 hwaddr
*plen
, bool is_write
,
616 MemoryRegionSection section
;
617 AddressSpace
*as
= NULL
;
619 /* This can be MMIO, so setup MMIO bit. */
620 section
= flatview_do_translate(fv
, addr
, xlat
, plen
, NULL
,
621 is_write
, true, &as
, attrs
);
624 if (xen_enabled() && memory_access_is_direct(mr
, is_write
)) {
625 hwaddr page
= ((addr
& TARGET_PAGE_MASK
) + TARGET_PAGE_SIZE
) - addr
;
626 *plen
= MIN(page
, *plen
);
632 typedef struct TCGIOMMUNotifier
{
640 static void tcg_iommu_unmap_notify(IOMMUNotifier
*n
, IOMMUTLBEntry
*iotlb
)
642 TCGIOMMUNotifier
*notifier
= container_of(n
, TCGIOMMUNotifier
, n
);
644 if (!notifier
->active
) {
647 tlb_flush(notifier
->cpu
);
648 notifier
->active
= false;
649 /* We leave the notifier struct on the list to avoid reallocating it later.
650 * Generally the number of IOMMUs a CPU deals with will be small.
651 * In any case we can't unregister the iommu notifier from a notify
656 static void tcg_register_iommu_notifier(CPUState
*cpu
,
657 IOMMUMemoryRegion
*iommu_mr
,
660 /* Make sure this CPU has an IOMMU notifier registered for this
661 * IOMMU/IOMMU index combination, so that we can flush its TLB
662 * when the IOMMU tells us the mappings we've cached have changed.
664 MemoryRegion
*mr
= MEMORY_REGION(iommu_mr
);
665 TCGIOMMUNotifier
*notifier
;
668 for (i
= 0; i
< cpu
->iommu_notifiers
->len
; i
++) {
669 notifier
= g_array_index(cpu
->iommu_notifiers
, TCGIOMMUNotifier
*, i
);
670 if (notifier
->mr
== mr
&& notifier
->iommu_idx
== iommu_idx
) {
674 if (i
== cpu
->iommu_notifiers
->len
) {
675 /* Not found, add a new entry at the end of the array */
676 cpu
->iommu_notifiers
= g_array_set_size(cpu
->iommu_notifiers
, i
+ 1);
677 notifier
= g_new0(TCGIOMMUNotifier
, 1);
678 g_array_index(cpu
->iommu_notifiers
, TCGIOMMUNotifier
*, i
) = notifier
;
681 notifier
->iommu_idx
= iommu_idx
;
683 /* Rather than trying to register interest in the specific part
684 * of the iommu's address space that we've accessed and then
685 * expand it later as subsequent accesses touch more of it, we
686 * just register interest in the whole thing, on the assumption
687 * that iommu reconfiguration will be rare.
689 iommu_notifier_init(¬ifier
->n
,
690 tcg_iommu_unmap_notify
,
691 IOMMU_NOTIFIER_UNMAP
,
695 memory_region_register_iommu_notifier(notifier
->mr
, ¬ifier
->n
);
698 if (!notifier
->active
) {
699 notifier
->active
= true;
703 static void tcg_iommu_free_notifier_list(CPUState
*cpu
)
705 /* Destroy the CPU's notifier list */
707 TCGIOMMUNotifier
*notifier
;
709 for (i
= 0; i
< cpu
->iommu_notifiers
->len
; i
++) {
710 notifier
= g_array_index(cpu
->iommu_notifiers
, TCGIOMMUNotifier
*, i
);
711 memory_region_unregister_iommu_notifier(notifier
->mr
, ¬ifier
->n
);
714 g_array_free(cpu
->iommu_notifiers
, true);
717 /* Called from RCU critical section */
718 MemoryRegionSection
*
719 address_space_translate_for_iotlb(CPUState
*cpu
, int asidx
, hwaddr addr
,
720 hwaddr
*xlat
, hwaddr
*plen
,
721 MemTxAttrs attrs
, int *prot
)
723 MemoryRegionSection
*section
;
724 IOMMUMemoryRegion
*iommu_mr
;
725 IOMMUMemoryRegionClass
*imrc
;
728 AddressSpaceDispatch
*d
= atomic_rcu_read(&cpu
->cpu_ases
[asidx
].memory_dispatch
);
731 section
= address_space_translate_internal(d
, addr
, &addr
, plen
, false);
733 iommu_mr
= memory_region_get_iommu(section
->mr
);
738 imrc
= memory_region_get_iommu_class_nocheck(iommu_mr
);
740 iommu_idx
= imrc
->attrs_to_index(iommu_mr
, attrs
);
741 tcg_register_iommu_notifier(cpu
, iommu_mr
, iommu_idx
);
742 /* We need all the permissions, so pass IOMMU_NONE so the IOMMU
743 * doesn't short-cut its translation table walk.
745 iotlb
= imrc
->translate(iommu_mr
, addr
, IOMMU_NONE
, iommu_idx
);
746 addr
= ((iotlb
.translated_addr
& ~iotlb
.addr_mask
)
747 | (addr
& iotlb
.addr_mask
));
748 /* Update the caller's prot bits to remove permissions the IOMMU
749 * is giving us a failure response for. If we get down to no
750 * permissions left at all we can give up now.
752 if (!(iotlb
.perm
& IOMMU_RO
)) {
753 *prot
&= ~(PAGE_READ
| PAGE_EXEC
);
755 if (!(iotlb
.perm
& IOMMU_WO
)) {
756 *prot
&= ~PAGE_WRITE
;
763 d
= flatview_to_dispatch(address_space_to_flatview(iotlb
.target_as
));
766 assert(!memory_region_is_iommu(section
->mr
));
771 return &d
->map
.sections
[PHYS_SECTION_UNASSIGNED
];
775 #if !defined(CONFIG_USER_ONLY)
777 static int cpu_common_post_load(void *opaque
, int version_id
)
779 CPUState
*cpu
= opaque
;
781 /* 0x01 was CPU_INTERRUPT_EXIT. This line can be removed when the
782 version_id is increased. */
783 cpu
->interrupt_request
&= ~0x01;
786 /* loadvm has just updated the content of RAM, bypassing the
787 * usual mechanisms that ensure we flush TBs for writes to
788 * memory we've translated code from. So we must flush all TBs,
789 * which will now be stale.
796 static int cpu_common_pre_load(void *opaque
)
798 CPUState
*cpu
= opaque
;
800 cpu
->exception_index
= -1;
805 static bool cpu_common_exception_index_needed(void *opaque
)
807 CPUState
*cpu
= opaque
;
809 return tcg_enabled() && cpu
->exception_index
!= -1;
812 static const VMStateDescription vmstate_cpu_common_exception_index
= {
813 .name
= "cpu_common/exception_index",
815 .minimum_version_id
= 1,
816 .needed
= cpu_common_exception_index_needed
,
817 .fields
= (VMStateField
[]) {
818 VMSTATE_INT32(exception_index
, CPUState
),
819 VMSTATE_END_OF_LIST()
823 static bool cpu_common_crash_occurred_needed(void *opaque
)
825 CPUState
*cpu
= opaque
;
827 return cpu
->crash_occurred
;
830 static const VMStateDescription vmstate_cpu_common_crash_occurred
= {
831 .name
= "cpu_common/crash_occurred",
833 .minimum_version_id
= 1,
834 .needed
= cpu_common_crash_occurred_needed
,
835 .fields
= (VMStateField
[]) {
836 VMSTATE_BOOL(crash_occurred
, CPUState
),
837 VMSTATE_END_OF_LIST()
841 const VMStateDescription vmstate_cpu_common
= {
842 .name
= "cpu_common",
844 .minimum_version_id
= 1,
845 .pre_load
= cpu_common_pre_load
,
846 .post_load
= cpu_common_post_load
,
847 .fields
= (VMStateField
[]) {
848 VMSTATE_UINT32(halted
, CPUState
),
849 VMSTATE_UINT32(interrupt_request
, CPUState
),
850 VMSTATE_END_OF_LIST()
852 .subsections
= (const VMStateDescription
*[]) {
853 &vmstate_cpu_common_exception_index
,
854 &vmstate_cpu_common_crash_occurred
,
861 CPUState
*qemu_get_cpu(int index
)
866 if (cpu
->cpu_index
== index
) {
874 #if !defined(CONFIG_USER_ONLY)
875 void cpu_address_space_init(CPUState
*cpu
, int asidx
,
876 const char *prefix
, MemoryRegion
*mr
)
878 CPUAddressSpace
*newas
;
879 AddressSpace
*as
= g_new0(AddressSpace
, 1);
883 as_name
= g_strdup_printf("%s-%d", prefix
, cpu
->cpu_index
);
884 address_space_init(as
, mr
, as_name
);
887 /* Target code should have set num_ases before calling us */
888 assert(asidx
< cpu
->num_ases
);
891 /* address space 0 gets the convenience alias */
895 /* KVM cannot currently support multiple address spaces. */
896 assert(asidx
== 0 || !kvm_enabled());
898 if (!cpu
->cpu_ases
) {
899 cpu
->cpu_ases
= g_new0(CPUAddressSpace
, cpu
->num_ases
);
902 newas
= &cpu
->cpu_ases
[asidx
];
906 newas
->tcg_as_listener
.commit
= tcg_commit
;
907 memory_listener_register(&newas
->tcg_as_listener
, as
);
911 AddressSpace
*cpu_get_address_space(CPUState
*cpu
, int asidx
)
913 /* Return the AddressSpace corresponding to the specified index */
914 return cpu
->cpu_ases
[asidx
].as
;
918 void cpu_exec_unrealizefn(CPUState
*cpu
)
920 CPUClass
*cc
= CPU_GET_CLASS(cpu
);
922 cpu_list_remove(cpu
);
924 if (cc
->vmsd
!= NULL
) {
925 vmstate_unregister(NULL
, cc
->vmsd
, cpu
);
927 if (qdev_get_vmsd(DEVICE(cpu
)) == NULL
) {
928 vmstate_unregister(NULL
, &vmstate_cpu_common
, cpu
);
930 #ifndef CONFIG_USER_ONLY
931 tcg_iommu_free_notifier_list(cpu
);
935 Property cpu_common_props
[] = {
936 #ifndef CONFIG_USER_ONLY
937 /* Create a memory property for softmmu CPU object,
938 * so users can wire up its memory. (This can't go in qom/cpu.c
939 * because that file is compiled only once for both user-mode
940 * and system builds.) The default if no link is set up is to use
941 * the system address space.
943 DEFINE_PROP_LINK("memory", CPUState
, memory
, TYPE_MEMORY_REGION
,
946 DEFINE_PROP_END_OF_LIST(),
949 void cpu_exec_initfn(CPUState
*cpu
)
954 #ifndef CONFIG_USER_ONLY
955 cpu
->thread_id
= qemu_get_thread_id();
956 cpu
->memory
= system_memory
;
957 object_ref(OBJECT(cpu
->memory
));
961 void cpu_exec_realizefn(CPUState
*cpu
, Error
**errp
)
963 CPUClass
*cc
= CPU_GET_CLASS(cpu
);
964 static bool tcg_target_initialized
;
968 if (tcg_enabled() && !tcg_target_initialized
) {
969 tcg_target_initialized
= true;
970 cc
->tcg_initialize();
974 #ifndef CONFIG_USER_ONLY
975 if (qdev_get_vmsd(DEVICE(cpu
)) == NULL
) {
976 vmstate_register(NULL
, cpu
->cpu_index
, &vmstate_cpu_common
, cpu
);
978 if (cc
->vmsd
!= NULL
) {
979 vmstate_register(NULL
, cpu
->cpu_index
, cc
->vmsd
, cpu
);
982 cpu
->iommu_notifiers
= g_array_new(false, true, sizeof(TCGIOMMUNotifier
*));
986 const char *parse_cpu_model(const char *cpu_model
)
990 gchar
**model_pieces
;
991 const char *cpu_type
;
993 model_pieces
= g_strsplit(cpu_model
, ",", 2);
995 oc
= cpu_class_by_name(CPU_RESOLVING_TYPE
, model_pieces
[0]);
997 error_report("unable to find CPU model '%s'", model_pieces
[0]);
998 g_strfreev(model_pieces
);
1002 cpu_type
= object_class_get_name(oc
);
1004 cc
->parse_features(cpu_type
, model_pieces
[1], &error_fatal
);
1005 g_strfreev(model_pieces
);
1009 #if defined(CONFIG_USER_ONLY)
1010 void tb_invalidate_phys_addr(target_ulong addr
)
1013 tb_invalidate_phys_page_range(addr
, addr
+ 1, 0);
1017 static void breakpoint_invalidate(CPUState
*cpu
, target_ulong pc
)
1019 tb_invalidate_phys_addr(pc
);
1022 void tb_invalidate_phys_addr(AddressSpace
*as
, hwaddr addr
, MemTxAttrs attrs
)
1024 ram_addr_t ram_addr
;
1028 if (!tcg_enabled()) {
1033 mr
= address_space_translate(as
, addr
, &addr
, &l
, false, attrs
);
1034 if (!(memory_region_is_ram(mr
)
1035 || memory_region_is_romd(mr
))) {
1039 ram_addr
= memory_region_get_ram_addr(mr
) + addr
;
1040 tb_invalidate_phys_page_range(ram_addr
, ram_addr
+ 1, 0);
1044 static void breakpoint_invalidate(CPUState
*cpu
, target_ulong pc
)
1047 hwaddr phys
= cpu_get_phys_page_attrs_debug(cpu
, pc
, &attrs
);
1048 int asidx
= cpu_asidx_from_attrs(cpu
, attrs
);
1050 /* Locks grabbed by tb_invalidate_phys_addr */
1051 tb_invalidate_phys_addr(cpu
->cpu_ases
[asidx
].as
,
1052 phys
| (pc
& ~TARGET_PAGE_MASK
), attrs
);
1057 #if defined(CONFIG_USER_ONLY)
1058 void cpu_watchpoint_remove_all(CPUState
*cpu
, int mask
)
1063 int cpu_watchpoint_remove(CPUState
*cpu
, vaddr addr
, vaddr len
,
1069 void cpu_watchpoint_remove_by_ref(CPUState
*cpu
, CPUWatchpoint
*watchpoint
)
1073 int cpu_watchpoint_insert(CPUState
*cpu
, vaddr addr
, vaddr len
,
1074 int flags
, CPUWatchpoint
**watchpoint
)
1079 /* Add a watchpoint. */
1080 int cpu_watchpoint_insert(CPUState
*cpu
, vaddr addr
, vaddr len
,
1081 int flags
, CPUWatchpoint
**watchpoint
)
1085 /* forbid ranges which are empty or run off the end of the address space */
1086 if (len
== 0 || (addr
+ len
- 1) < addr
) {
1087 error_report("tried to set invalid watchpoint at %"
1088 VADDR_PRIx
", len=%" VADDR_PRIu
, addr
, len
);
1091 wp
= g_malloc(sizeof(*wp
));
1097 /* keep all GDB-injected watchpoints in front */
1098 if (flags
& BP_GDB
) {
1099 QTAILQ_INSERT_HEAD(&cpu
->watchpoints
, wp
, entry
);
1101 QTAILQ_INSERT_TAIL(&cpu
->watchpoints
, wp
, entry
);
1104 tlb_flush_page(cpu
, addr
);
1111 /* Remove a specific watchpoint. */
1112 int cpu_watchpoint_remove(CPUState
*cpu
, vaddr addr
, vaddr len
,
1117 QTAILQ_FOREACH(wp
, &cpu
->watchpoints
, entry
) {
1118 if (addr
== wp
->vaddr
&& len
== wp
->len
1119 && flags
== (wp
->flags
& ~BP_WATCHPOINT_HIT
)) {
1120 cpu_watchpoint_remove_by_ref(cpu
, wp
);
1127 /* Remove a specific watchpoint by reference. */
1128 void cpu_watchpoint_remove_by_ref(CPUState
*cpu
, CPUWatchpoint
*watchpoint
)
1130 QTAILQ_REMOVE(&cpu
->watchpoints
, watchpoint
, entry
);
1132 tlb_flush_page(cpu
, watchpoint
->vaddr
);
1137 /* Remove all matching watchpoints. */
1138 void cpu_watchpoint_remove_all(CPUState
*cpu
, int mask
)
1140 CPUWatchpoint
*wp
, *next
;
1142 QTAILQ_FOREACH_SAFE(wp
, &cpu
->watchpoints
, entry
, next
) {
1143 if (wp
->flags
& mask
) {
1144 cpu_watchpoint_remove_by_ref(cpu
, wp
);
1149 /* Return true if this watchpoint address matches the specified
1150 * access (ie the address range covered by the watchpoint overlaps
1151 * partially or completely with the address range covered by the
1154 static inline bool cpu_watchpoint_address_matches(CPUWatchpoint
*wp
,
1158 /* We know the lengths are non-zero, but a little caution is
1159 * required to avoid errors in the case where the range ends
1160 * exactly at the top of the address space and so addr + len
1161 * wraps round to zero.
1163 vaddr wpend
= wp
->vaddr
+ wp
->len
- 1;
1164 vaddr addrend
= addr
+ len
- 1;
1166 return !(addr
> wpend
|| wp
->vaddr
> addrend
);
1171 /* Add a breakpoint. */
1172 int cpu_breakpoint_insert(CPUState
*cpu
, vaddr pc
, int flags
,
1173 CPUBreakpoint
**breakpoint
)
1177 bp
= g_malloc(sizeof(*bp
));
1182 /* keep all GDB-injected breakpoints in front */
1183 if (flags
& BP_GDB
) {
1184 QTAILQ_INSERT_HEAD(&cpu
->breakpoints
, bp
, entry
);
1186 QTAILQ_INSERT_TAIL(&cpu
->breakpoints
, bp
, entry
);
1189 breakpoint_invalidate(cpu
, pc
);
1197 /* Remove a specific breakpoint. */
1198 int cpu_breakpoint_remove(CPUState
*cpu
, vaddr pc
, int flags
)
1202 QTAILQ_FOREACH(bp
, &cpu
->breakpoints
, entry
) {
1203 if (bp
->pc
== pc
&& bp
->flags
== flags
) {
1204 cpu_breakpoint_remove_by_ref(cpu
, bp
);
1211 /* Remove a specific breakpoint by reference. */
1212 void cpu_breakpoint_remove_by_ref(CPUState
*cpu
, CPUBreakpoint
*breakpoint
)
1214 QTAILQ_REMOVE(&cpu
->breakpoints
, breakpoint
, entry
);
1216 breakpoint_invalidate(cpu
, breakpoint
->pc
);
1221 /* Remove all matching breakpoints. */
1222 void cpu_breakpoint_remove_all(CPUState
*cpu
, int mask
)
1224 CPUBreakpoint
*bp
, *next
;
1226 QTAILQ_FOREACH_SAFE(bp
, &cpu
->breakpoints
, entry
, next
) {
1227 if (bp
->flags
& mask
) {
1228 cpu_breakpoint_remove_by_ref(cpu
, bp
);
1233 /* enable or disable single step mode. EXCP_DEBUG is returned by the
1234 CPU loop after each instruction */
1235 void cpu_single_step(CPUState
*cpu
, int enabled
)
1237 if (cpu
->singlestep_enabled
!= enabled
) {
1238 cpu
->singlestep_enabled
= enabled
;
1239 if (kvm_enabled()) {
1240 kvm_update_guest_debug(cpu
, 0);
1242 /* must flush all the translated code to avoid inconsistencies */
1243 /* XXX: only flush what is necessary */
1249 void cpu_abort(CPUState
*cpu
, const char *fmt
, ...)
1256 fprintf(stderr
, "qemu: fatal: ");
1257 vfprintf(stderr
, fmt
, ap
);
1258 fprintf(stderr
, "\n");
1259 cpu_dump_state(cpu
, stderr
, CPU_DUMP_FPU
| CPU_DUMP_CCOP
);
1260 if (qemu_log_separate()) {
1262 qemu_log("qemu: fatal: ");
1263 qemu_log_vprintf(fmt
, ap2
);
1265 log_cpu_state(cpu
, CPU_DUMP_FPU
| CPU_DUMP_CCOP
);
1273 #if defined(CONFIG_USER_ONLY)
1275 struct sigaction act
;
1276 sigfillset(&act
.sa_mask
);
1277 act
.sa_handler
= SIG_DFL
;
1279 sigaction(SIGABRT
, &act
, NULL
);
1285 #if !defined(CONFIG_USER_ONLY)
1286 /* Called from RCU critical section */
1287 static RAMBlock
*qemu_get_ram_block(ram_addr_t addr
)
1291 block
= atomic_rcu_read(&ram_list
.mru_block
);
1292 if (block
&& addr
- block
->offset
< block
->max_length
) {
1295 RAMBLOCK_FOREACH(block
) {
1296 if (addr
- block
->offset
< block
->max_length
) {
1301 fprintf(stderr
, "Bad ram offset %" PRIx64
"\n", (uint64_t)addr
);
1305 /* It is safe to write mru_block outside the iothread lock. This
1310 * xxx removed from list
1314 * call_rcu(reclaim_ramblock, xxx);
1317 * atomic_rcu_set is not needed here. The block was already published
1318 * when it was placed into the list. Here we're just making an extra
1319 * copy of the pointer.
1321 ram_list
.mru_block
= block
;
1325 static void tlb_reset_dirty_range_all(ram_addr_t start
, ram_addr_t length
)
1332 assert(tcg_enabled());
1333 end
= TARGET_PAGE_ALIGN(start
+ length
);
1334 start
&= TARGET_PAGE_MASK
;
1337 block
= qemu_get_ram_block(start
);
1338 assert(block
== qemu_get_ram_block(end
- 1));
1339 start1
= (uintptr_t)ramblock_ptr(block
, start
- block
->offset
);
1341 tlb_reset_dirty(cpu
, start1
, length
);
1346 /* Note: start and end must be within the same ram block. */
1347 bool cpu_physical_memory_test_and_clear_dirty(ram_addr_t start
,
1351 DirtyMemoryBlocks
*blocks
;
1352 unsigned long end
, page
;
1359 end
= TARGET_PAGE_ALIGN(start
+ length
) >> TARGET_PAGE_BITS
;
1360 page
= start
>> TARGET_PAGE_BITS
;
1364 blocks
= atomic_rcu_read(&ram_list
.dirty_memory
[client
]);
1366 while (page
< end
) {
1367 unsigned long idx
= page
/ DIRTY_MEMORY_BLOCK_SIZE
;
1368 unsigned long offset
= page
% DIRTY_MEMORY_BLOCK_SIZE
;
1369 unsigned long num
= MIN(end
- page
, DIRTY_MEMORY_BLOCK_SIZE
- offset
);
1371 dirty
|= bitmap_test_and_clear_atomic(blocks
->blocks
[idx
],
1378 if (dirty
&& tcg_enabled()) {
1379 tlb_reset_dirty_range_all(start
, length
);
1385 DirtyBitmapSnapshot
*cpu_physical_memory_snapshot_and_clear_dirty
1386 (ram_addr_t start
, ram_addr_t length
, unsigned client
)
1388 DirtyMemoryBlocks
*blocks
;
1389 unsigned long align
= 1UL << (TARGET_PAGE_BITS
+ BITS_PER_LEVEL
);
1390 ram_addr_t first
= QEMU_ALIGN_DOWN(start
, align
);
1391 ram_addr_t last
= QEMU_ALIGN_UP(start
+ length
, align
);
1392 DirtyBitmapSnapshot
*snap
;
1393 unsigned long page
, end
, dest
;
1395 snap
= g_malloc0(sizeof(*snap
) +
1396 ((last
- first
) >> (TARGET_PAGE_BITS
+ 3)));
1397 snap
->start
= first
;
1400 page
= first
>> TARGET_PAGE_BITS
;
1401 end
= last
>> TARGET_PAGE_BITS
;
1406 blocks
= atomic_rcu_read(&ram_list
.dirty_memory
[client
]);
1408 while (page
< end
) {
1409 unsigned long idx
= page
/ DIRTY_MEMORY_BLOCK_SIZE
;
1410 unsigned long offset
= page
% DIRTY_MEMORY_BLOCK_SIZE
;
1411 unsigned long num
= MIN(end
- page
, DIRTY_MEMORY_BLOCK_SIZE
- offset
);
1413 assert(QEMU_IS_ALIGNED(offset
, (1 << BITS_PER_LEVEL
)));
1414 assert(QEMU_IS_ALIGNED(num
, (1 << BITS_PER_LEVEL
)));
1415 offset
>>= BITS_PER_LEVEL
;
1417 bitmap_copy_and_clear_atomic(snap
->dirty
+ dest
,
1418 blocks
->blocks
[idx
] + offset
,
1421 dest
+= num
>> BITS_PER_LEVEL
;
1426 if (tcg_enabled()) {
1427 tlb_reset_dirty_range_all(start
, length
);
1433 bool cpu_physical_memory_snapshot_get_dirty(DirtyBitmapSnapshot
*snap
,
1437 unsigned long page
, end
;
1439 assert(start
>= snap
->start
);
1440 assert(start
+ length
<= snap
->end
);
1442 end
= TARGET_PAGE_ALIGN(start
+ length
- snap
->start
) >> TARGET_PAGE_BITS
;
1443 page
= (start
- snap
->start
) >> TARGET_PAGE_BITS
;
1445 while (page
< end
) {
1446 if (test_bit(page
, snap
->dirty
)) {
1454 /* Called from RCU critical section */
1455 hwaddr
memory_region_section_get_iotlb(CPUState
*cpu
,
1456 MemoryRegionSection
*section
,
1458 hwaddr paddr
, hwaddr xlat
,
1460 target_ulong
*address
)
1465 if (memory_region_is_ram(section
->mr
)) {
1467 iotlb
= memory_region_get_ram_addr(section
->mr
) + xlat
;
1468 if (!section
->readonly
) {
1469 iotlb
|= PHYS_SECTION_NOTDIRTY
;
1471 iotlb
|= PHYS_SECTION_ROM
;
1474 AddressSpaceDispatch
*d
;
1476 d
= flatview_to_dispatch(section
->fv
);
1477 iotlb
= section
- d
->map
.sections
;
1481 /* Make accesses to pages with watchpoints go via the
1482 watchpoint trap routines. */
1483 QTAILQ_FOREACH(wp
, &cpu
->watchpoints
, entry
) {
1484 if (cpu_watchpoint_address_matches(wp
, vaddr
, TARGET_PAGE_SIZE
)) {
1485 /* Avoid trapping reads of pages with a write breakpoint. */
1486 if ((prot
& PAGE_WRITE
) || (wp
->flags
& BP_MEM_READ
)) {
1487 iotlb
= PHYS_SECTION_WATCH
+ paddr
;
1488 *address
|= TLB_MMIO
;
1496 #endif /* defined(CONFIG_USER_ONLY) */
1498 #if !defined(CONFIG_USER_ONLY)
1500 static int subpage_register (subpage_t
*mmio
, uint32_t start
, uint32_t end
,
1502 static subpage_t
*subpage_init(FlatView
*fv
, hwaddr base
);
1504 static void *(*phys_mem_alloc
)(size_t size
, uint64_t *align
, bool shared
) =
1505 qemu_anon_ram_alloc
;
1508 * Set a custom physical guest memory alloator.
1509 * Accelerators with unusual needs may need this. Hopefully, we can
1510 * get rid of it eventually.
1512 void phys_mem_set_alloc(void *(*alloc
)(size_t, uint64_t *align
, bool shared
))
1514 phys_mem_alloc
= alloc
;
1517 static uint16_t phys_section_add(PhysPageMap
*map
,
1518 MemoryRegionSection
*section
)
1520 /* The physical section number is ORed with a page-aligned
1521 * pointer to produce the iotlb entries. Thus it should
1522 * never overflow into the page-aligned value.
1524 assert(map
->sections_nb
< TARGET_PAGE_SIZE
);
1526 if (map
->sections_nb
== map
->sections_nb_alloc
) {
1527 map
->sections_nb_alloc
= MAX(map
->sections_nb_alloc
* 2, 16);
1528 map
->sections
= g_renew(MemoryRegionSection
, map
->sections
,
1529 map
->sections_nb_alloc
);
1531 map
->sections
[map
->sections_nb
] = *section
;
1532 memory_region_ref(section
->mr
);
1533 return map
->sections_nb
++;
1536 static void phys_section_destroy(MemoryRegion
*mr
)
1538 bool have_sub_page
= mr
->subpage
;
1540 memory_region_unref(mr
);
1542 if (have_sub_page
) {
1543 subpage_t
*subpage
= container_of(mr
, subpage_t
, iomem
);
1544 object_unref(OBJECT(&subpage
->iomem
));
1549 static void phys_sections_free(PhysPageMap
*map
)
1551 while (map
->sections_nb
> 0) {
1552 MemoryRegionSection
*section
= &map
->sections
[--map
->sections_nb
];
1553 phys_section_destroy(section
->mr
);
1555 g_free(map
->sections
);
1559 static void register_subpage(FlatView
*fv
, MemoryRegionSection
*section
)
1561 AddressSpaceDispatch
*d
= flatview_to_dispatch(fv
);
1563 hwaddr base
= section
->offset_within_address_space
1565 MemoryRegionSection
*existing
= phys_page_find(d
, base
);
1566 MemoryRegionSection subsection
= {
1567 .offset_within_address_space
= base
,
1568 .size
= int128_make64(TARGET_PAGE_SIZE
),
1572 assert(existing
->mr
->subpage
|| existing
->mr
== &io_mem_unassigned
);
1574 if (!(existing
->mr
->subpage
)) {
1575 subpage
= subpage_init(fv
, base
);
1577 subsection
.mr
= &subpage
->iomem
;
1578 phys_page_set(d
, base
>> TARGET_PAGE_BITS
, 1,
1579 phys_section_add(&d
->map
, &subsection
));
1581 subpage
= container_of(existing
->mr
, subpage_t
, iomem
);
1583 start
= section
->offset_within_address_space
& ~TARGET_PAGE_MASK
;
1584 end
= start
+ int128_get64(section
->size
) - 1;
1585 subpage_register(subpage
, start
, end
,
1586 phys_section_add(&d
->map
, section
));
1590 static void register_multipage(FlatView
*fv
,
1591 MemoryRegionSection
*section
)
1593 AddressSpaceDispatch
*d
= flatview_to_dispatch(fv
);
1594 hwaddr start_addr
= section
->offset_within_address_space
;
1595 uint16_t section_index
= phys_section_add(&d
->map
, section
);
1596 uint64_t num_pages
= int128_get64(int128_rshift(section
->size
,
1600 phys_page_set(d
, start_addr
>> TARGET_PAGE_BITS
, num_pages
, section_index
);
1604 * The range in *section* may look like this:
1608 * where s stands for subpage and P for page.
1610 void flatview_add_to_dispatch(FlatView
*fv
, MemoryRegionSection
*section
)
1612 MemoryRegionSection remain
= *section
;
1613 Int128 page_size
= int128_make64(TARGET_PAGE_SIZE
);
1615 /* register first subpage */
1616 if (remain
.offset_within_address_space
& ~TARGET_PAGE_MASK
) {
1617 uint64_t left
= TARGET_PAGE_ALIGN(remain
.offset_within_address_space
)
1618 - remain
.offset_within_address_space
;
1620 MemoryRegionSection now
= remain
;
1621 now
.size
= int128_min(int128_make64(left
), now
.size
);
1622 register_subpage(fv
, &now
);
1623 if (int128_eq(remain
.size
, now
.size
)) {
1626 remain
.size
= int128_sub(remain
.size
, now
.size
);
1627 remain
.offset_within_address_space
+= int128_get64(now
.size
);
1628 remain
.offset_within_region
+= int128_get64(now
.size
);
1631 /* register whole pages */
1632 if (int128_ge(remain
.size
, page_size
)) {
1633 MemoryRegionSection now
= remain
;
1634 now
.size
= int128_and(now
.size
, int128_neg(page_size
));
1635 register_multipage(fv
, &now
);
1636 if (int128_eq(remain
.size
, now
.size
)) {
1639 remain
.size
= int128_sub(remain
.size
, now
.size
);
1640 remain
.offset_within_address_space
+= int128_get64(now
.size
);
1641 remain
.offset_within_region
+= int128_get64(now
.size
);
1644 /* register last subpage */
1645 register_subpage(fv
, &remain
);
1648 void qemu_flush_coalesced_mmio_buffer(void)
1651 kvm_flush_coalesced_mmio_buffer();
1654 void qemu_mutex_lock_ramlist(void)
1656 qemu_mutex_lock(&ram_list
.mutex
);
1659 void qemu_mutex_unlock_ramlist(void)
1661 qemu_mutex_unlock(&ram_list
.mutex
);
1664 void ram_block_dump(Monitor
*mon
)
1670 monitor_printf(mon
, "%24s %8s %18s %18s %18s\n",
1671 "Block Name", "PSize", "Offset", "Used", "Total");
1672 RAMBLOCK_FOREACH(block
) {
1673 psize
= size_to_str(block
->page_size
);
1674 monitor_printf(mon
, "%24s %8s 0x%016" PRIx64
" 0x%016" PRIx64
1675 " 0x%016" PRIx64
"\n", block
->idstr
, psize
,
1676 (uint64_t)block
->offset
,
1677 (uint64_t)block
->used_length
,
1678 (uint64_t)block
->max_length
);
1686 * FIXME TOCTTOU: this iterates over memory backends' mem-path, which
1687 * may or may not name the same files / on the same filesystem now as
1688 * when we actually open and map them. Iterate over the file
1689 * descriptors instead, and use qemu_fd_getpagesize().
1691 static int find_min_backend_pagesize(Object
*obj
, void *opaque
)
1693 long *hpsize_min
= opaque
;
1695 if (object_dynamic_cast(obj
, TYPE_MEMORY_BACKEND
)) {
1696 HostMemoryBackend
*backend
= MEMORY_BACKEND(obj
);
1697 long hpsize
= host_memory_backend_pagesize(backend
);
1699 if (host_memory_backend_is_mapped(backend
) && (hpsize
< *hpsize_min
)) {
1700 *hpsize_min
= hpsize
;
1707 static int find_max_backend_pagesize(Object
*obj
, void *opaque
)
1709 long *hpsize_max
= opaque
;
1711 if (object_dynamic_cast(obj
, TYPE_MEMORY_BACKEND
)) {
1712 HostMemoryBackend
*backend
= MEMORY_BACKEND(obj
);
1713 long hpsize
= host_memory_backend_pagesize(backend
);
1715 if (host_memory_backend_is_mapped(backend
) && (hpsize
> *hpsize_max
)) {
1716 *hpsize_max
= hpsize
;
1724 * TODO: We assume right now that all mapped host memory backends are
1725 * used as RAM, however some might be used for different purposes.
1727 long qemu_minrampagesize(void)
1729 long hpsize
= LONG_MAX
;
1730 long mainrampagesize
;
1731 Object
*memdev_root
;
1733 mainrampagesize
= qemu_mempath_getpagesize(mem_path
);
1735 /* it's possible we have memory-backend objects with
1736 * hugepage-backed RAM. these may get mapped into system
1737 * address space via -numa parameters or memory hotplug
1738 * hooks. we want to take these into account, but we
1739 * also want to make sure these supported hugepage
1740 * sizes are applicable across the entire range of memory
1741 * we may boot from, so we take the min across all
1742 * backends, and assume normal pages in cases where a
1743 * backend isn't backed by hugepages.
1745 memdev_root
= object_resolve_path("/objects", NULL
);
1747 object_child_foreach(memdev_root
, find_min_backend_pagesize
, &hpsize
);
1749 if (hpsize
== LONG_MAX
) {
1750 /* No additional memory regions found ==> Report main RAM page size */
1751 return mainrampagesize
;
1754 /* If NUMA is disabled or the NUMA nodes are not backed with a
1755 * memory-backend, then there is at least one node using "normal" RAM,
1756 * so if its page size is smaller we have got to report that size instead.
1758 if (hpsize
> mainrampagesize
&&
1759 (nb_numa_nodes
== 0 || numa_info
[0].node_memdev
== NULL
)) {
1762 error_report("Huge page support disabled (n/a for main memory).");
1765 return mainrampagesize
;
1771 long qemu_maxrampagesize(void)
1773 long pagesize
= qemu_mempath_getpagesize(mem_path
);
1774 Object
*memdev_root
= object_resolve_path("/objects", NULL
);
1777 object_child_foreach(memdev_root
, find_max_backend_pagesize
,
1783 long qemu_minrampagesize(void)
1785 return getpagesize();
1787 long qemu_maxrampagesize(void)
1789 return getpagesize();
1794 static int64_t get_file_size(int fd
)
1796 int64_t size
= lseek(fd
, 0, SEEK_END
);
1803 static int file_ram_open(const char *path
,
1804 const char *region_name
,
1809 char *sanitized_name
;
1815 fd
= open(path
, O_RDWR
);
1817 /* @path names an existing file, use it */
1820 if (errno
== ENOENT
) {
1821 /* @path names a file that doesn't exist, create it */
1822 fd
= open(path
, O_RDWR
| O_CREAT
| O_EXCL
, 0644);
1827 } else if (errno
== EISDIR
) {
1828 /* @path names a directory, create a file there */
1829 /* Make name safe to use with mkstemp by replacing '/' with '_'. */
1830 sanitized_name
= g_strdup(region_name
);
1831 for (c
= sanitized_name
; *c
!= '\0'; c
++) {
1837 filename
= g_strdup_printf("%s/qemu_back_mem.%s.XXXXXX", path
,
1839 g_free(sanitized_name
);
1841 fd
= mkstemp(filename
);
1849 if (errno
!= EEXIST
&& errno
!= EINTR
) {
1850 error_setg_errno(errp
, errno
,
1851 "can't open backing store %s for guest RAM",
1856 * Try again on EINTR and EEXIST. The latter happens when
1857 * something else creates the file between our two open().
1864 static void *file_ram_alloc(RAMBlock
*block
,
1872 block
->page_size
= qemu_fd_getpagesize(fd
);
1873 if (block
->mr
->align
% block
->page_size
) {
1874 error_setg(errp
, "alignment 0x%" PRIx64
1875 " must be multiples of page size 0x%zx",
1876 block
->mr
->align
, block
->page_size
);
1878 } else if (block
->mr
->align
&& !is_power_of_2(block
->mr
->align
)) {
1879 error_setg(errp
, "alignment 0x%" PRIx64
1880 " must be a power of two", block
->mr
->align
);
1883 block
->mr
->align
= MAX(block
->page_size
, block
->mr
->align
);
1884 #if defined(__s390x__)
1885 if (kvm_enabled()) {
1886 block
->mr
->align
= MAX(block
->mr
->align
, QEMU_VMALLOC_ALIGN
);
1890 if (memory
< block
->page_size
) {
1891 error_setg(errp
, "memory size 0x" RAM_ADDR_FMT
" must be equal to "
1892 "or larger than page size 0x%zx",
1893 memory
, block
->page_size
);
1897 memory
= ROUND_UP(memory
, block
->page_size
);
1900 * ftruncate is not supported by hugetlbfs in older
1901 * hosts, so don't bother bailing out on errors.
1902 * If anything goes wrong with it under other filesystems,
1905 * Do not truncate the non-empty backend file to avoid corrupting
1906 * the existing data in the file. Disabling shrinking is not
1907 * enough. For example, the current vNVDIMM implementation stores
1908 * the guest NVDIMM labels at the end of the backend file. If the
1909 * backend file is later extended, QEMU will not be able to find
1910 * those labels. Therefore, extending the non-empty backend file
1911 * is disabled as well.
1913 if (truncate
&& ftruncate(fd
, memory
)) {
1914 perror("ftruncate");
1917 area
= qemu_ram_mmap(fd
, memory
, block
->mr
->align
,
1918 block
->flags
& RAM_SHARED
);
1919 if (area
== MAP_FAILED
) {
1920 error_setg_errno(errp
, errno
,
1921 "unable to map backing store for guest RAM");
1926 os_mem_prealloc(fd
, area
, memory
, smp_cpus
, errp
);
1927 if (errp
&& *errp
) {
1928 qemu_ram_munmap(fd
, area
, memory
);
1938 /* Allocate space within the ram_addr_t space that governs the
1940 * Called with the ramlist lock held.
1942 static ram_addr_t
find_ram_offset(ram_addr_t size
)
1944 RAMBlock
*block
, *next_block
;
1945 ram_addr_t offset
= RAM_ADDR_MAX
, mingap
= RAM_ADDR_MAX
;
1947 assert(size
!= 0); /* it would hand out same offset multiple times */
1949 if (QLIST_EMPTY_RCU(&ram_list
.blocks
)) {
1953 RAMBLOCK_FOREACH(block
) {
1954 ram_addr_t candidate
, next
= RAM_ADDR_MAX
;
1956 /* Align blocks to start on a 'long' in the bitmap
1957 * which makes the bitmap sync'ing take the fast path.
1959 candidate
= block
->offset
+ block
->max_length
;
1960 candidate
= ROUND_UP(candidate
, BITS_PER_LONG
<< TARGET_PAGE_BITS
);
1962 /* Search for the closest following block
1965 RAMBLOCK_FOREACH(next_block
) {
1966 if (next_block
->offset
>= candidate
) {
1967 next
= MIN(next
, next_block
->offset
);
1971 /* If it fits remember our place and remember the size
1972 * of gap, but keep going so that we might find a smaller
1973 * gap to fill so avoiding fragmentation.
1975 if (next
- candidate
>= size
&& next
- candidate
< mingap
) {
1977 mingap
= next
- candidate
;
1980 trace_find_ram_offset_loop(size
, candidate
, offset
, next
, mingap
);
1983 if (offset
== RAM_ADDR_MAX
) {
1984 fprintf(stderr
, "Failed to find gap of requested size: %" PRIu64
"\n",
1989 trace_find_ram_offset(size
, offset
);
1994 static unsigned long last_ram_page(void)
1997 ram_addr_t last
= 0;
2000 RAMBLOCK_FOREACH(block
) {
2001 last
= MAX(last
, block
->offset
+ block
->max_length
);
2004 return last
>> TARGET_PAGE_BITS
;
2007 static void qemu_ram_setup_dump(void *addr
, ram_addr_t size
)
2011 /* Use MADV_DONTDUMP, if user doesn't want the guest memory in the core */
2012 if (!machine_dump_guest_core(current_machine
)) {
2013 ret
= qemu_madvise(addr
, size
, QEMU_MADV_DONTDUMP
);
2015 perror("qemu_madvise");
2016 fprintf(stderr
, "madvise doesn't support MADV_DONTDUMP, "
2017 "but dump_guest_core=off specified\n");
2022 const char *qemu_ram_get_idstr(RAMBlock
*rb
)
2027 void *qemu_ram_get_host_addr(RAMBlock
*rb
)
2032 ram_addr_t
qemu_ram_get_offset(RAMBlock
*rb
)
2037 ram_addr_t
qemu_ram_get_used_length(RAMBlock
*rb
)
2039 return rb
->used_length
;
2042 bool qemu_ram_is_shared(RAMBlock
*rb
)
2044 return rb
->flags
& RAM_SHARED
;
2047 /* Note: Only set at the start of postcopy */
2048 bool qemu_ram_is_uf_zeroable(RAMBlock
*rb
)
2050 return rb
->flags
& RAM_UF_ZEROPAGE
;
2053 void qemu_ram_set_uf_zeroable(RAMBlock
*rb
)
2055 rb
->flags
|= RAM_UF_ZEROPAGE
;
2058 bool qemu_ram_is_migratable(RAMBlock
*rb
)
2060 return rb
->flags
& RAM_MIGRATABLE
;
2063 void qemu_ram_set_migratable(RAMBlock
*rb
)
2065 rb
->flags
|= RAM_MIGRATABLE
;
2068 void qemu_ram_unset_migratable(RAMBlock
*rb
)
2070 rb
->flags
&= ~RAM_MIGRATABLE
;
2073 /* Called with iothread lock held. */
2074 void qemu_ram_set_idstr(RAMBlock
*new_block
, const char *name
, DeviceState
*dev
)
2079 assert(!new_block
->idstr
[0]);
2082 char *id
= qdev_get_dev_path(dev
);
2084 snprintf(new_block
->idstr
, sizeof(new_block
->idstr
), "%s/", id
);
2088 pstrcat(new_block
->idstr
, sizeof(new_block
->idstr
), name
);
2091 RAMBLOCK_FOREACH(block
) {
2092 if (block
!= new_block
&&
2093 !strcmp(block
->idstr
, new_block
->idstr
)) {
2094 fprintf(stderr
, "RAMBlock \"%s\" already registered, abort!\n",
2102 /* Called with iothread lock held. */
2103 void qemu_ram_unset_idstr(RAMBlock
*block
)
2105 /* FIXME: arch_init.c assumes that this is not called throughout
2106 * migration. Ignore the problem since hot-unplug during migration
2107 * does not work anyway.
2110 memset(block
->idstr
, 0, sizeof(block
->idstr
));
2114 size_t qemu_ram_pagesize(RAMBlock
*rb
)
2116 return rb
->page_size
;
2119 /* Returns the largest size of page in use */
2120 size_t qemu_ram_pagesize_largest(void)
2125 RAMBLOCK_FOREACH(block
) {
2126 largest
= MAX(largest
, qemu_ram_pagesize(block
));
2132 static int memory_try_enable_merging(void *addr
, size_t len
)
2134 if (!machine_mem_merge(current_machine
)) {
2135 /* disabled by the user */
2139 return qemu_madvise(addr
, len
, QEMU_MADV_MERGEABLE
);
2142 /* Only legal before guest might have detected the memory size: e.g. on
2143 * incoming migration, or right after reset.
2145 * As memory core doesn't know how is memory accessed, it is up to
2146 * resize callback to update device state and/or add assertions to detect
2147 * misuse, if necessary.
2149 int qemu_ram_resize(RAMBlock
*block
, ram_addr_t newsize
, Error
**errp
)
2153 newsize
= HOST_PAGE_ALIGN(newsize
);
2155 if (block
->used_length
== newsize
) {
2159 if (!(block
->flags
& RAM_RESIZEABLE
)) {
2160 error_setg_errno(errp
, EINVAL
,
2161 "Length mismatch: %s: 0x" RAM_ADDR_FMT
2162 " in != 0x" RAM_ADDR_FMT
, block
->idstr
,
2163 newsize
, block
->used_length
);
2167 if (block
->max_length
< newsize
) {
2168 error_setg_errno(errp
, EINVAL
,
2169 "Length too large: %s: 0x" RAM_ADDR_FMT
2170 " > 0x" RAM_ADDR_FMT
, block
->idstr
,
2171 newsize
, block
->max_length
);
2175 cpu_physical_memory_clear_dirty_range(block
->offset
, block
->used_length
);
2176 block
->used_length
= newsize
;
2177 cpu_physical_memory_set_dirty_range(block
->offset
, block
->used_length
,
2179 memory_region_set_size(block
->mr
, newsize
);
2180 if (block
->resized
) {
2181 block
->resized(block
->idstr
, newsize
, block
->host
);
2186 /* Called with ram_list.mutex held */
2187 static void dirty_memory_extend(ram_addr_t old_ram_size
,
2188 ram_addr_t new_ram_size
)
2190 ram_addr_t old_num_blocks
= DIV_ROUND_UP(old_ram_size
,
2191 DIRTY_MEMORY_BLOCK_SIZE
);
2192 ram_addr_t new_num_blocks
= DIV_ROUND_UP(new_ram_size
,
2193 DIRTY_MEMORY_BLOCK_SIZE
);
2196 /* Only need to extend if block count increased */
2197 if (new_num_blocks
<= old_num_blocks
) {
2201 for (i
= 0; i
< DIRTY_MEMORY_NUM
; i
++) {
2202 DirtyMemoryBlocks
*old_blocks
;
2203 DirtyMemoryBlocks
*new_blocks
;
2206 old_blocks
= atomic_rcu_read(&ram_list
.dirty_memory
[i
]);
2207 new_blocks
= g_malloc(sizeof(*new_blocks
) +
2208 sizeof(new_blocks
->blocks
[0]) * new_num_blocks
);
2210 if (old_num_blocks
) {
2211 memcpy(new_blocks
->blocks
, old_blocks
->blocks
,
2212 old_num_blocks
* sizeof(old_blocks
->blocks
[0]));
2215 for (j
= old_num_blocks
; j
< new_num_blocks
; j
++) {
2216 new_blocks
->blocks
[j
] = bitmap_new(DIRTY_MEMORY_BLOCK_SIZE
);
2219 atomic_rcu_set(&ram_list
.dirty_memory
[i
], new_blocks
);
2222 g_free_rcu(old_blocks
, rcu
);
2227 static void ram_block_add(RAMBlock
*new_block
, Error
**errp
, bool shared
)
2230 RAMBlock
*last_block
= NULL
;
2231 ram_addr_t old_ram_size
, new_ram_size
;
2234 old_ram_size
= last_ram_page();
2236 qemu_mutex_lock_ramlist();
2237 new_block
->offset
= find_ram_offset(new_block
->max_length
);
2239 if (!new_block
->host
) {
2240 if (xen_enabled()) {
2241 xen_ram_alloc(new_block
->offset
, new_block
->max_length
,
2242 new_block
->mr
, &err
);
2244 error_propagate(errp
, err
);
2245 qemu_mutex_unlock_ramlist();
2249 new_block
->host
= phys_mem_alloc(new_block
->max_length
,
2250 &new_block
->mr
->align
, shared
);
2251 if (!new_block
->host
) {
2252 error_setg_errno(errp
, errno
,
2253 "cannot set up guest memory '%s'",
2254 memory_region_name(new_block
->mr
));
2255 qemu_mutex_unlock_ramlist();
2258 memory_try_enable_merging(new_block
->host
, new_block
->max_length
);
2262 new_ram_size
= MAX(old_ram_size
,
2263 (new_block
->offset
+ new_block
->max_length
) >> TARGET_PAGE_BITS
);
2264 if (new_ram_size
> old_ram_size
) {
2265 dirty_memory_extend(old_ram_size
, new_ram_size
);
2267 /* Keep the list sorted from biggest to smallest block. Unlike QTAILQ,
2268 * QLIST (which has an RCU-friendly variant) does not have insertion at
2269 * tail, so save the last element in last_block.
2271 RAMBLOCK_FOREACH(block
) {
2273 if (block
->max_length
< new_block
->max_length
) {
2278 QLIST_INSERT_BEFORE_RCU(block
, new_block
, next
);
2279 } else if (last_block
) {
2280 QLIST_INSERT_AFTER_RCU(last_block
, new_block
, next
);
2281 } else { /* list is empty */
2282 QLIST_INSERT_HEAD_RCU(&ram_list
.blocks
, new_block
, next
);
2284 ram_list
.mru_block
= NULL
;
2286 /* Write list before version */
2289 qemu_mutex_unlock_ramlist();
2291 cpu_physical_memory_set_dirty_range(new_block
->offset
,
2292 new_block
->used_length
,
2295 if (new_block
->host
) {
2296 qemu_ram_setup_dump(new_block
->host
, new_block
->max_length
);
2297 qemu_madvise(new_block
->host
, new_block
->max_length
, QEMU_MADV_HUGEPAGE
);
2298 /* MADV_DONTFORK is also needed by KVM in absence of synchronous MMU */
2299 qemu_madvise(new_block
->host
, new_block
->max_length
, QEMU_MADV_DONTFORK
);
2300 ram_block_notify_add(new_block
->host
, new_block
->max_length
);
2305 RAMBlock
*qemu_ram_alloc_from_fd(ram_addr_t size
, MemoryRegion
*mr
,
2306 uint32_t ram_flags
, int fd
,
2309 RAMBlock
*new_block
;
2310 Error
*local_err
= NULL
;
2313 /* Just support these ram flags by now. */
2314 assert((ram_flags
& ~(RAM_SHARED
| RAM_PMEM
)) == 0);
2316 if (xen_enabled()) {
2317 error_setg(errp
, "-mem-path not supported with Xen");
2321 if (kvm_enabled() && !kvm_has_sync_mmu()) {
2323 "host lacks kvm mmu notifiers, -mem-path unsupported");
2327 if (phys_mem_alloc
!= qemu_anon_ram_alloc
) {
2329 * file_ram_alloc() needs to allocate just like
2330 * phys_mem_alloc, but we haven't bothered to provide
2334 "-mem-path not supported with this accelerator");
2338 size
= HOST_PAGE_ALIGN(size
);
2339 file_size
= get_file_size(fd
);
2340 if (file_size
> 0 && file_size
< size
) {
2341 error_setg(errp
, "backing store %s size 0x%" PRIx64
2342 " does not match 'size' option 0x" RAM_ADDR_FMT
,
2343 mem_path
, file_size
, size
);
2347 new_block
= g_malloc0(sizeof(*new_block
));
2349 new_block
->used_length
= size
;
2350 new_block
->max_length
= size
;
2351 new_block
->flags
= ram_flags
;
2352 new_block
->host
= file_ram_alloc(new_block
, size
, fd
, !file_size
, errp
);
2353 if (!new_block
->host
) {
2358 ram_block_add(new_block
, &local_err
, ram_flags
& RAM_SHARED
);
2361 error_propagate(errp
, local_err
);
2369 RAMBlock
*qemu_ram_alloc_from_file(ram_addr_t size
, MemoryRegion
*mr
,
2370 uint32_t ram_flags
, const char *mem_path
,
2377 fd
= file_ram_open(mem_path
, memory_region_name(mr
), &created
, errp
);
2382 block
= qemu_ram_alloc_from_fd(size
, mr
, ram_flags
, fd
, errp
);
2396 RAMBlock
*qemu_ram_alloc_internal(ram_addr_t size
, ram_addr_t max_size
,
2397 void (*resized
)(const char*,
2400 void *host
, bool resizeable
, bool share
,
2401 MemoryRegion
*mr
, Error
**errp
)
2403 RAMBlock
*new_block
;
2404 Error
*local_err
= NULL
;
2406 size
= HOST_PAGE_ALIGN(size
);
2407 max_size
= HOST_PAGE_ALIGN(max_size
);
2408 new_block
= g_malloc0(sizeof(*new_block
));
2410 new_block
->resized
= resized
;
2411 new_block
->used_length
= size
;
2412 new_block
->max_length
= max_size
;
2413 assert(max_size
>= size
);
2415 new_block
->page_size
= getpagesize();
2416 new_block
->host
= host
;
2418 new_block
->flags
|= RAM_PREALLOC
;
2421 new_block
->flags
|= RAM_RESIZEABLE
;
2423 ram_block_add(new_block
, &local_err
, share
);
2426 error_propagate(errp
, local_err
);
2432 RAMBlock
*qemu_ram_alloc_from_ptr(ram_addr_t size
, void *host
,
2433 MemoryRegion
*mr
, Error
**errp
)
2435 return qemu_ram_alloc_internal(size
, size
, NULL
, host
, false,
2439 RAMBlock
*qemu_ram_alloc(ram_addr_t size
, bool share
,
2440 MemoryRegion
*mr
, Error
**errp
)
2442 return qemu_ram_alloc_internal(size
, size
, NULL
, NULL
, false,
2446 RAMBlock
*qemu_ram_alloc_resizeable(ram_addr_t size
, ram_addr_t maxsz
,
2447 void (*resized
)(const char*,
2450 MemoryRegion
*mr
, Error
**errp
)
2452 return qemu_ram_alloc_internal(size
, maxsz
, resized
, NULL
, true,
2456 static void reclaim_ramblock(RAMBlock
*block
)
2458 if (block
->flags
& RAM_PREALLOC
) {
2460 } else if (xen_enabled()) {
2461 xen_invalidate_map_cache_entry(block
->host
);
2463 } else if (block
->fd
>= 0) {
2464 qemu_ram_munmap(block
->fd
, block
->host
, block
->max_length
);
2468 qemu_anon_ram_free(block
->host
, block
->max_length
);
2473 void qemu_ram_free(RAMBlock
*block
)
2480 ram_block_notify_remove(block
->host
, block
->max_length
);
2483 qemu_mutex_lock_ramlist();
2484 QLIST_REMOVE_RCU(block
, next
);
2485 ram_list
.mru_block
= NULL
;
2486 /* Write list before version */
2489 call_rcu(block
, reclaim_ramblock
, rcu
);
2490 qemu_mutex_unlock_ramlist();
2494 void qemu_ram_remap(ram_addr_t addr
, ram_addr_t length
)
2501 RAMBLOCK_FOREACH(block
) {
2502 offset
= addr
- block
->offset
;
2503 if (offset
< block
->max_length
) {
2504 vaddr
= ramblock_ptr(block
, offset
);
2505 if (block
->flags
& RAM_PREALLOC
) {
2507 } else if (xen_enabled()) {
2511 if (block
->fd
>= 0) {
2512 flags
|= (block
->flags
& RAM_SHARED
?
2513 MAP_SHARED
: MAP_PRIVATE
);
2514 area
= mmap(vaddr
, length
, PROT_READ
| PROT_WRITE
,
2515 flags
, block
->fd
, offset
);
2518 * Remap needs to match alloc. Accelerators that
2519 * set phys_mem_alloc never remap. If they did,
2520 * we'd need a remap hook here.
2522 assert(phys_mem_alloc
== qemu_anon_ram_alloc
);
2524 flags
|= MAP_PRIVATE
| MAP_ANONYMOUS
;
2525 area
= mmap(vaddr
, length
, PROT_READ
| PROT_WRITE
,
2528 if (area
!= vaddr
) {
2529 error_report("Could not remap addr: "
2530 RAM_ADDR_FMT
"@" RAM_ADDR_FMT
"",
2534 memory_try_enable_merging(vaddr
, length
);
2535 qemu_ram_setup_dump(vaddr
, length
);
2540 #endif /* !_WIN32 */
2542 /* Return a host pointer to ram allocated with qemu_ram_alloc.
2543 * This should not be used for general purpose DMA. Use address_space_map
2544 * or address_space_rw instead. For local memory (e.g. video ram) that the
2545 * device owns, use memory_region_get_ram_ptr.
2547 * Called within RCU critical section.
2549 void *qemu_map_ram_ptr(RAMBlock
*ram_block
, ram_addr_t addr
)
2551 RAMBlock
*block
= ram_block
;
2553 if (block
== NULL
) {
2554 block
= qemu_get_ram_block(addr
);
2555 addr
-= block
->offset
;
2558 if (xen_enabled() && block
->host
== NULL
) {
2559 /* We need to check if the requested address is in the RAM
2560 * because we don't want to map the entire memory in QEMU.
2561 * In that case just map until the end of the page.
2563 if (block
->offset
== 0) {
2564 return xen_map_cache(addr
, 0, 0, false);
2567 block
->host
= xen_map_cache(block
->offset
, block
->max_length
, 1, false);
2569 return ramblock_ptr(block
, addr
);
2572 /* Return a host pointer to guest's ram. Similar to qemu_map_ram_ptr
2573 * but takes a size argument.
2575 * Called within RCU critical section.
2577 static void *qemu_ram_ptr_length(RAMBlock
*ram_block
, ram_addr_t addr
,
2578 hwaddr
*size
, bool lock
)
2580 RAMBlock
*block
= ram_block
;
2585 if (block
== NULL
) {
2586 block
= qemu_get_ram_block(addr
);
2587 addr
-= block
->offset
;
2589 *size
= MIN(*size
, block
->max_length
- addr
);
2591 if (xen_enabled() && block
->host
== NULL
) {
2592 /* We need to check if the requested address is in the RAM
2593 * because we don't want to map the entire memory in QEMU.
2594 * In that case just map the requested area.
2596 if (block
->offset
== 0) {
2597 return xen_map_cache(addr
, *size
, lock
, lock
);
2600 block
->host
= xen_map_cache(block
->offset
, block
->max_length
, 1, lock
);
2603 return ramblock_ptr(block
, addr
);
2606 /* Return the offset of a hostpointer within a ramblock */
2607 ram_addr_t
qemu_ram_block_host_offset(RAMBlock
*rb
, void *host
)
2609 ram_addr_t res
= (uint8_t *)host
- (uint8_t *)rb
->host
;
2610 assert((uintptr_t)host
>= (uintptr_t)rb
->host
);
2611 assert(res
< rb
->max_length
);
2617 * Translates a host ptr back to a RAMBlock, a ram_addr and an offset
2620 * ptr: Host pointer to look up
2621 * round_offset: If true round the result offset down to a page boundary
2622 * *ram_addr: set to result ram_addr
2623 * *offset: set to result offset within the RAMBlock
2625 * Returns: RAMBlock (or NULL if not found)
2627 * By the time this function returns, the returned pointer is not protected
2628 * by RCU anymore. If the caller is not within an RCU critical section and
2629 * does not hold the iothread lock, it must have other means of protecting the
2630 * pointer, such as a reference to the region that includes the incoming
2633 RAMBlock
*qemu_ram_block_from_host(void *ptr
, bool round_offset
,
2637 uint8_t *host
= ptr
;
2639 if (xen_enabled()) {
2640 ram_addr_t ram_addr
;
2642 ram_addr
= xen_ram_addr_from_mapcache(ptr
);
2643 block
= qemu_get_ram_block(ram_addr
);
2645 *offset
= ram_addr
- block
->offset
;
2652 block
= atomic_rcu_read(&ram_list
.mru_block
);
2653 if (block
&& block
->host
&& host
- block
->host
< block
->max_length
) {
2657 RAMBLOCK_FOREACH(block
) {
2658 /* This case append when the block is not mapped. */
2659 if (block
->host
== NULL
) {
2662 if (host
- block
->host
< block
->max_length
) {
2671 *offset
= (host
- block
->host
);
2673 *offset
&= TARGET_PAGE_MASK
;
2680 * Finds the named RAMBlock
2682 * name: The name of RAMBlock to find
2684 * Returns: RAMBlock (or NULL if not found)
2686 RAMBlock
*qemu_ram_block_by_name(const char *name
)
2690 RAMBLOCK_FOREACH(block
) {
2691 if (!strcmp(name
, block
->idstr
)) {
2699 /* Some of the softmmu routines need to translate from a host pointer
2700 (typically a TLB entry) back to a ram offset. */
2701 ram_addr_t
qemu_ram_addr_from_host(void *ptr
)
2706 block
= qemu_ram_block_from_host(ptr
, false, &offset
);
2708 return RAM_ADDR_INVALID
;
2711 return block
->offset
+ offset
;
2714 /* Called within RCU critical section. */
2715 void memory_notdirty_write_prepare(NotDirtyInfo
*ndi
,
2718 ram_addr_t ram_addr
,
2722 ndi
->ram_addr
= ram_addr
;
2723 ndi
->mem_vaddr
= mem_vaddr
;
2727 assert(tcg_enabled());
2728 if (!cpu_physical_memory_get_dirty_flag(ram_addr
, DIRTY_MEMORY_CODE
)) {
2729 ndi
->pages
= page_collection_lock(ram_addr
, ram_addr
+ size
);
2730 tb_invalidate_phys_page_fast(ndi
->pages
, ram_addr
, size
);
2734 /* Called within RCU critical section. */
2735 void memory_notdirty_write_complete(NotDirtyInfo
*ndi
)
2738 assert(tcg_enabled());
2739 page_collection_unlock(ndi
->pages
);
2743 /* Set both VGA and migration bits for simplicity and to remove
2744 * the notdirty callback faster.
2746 cpu_physical_memory_set_dirty_range(ndi
->ram_addr
, ndi
->size
,
2747 DIRTY_CLIENTS_NOCODE
);
2748 /* we remove the notdirty callback only if the code has been
2750 if (!cpu_physical_memory_is_clean(ndi
->ram_addr
)) {
2751 tlb_set_dirty(ndi
->cpu
, ndi
->mem_vaddr
);
2755 /* Called within RCU critical section. */
2756 static void notdirty_mem_write(void *opaque
, hwaddr ram_addr
,
2757 uint64_t val
, unsigned size
)
2761 memory_notdirty_write_prepare(&ndi
, current_cpu
, current_cpu
->mem_io_vaddr
,
2764 stn_p(qemu_map_ram_ptr(NULL
, ram_addr
), size
, val
);
2765 memory_notdirty_write_complete(&ndi
);
2768 static bool notdirty_mem_accepts(void *opaque
, hwaddr addr
,
2769 unsigned size
, bool is_write
,
2775 static const MemoryRegionOps notdirty_mem_ops
= {
2776 .write
= notdirty_mem_write
,
2777 .valid
.accepts
= notdirty_mem_accepts
,
2778 .endianness
= DEVICE_NATIVE_ENDIAN
,
2780 .min_access_size
= 1,
2781 .max_access_size
= 8,
2785 .min_access_size
= 1,
2786 .max_access_size
= 8,
2791 /* Generate a debug exception if a watchpoint has been hit. */
2792 static void check_watchpoint(int offset
, int len
, MemTxAttrs attrs
, int flags
)
2794 CPUState
*cpu
= current_cpu
;
2795 CPUClass
*cc
= CPU_GET_CLASS(cpu
);
2799 assert(tcg_enabled());
2800 if (cpu
->watchpoint_hit
) {
2801 /* We re-entered the check after replacing the TB. Now raise
2802 * the debug interrupt so that is will trigger after the
2803 * current instruction. */
2804 cpu_interrupt(cpu
, CPU_INTERRUPT_DEBUG
);
2807 vaddr
= (cpu
->mem_io_vaddr
& TARGET_PAGE_MASK
) + offset
;
2808 vaddr
= cc
->adjust_watchpoint_address(cpu
, vaddr
, len
);
2809 QTAILQ_FOREACH(wp
, &cpu
->watchpoints
, entry
) {
2810 if (cpu_watchpoint_address_matches(wp
, vaddr
, len
)
2811 && (wp
->flags
& flags
)) {
2812 if (flags
== BP_MEM_READ
) {
2813 wp
->flags
|= BP_WATCHPOINT_HIT_READ
;
2815 wp
->flags
|= BP_WATCHPOINT_HIT_WRITE
;
2817 wp
->hitaddr
= vaddr
;
2818 wp
->hitattrs
= attrs
;
2819 if (!cpu
->watchpoint_hit
) {
2820 if (wp
->flags
& BP_CPU
&&
2821 !cc
->debug_check_watchpoint(cpu
, wp
)) {
2822 wp
->flags
&= ~BP_WATCHPOINT_HIT
;
2825 cpu
->watchpoint_hit
= wp
;
2828 tb_check_watchpoint(cpu
);
2829 if (wp
->flags
& BP_STOP_BEFORE_ACCESS
) {
2830 cpu
->exception_index
= EXCP_DEBUG
;
2834 /* Force execution of one insn next time. */
2835 cpu
->cflags_next_tb
= 1 | curr_cflags();
2837 cpu_loop_exit_noexc(cpu
);
2841 wp
->flags
&= ~BP_WATCHPOINT_HIT
;
2846 /* Watchpoint access routines. Watchpoints are inserted using TLB tricks,
2847 so these check for a hit then pass through to the normal out-of-line
2849 static MemTxResult
watch_mem_read(void *opaque
, hwaddr addr
, uint64_t *pdata
,
2850 unsigned size
, MemTxAttrs attrs
)
2854 int asidx
= cpu_asidx_from_attrs(current_cpu
, attrs
);
2855 AddressSpace
*as
= current_cpu
->cpu_ases
[asidx
].as
;
2857 check_watchpoint(addr
& ~TARGET_PAGE_MASK
, size
, attrs
, BP_MEM_READ
);
2860 data
= address_space_ldub(as
, addr
, attrs
, &res
);
2863 data
= address_space_lduw(as
, addr
, attrs
, &res
);
2866 data
= address_space_ldl(as
, addr
, attrs
, &res
);
2869 data
= address_space_ldq(as
, addr
, attrs
, &res
);
2877 static MemTxResult
watch_mem_write(void *opaque
, hwaddr addr
,
2878 uint64_t val
, unsigned size
,
2882 int asidx
= cpu_asidx_from_attrs(current_cpu
, attrs
);
2883 AddressSpace
*as
= current_cpu
->cpu_ases
[asidx
].as
;
2885 check_watchpoint(addr
& ~TARGET_PAGE_MASK
, size
, attrs
, BP_MEM_WRITE
);
2888 address_space_stb(as
, addr
, val
, attrs
, &res
);
2891 address_space_stw(as
, addr
, val
, attrs
, &res
);
2894 address_space_stl(as
, addr
, val
, attrs
, &res
);
2897 address_space_stq(as
, addr
, val
, attrs
, &res
);
2904 static const MemoryRegionOps watch_mem_ops
= {
2905 .read_with_attrs
= watch_mem_read
,
2906 .write_with_attrs
= watch_mem_write
,
2907 .endianness
= DEVICE_NATIVE_ENDIAN
,
2909 .min_access_size
= 1,
2910 .max_access_size
= 8,
2914 .min_access_size
= 1,
2915 .max_access_size
= 8,
2920 static MemTxResult
flatview_read(FlatView
*fv
, hwaddr addr
,
2921 MemTxAttrs attrs
, uint8_t *buf
, hwaddr len
);
2922 static MemTxResult
flatview_write(FlatView
*fv
, hwaddr addr
, MemTxAttrs attrs
,
2923 const uint8_t *buf
, hwaddr len
);
2924 static bool flatview_access_valid(FlatView
*fv
, hwaddr addr
, hwaddr len
,
2925 bool is_write
, MemTxAttrs attrs
);
2927 static MemTxResult
subpage_read(void *opaque
, hwaddr addr
, uint64_t *data
,
2928 unsigned len
, MemTxAttrs attrs
)
2930 subpage_t
*subpage
= opaque
;
2934 #if defined(DEBUG_SUBPAGE)
2935 printf("%s: subpage %p len %u addr " TARGET_FMT_plx
"\n", __func__
,
2936 subpage
, len
, addr
);
2938 res
= flatview_read(subpage
->fv
, addr
+ subpage
->base
, attrs
, buf
, len
);
2942 *data
= ldn_p(buf
, len
);
2946 static MemTxResult
subpage_write(void *opaque
, hwaddr addr
,
2947 uint64_t value
, unsigned len
, MemTxAttrs attrs
)
2949 subpage_t
*subpage
= opaque
;
2952 #if defined(DEBUG_SUBPAGE)
2953 printf("%s: subpage %p len %u addr " TARGET_FMT_plx
2954 " value %"PRIx64
"\n",
2955 __func__
, subpage
, len
, addr
, value
);
2957 stn_p(buf
, len
, value
);
2958 return flatview_write(subpage
->fv
, addr
+ subpage
->base
, attrs
, buf
, len
);
2961 static bool subpage_accepts(void *opaque
, hwaddr addr
,
2962 unsigned len
, bool is_write
,
2965 subpage_t
*subpage
= opaque
;
2966 #if defined(DEBUG_SUBPAGE)
2967 printf("%s: subpage %p %c len %u addr " TARGET_FMT_plx
"\n",
2968 __func__
, subpage
, is_write
? 'w' : 'r', len
, addr
);
2971 return flatview_access_valid(subpage
->fv
, addr
+ subpage
->base
,
2972 len
, is_write
, attrs
);
2975 static const MemoryRegionOps subpage_ops
= {
2976 .read_with_attrs
= subpage_read
,
2977 .write_with_attrs
= subpage_write
,
2978 .impl
.min_access_size
= 1,
2979 .impl
.max_access_size
= 8,
2980 .valid
.min_access_size
= 1,
2981 .valid
.max_access_size
= 8,
2982 .valid
.accepts
= subpage_accepts
,
2983 .endianness
= DEVICE_NATIVE_ENDIAN
,
2986 static int subpage_register (subpage_t
*mmio
, uint32_t start
, uint32_t end
,
2991 if (start
>= TARGET_PAGE_SIZE
|| end
>= TARGET_PAGE_SIZE
)
2993 idx
= SUBPAGE_IDX(start
);
2994 eidx
= SUBPAGE_IDX(end
);
2995 #if defined(DEBUG_SUBPAGE)
2996 printf("%s: %p start %08x end %08x idx %08x eidx %08x section %d\n",
2997 __func__
, mmio
, start
, end
, idx
, eidx
, section
);
2999 for (; idx
<= eidx
; idx
++) {
3000 mmio
->sub_section
[idx
] = section
;
3006 static subpage_t
*subpage_init(FlatView
*fv
, hwaddr base
)
3010 mmio
= g_malloc0(sizeof(subpage_t
) + TARGET_PAGE_SIZE
* sizeof(uint16_t));
3013 memory_region_init_io(&mmio
->iomem
, NULL
, &subpage_ops
, mmio
,
3014 NULL
, TARGET_PAGE_SIZE
);
3015 mmio
->iomem
.subpage
= true;
3016 #if defined(DEBUG_SUBPAGE)
3017 printf("%s: %p base " TARGET_FMT_plx
" len %08x\n", __func__
,
3018 mmio
, base
, TARGET_PAGE_SIZE
);
3020 subpage_register(mmio
, 0, TARGET_PAGE_SIZE
-1, PHYS_SECTION_UNASSIGNED
);
3025 static uint16_t dummy_section(PhysPageMap
*map
, FlatView
*fv
, MemoryRegion
*mr
)
3028 MemoryRegionSection section
= {
3031 .offset_within_address_space
= 0,
3032 .offset_within_region
= 0,
3033 .size
= int128_2_64(),
3036 return phys_section_add(map
, §ion
);
3039 static void readonly_mem_write(void *opaque
, hwaddr addr
,
3040 uint64_t val
, unsigned size
)
3042 /* Ignore any write to ROM. */
3045 static bool readonly_mem_accepts(void *opaque
, hwaddr addr
,
3046 unsigned size
, bool is_write
,
3052 /* This will only be used for writes, because reads are special cased
3053 * to directly access the underlying host ram.
3055 static const MemoryRegionOps readonly_mem_ops
= {
3056 .write
= readonly_mem_write
,
3057 .valid
.accepts
= readonly_mem_accepts
,
3058 .endianness
= DEVICE_NATIVE_ENDIAN
,
3060 .min_access_size
= 1,
3061 .max_access_size
= 8,
3065 .min_access_size
= 1,
3066 .max_access_size
= 8,
3071 MemoryRegionSection
*iotlb_to_section(CPUState
*cpu
,
3072 hwaddr index
, MemTxAttrs attrs
)
3074 int asidx
= cpu_asidx_from_attrs(cpu
, attrs
);
3075 CPUAddressSpace
*cpuas
= &cpu
->cpu_ases
[asidx
];
3076 AddressSpaceDispatch
*d
= atomic_rcu_read(&cpuas
->memory_dispatch
);
3077 MemoryRegionSection
*sections
= d
->map
.sections
;
3079 return §ions
[index
& ~TARGET_PAGE_MASK
];
3082 static void io_mem_init(void)
3084 memory_region_init_io(&io_mem_rom
, NULL
, &readonly_mem_ops
,
3085 NULL
, NULL
, UINT64_MAX
);
3086 memory_region_init_io(&io_mem_unassigned
, NULL
, &unassigned_mem_ops
, NULL
,
3089 /* io_mem_notdirty calls tb_invalidate_phys_page_fast,
3090 * which can be called without the iothread mutex.
3092 memory_region_init_io(&io_mem_notdirty
, NULL
, ¬dirty_mem_ops
, NULL
,
3094 memory_region_clear_global_locking(&io_mem_notdirty
);
3096 memory_region_init_io(&io_mem_watch
, NULL
, &watch_mem_ops
, NULL
,
3100 AddressSpaceDispatch
*address_space_dispatch_new(FlatView
*fv
)
3102 AddressSpaceDispatch
*d
= g_new0(AddressSpaceDispatch
, 1);
3105 n
= dummy_section(&d
->map
, fv
, &io_mem_unassigned
);
3106 assert(n
== PHYS_SECTION_UNASSIGNED
);
3107 n
= dummy_section(&d
->map
, fv
, &io_mem_notdirty
);
3108 assert(n
== PHYS_SECTION_NOTDIRTY
);
3109 n
= dummy_section(&d
->map
, fv
, &io_mem_rom
);
3110 assert(n
== PHYS_SECTION_ROM
);
3111 n
= dummy_section(&d
->map
, fv
, &io_mem_watch
);
3112 assert(n
== PHYS_SECTION_WATCH
);
3114 d
->phys_map
= (PhysPageEntry
) { .ptr
= PHYS_MAP_NODE_NIL
, .skip
= 1 };
3119 void address_space_dispatch_free(AddressSpaceDispatch
*d
)
3121 phys_sections_free(&d
->map
);
3125 static void tcg_commit(MemoryListener
*listener
)
3127 CPUAddressSpace
*cpuas
;
3128 AddressSpaceDispatch
*d
;
3130 assert(tcg_enabled());
3131 /* since each CPU stores ram addresses in its TLB cache, we must
3132 reset the modified entries */
3133 cpuas
= container_of(listener
, CPUAddressSpace
, tcg_as_listener
);
3134 cpu_reloading_memory_map();
3135 /* The CPU and TLB are protected by the iothread lock.
3136 * We reload the dispatch pointer now because cpu_reloading_memory_map()
3137 * may have split the RCU critical section.
3139 d
= address_space_to_dispatch(cpuas
->as
);
3140 atomic_rcu_set(&cpuas
->memory_dispatch
, d
);
3141 tlb_flush(cpuas
->cpu
);
3144 static void memory_map_init(void)
3146 system_memory
= g_malloc(sizeof(*system_memory
));
3148 memory_region_init(system_memory
, NULL
, "system", UINT64_MAX
);
3149 address_space_init(&address_space_memory
, system_memory
, "memory");
3151 system_io
= g_malloc(sizeof(*system_io
));
3152 memory_region_init_io(system_io
, NULL
, &unassigned_io_ops
, NULL
, "io",
3154 address_space_init(&address_space_io
, system_io
, "I/O");
3157 MemoryRegion
*get_system_memory(void)
3159 return system_memory
;
3162 MemoryRegion
*get_system_io(void)
3167 #endif /* !defined(CONFIG_USER_ONLY) */
3169 /* physical memory access (slow version, mainly for debug) */
3170 #if defined(CONFIG_USER_ONLY)
3171 int cpu_memory_rw_debug(CPUState
*cpu
, target_ulong addr
,
3172 uint8_t *buf
, target_ulong len
, int is_write
)
3175 target_ulong l
, page
;
3179 page
= addr
& TARGET_PAGE_MASK
;
3180 l
= (page
+ TARGET_PAGE_SIZE
) - addr
;
3183 flags
= page_get_flags(page
);
3184 if (!(flags
& PAGE_VALID
))
3187 if (!(flags
& PAGE_WRITE
))
3189 /* XXX: this code should not depend on lock_user */
3190 if (!(p
= lock_user(VERIFY_WRITE
, addr
, l
, 0)))
3193 unlock_user(p
, addr
, l
);
3195 if (!(flags
& PAGE_READ
))
3197 /* XXX: this code should not depend on lock_user */
3198 if (!(p
= lock_user(VERIFY_READ
, addr
, l
, 1)))
3201 unlock_user(p
, addr
, 0);
3212 static void invalidate_and_set_dirty(MemoryRegion
*mr
, hwaddr addr
,
3215 uint8_t dirty_log_mask
= memory_region_get_dirty_log_mask(mr
);
3216 addr
+= memory_region_get_ram_addr(mr
);
3218 /* No early return if dirty_log_mask is or becomes 0, because
3219 * cpu_physical_memory_set_dirty_range will still call
3220 * xen_modified_memory.
3222 if (dirty_log_mask
) {
3224 cpu_physical_memory_range_includes_clean(addr
, length
, dirty_log_mask
);
3226 if (dirty_log_mask
& (1 << DIRTY_MEMORY_CODE
)) {
3227 assert(tcg_enabled());
3228 tb_invalidate_phys_range(addr
, addr
+ length
);
3229 dirty_log_mask
&= ~(1 << DIRTY_MEMORY_CODE
);
3231 cpu_physical_memory_set_dirty_range(addr
, length
, dirty_log_mask
);
3234 void memory_region_flush_rom_device(MemoryRegion
*mr
, hwaddr addr
, hwaddr size
)
3237 * In principle this function would work on other memory region types too,
3238 * but the ROM device use case is the only one where this operation is
3239 * necessary. Other memory regions should use the
3240 * address_space_read/write() APIs.
3242 assert(memory_region_is_romd(mr
));
3244 invalidate_and_set_dirty(mr
, addr
, size
);
3247 static int memory_access_size(MemoryRegion
*mr
, unsigned l
, hwaddr addr
)
3249 unsigned access_size_max
= mr
->ops
->valid
.max_access_size
;
3251 /* Regions are assumed to support 1-4 byte accesses unless
3252 otherwise specified. */
3253 if (access_size_max
== 0) {
3254 access_size_max
= 4;
3257 /* Bound the maximum access by the alignment of the address. */
3258 if (!mr
->ops
->impl
.unaligned
) {
3259 unsigned align_size_max
= addr
& -addr
;
3260 if (align_size_max
!= 0 && align_size_max
< access_size_max
) {
3261 access_size_max
= align_size_max
;
3265 /* Don't attempt accesses larger than the maximum. */
3266 if (l
> access_size_max
) {
3267 l
= access_size_max
;
3274 static bool prepare_mmio_access(MemoryRegion
*mr
)
3276 bool unlocked
= !qemu_mutex_iothread_locked();
3277 bool release_lock
= false;
3279 if (unlocked
&& mr
->global_locking
) {
3280 qemu_mutex_lock_iothread();
3282 release_lock
= true;
3284 if (mr
->flush_coalesced_mmio
) {
3286 qemu_mutex_lock_iothread();
3288 qemu_flush_coalesced_mmio_buffer();
3290 qemu_mutex_unlock_iothread();
3294 return release_lock
;
3297 /* Called within RCU critical section. */
3298 static MemTxResult
flatview_write_continue(FlatView
*fv
, hwaddr addr
,
3301 hwaddr len
, hwaddr addr1
,
3302 hwaddr l
, MemoryRegion
*mr
)
3306 MemTxResult result
= MEMTX_OK
;
3307 bool release_lock
= false;
3310 if (!memory_access_is_direct(mr
, true)) {
3311 release_lock
|= prepare_mmio_access(mr
);
3312 l
= memory_access_size(mr
, l
, addr1
);
3313 /* XXX: could force current_cpu to NULL to avoid
3315 val
= ldn_p(buf
, l
);
3316 result
|= memory_region_dispatch_write(mr
, addr1
, val
, l
, attrs
);
3319 ptr
= qemu_ram_ptr_length(mr
->ram_block
, addr1
, &l
, false);
3320 memcpy(ptr
, buf
, l
);
3321 invalidate_and_set_dirty(mr
, addr1
, l
);
3325 qemu_mutex_unlock_iothread();
3326 release_lock
= false;
3338 mr
= flatview_translate(fv
, addr
, &addr1
, &l
, true, attrs
);
3344 /* Called from RCU critical section. */
3345 static MemTxResult
flatview_write(FlatView
*fv
, hwaddr addr
, MemTxAttrs attrs
,
3346 const uint8_t *buf
, hwaddr len
)
3351 MemTxResult result
= MEMTX_OK
;
3354 mr
= flatview_translate(fv
, addr
, &addr1
, &l
, true, attrs
);
3355 result
= flatview_write_continue(fv
, addr
, attrs
, buf
, len
,
3361 /* Called within RCU critical section. */
3362 MemTxResult
flatview_read_continue(FlatView
*fv
, hwaddr addr
,
3363 MemTxAttrs attrs
, uint8_t *buf
,
3364 hwaddr len
, hwaddr addr1
, hwaddr l
,
3369 MemTxResult result
= MEMTX_OK
;
3370 bool release_lock
= false;
3373 if (!memory_access_is_direct(mr
, false)) {
3375 release_lock
|= prepare_mmio_access(mr
);
3376 l
= memory_access_size(mr
, l
, addr1
);
3377 result
|= memory_region_dispatch_read(mr
, addr1
, &val
, l
, attrs
);
3381 ptr
= qemu_ram_ptr_length(mr
->ram_block
, addr1
, &l
, false);
3382 memcpy(buf
, ptr
, l
);
3386 qemu_mutex_unlock_iothread();
3387 release_lock
= false;
3399 mr
= flatview_translate(fv
, addr
, &addr1
, &l
, false, attrs
);
3405 /* Called from RCU critical section. */
3406 static MemTxResult
flatview_read(FlatView
*fv
, hwaddr addr
,
3407 MemTxAttrs attrs
, uint8_t *buf
, hwaddr len
)
3414 mr
= flatview_translate(fv
, addr
, &addr1
, &l
, false, attrs
);
3415 return flatview_read_continue(fv
, addr
, attrs
, buf
, len
,
3419 MemTxResult
address_space_read_full(AddressSpace
*as
, hwaddr addr
,
3420 MemTxAttrs attrs
, uint8_t *buf
, hwaddr len
)
3422 MemTxResult result
= MEMTX_OK
;
3427 fv
= address_space_to_flatview(as
);
3428 result
= flatview_read(fv
, addr
, attrs
, buf
, len
);
3435 MemTxResult
address_space_write(AddressSpace
*as
, hwaddr addr
,
3437 const uint8_t *buf
, hwaddr len
)
3439 MemTxResult result
= MEMTX_OK
;
3444 fv
= address_space_to_flatview(as
);
3445 result
= flatview_write(fv
, addr
, attrs
, buf
, len
);
3452 MemTxResult
address_space_rw(AddressSpace
*as
, hwaddr addr
, MemTxAttrs attrs
,
3453 uint8_t *buf
, hwaddr len
, bool is_write
)
3456 return address_space_write(as
, addr
, attrs
, buf
, len
);
3458 return address_space_read_full(as
, addr
, attrs
, buf
, len
);
3462 void cpu_physical_memory_rw(hwaddr addr
, uint8_t *buf
,
3463 hwaddr len
, int is_write
)
3465 address_space_rw(&address_space_memory
, addr
, MEMTXATTRS_UNSPECIFIED
,
3466 buf
, len
, is_write
);
3469 enum write_rom_type
{
3474 static inline MemTxResult
address_space_write_rom_internal(AddressSpace
*as
,
3479 enum write_rom_type type
)
3489 mr
= address_space_translate(as
, addr
, &addr1
, &l
, true, attrs
);
3491 if (!(memory_region_is_ram(mr
) ||
3492 memory_region_is_romd(mr
))) {
3493 l
= memory_access_size(mr
, l
, addr1
);
3496 ptr
= qemu_map_ram_ptr(mr
->ram_block
, addr1
);
3499 memcpy(ptr
, buf
, l
);
3500 invalidate_and_set_dirty(mr
, addr1
, l
);
3503 flush_icache_range((uintptr_t)ptr
, (uintptr_t)ptr
+ l
);
3515 /* used for ROM loading : can write in RAM and ROM */
3516 MemTxResult
address_space_write_rom(AddressSpace
*as
, hwaddr addr
,
3518 const uint8_t *buf
, hwaddr len
)
3520 return address_space_write_rom_internal(as
, addr
, attrs
,
3521 buf
, len
, WRITE_DATA
);
3524 void cpu_flush_icache_range(hwaddr start
, hwaddr len
)
3527 * This function should do the same thing as an icache flush that was
3528 * triggered from within the guest. For TCG we are always cache coherent,
3529 * so there is no need to flush anything. For KVM / Xen we need to flush
3530 * the host's instruction cache at least.
3532 if (tcg_enabled()) {
3536 address_space_write_rom_internal(&address_space_memory
,
3537 start
, MEMTXATTRS_UNSPECIFIED
,
3538 NULL
, len
, FLUSH_CACHE
);
3549 static BounceBuffer bounce
;
3551 typedef struct MapClient
{
3553 QLIST_ENTRY(MapClient
) link
;
3556 QemuMutex map_client_list_lock
;
3557 static QLIST_HEAD(, MapClient
) map_client_list
3558 = QLIST_HEAD_INITIALIZER(map_client_list
);
3560 static void cpu_unregister_map_client_do(MapClient
*client
)
3562 QLIST_REMOVE(client
, link
);
3566 static void cpu_notify_map_clients_locked(void)
3570 while (!QLIST_EMPTY(&map_client_list
)) {
3571 client
= QLIST_FIRST(&map_client_list
);
3572 qemu_bh_schedule(client
->bh
);
3573 cpu_unregister_map_client_do(client
);
3577 void cpu_register_map_client(QEMUBH
*bh
)
3579 MapClient
*client
= g_malloc(sizeof(*client
));
3581 qemu_mutex_lock(&map_client_list_lock
);
3583 QLIST_INSERT_HEAD(&map_client_list
, client
, link
);
3584 if (!atomic_read(&bounce
.in_use
)) {
3585 cpu_notify_map_clients_locked();
3587 qemu_mutex_unlock(&map_client_list_lock
);
3590 void cpu_exec_init_all(void)
3592 qemu_mutex_init(&ram_list
.mutex
);
3593 /* The data structures we set up here depend on knowing the page size,
3594 * so no more changes can be made after this point.
3595 * In an ideal world, nothing we did before we had finished the
3596 * machine setup would care about the target page size, and we could
3597 * do this much later, rather than requiring board models to state
3598 * up front what their requirements are.
3600 finalize_target_page_bits();
3603 qemu_mutex_init(&map_client_list_lock
);
3606 void cpu_unregister_map_client(QEMUBH
*bh
)
3610 qemu_mutex_lock(&map_client_list_lock
);
3611 QLIST_FOREACH(client
, &map_client_list
, link
) {
3612 if (client
->bh
== bh
) {
3613 cpu_unregister_map_client_do(client
);
3617 qemu_mutex_unlock(&map_client_list_lock
);
3620 static void cpu_notify_map_clients(void)
3622 qemu_mutex_lock(&map_client_list_lock
);
3623 cpu_notify_map_clients_locked();
3624 qemu_mutex_unlock(&map_client_list_lock
);
3627 static bool flatview_access_valid(FlatView
*fv
, hwaddr addr
, hwaddr len
,
3628 bool is_write
, MemTxAttrs attrs
)
3635 mr
= flatview_translate(fv
, addr
, &xlat
, &l
, is_write
, attrs
);
3636 if (!memory_access_is_direct(mr
, is_write
)) {
3637 l
= memory_access_size(mr
, l
, addr
);
3638 if (!memory_region_access_valid(mr
, xlat
, l
, is_write
, attrs
)) {
3649 bool address_space_access_valid(AddressSpace
*as
, hwaddr addr
,
3650 hwaddr len
, bool is_write
,
3657 fv
= address_space_to_flatview(as
);
3658 result
= flatview_access_valid(fv
, addr
, len
, is_write
, attrs
);
3664 flatview_extend_translation(FlatView
*fv
, hwaddr addr
,
3666 MemoryRegion
*mr
, hwaddr base
, hwaddr len
,
3667 bool is_write
, MemTxAttrs attrs
)
3671 MemoryRegion
*this_mr
;
3677 if (target_len
== 0) {
3682 this_mr
= flatview_translate(fv
, addr
, &xlat
,
3683 &len
, is_write
, attrs
);
3684 if (this_mr
!= mr
|| xlat
!= base
+ done
) {
3690 /* Map a physical memory region into a host virtual address.
3691 * May map a subset of the requested range, given by and returned in *plen.
3692 * May return NULL if resources needed to perform the mapping are exhausted.
3693 * Use only for reads OR writes - not for read-modify-write operations.
3694 * Use cpu_register_map_client() to know when retrying the map operation is
3695 * likely to succeed.
3697 void *address_space_map(AddressSpace
*as
,
3715 fv
= address_space_to_flatview(as
);
3716 mr
= flatview_translate(fv
, addr
, &xlat
, &l
, is_write
, attrs
);
3718 if (!memory_access_is_direct(mr
, is_write
)) {
3719 if (atomic_xchg(&bounce
.in_use
, true)) {
3723 /* Avoid unbounded allocations */
3724 l
= MIN(l
, TARGET_PAGE_SIZE
);
3725 bounce
.buffer
= qemu_memalign(TARGET_PAGE_SIZE
, l
);
3729 memory_region_ref(mr
);
3732 flatview_read(fv
, addr
, MEMTXATTRS_UNSPECIFIED
,
3738 return bounce
.buffer
;
3742 memory_region_ref(mr
);
3743 *plen
= flatview_extend_translation(fv
, addr
, len
, mr
, xlat
,
3744 l
, is_write
, attrs
);
3745 ptr
= qemu_ram_ptr_length(mr
->ram_block
, xlat
, plen
, true);
3751 /* Unmaps a memory region previously mapped by address_space_map().
3752 * Will also mark the memory as dirty if is_write == 1. access_len gives
3753 * the amount of memory that was actually read or written by the caller.
3755 void address_space_unmap(AddressSpace
*as
, void *buffer
, hwaddr len
,
3756 int is_write
, hwaddr access_len
)
3758 if (buffer
!= bounce
.buffer
) {
3762 mr
= memory_region_from_host(buffer
, &addr1
);
3765 invalidate_and_set_dirty(mr
, addr1
, access_len
);
3767 if (xen_enabled()) {
3768 xen_invalidate_map_cache_entry(buffer
);
3770 memory_region_unref(mr
);
3774 address_space_write(as
, bounce
.addr
, MEMTXATTRS_UNSPECIFIED
,
3775 bounce
.buffer
, access_len
);
3777 qemu_vfree(bounce
.buffer
);
3778 bounce
.buffer
= NULL
;
3779 memory_region_unref(bounce
.mr
);
3780 atomic_mb_set(&bounce
.in_use
, false);
3781 cpu_notify_map_clients();
3784 void *cpu_physical_memory_map(hwaddr addr
,
3788 return address_space_map(&address_space_memory
, addr
, plen
, is_write
,
3789 MEMTXATTRS_UNSPECIFIED
);
3792 void cpu_physical_memory_unmap(void *buffer
, hwaddr len
,
3793 int is_write
, hwaddr access_len
)
3795 return address_space_unmap(&address_space_memory
, buffer
, len
, is_write
, access_len
);
3798 #define ARG1_DECL AddressSpace *as
3801 #define TRANSLATE(...) address_space_translate(as, __VA_ARGS__)
3802 #define RCU_READ_LOCK(...) rcu_read_lock()
3803 #define RCU_READ_UNLOCK(...) rcu_read_unlock()
3804 #include "memory_ldst.inc.c"
3806 int64_t address_space_cache_init(MemoryRegionCache
*cache
,
3812 AddressSpaceDispatch
*d
;
3819 cache
->fv
= address_space_get_flatview(as
);
3820 d
= flatview_to_dispatch(cache
->fv
);
3821 cache
->mrs
= *address_space_translate_internal(d
, addr
, &cache
->xlat
, &l
, true);
3824 memory_region_ref(mr
);
3825 if (memory_access_is_direct(mr
, is_write
)) {
3826 /* We don't care about the memory attributes here as we're only
3827 * doing this if we found actual RAM, which behaves the same
3828 * regardless of attributes; so UNSPECIFIED is fine.
3830 l
= flatview_extend_translation(cache
->fv
, addr
, len
, mr
,
3831 cache
->xlat
, l
, is_write
,
3832 MEMTXATTRS_UNSPECIFIED
);
3833 cache
->ptr
= qemu_ram_ptr_length(mr
->ram_block
, cache
->xlat
, &l
, true);
3839 cache
->is_write
= is_write
;
3843 void address_space_cache_invalidate(MemoryRegionCache
*cache
,
3847 assert(cache
->is_write
);
3848 if (likely(cache
->ptr
)) {
3849 invalidate_and_set_dirty(cache
->mrs
.mr
, addr
+ cache
->xlat
, access_len
);
3853 void address_space_cache_destroy(MemoryRegionCache
*cache
)
3855 if (!cache
->mrs
.mr
) {
3859 if (xen_enabled()) {
3860 xen_invalidate_map_cache_entry(cache
->ptr
);
3862 memory_region_unref(cache
->mrs
.mr
);
3863 flatview_unref(cache
->fv
);
3864 cache
->mrs
.mr
= NULL
;
3868 /* Called from RCU critical section. This function has the same
3869 * semantics as address_space_translate, but it only works on a
3870 * predefined range of a MemoryRegion that was mapped with
3871 * address_space_cache_init.
3873 static inline MemoryRegion
*address_space_translate_cached(
3874 MemoryRegionCache
*cache
, hwaddr addr
, hwaddr
*xlat
,
3875 hwaddr
*plen
, bool is_write
, MemTxAttrs attrs
)
3877 MemoryRegionSection section
;
3879 IOMMUMemoryRegion
*iommu_mr
;
3880 AddressSpace
*target_as
;
3882 assert(!cache
->ptr
);
3883 *xlat
= addr
+ cache
->xlat
;
3886 iommu_mr
= memory_region_get_iommu(mr
);
3892 section
= address_space_translate_iommu(iommu_mr
, xlat
, plen
,
3893 NULL
, is_write
, true,
3898 /* Called from RCU critical section. address_space_read_cached uses this
3899 * out of line function when the target is an MMIO or IOMMU region.
3902 address_space_read_cached_slow(MemoryRegionCache
*cache
, hwaddr addr
,
3903 void *buf
, hwaddr len
)
3909 mr
= address_space_translate_cached(cache
, addr
, &addr1
, &l
, false,
3910 MEMTXATTRS_UNSPECIFIED
);
3911 flatview_read_continue(cache
->fv
,
3912 addr
, MEMTXATTRS_UNSPECIFIED
, buf
, len
,
3916 /* Called from RCU critical section. address_space_write_cached uses this
3917 * out of line function when the target is an MMIO or IOMMU region.
3920 address_space_write_cached_slow(MemoryRegionCache
*cache
, hwaddr addr
,
3921 const void *buf
, hwaddr len
)
3927 mr
= address_space_translate_cached(cache
, addr
, &addr1
, &l
, true,
3928 MEMTXATTRS_UNSPECIFIED
);
3929 flatview_write_continue(cache
->fv
,
3930 addr
, MEMTXATTRS_UNSPECIFIED
, buf
, len
,
3934 #define ARG1_DECL MemoryRegionCache *cache
3936 #define SUFFIX _cached_slow
3937 #define TRANSLATE(...) address_space_translate_cached(cache, __VA_ARGS__)
3938 #define RCU_READ_LOCK() ((void)0)
3939 #define RCU_READ_UNLOCK() ((void)0)
3940 #include "memory_ldst.inc.c"
3942 /* virtual memory access for debug (includes writing to ROM) */
3943 int cpu_memory_rw_debug(CPUState
*cpu
, target_ulong addr
,
3944 uint8_t *buf
, target_ulong len
, int is_write
)
3947 target_ulong l
, page
;
3949 cpu_synchronize_state(cpu
);
3954 page
= addr
& TARGET_PAGE_MASK
;
3955 phys_addr
= cpu_get_phys_page_attrs_debug(cpu
, page
, &attrs
);
3956 asidx
= cpu_asidx_from_attrs(cpu
, attrs
);
3957 /* if no physical page mapped, return an error */
3958 if (phys_addr
== -1)
3960 l
= (page
+ TARGET_PAGE_SIZE
) - addr
;
3963 phys_addr
+= (addr
& ~TARGET_PAGE_MASK
);
3965 address_space_write_rom(cpu
->cpu_ases
[asidx
].as
, phys_addr
,
3968 address_space_rw(cpu
->cpu_ases
[asidx
].as
, phys_addr
,
3979 * Allows code that needs to deal with migration bitmaps etc to still be built
3980 * target independent.
3982 size_t qemu_target_page_size(void)
3984 return TARGET_PAGE_SIZE
;
3987 int qemu_target_page_bits(void)
3989 return TARGET_PAGE_BITS
;
3992 int qemu_target_page_bits_min(void)
3994 return TARGET_PAGE_BITS_MIN
;
3998 bool target_words_bigendian(void)
4000 #if defined(TARGET_WORDS_BIGENDIAN)
4007 #ifndef CONFIG_USER_ONLY
4008 bool cpu_physical_memory_is_io(hwaddr phys_addr
)
4015 mr
= address_space_translate(&address_space_memory
,
4016 phys_addr
, &phys_addr
, &l
, false,
4017 MEMTXATTRS_UNSPECIFIED
);
4019 res
= !(memory_region_is_ram(mr
) || memory_region_is_romd(mr
));
4024 int qemu_ram_foreach_block(RAMBlockIterFunc func
, void *opaque
)
4030 RAMBLOCK_FOREACH(block
) {
4031 ret
= func(block
, opaque
);
4041 * Unmap pages of memory from start to start+length such that
4042 * they a) read as 0, b) Trigger whatever fault mechanism
4043 * the OS provides for postcopy.
4044 * The pages must be unmapped by the end of the function.
4045 * Returns: 0 on success, none-0 on failure
4048 int ram_block_discard_range(RAMBlock
*rb
, uint64_t start
, size_t length
)
4052 uint8_t *host_startaddr
= rb
->host
+ start
;
4054 if ((uintptr_t)host_startaddr
& (rb
->page_size
- 1)) {
4055 error_report("ram_block_discard_range: Unaligned start address: %p",
4060 if ((start
+ length
) <= rb
->used_length
) {
4061 bool need_madvise
, need_fallocate
;
4062 uint8_t *host_endaddr
= host_startaddr
+ length
;
4063 if ((uintptr_t)host_endaddr
& (rb
->page_size
- 1)) {
4064 error_report("ram_block_discard_range: Unaligned end address: %p",
4069 errno
= ENOTSUP
; /* If we are missing MADVISE etc */
4071 /* The logic here is messy;
4072 * madvise DONTNEED fails for hugepages
4073 * fallocate works on hugepages and shmem
4075 need_madvise
= (rb
->page_size
== qemu_host_page_size
);
4076 need_fallocate
= rb
->fd
!= -1;
4077 if (need_fallocate
) {
4078 /* For a file, this causes the area of the file to be zero'd
4079 * if read, and for hugetlbfs also causes it to be unmapped
4080 * so a userfault will trigger.
4082 #ifdef CONFIG_FALLOCATE_PUNCH_HOLE
4083 ret
= fallocate(rb
->fd
, FALLOC_FL_PUNCH_HOLE
| FALLOC_FL_KEEP_SIZE
,
4087 error_report("ram_block_discard_range: Failed to fallocate "
4088 "%s:%" PRIx64
" +%zx (%d)",
4089 rb
->idstr
, start
, length
, ret
);
4094 error_report("ram_block_discard_range: fallocate not available/file"
4095 "%s:%" PRIx64
" +%zx (%d)",
4096 rb
->idstr
, start
, length
, ret
);
4101 /* For normal RAM this causes it to be unmapped,
4102 * for shared memory it causes the local mapping to disappear
4103 * and to fall back on the file contents (which we just
4104 * fallocate'd away).
4106 #if defined(CONFIG_MADVISE)
4107 ret
= madvise(host_startaddr
, length
, MADV_DONTNEED
);
4110 error_report("ram_block_discard_range: Failed to discard range "
4111 "%s:%" PRIx64
" +%zx (%d)",
4112 rb
->idstr
, start
, length
, ret
);
4117 error_report("ram_block_discard_range: MADVISE not available"
4118 "%s:%" PRIx64
" +%zx (%d)",
4119 rb
->idstr
, start
, length
, ret
);
4123 trace_ram_block_discard_range(rb
->idstr
, host_startaddr
, length
,
4124 need_madvise
, need_fallocate
, ret
);
4126 error_report("ram_block_discard_range: Overrun block '%s' (%" PRIu64
4127 "/%zx/" RAM_ADDR_FMT
")",
4128 rb
->idstr
, start
, length
, rb
->used_length
);
4135 bool ramblock_is_pmem(RAMBlock
*rb
)
4137 return rb
->flags
& RAM_PMEM
;
4142 void page_size_init(void)
4144 /* NOTE: we can always suppose that qemu_host_page_size >=
4146 if (qemu_host_page_size
== 0) {
4147 qemu_host_page_size
= qemu_real_host_page_size
;
4149 if (qemu_host_page_size
< TARGET_PAGE_SIZE
) {
4150 qemu_host_page_size
= TARGET_PAGE_SIZE
;
4152 qemu_host_page_mask
= -(intptr_t)qemu_host_page_size
;
4155 #if !defined(CONFIG_USER_ONLY)
4157 static void mtree_print_phys_entries(int start
, int end
, int skip
, int ptr
)
4159 if (start
== end
- 1) {
4160 qemu_printf("\t%3d ", start
);
4162 qemu_printf("\t%3d..%-3d ", start
, end
- 1);
4164 qemu_printf(" skip=%d ", skip
);
4165 if (ptr
== PHYS_MAP_NODE_NIL
) {
4166 qemu_printf(" ptr=NIL");
4168 qemu_printf(" ptr=#%d", ptr
);
4170 qemu_printf(" ptr=[%d]", ptr
);
4175 #define MR_SIZE(size) (int128_nz(size) ? (hwaddr)int128_get64( \
4176 int128_sub((size), int128_one())) : 0)
4178 void mtree_print_dispatch(AddressSpaceDispatch
*d
, MemoryRegion
*root
)
4182 qemu_printf(" Dispatch\n");
4183 qemu_printf(" Physical sections\n");
4185 for (i
= 0; i
< d
->map
.sections_nb
; ++i
) {
4186 MemoryRegionSection
*s
= d
->map
.sections
+ i
;
4187 const char *names
[] = { " [unassigned]", " [not dirty]",
4188 " [ROM]", " [watch]" };
4190 qemu_printf(" #%d @" TARGET_FMT_plx
".." TARGET_FMT_plx
4193 s
->offset_within_address_space
,
4194 s
->offset_within_address_space
+ MR_SIZE(s
->mr
->size
),
4195 s
->mr
->name
? s
->mr
->name
: "(noname)",
4196 i
< ARRAY_SIZE(names
) ? names
[i
] : "",
4197 s
->mr
== root
? " [ROOT]" : "",
4198 s
== d
->mru_section
? " [MRU]" : "",
4199 s
->mr
->is_iommu
? " [iommu]" : "");
4202 qemu_printf(" alias=%s", s
->mr
->alias
->name
?
4203 s
->mr
->alias
->name
: "noname");
4208 qemu_printf(" Nodes (%d bits per level, %d levels) ptr=[%d] skip=%d\n",
4209 P_L2_BITS
, P_L2_LEVELS
, d
->phys_map
.ptr
, d
->phys_map
.skip
);
4210 for (i
= 0; i
< d
->map
.nodes_nb
; ++i
) {
4213 Node
*n
= d
->map
.nodes
+ i
;
4215 qemu_printf(" [%d]\n", i
);
4217 for (j
= 0, jprev
= 0, prev
= *n
[0]; j
< ARRAY_SIZE(*n
); ++j
) {
4218 PhysPageEntry
*pe
= *n
+ j
;
4220 if (pe
->ptr
== prev
.ptr
&& pe
->skip
== prev
.skip
) {
4224 mtree_print_phys_entries(jprev
, j
, prev
.skip
, prev
.ptr
);
4230 if (jprev
!= ARRAY_SIZE(*n
)) {
4231 mtree_print_phys_entries(jprev
, j
, prev
.skip
, prev
.ptr
);