target-microblaze/op_helper.c

   1 /*
   2  *  Microblaze helper routines.
   3  *
   4  *  Copyright (c) 2009 Edgar E. Iglesias <edgar.iglesias@gmail.com>.
   5  *  Copyright (c) 2009-2012 PetaLogix Qld Pty Ltd.
   6  *
   7  * This library is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU Lesser General Public
   9  * License as published by the Free Software Foundation; either
  10  * version 2 of the License, or (at your option) any later version.
  11  *
  12  * This library is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * Lesser General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU Lesser General Public
  18  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  19  */
  20
  21 #include "qemu/osdep.h"
  22 #include "cpu.h"
  23 #include "exec/helper-proto.h"
  24 #include "qemu/host-utils.h"
  25 #include "exec/cpu_ldst.h"
  26
  27 #define D(x)
  28
  29 #if !defined(CONFIG_USER_ONLY)
  30
  31 /* Try to fill the TLB and return an exception if error. If retaddr is
  32  * NULL, it means that the function was called in C code (i.e. not
  33  * from generated code or from helper.c)
  34  */
  35 void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx,
  36               uintptr_t retaddr)
  37 {
  38     int ret;
  39
  40     ret = mb_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx);
  41     if (unlikely(ret)) {
  42         if (retaddr) {
  43             /* now we have a real cpu fault */
  44             cpu_restore_state(cs, retaddr);
  45         }
  46         cpu_loop_exit(cs);
  47     }
  48 }
  49 #endif
  50
  51 void helper_put(uint32_t id, uint32_t ctrl, uint32_t data)
  52 {
  53     int test = ctrl & STREAM_TEST;
  54     int atomic = ctrl & STREAM_ATOMIC;
  55     int control = ctrl & STREAM_CONTROL;
  56     int nonblock = ctrl & STREAM_NONBLOCK;
  57     int exception = ctrl & STREAM_EXCEPTION;
  58
  59     qemu_log_mask(LOG_UNIMP, "Unhandled stream put to stream-id=%d data=%x %s%s%s%s%s\n",
  60              id, data,
  61              test ? "t" : "",
  62              nonblock ? "n" : "",
  63              exception ? "e" : "",
  64              control ? "c" : "",
  65              atomic ? "a" : "");
  66 }
  67
  68 uint32_t helper_get(uint32_t id, uint32_t ctrl)
  69 {
  70     int test = ctrl & STREAM_TEST;
  71     int atomic = ctrl & STREAM_ATOMIC;
  72     int control = ctrl & STREAM_CONTROL;
  73     int nonblock = ctrl & STREAM_NONBLOCK;
  74     int exception = ctrl & STREAM_EXCEPTION;
  75
  76     qemu_log_mask(LOG_UNIMP, "Unhandled stream get from stream-id=%d %s%s%s%s%s\n",
  77              id,
  78              test ? "t" : "",
  79              nonblock ? "n" : "",
  80              exception ? "e" : "",
  81              control ? "c" : "",
  82              atomic ? "a" : "");
  83     return 0xdead0000 | id;
  84 }
  85
  86 void helper_raise_exception(CPUMBState *env, uint32_t index)
  87 {
  88     CPUState *cs = CPU(mb_env_get_cpu(env));
  89
  90     cs->exception_index = index;
  91     cpu_loop_exit(cs);
  92 }
  93
  94 void helper_debug(CPUMBState *env)
  95 {
  96     int i;
  97
  98     qemu_log("PC=%8.8x\n", env->sregs[SR_PC]);
  99     qemu_log("rmsr=%x resr=%x rear=%x debug[%x] imm=%x iflags=%x\n",
 100              env->sregs[SR_MSR], env->sregs[SR_ESR], env->sregs[SR_EAR],
 101              env->debug, env->imm, env->iflags);
 102     qemu_log("btaken=%d btarget=%x mode=%s(saved=%s) eip=%d ie=%d\n",
 103              env->btaken, env->btarget,
 104              (env->sregs[SR_MSR] & MSR_UM) ? "user" : "kernel",
 105              (env->sregs[SR_MSR] & MSR_UMS) ? "user" : "kernel",
 106              (env->sregs[SR_MSR] & MSR_EIP),
 107              (env->sregs[SR_MSR] & MSR_IE));
 108     for (i = 0; i < 32; i++) {
 109         qemu_log("r%2.2d=%8.8x ", i, env->regs[i]);
 110         if ((i + 1) % 4 == 0)
 111             qemu_log("\n");
 112     }
 113     qemu_log("\n\n");
 114 }
 115
 116 static inline uint32_t compute_carry(uint32_t a, uint32_t b, uint32_t cin)
 117 {
 118     uint32_t cout = 0;
 119
 120     if ((b == ~0) && cin)
 121         cout = 1;
 122     else if ((~0 - a) < (b + cin))
 123         cout = 1;
 124     return cout;
 125 }
 126
 127 uint32_t helper_cmp(uint32_t a, uint32_t b)
 128 {
 129     uint32_t t;
 130
 131     t = b + ~a + 1;
 132     if ((b & 0x80000000) ^ (a & 0x80000000))
 133         t = (t & 0x7fffffff) | (b & 0x80000000);
 134     return t;
 135 }
 136
 137 uint32_t helper_cmpu(uint32_t a, uint32_t b)
 138 {
 139     uint32_t t;
 140
 141     t = b + ~a + 1;
 142     if ((b & 0x80000000) ^ (a & 0x80000000))
 143         t = (t & 0x7fffffff) | (a & 0x80000000);
 144     return t;
 145 }
 146
 147 uint32_t helper_clz(uint32_t t0)
 148 {
 149     return clz32(t0);
 150 }
 151
 152 uint32_t helper_carry(uint32_t a, uint32_t b, uint32_t cf)
 153 {
 154     return compute_carry(a, b, cf);
 155 }
 156
 157 static inline int div_prepare(CPUMBState *env, uint32_t a, uint32_t b)
 158 {
 159     if (b == 0) {
 160         env->sregs[SR_MSR] |= MSR_DZ;
 161
 162         if ((env->sregs[SR_MSR] & MSR_EE)
 163             && !(env->pvr.regs[2] & PVR2_DIV_ZERO_EXC_MASK)) {
 164             env->sregs[SR_ESR] = ESR_EC_DIVZERO;
 165             helper_raise_exception(env, EXCP_HW_EXCP);
 166         }
 167         return 0;
 168     }
 169     env->sregs[SR_MSR] &= ~MSR_DZ;
 170     return 1;
 171 }
 172
 173 uint32_t helper_divs(CPUMBState *env, uint32_t a, uint32_t b)
 174 {
 175     if (!div_prepare(env, a, b)) {
 176         return 0;
 177     }
 178     return (int32_t)a / (int32_t)b;
 179 }
 180
 181 uint32_t helper_divu(CPUMBState *env, uint32_t a, uint32_t b)
 182 {
 183     if (!div_prepare(env, a, b)) {
 184         return 0;
 185     }
 186     return a / b;
 187 }
 188
 189 /* raise FPU exception.  */
 190 static void raise_fpu_exception(CPUMBState *env)
 191 {
 192     env->sregs[SR_ESR] = ESR_EC_FPU;
 193     helper_raise_exception(env, EXCP_HW_EXCP);
 194 }
 195
 196 static void update_fpu_flags(CPUMBState *env, int flags)
 197 {
 198     int raise = 0;
 199
 200     if (flags & float_flag_invalid) {
 201         env->sregs[SR_FSR] |= FSR_IO;
 202         raise = 1;
 203     }
 204     if (flags & float_flag_divbyzero) {
 205         env->sregs[SR_FSR] |= FSR_DZ;
 206         raise = 1;
 207     }
 208     if (flags & float_flag_overflow) {
 209         env->sregs[SR_FSR] |= FSR_OF;
 210         raise = 1;
 211     }
 212     if (flags & float_flag_underflow) {
 213         env->sregs[SR_FSR] |= FSR_UF;
 214         raise = 1;
 215     }
 216     if (raise
 217         && (env->pvr.regs[2] & PVR2_FPU_EXC_MASK)
 218         && (env->sregs[SR_MSR] & MSR_EE)) {
 219         raise_fpu_exception(env);
 220     }
 221 }
 222
 223 uint32_t helper_fadd(CPUMBState *env, uint32_t a, uint32_t b)
 224 {
 225     CPU_FloatU fd, fa, fb;
 226     int flags;
 227
 228     set_float_exception_flags(0, &env->fp_status);
 229     fa.l = a;
 230     fb.l = b;
 231     fd.f = float32_add(fa.f, fb.f, &env->fp_status);
 232
 233     flags = get_float_exception_flags(&env->fp_status);
 234     update_fpu_flags(env, flags);
 235     return fd.l;
 236 }
 237
 238 uint32_t helper_frsub(CPUMBState *env, uint32_t a, uint32_t b)
 239 {
 240     CPU_FloatU fd, fa, fb;
 241     int flags;
 242
 243     set_float_exception_flags(0, &env->fp_status);
 244     fa.l = a;
 245     fb.l = b;
 246     fd.f = float32_sub(fb.f, fa.f, &env->fp_status);
 247     flags = get_float_exception_flags(&env->fp_status);
 248     update_fpu_flags(env, flags);
 249     return fd.l;
 250 }
 251
 252 uint32_t helper_fmul(CPUMBState *env, uint32_t a, uint32_t b)
 253 {
 254     CPU_FloatU fd, fa, fb;
 255     int flags;
 256
 257     set_float_exception_flags(0, &env->fp_status);
 258     fa.l = a;
 259     fb.l = b;
 260     fd.f = float32_mul(fa.f, fb.f, &env->fp_status);
 261     flags = get_float_exception_flags(&env->fp_status);
 262     update_fpu_flags(env, flags);
 263
 264     return fd.l;
 265 }
 266
 267 uint32_t helper_fdiv(CPUMBState *env, uint32_t a, uint32_t b)
 268 {
 269     CPU_FloatU fd, fa, fb;
 270     int flags;
 271
 272     set_float_exception_flags(0, &env->fp_status);
 273     fa.l = a;
 274     fb.l = b;
 275     fd.f = float32_div(fb.f, fa.f, &env->fp_status);
 276     flags = get_float_exception_flags(&env->fp_status);
 277     update_fpu_flags(env, flags);
 278
 279     return fd.l;
 280 }
 281
 282 uint32_t helper_fcmp_un(CPUMBState *env, uint32_t a, uint32_t b)
 283 {
 284     CPU_FloatU fa, fb;
 285     uint32_t r = 0;
 286
 287     fa.l = a;
 288     fb.l = b;
 289
 290     if (float32_is_signaling_nan(fa.f) || float32_is_signaling_nan(fb.f)) {
 291         update_fpu_flags(env, float_flag_invalid);
 292         r = 1;
 293     }
 294
 295     if (float32_is_quiet_nan(fa.f) || float32_is_quiet_nan(fb.f)) {
 296         r = 1;
 297     }
 298
 299     return r;
 300 }
 301
 302 uint32_t helper_fcmp_lt(CPUMBState *env, uint32_t a, uint32_t b)
 303 {
 304     CPU_FloatU fa, fb;
 305     int r;
 306     int flags;
 307
 308     set_float_exception_flags(0, &env->fp_status);
 309     fa.l = a;
 310     fb.l = b;
 311     r = float32_lt(fb.f, fa.f, &env->fp_status);
 312     flags = get_float_exception_flags(&env->fp_status);
 313     update_fpu_flags(env, flags & float_flag_invalid);
 314
 315     return r;
 316 }
 317
 318 uint32_t helper_fcmp_eq(CPUMBState *env, uint32_t a, uint32_t b)
 319 {
 320     CPU_FloatU fa, fb;
 321     int flags;
 322     int r;
 323
 324     set_float_exception_flags(0, &env->fp_status);
 325     fa.l = a;
 326     fb.l = b;
 327     r = float32_eq_quiet(fa.f, fb.f, &env->fp_status);
 328     flags = get_float_exception_flags(&env->fp_status);
 329     update_fpu_flags(env, flags & float_flag_invalid);
 330
 331     return r;
 332 }
 333
 334 uint32_t helper_fcmp_le(CPUMBState *env, uint32_t a, uint32_t b)
 335 {
 336     CPU_FloatU fa, fb;
 337     int flags;
 338     int r;
 339
 340     fa.l = a;
 341     fb.l = b;
 342     set_float_exception_flags(0, &env->fp_status);
 343     r = float32_le(fa.f, fb.f, &env->fp_status);
 344     flags = get_float_exception_flags(&env->fp_status);
 345     update_fpu_flags(env, flags & float_flag_invalid);
 346
 347
 348     return r;
 349 }
 350
 351 uint32_t helper_fcmp_gt(CPUMBState *env, uint32_t a, uint32_t b)
 352 {
 353     CPU_FloatU fa, fb;
 354     int flags, r;
 355
 356     fa.l = a;
 357     fb.l = b;
 358     set_float_exception_flags(0, &env->fp_status);
 359     r = float32_lt(fa.f, fb.f, &env->fp_status);
 360     flags = get_float_exception_flags(&env->fp_status);
 361     update_fpu_flags(env, flags & float_flag_invalid);
 362     return r;
 363 }
 364
 365 uint32_t helper_fcmp_ne(CPUMBState *env, uint32_t a, uint32_t b)
 366 {
 367     CPU_FloatU fa, fb;
 368     int flags, r;
 369
 370     fa.l = a;
 371     fb.l = b;
 372     set_float_exception_flags(0, &env->fp_status);
 373     r = !float32_eq_quiet(fa.f, fb.f, &env->fp_status);
 374     flags = get_float_exception_flags(&env->fp_status);
 375     update_fpu_flags(env, flags & float_flag_invalid);
 376
 377     return r;
 378 }
 379
 380 uint32_t helper_fcmp_ge(CPUMBState *env, uint32_t a, uint32_t b)
 381 {
 382     CPU_FloatU fa, fb;
 383     int flags, r;
 384
 385     fa.l = a;
 386     fb.l = b;
 387     set_float_exception_flags(0, &env->fp_status);
 388     r = !float32_lt(fa.f, fb.f, &env->fp_status);
 389     flags = get_float_exception_flags(&env->fp_status);
 390     update_fpu_flags(env, flags & float_flag_invalid);
 391
 392     return r;
 393 }
 394
 395 uint32_t helper_flt(CPUMBState *env, uint32_t a)
 396 {
 397     CPU_FloatU fd, fa;
 398
 399     fa.l = a;
 400     fd.f = int32_to_float32(fa.l, &env->fp_status);
 401     return fd.l;
 402 }
 403
 404 uint32_t helper_fint(CPUMBState *env, uint32_t a)
 405 {
 406     CPU_FloatU fa;
 407     uint32_t r;
 408     int flags;
 409
 410     set_float_exception_flags(0, &env->fp_status);
 411     fa.l = a;
 412     r = float32_to_int32(fa.f, &env->fp_status);
 413     flags = get_float_exception_flags(&env->fp_status);
 414     update_fpu_flags(env, flags);
 415
 416     return r;
 417 }
 418
 419 uint32_t helper_fsqrt(CPUMBState *env, uint32_t a)
 420 {
 421     CPU_FloatU fd, fa;
 422     int flags;
 423
 424     set_float_exception_flags(0, &env->fp_status);
 425     fa.l = a;
 426     fd.l = float32_sqrt(fa.f, &env->fp_status);
 427     flags = get_float_exception_flags(&env->fp_status);
 428     update_fpu_flags(env, flags);
 429
 430     return fd.l;
 431 }
 432
 433 uint32_t helper_pcmpbf(uint32_t a, uint32_t b)
 434 {
 435     unsigned int i;
 436     uint32_t mask = 0xff000000;
 437
 438     for (i = 0; i < 4; i++) {
 439         if ((a & mask) == (b & mask))
 440             return i + 1;
 441         mask >>= 8;
 442     }
 443     return 0;
 444 }
 445
 446 void helper_memalign(CPUMBState *env, uint32_t addr, uint32_t dr, uint32_t wr,
 447                      uint32_t mask)
 448 {
 449     if (addr & mask) {
 450             qemu_log_mask(CPU_LOG_INT,
 451                           "unaligned access addr=%x mask=%x, wr=%d dr=r%d\n",
 452                           addr, mask, wr, dr);
 453             env->sregs[SR_EAR] = addr;
 454             env->sregs[SR_ESR] = ESR_EC_UNALIGNED_DATA | (wr << 10) \
 455                                  | (dr & 31) << 5;
 456             if (mask == 3) {
 457                 env->sregs[SR_ESR] |= 1 << 11;
 458             }
 459             if (!(env->sregs[SR_MSR] & MSR_EE)) {
 460                 return;
 461             }
 462             helper_raise_exception(env, EXCP_HW_EXCP);
 463     }
 464 }
 465
 466 void helper_stackprot(CPUMBState *env, uint32_t addr)
 467 {
 468     if (addr < env->slr || addr > env->shr) {
 469         qemu_log_mask(CPU_LOG_INT, "Stack protector violation at %x %x %x\n",
 470                       addr, env->slr, env->shr);
 471         env->sregs[SR_EAR] = addr;
 472         env->sregs[SR_ESR] = ESR_EC_STACKPROT;
 473         helper_raise_exception(env, EXCP_HW_EXCP);
 474     }
 475 }
 476
 477 #if !defined(CONFIG_USER_ONLY)
 478 /* Writes/reads to the MMU's special regs end up here.  */
 479 uint32_t helper_mmu_read(CPUMBState *env, uint32_t rn)
 480 {
 481     return mmu_read(env, rn);
 482 }
 483
 484 void helper_mmu_write(CPUMBState *env, uint32_t rn, uint32_t v)
 485 {
 486     mmu_write(env, rn, v);
 487 }
 488
 489 void mb_cpu_unassigned_access(CPUState *cs, hwaddr addr,
 490                               bool is_write, bool is_exec, int is_asi,
 491                               unsigned size)
 492 {
 493     MicroBlazeCPU *cpu;
 494     CPUMBState *env;
 495
 496     qemu_log_mask(CPU_LOG_INT, "Unassigned " TARGET_FMT_plx " wr=%d exe=%d\n",
 497              addr, is_write ? 1 : 0, is_exec ? 1 : 0);
 498     if (cs == NULL) {
 499         return;
 500     }
 501     cpu = MICROBLAZE_CPU(cs);
 502     env = &cpu->env;
 503     if (!(env->sregs[SR_MSR] & MSR_EE)) {
 504         return;
 505     }
 506
 507     env->sregs[SR_EAR] = addr;
 508     if (is_exec) {
 509         if ((env->pvr.regs[2] & PVR2_IOPB_BUS_EXC_MASK)) {
 510             env->sregs[SR_ESR] = ESR_EC_INSN_BUS;
 511             helper_raise_exception(env, EXCP_HW_EXCP);
 512         }
 513     } else {
 514         if ((env->pvr.regs[2] & PVR2_DOPB_BUS_EXC_MASK)) {
 515             env->sregs[SR_ESR] = ESR_EC_DATA_BUS;
 516             helper_raise_exception(env, EXCP_HW_EXCP);
 517         }
 518     }
 519 }
 520 #endif