hw/etraxfs_ser.c

   1 /*
   2  * QEMU ETRAX System Emulator
   3  *
   4  * Copyright (c) 2007 Edgar E. Iglesias, Axis Communications AB.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "sysbus.h"
  26 #include "qemu-char.h"
  27 #include "qemu-log.h"
  28
  29 #define D(x)
  30
  31 #define RW_TR_CTRL     (0x00 / 4)
  32 #define RW_TR_DMA_EN   (0x04 / 4)
  33 #define RW_REC_CTRL    (0x08 / 4)
  34 #define RW_DOUT        (0x1c / 4)
  35 #define RS_STAT_DIN    (0x20 / 4)
  36 #define R_STAT_DIN     (0x24 / 4)
  37 #define RW_INTR_MASK   (0x2c / 4)
  38 #define RW_ACK_INTR    (0x30 / 4)
  39 #define R_INTR         (0x34 / 4)
  40 #define R_MASKED_INTR  (0x38 / 4)
  41 #define R_MAX          (0x3c / 4)
  42
  43 #define STAT_DAV     16
  44 #define STAT_TR_IDLE 22
  45 #define STAT_TR_RDY  24
  46
  47 struct etrax_serial
  48 {
  49     SysBusDevice busdev;
  50     CharDriverState *chr;
  51     qemu_irq irq;
  52
  53     int pending_tx;
  54
  55     uint8_t rx_fifo[16];
  56     unsigned int rx_fifo_pos;
  57     unsigned int rx_fifo_len;
  58
  59     /* Control registers.  */
  60     uint32_t regs[R_MAX];
  61 };
  62
  63 static void ser_update_irq(struct etrax_serial *s)
  64 {
  65
  66     if (s->rx_fifo_len) {
  67         s->regs[R_INTR] |= 8;
  68     } else {
  69         s->regs[R_INTR] &= ~8;
  70     }
  71
  72     s->regs[R_MASKED_INTR] = s->regs[R_INTR] & s->regs[RW_INTR_MASK];
  73     qemu_set_irq(s->irq, !!s->regs[R_MASKED_INTR]);
  74 }
  75
  76 static uint32_t ser_readl (void *opaque, target_phys_addr_t addr)
  77 {
  78     struct etrax_serial *s = opaque;
  79     D(CPUState *env = s->env);
  80     uint32_t r = 0;
  81
  82     addr >>= 2;
  83     switch (addr)
  84     {
  85         case R_STAT_DIN:
  86             r = s->rx_fifo[(s->rx_fifo_pos - s->rx_fifo_len) & 15];
  87             if (s->rx_fifo_len) {
  88                 r |= 1 << STAT_DAV;
  89             }
  90             r |= 1 << STAT_TR_RDY;
  91             r |= 1 << STAT_TR_IDLE;
  92             break;
  93         case RS_STAT_DIN:
  94             r = s->rx_fifo[(s->rx_fifo_pos - s->rx_fifo_len) & 15];
  95             if (s->rx_fifo_len) {
  96                 r |= 1 << STAT_DAV;
  97                 s->rx_fifo_len--;
  98             }
  99             r |= 1 << STAT_TR_RDY;
 100             r |= 1 << STAT_TR_IDLE;
 101             break;
 102         default:
 103             r = s->regs[addr];
 104             D(qemu_log("%s " TARGET_FMT_plx "=%x\n", __func__, addr, r));
 105             break;
 106     }
 107     return r;
 108 }
 109
 110 static void
 111 ser_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
 112 {
 113     struct etrax_serial *s = opaque;
 114     unsigned char ch = value;
 115     D(CPUState *env = s->env);
 116
 117     D(qemu_log("%s " TARGET_FMT_plx "=%x\n",  __func__, addr, value));
 118     addr >>= 2;
 119     switch (addr)
 120     {
 121         case RW_DOUT:
 122             qemu_chr_fe_write(s->chr, &ch, 1);
 123             s->regs[R_INTR] |= 3;
 124             s->pending_tx = 1;
 125             s->regs[addr] = value;
 126             break;
 127         case RW_ACK_INTR:
 128             if (s->pending_tx) {
 129                 value &= ~1;
 130                 s->pending_tx = 0;
 131                 D(qemu_log("fixedup value=%x r_intr=%x\n",
 132                            value, s->regs[R_INTR]));
 133             }
 134             s->regs[addr] = value;
 135             s->regs[R_INTR] &= ~value;
 136             D(printf("r_intr=%x\n", s->regs[R_INTR]));
 137             break;
 138         default:
 139             s->regs[addr] = value;
 140             break;
 141     }
 142     ser_update_irq(s);
 143 }
 144
 145 static CPUReadMemoryFunc * const ser_read[] = {
 146     NULL, NULL,
 147     &ser_readl,
 148 };
 149
 150 static CPUWriteMemoryFunc * const ser_write[] = {
 151     NULL, NULL,
 152     &ser_writel,
 153 };
 154
 155 static void serial_receive(void *opaque, const uint8_t *buf, int size)
 156 {
 157     struct etrax_serial *s = opaque;
 158     int i;
 159
 160     /* Got a byte.  */
 161     if (s->rx_fifo_len >= 16) {
 162         qemu_log("WARNING: UART dropped char.\n");
 163         return;
 164     }
 165
 166     for (i = 0; i < size; i++) {
 167         s->rx_fifo[s->rx_fifo_pos] = buf[i];
 168         s->rx_fifo_pos++;
 169         s->rx_fifo_pos &= 15;
 170         s->rx_fifo_len++;
 171     }
 172
 173     ser_update_irq(s);
 174 }
 175
 176 static int serial_can_receive(void *opaque)
 177 {
 178     struct etrax_serial *s = opaque;
 179     int r;
 180
 181     /* Is the receiver enabled?  */
 182     if (!(s->regs[RW_REC_CTRL] & (1 << 3))) {
 183         return 0;
 184     }
 185
 186     r = sizeof(s->rx_fifo) - s->rx_fifo_len;
 187     return r;
 188 }
 189
 190 static void serial_event(void *opaque, int event)
 191 {
 192
 193 }
 194
 195 static void etraxfs_ser_reset(DeviceState *d)
 196 {
 197     struct etrax_serial *s = container_of(d, typeof(*s), busdev.qdev);
 198
 199     /* transmitter begins ready and idle.  */
 200     s->regs[RS_STAT_DIN] |= (1 << STAT_TR_RDY);
 201     s->regs[RS_STAT_DIN] |= (1 << STAT_TR_IDLE);
 202
 203     s->regs[RW_REC_CTRL] = 0x10000;
 204
 205 }
 206
 207 static int etraxfs_ser_init(SysBusDevice *dev)
 208 {
 209     struct etrax_serial *s = FROM_SYSBUS(typeof (*s), dev);
 210     int ser_regs;
 211
 212     sysbus_init_irq(dev, &s->irq);
 213     ser_regs = cpu_register_io_memory(ser_read, ser_write, s,
 214                                       DEVICE_NATIVE_ENDIAN);
 215     sysbus_init_mmio(dev, R_MAX * 4, ser_regs);
 216     s->chr = qdev_init_chardev(&dev->qdev);
 217     if (s->chr)
 218         qemu_chr_add_handlers(s->chr,
 219                       serial_can_receive, serial_receive,
 220                       serial_event, s);
 221     return 0;
 222 }
 223
 224 static SysBusDeviceInfo etraxfs_ser_info = {
 225     .init = etraxfs_ser_init,
 226     .qdev.name  = "etraxfs,serial",
 227     .qdev.size  = sizeof(struct etrax_serial),
 228     .qdev.reset = etraxfs_ser_reset,
 229 };
 230
 231 static void etraxfs_serial_register(void)
 232 {
 233     sysbus_register_withprop(&etraxfs_ser_info);
 234 }
 235
 236 device_init(etraxfs_serial_register)