2 * TriCore emulation for qemu: main translation routines.
4 * Copyright (c) 2013-2014 Bastian Koppelmann C-Lab/University Paderborn
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
21 #include "qemu/osdep.h"
23 #include "disas/disas.h"
24 #include "exec/exec-all.h"
26 #include "exec/cpu_ldst.h"
28 #include "exec/helper-proto.h"
29 #include "exec/helper-gen.h"
31 #include "tricore-opcodes.h"
42 static TCGv cpu_gpr_a
[16];
43 static TCGv cpu_gpr_d
[16];
45 static TCGv cpu_PSW_C
;
46 static TCGv cpu_PSW_V
;
47 static TCGv cpu_PSW_SV
;
48 static TCGv cpu_PSW_AV
;
49 static TCGv cpu_PSW_SAV
;
51 static TCGv_env cpu_env
;
53 #include "exec/gen-icount.h"
55 static const char *regnames_a
[] = {
56 "a0" , "a1" , "a2" , "a3" , "a4" , "a5" ,
57 "a6" , "a7" , "a8" , "a9" , "sp" , "a11" ,
58 "a12" , "a13" , "a14" , "a15",
61 static const char *regnames_d
[] = {
62 "d0" , "d1" , "d2" , "d3" , "d4" , "d5" ,
63 "d6" , "d7" , "d8" , "d9" , "d10" , "d11" ,
64 "d12" , "d13" , "d14" , "d15",
67 typedef struct DisasContext
{
68 struct TranslationBlock
*tb
;
69 target_ulong pc
, saved_pc
, next_pc
;
71 int singlestep_enabled
;
72 /* Routine used to access memory */
74 uint32_t hflags
, saved_hflags
;
93 void tricore_cpu_dump_state(CPUState
*cs
, FILE *f
,
94 fprintf_function cpu_fprintf
, int flags
)
96 TriCoreCPU
*cpu
= TRICORE_CPU(cs
);
97 CPUTriCoreState
*env
= &cpu
->env
;
103 cpu_fprintf(f
, "PC: " TARGET_FMT_lx
, env
->PC
);
104 cpu_fprintf(f
, " PSW: " TARGET_FMT_lx
, psw
);
105 cpu_fprintf(f
, " ICR: " TARGET_FMT_lx
, env
->ICR
);
106 cpu_fprintf(f
, "\nPCXI: " TARGET_FMT_lx
, env
->PCXI
);
107 cpu_fprintf(f
, " FCX: " TARGET_FMT_lx
, env
->FCX
);
108 cpu_fprintf(f
, " LCX: " TARGET_FMT_lx
, env
->LCX
);
110 for (i
= 0; i
< 16; ++i
) {
112 cpu_fprintf(f
, "\nGPR A%02d:", i
);
114 cpu_fprintf(f
, " " TARGET_FMT_lx
, env
->gpr_a
[i
]);
116 for (i
= 0; i
< 16; ++i
) {
118 cpu_fprintf(f
, "\nGPR D%02d:", i
);
120 cpu_fprintf(f
, " " TARGET_FMT_lx
, env
->gpr_d
[i
]);
122 cpu_fprintf(f
, "\n");
126 * Functions to generate micro-ops
129 /* Makros for generating helpers */
131 #define gen_helper_1arg(name, arg) do { \
132 TCGv_i32 helper_tmp = tcg_const_i32(arg); \
133 gen_helper_##name(cpu_env, helper_tmp); \
134 tcg_temp_free_i32(helper_tmp); \
137 #define GEN_HELPER_LL(name, ret, arg0, arg1, n) do { \
138 TCGv arg00 = tcg_temp_new(); \
139 TCGv arg01 = tcg_temp_new(); \
140 TCGv arg11 = tcg_temp_new(); \
141 tcg_gen_sari_tl(arg00, arg0, 16); \
142 tcg_gen_ext16s_tl(arg01, arg0); \
143 tcg_gen_ext16s_tl(arg11, arg1); \
144 gen_helper_##name(ret, arg00, arg01, arg11, arg11, n); \
145 tcg_temp_free(arg00); \
146 tcg_temp_free(arg01); \
147 tcg_temp_free(arg11); \
150 #define GEN_HELPER_LU(name, ret, arg0, arg1, n) do { \
151 TCGv arg00 = tcg_temp_new(); \
152 TCGv arg01 = tcg_temp_new(); \
153 TCGv arg10 = tcg_temp_new(); \
154 TCGv arg11 = tcg_temp_new(); \
155 tcg_gen_sari_tl(arg00, arg0, 16); \
156 tcg_gen_ext16s_tl(arg01, arg0); \
157 tcg_gen_sari_tl(arg11, arg1, 16); \
158 tcg_gen_ext16s_tl(arg10, arg1); \
159 gen_helper_##name(ret, arg00, arg01, arg10, arg11, n); \
160 tcg_temp_free(arg00); \
161 tcg_temp_free(arg01); \
162 tcg_temp_free(arg10); \
163 tcg_temp_free(arg11); \
166 #define GEN_HELPER_UL(name, ret, arg0, arg1, n) do { \
167 TCGv arg00 = tcg_temp_new(); \
168 TCGv arg01 = tcg_temp_new(); \
169 TCGv arg10 = tcg_temp_new(); \
170 TCGv arg11 = tcg_temp_new(); \
171 tcg_gen_sari_tl(arg00, arg0, 16); \
172 tcg_gen_ext16s_tl(arg01, arg0); \
173 tcg_gen_sari_tl(arg10, arg1, 16); \
174 tcg_gen_ext16s_tl(arg11, arg1); \
175 gen_helper_##name(ret, arg00, arg01, arg10, arg11, n); \
176 tcg_temp_free(arg00); \
177 tcg_temp_free(arg01); \
178 tcg_temp_free(arg10); \
179 tcg_temp_free(arg11); \
182 #define GEN_HELPER_UU(name, ret, arg0, arg1, n) do { \
183 TCGv arg00 = tcg_temp_new(); \
184 TCGv arg01 = tcg_temp_new(); \
185 TCGv arg11 = tcg_temp_new(); \
186 tcg_gen_sari_tl(arg01, arg0, 16); \
187 tcg_gen_ext16s_tl(arg00, arg0); \
188 tcg_gen_sari_tl(arg11, arg1, 16); \
189 gen_helper_##name(ret, arg00, arg01, arg11, arg11, n); \
190 tcg_temp_free(arg00); \
191 tcg_temp_free(arg01); \
192 tcg_temp_free(arg11); \
195 #define GEN_HELPER_RRR(name, rl, rh, al1, ah1, arg2) do { \
196 TCGv_i64 ret = tcg_temp_new_i64(); \
197 TCGv_i64 arg1 = tcg_temp_new_i64(); \
199 tcg_gen_concat_i32_i64(arg1, al1, ah1); \
200 gen_helper_##name(ret, arg1, arg2); \
201 tcg_gen_extr_i64_i32(rl, rh, ret); \
203 tcg_temp_free_i64(ret); \
204 tcg_temp_free_i64(arg1); \
207 #define GEN_HELPER_RR(name, rl, rh, arg1, arg2) do { \
208 TCGv_i64 ret = tcg_temp_new_i64(); \
210 gen_helper_##name(ret, cpu_env, arg1, arg2); \
211 tcg_gen_extr_i64_i32(rl, rh, ret); \
213 tcg_temp_free_i64(ret); \
216 #define EA_ABS_FORMAT(con) (((con & 0x3C000) << 14) + (con & 0x3FFF))
217 #define EA_B_ABSOLUT(con) (((offset & 0xf00000) << 8) | \
218 ((offset & 0x0fffff) << 1))
220 /* For two 32-bit registers used a 64-bit register, the first
221 registernumber needs to be even. Otherwise we trap. */
222 static inline void generate_trap(DisasContext
*ctx
, int class, int tin
);
223 #define CHECK_REG_PAIR(reg) do { \
225 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_OPD); \
229 /* Functions for load/save to/from memory */
231 static inline void gen_offset_ld(DisasContext
*ctx
, TCGv r1
, TCGv r2
,
232 int16_t con
, TCGMemOp mop
)
234 TCGv temp
= tcg_temp_new();
235 tcg_gen_addi_tl(temp
, r2
, con
);
236 tcg_gen_qemu_ld_tl(r1
, temp
, ctx
->mem_idx
, mop
);
240 static inline void gen_offset_st(DisasContext
*ctx
, TCGv r1
, TCGv r2
,
241 int16_t con
, TCGMemOp mop
)
243 TCGv temp
= tcg_temp_new();
244 tcg_gen_addi_tl(temp
, r2
, con
);
245 tcg_gen_qemu_st_tl(r1
, temp
, ctx
->mem_idx
, mop
);
249 static void gen_st_2regs_64(TCGv rh
, TCGv rl
, TCGv address
, DisasContext
*ctx
)
251 TCGv_i64 temp
= tcg_temp_new_i64();
253 tcg_gen_concat_i32_i64(temp
, rl
, rh
);
254 tcg_gen_qemu_st_i64(temp
, address
, ctx
->mem_idx
, MO_LEQ
);
256 tcg_temp_free_i64(temp
);
259 static void gen_offset_st_2regs(TCGv rh
, TCGv rl
, TCGv base
, int16_t con
,
262 TCGv temp
= tcg_temp_new();
263 tcg_gen_addi_tl(temp
, base
, con
);
264 gen_st_2regs_64(rh
, rl
, temp
, ctx
);
268 static void gen_ld_2regs_64(TCGv rh
, TCGv rl
, TCGv address
, DisasContext
*ctx
)
270 TCGv_i64 temp
= tcg_temp_new_i64();
272 tcg_gen_qemu_ld_i64(temp
, address
, ctx
->mem_idx
, MO_LEQ
);
273 /* write back to two 32 bit regs */
274 tcg_gen_extr_i64_i32(rl
, rh
, temp
);
276 tcg_temp_free_i64(temp
);
279 static void gen_offset_ld_2regs(TCGv rh
, TCGv rl
, TCGv base
, int16_t con
,
282 TCGv temp
= tcg_temp_new();
283 tcg_gen_addi_tl(temp
, base
, con
);
284 gen_ld_2regs_64(rh
, rl
, temp
, ctx
);
288 static void gen_st_preincr(DisasContext
*ctx
, TCGv r1
, TCGv r2
, int16_t off
,
291 TCGv temp
= tcg_temp_new();
292 tcg_gen_addi_tl(temp
, r2
, off
);
293 tcg_gen_qemu_st_tl(r1
, temp
, ctx
->mem_idx
, mop
);
294 tcg_gen_mov_tl(r2
, temp
);
298 static void gen_ld_preincr(DisasContext
*ctx
, TCGv r1
, TCGv r2
, int16_t off
,
301 TCGv temp
= tcg_temp_new();
302 tcg_gen_addi_tl(temp
, r2
, off
);
303 tcg_gen_qemu_ld_tl(r1
, temp
, ctx
->mem_idx
, mop
);
304 tcg_gen_mov_tl(r2
, temp
);
308 /* M(EA, word) = (M(EA, word) & ~E[a][63:32]) | (E[a][31:0] & E[a][63:32]); */
309 static void gen_ldmst(DisasContext
*ctx
, int ereg
, TCGv ea
)
311 TCGv temp
= tcg_temp_new();
312 TCGv temp2
= tcg_temp_new();
314 CHECK_REG_PAIR(ereg
);
315 /* temp = (M(EA, word) */
316 tcg_gen_qemu_ld_tl(temp
, ea
, ctx
->mem_idx
, MO_LEUL
);
317 /* temp = temp & ~E[a][63:32]) */
318 tcg_gen_andc_tl(temp
, temp
, cpu_gpr_d
[ereg
+1]);
319 /* temp2 = (E[a][31:0] & E[a][63:32]); */
320 tcg_gen_and_tl(temp2
, cpu_gpr_d
[ereg
], cpu_gpr_d
[ereg
+1]);
321 /* temp = temp | temp2; */
322 tcg_gen_or_tl(temp
, temp
, temp2
);
323 /* M(EA, word) = temp; */
324 tcg_gen_qemu_st_tl(temp
, ea
, ctx
->mem_idx
, MO_LEUL
);
327 tcg_temp_free(temp2
);
330 /* tmp = M(EA, word);
333 static void gen_swap(DisasContext
*ctx
, int reg
, TCGv ea
)
335 TCGv temp
= tcg_temp_new();
337 tcg_gen_qemu_ld_tl(temp
, ea
, ctx
->mem_idx
, MO_LEUL
);
338 tcg_gen_qemu_st_tl(cpu_gpr_d
[reg
], ea
, ctx
->mem_idx
, MO_LEUL
);
339 tcg_gen_mov_tl(cpu_gpr_d
[reg
], temp
);
344 static void gen_cmpswap(DisasContext
*ctx
, int reg
, TCGv ea
)
346 TCGv temp
= tcg_temp_new();
347 TCGv temp2
= tcg_temp_new();
348 tcg_gen_qemu_ld_tl(temp
, ea
, ctx
->mem_idx
, MO_LEUL
);
349 tcg_gen_movcond_tl(TCG_COND_EQ
, temp2
, cpu_gpr_d
[reg
+1], temp
,
350 cpu_gpr_d
[reg
], temp
);
351 tcg_gen_qemu_st_tl(temp2
, ea
, ctx
->mem_idx
, MO_LEUL
);
352 tcg_gen_mov_tl(cpu_gpr_d
[reg
], temp
);
355 tcg_temp_free(temp2
);
358 static void gen_swapmsk(DisasContext
*ctx
, int reg
, TCGv ea
)
360 TCGv temp
= tcg_temp_new();
361 TCGv temp2
= tcg_temp_new();
362 TCGv temp3
= tcg_temp_new();
364 tcg_gen_qemu_ld_tl(temp
, ea
, ctx
->mem_idx
, MO_LEUL
);
365 tcg_gen_and_tl(temp2
, cpu_gpr_d
[reg
], cpu_gpr_d
[reg
+1]);
366 tcg_gen_andc_tl(temp3
, temp
, cpu_gpr_d
[reg
+1]);
367 tcg_gen_or_tl(temp2
, temp2
, temp3
);
368 tcg_gen_qemu_st_tl(temp2
, ea
, ctx
->mem_idx
, MO_LEUL
);
369 tcg_gen_mov_tl(cpu_gpr_d
[reg
], temp
);
372 tcg_temp_free(temp2
);
373 tcg_temp_free(temp3
);
377 /* We generate loads and store to core special function register (csfr) through
378 the function gen_mfcr and gen_mtcr. To handle access permissions, we use 3
379 makros R, A and E, which allow read-only, all and endinit protected access.
380 These makros also specify in which ISA version the csfr was introduced. */
381 #define R(ADDRESS, REG, FEATURE) \
383 if (tricore_feature(env, FEATURE)) { \
384 tcg_gen_ld_tl(ret, cpu_env, offsetof(CPUTriCoreState, REG)); \
387 #define A(ADDRESS, REG, FEATURE) R(ADDRESS, REG, FEATURE)
388 #define E(ADDRESS, REG, FEATURE) R(ADDRESS, REG, FEATURE)
389 static inline void gen_mfcr(CPUTriCoreState
*env
, TCGv ret
, int32_t offset
)
391 /* since we're caching PSW make this a special case */
392 if (offset
== 0xfe04) {
393 gen_helper_psw_read(ret
, cpu_env
);
404 #define R(ADDRESS, REG, FEATURE) /* don't gen writes to read-only reg,
405 since no execption occurs */
406 #define A(ADDRESS, REG, FEATURE) R(ADDRESS, REG, FEATURE) \
408 if (tricore_feature(env, FEATURE)) { \
409 tcg_gen_st_tl(r1, cpu_env, offsetof(CPUTriCoreState, REG)); \
412 /* Endinit protected registers
413 TODO: Since the endinit bit is in a register of a not yet implemented
414 watchdog device, we handle endinit protected registers like
415 all-access registers for now. */
416 #define E(ADDRESS, REG, FEATURE) A(ADDRESS, REG, FEATURE)
417 static inline void gen_mtcr(CPUTriCoreState
*env
, DisasContext
*ctx
, TCGv r1
,
420 if ((ctx
->hflags
& TRICORE_HFLAG_KUU
) == TRICORE_HFLAG_SM
) {
421 /* since we're caching PSW make this a special case */
422 if (offset
== 0xfe04) {
423 gen_helper_psw_write(cpu_env
, r1
);
430 /* generate privilege trap */
434 /* Functions for arithmetic instructions */
436 static inline void gen_add_d(TCGv ret
, TCGv r1
, TCGv r2
)
438 TCGv t0
= tcg_temp_new_i32();
439 TCGv result
= tcg_temp_new_i32();
440 /* Addition and set V/SV bits */
441 tcg_gen_add_tl(result
, r1
, r2
);
443 tcg_gen_xor_tl(cpu_PSW_V
, result
, r1
);
444 tcg_gen_xor_tl(t0
, r1
, r2
);
445 tcg_gen_andc_tl(cpu_PSW_V
, cpu_PSW_V
, t0
);
447 tcg_gen_or_tl(cpu_PSW_SV
, cpu_PSW_SV
, cpu_PSW_V
);
448 /* Calc AV/SAV bits */
449 tcg_gen_add_tl(cpu_PSW_AV
, result
, result
);
450 tcg_gen_xor_tl(cpu_PSW_AV
, result
, cpu_PSW_AV
);
452 tcg_gen_or_tl(cpu_PSW_SAV
, cpu_PSW_SAV
, cpu_PSW_AV
);
453 /* write back result */
454 tcg_gen_mov_tl(ret
, result
);
456 tcg_temp_free(result
);
461 gen_add64_d(TCGv_i64 ret
, TCGv_i64 r1
, TCGv_i64 r2
)
463 TCGv temp
= tcg_temp_new();
464 TCGv_i64 t0
= tcg_temp_new_i64();
465 TCGv_i64 t1
= tcg_temp_new_i64();
466 TCGv_i64 result
= tcg_temp_new_i64();
468 tcg_gen_add_i64(result
, r1
, r2
);
470 tcg_gen_xor_i64(t1
, result
, r1
);
471 tcg_gen_xor_i64(t0
, r1
, r2
);
472 tcg_gen_andc_i64(t1
, t1
, t0
);
473 tcg_gen_extrh_i64_i32(cpu_PSW_V
, t1
);
475 tcg_gen_or_tl(cpu_PSW_SV
, cpu_PSW_SV
, cpu_PSW_V
);
476 /* calc AV/SAV bits */
477 tcg_gen_extrh_i64_i32(temp
, result
);
478 tcg_gen_add_tl(cpu_PSW_AV
, temp
, temp
);
479 tcg_gen_xor_tl(cpu_PSW_AV
, temp
, cpu_PSW_AV
);
481 tcg_gen_or_tl(cpu_PSW_SAV
, cpu_PSW_SAV
, cpu_PSW_AV
);
482 /* write back result */
483 tcg_gen_mov_i64(ret
, result
);
486 tcg_temp_free_i64(result
);
487 tcg_temp_free_i64(t0
);
488 tcg_temp_free_i64(t1
);
492 gen_addsub64_h(TCGv ret_low
, TCGv ret_high
, TCGv r1_low
, TCGv r1_high
, TCGv r2
,
493 TCGv r3
, void(*op1
)(TCGv
, TCGv
, TCGv
),
494 void(*op2
)(TCGv
, TCGv
, TCGv
))
496 TCGv temp
= tcg_temp_new();
497 TCGv temp2
= tcg_temp_new();
498 TCGv temp3
= tcg_temp_new();
499 TCGv temp4
= tcg_temp_new();
501 (*op1
)(temp
, r1_low
, r2
);
503 tcg_gen_xor_tl(temp2
, temp
, r1_low
);
504 tcg_gen_xor_tl(temp3
, r1_low
, r2
);
505 if (op1
== tcg_gen_add_tl
) {
506 tcg_gen_andc_tl(temp2
, temp2
, temp3
);
508 tcg_gen_and_tl(temp2
, temp2
, temp3
);
511 (*op2
)(temp3
, r1_high
, r3
);
513 tcg_gen_xor_tl(cpu_PSW_V
, temp3
, r1_high
);
514 tcg_gen_xor_tl(temp4
, r1_high
, r3
);
515 if (op2
== tcg_gen_add_tl
) {
516 tcg_gen_andc_tl(cpu_PSW_V
, cpu_PSW_V
, temp4
);
518 tcg_gen_and_tl(cpu_PSW_V
, cpu_PSW_V
, temp4
);
520 /* combine V0/V1 bits */
521 tcg_gen_or_tl(cpu_PSW_V
, cpu_PSW_V
, temp2
);
523 tcg_gen_or_tl(cpu_PSW_SV
, cpu_PSW_SV
, cpu_PSW_V
);
525 tcg_gen_mov_tl(ret_low
, temp
);
526 tcg_gen_mov_tl(ret_high
, temp3
);
528 tcg_gen_add_tl(temp
, ret_low
, ret_low
);
529 tcg_gen_xor_tl(temp
, temp
, ret_low
);
530 tcg_gen_add_tl(cpu_PSW_AV
, ret_high
, ret_high
);
531 tcg_gen_xor_tl(cpu_PSW_AV
, cpu_PSW_AV
, ret_high
);
532 tcg_gen_or_tl(cpu_PSW_AV
, cpu_PSW_AV
, temp
);
534 tcg_gen_or_tl(cpu_PSW_SAV
, cpu_PSW_SAV
, cpu_PSW_AV
);
537 tcg_temp_free(temp2
);
538 tcg_temp_free(temp3
);
539 tcg_temp_free(temp4
);
542 /* ret = r2 + (r1 * r3); */
543 static inline void gen_madd32_d(TCGv ret
, TCGv r1
, TCGv r2
, TCGv r3
)
545 TCGv_i64 t1
= tcg_temp_new_i64();
546 TCGv_i64 t2
= tcg_temp_new_i64();
547 TCGv_i64 t3
= tcg_temp_new_i64();
549 tcg_gen_ext_i32_i64(t1
, r1
);
550 tcg_gen_ext_i32_i64(t2
, r2
);
551 tcg_gen_ext_i32_i64(t3
, r3
);
553 tcg_gen_mul_i64(t1
, t1
, t3
);
554 tcg_gen_add_i64(t1
, t2
, t1
);
556 tcg_gen_extrl_i64_i32(ret
, t1
);
559 tcg_gen_setcondi_i64(TCG_COND_GT
, t3
, t1
, 0x7fffffffLL
);
560 /* t1 < -0x80000000 */
561 tcg_gen_setcondi_i64(TCG_COND_LT
, t2
, t1
, -0x80000000LL
);
562 tcg_gen_or_i64(t2
, t2
, t3
);
563 tcg_gen_extrl_i64_i32(cpu_PSW_V
, t2
);
564 tcg_gen_shli_tl(cpu_PSW_V
, cpu_PSW_V
, 31);
566 tcg_gen_or_tl(cpu_PSW_SV
, cpu_PSW_SV
, cpu_PSW_V
);
567 /* Calc AV/SAV bits */
568 tcg_gen_add_tl(cpu_PSW_AV
, ret
, ret
);
569 tcg_gen_xor_tl(cpu_PSW_AV
, ret
, cpu_PSW_AV
);
571 tcg_gen_or_tl(cpu_PSW_SAV
, cpu_PSW_SAV
, cpu_PSW_AV
);
573 tcg_temp_free_i64(t1
);
574 tcg_temp_free_i64(t2
);
575 tcg_temp_free_i64(t3
);
578 static inline void gen_maddi32_d(TCGv ret
, TCGv r1
, TCGv r2
, int32_t con
)
580 TCGv temp
= tcg_const_i32(con
);
581 gen_madd32_d(ret
, r1
, r2
, temp
);
586 gen_madd64_d(TCGv ret_low
, TCGv ret_high
, TCGv r1
, TCGv r2_low
, TCGv r2_high
,
589 TCGv t1
= tcg_temp_new();
590 TCGv t2
= tcg_temp_new();
591 TCGv t3
= tcg_temp_new();
592 TCGv t4
= tcg_temp_new();
594 tcg_gen_muls2_tl(t1
, t2
, r1
, r3
);
595 /* only the add can overflow */
596 tcg_gen_add2_tl(t3
, t4
, r2_low
, r2_high
, t1
, t2
);
598 tcg_gen_xor_tl(cpu_PSW_V
, t4
, r2_high
);
599 tcg_gen_xor_tl(t1
, r2_high
, t2
);
600 tcg_gen_andc_tl(cpu_PSW_V
, cpu_PSW_V
, t1
);
602 tcg_gen_or_tl(cpu_PSW_SV
, cpu_PSW_SV
, cpu_PSW_V
);
603 /* Calc AV/SAV bits */
604 tcg_gen_add_tl(cpu_PSW_AV
, t4
, t4
);
605 tcg_gen_xor_tl(cpu_PSW_AV
, t4
, cpu_PSW_AV
);
607 tcg_gen_or_tl(cpu_PSW_SAV
, cpu_PSW_SAV
, cpu_PSW_AV
);
608 /* write back the result */
609 tcg_gen_mov_tl(ret_low
, t3
);
610 tcg_gen_mov_tl(ret_high
, t4
);
619 gen_maddu64_d(TCGv ret_low
, TCGv ret_high
, TCGv r1
, TCGv r2_low
, TCGv r2_high
,
622 TCGv_i64 t1
= tcg_temp_new_i64();
623 TCGv_i64 t2
= tcg_temp_new_i64();
624 TCGv_i64 t3
= tcg_temp_new_i64();
626 tcg_gen_extu_i32_i64(t1
, r1
);
627 tcg_gen_concat_i32_i64(t2
, r2_low
, r2_high
);
628 tcg_gen_extu_i32_i64(t3
, r3
);
630 tcg_gen_mul_i64(t1
, t1
, t3
);
631 tcg_gen_add_i64(t2
, t2
, t1
);
632 /* write back result */
633 tcg_gen_extr_i64_i32(ret_low
, ret_high
, t2
);
634 /* only the add overflows, if t2 < t1
636 tcg_gen_setcond_i64(TCG_COND_LTU
, t2
, t2
, t1
);
637 tcg_gen_extrl_i64_i32(cpu_PSW_V
, t2
);
638 tcg_gen_shli_tl(cpu_PSW_V
, cpu_PSW_V
, 31);
640 tcg_gen_or_tl(cpu_PSW_SV
, cpu_PSW_SV
, cpu_PSW_V
);
641 /* Calc AV/SAV bits */
642 tcg_gen_add_tl(cpu_PSW_AV
, ret_high
, ret_high
);
643 tcg_gen_xor_tl(cpu_PSW_AV
, ret_high
, cpu_PSW_AV
);
645 tcg_gen_or_tl(cpu_PSW_SAV
, cpu_PSW_SAV
, cpu_PSW_AV
);
647 tcg_temp_free_i64(t1
);
648 tcg_temp_free_i64(t2
);
649 tcg_temp_free_i64(t3
);
653 gen_maddi64_d(TCGv ret_low
, TCGv ret_high
, TCGv r1
, TCGv r2_low
, TCGv r2_high
,
656 TCGv temp
= tcg_const_i32(con
);
657 gen_madd64_d(ret_low
, ret_high
, r1
, r2_low
, r2_high
, temp
);
662 gen_maddui64_d(TCGv ret_low
, TCGv ret_high
, TCGv r1
, TCGv r2_low
, TCGv r2_high
,
665 TCGv temp
= tcg_const_i32(con
);
666 gen_maddu64_d(ret_low
, ret_high
, r1
, r2_low
, r2_high
, temp
);
671 gen_madd_h(TCGv ret_low
, TCGv ret_high
, TCGv r1_low
, TCGv r1_high
, TCGv r2
,
672 TCGv r3
, uint32_t n
, uint32_t mode
)
674 TCGv temp
= tcg_const_i32(n
);
675 TCGv temp2
= tcg_temp_new();
676 TCGv_i64 temp64
= tcg_temp_new_i64();
679 GEN_HELPER_LL(mul_h
, temp64
, r2
, r3
, temp
);
682 GEN_HELPER_LU(mul_h
, temp64
, r2
, r3
, temp
);
685 GEN_HELPER_UL(mul_h
, temp64
, r2
, r3
, temp
);
688 GEN_HELPER_UU(mul_h
, temp64
, r2
, r3
, temp
);
691 tcg_gen_extr_i64_i32(temp
, temp2
, temp64
);
692 gen_addsub64_h(ret_low
, ret_high
, r1_low
, r1_high
, temp
, temp2
,
693 tcg_gen_add_tl
, tcg_gen_add_tl
);
695 tcg_temp_free(temp2
);
696 tcg_temp_free_i64(temp64
);
700 gen_maddsu_h(TCGv ret_low
, TCGv ret_high
, TCGv r1_low
, TCGv r1_high
, TCGv r2
,
701 TCGv r3
, uint32_t n
, uint32_t mode
)
703 TCGv temp
= tcg_const_i32(n
);
704 TCGv temp2
= tcg_temp_new();
705 TCGv_i64 temp64
= tcg_temp_new_i64();
708 GEN_HELPER_LL(mul_h
, temp64
, r2
, r3
, temp
);
711 GEN_HELPER_LU(mul_h
, temp64
, r2
, r3
, temp
);
714 GEN_HELPER_UL(mul_h
, temp64
, r2
, r3
, temp
);
717 GEN_HELPER_UU(mul_h
, temp64
, r2
, r3
, temp
);
720 tcg_gen_extr_i64_i32(temp
, temp2
, temp64
);
721 gen_addsub64_h(ret_low
, ret_high
, r1_low
, r1_high
, temp
, temp2
,
722 tcg_gen_sub_tl
, tcg_gen_add_tl
);
724 tcg_temp_free(temp2
);
725 tcg_temp_free_i64(temp64
);
729 gen_maddsum_h(TCGv ret_low
, TCGv ret_high
, TCGv r1_low
, TCGv r1_high
, TCGv r2
,
730 TCGv r3
, uint32_t n
, uint32_t mode
)
732 TCGv temp
= tcg_const_i32(n
);
733 TCGv_i64 temp64
= tcg_temp_new_i64();
734 TCGv_i64 temp64_2
= tcg_temp_new_i64();
735 TCGv_i64 temp64_3
= tcg_temp_new_i64();
738 GEN_HELPER_LL(mul_h
, temp64
, r2
, r3
, temp
);
741 GEN_HELPER_LU(mul_h
, temp64
, r2
, r3
, temp
);
744 GEN_HELPER_UL(mul_h
, temp64
, r2
, r3
, temp
);
747 GEN_HELPER_UU(mul_h
, temp64
, r2
, r3
, temp
);
750 tcg_gen_concat_i32_i64(temp64_3
, r1_low
, r1_high
);
751 tcg_gen_sari_i64(temp64_2
, temp64
, 32); /* high */
752 tcg_gen_ext32s_i64(temp64
, temp64
); /* low */
753 tcg_gen_sub_i64(temp64
, temp64_2
, temp64
);
754 tcg_gen_shli_i64(temp64
, temp64
, 16);
756 gen_add64_d(temp64_2
, temp64_3
, temp64
);
757 /* write back result */
758 tcg_gen_extr_i64_i32(ret_low
, ret_high
, temp64_2
);
761 tcg_temp_free_i64(temp64
);
762 tcg_temp_free_i64(temp64_2
);
763 tcg_temp_free_i64(temp64_3
);
766 static inline void gen_adds(TCGv ret
, TCGv r1
, TCGv r2
);
769 gen_madds_h(TCGv ret_low
, TCGv ret_high
, TCGv r1_low
, TCGv r1_high
, TCGv r2
,
770 TCGv r3
, uint32_t n
, uint32_t mode
)
772 TCGv temp
= tcg_const_i32(n
);
773 TCGv temp2
= tcg_temp_new();
774 TCGv temp3
= tcg_temp_new();
775 TCGv_i64 temp64
= tcg_temp_new_i64();
779 GEN_HELPER_LL(mul_h
, temp64
, r2
, r3
, temp
);
782 GEN_HELPER_LU(mul_h
, temp64
, r2
, r3
, temp
);
785 GEN_HELPER_UL(mul_h
, temp64
, r2
, r3
, temp
);
788 GEN_HELPER_UU(mul_h
, temp64
, r2
, r3
, temp
);
791 tcg_gen_extr_i64_i32(temp
, temp2
, temp64
);
792 gen_adds(ret_low
, r1_low
, temp
);
793 tcg_gen_mov_tl(temp
, cpu_PSW_V
);
794 tcg_gen_mov_tl(temp3
, cpu_PSW_AV
);
795 gen_adds(ret_high
, r1_high
, temp2
);
797 tcg_gen_or_tl(cpu_PSW_V
, cpu_PSW_V
, temp
);
798 /* combine av bits */
799 tcg_gen_or_tl(cpu_PSW_AV
, cpu_PSW_AV
, temp3
);
802 tcg_temp_free(temp2
);
803 tcg_temp_free(temp3
);
804 tcg_temp_free_i64(temp64
);
808 static inline void gen_subs(TCGv ret
, TCGv r1
, TCGv r2
);
811 gen_maddsus_h(TCGv ret_low
, TCGv ret_high
, TCGv r1_low
, TCGv r1_high
, TCGv r2
,
812 TCGv r3
, uint32_t n
, uint32_t mode
)
814 TCGv temp
= tcg_const_i32(n
);
815 TCGv temp2
= tcg_temp_new();
816 TCGv temp3
= tcg_temp_new();
817 TCGv_i64 temp64
= tcg_temp_new_i64();
821 GEN_HELPER_LL(mul_h
, temp64
, r2
, r3
, temp
);
824 GEN_HELPER_LU(mul_h
, temp64
, r2
, r3
, temp
);
827 GEN_HELPER_UL(mul_h
, temp64
, r2
, r3
, temp
);
830 GEN_HELPER_UU(mul_h
, temp64
, r2
, r3
, temp
);
833 tcg_gen_extr_i64_i32(temp
, temp2
, temp64
);
834 gen_subs(ret_low
, r1_low
, temp
);
835 tcg_gen_mov_tl(temp
, cpu_PSW_V
);
836 tcg_gen_mov_tl(temp3
, cpu_PSW_AV
);
837 gen_adds(ret_high
, r1_high
, temp2
);
839 tcg_gen_or_tl(cpu_PSW_V
, cpu_PSW_V
, temp
);
840 /* combine av bits */
841 tcg_gen_or_tl(cpu_PSW_AV
, cpu_PSW_AV
, temp3
);
844 tcg_temp_free(temp2
);
845 tcg_temp_free(temp3
);
846 tcg_temp_free_i64(temp64
);
851 gen_maddsums_h(TCGv ret_low
, TCGv ret_high
, TCGv r1_low
, TCGv r1_high
, TCGv r2
,
852 TCGv r3
, uint32_t n
, uint32_t mode
)
854 TCGv temp
= tcg_const_i32(n
);
855 TCGv_i64 temp64
= tcg_temp_new_i64();
856 TCGv_i64 temp64_2
= tcg_temp_new_i64();
860 GEN_HELPER_LL(mul_h
, temp64
, r2
, r3
, temp
);
863 GEN_HELPER_LU(mul_h
, temp64
, r2
, r3
, temp
);
866 GEN_HELPER_UL(mul_h
, temp64
, r2
, r3
, temp
);
869 GEN_HELPER_UU(mul_h
, temp64
, r2
, r3
, temp
);
872 tcg_gen_sari_i64(temp64_2
, temp64
, 32); /* high */
873 tcg_gen_ext32s_i64(temp64
, temp64
); /* low */
874 tcg_gen_sub_i64(temp64
, temp64_2
, temp64
);
875 tcg_gen_shli_i64(temp64
, temp64
, 16);
876 tcg_gen_concat_i32_i64(temp64_2
, r1_low
, r1_high
);
878 gen_helper_add64_ssov(temp64
, cpu_env
, temp64_2
, temp64
);
879 tcg_gen_extr_i64_i32(ret_low
, ret_high
, temp64
);
882 tcg_temp_free_i64(temp64
);
883 tcg_temp_free_i64(temp64_2
);
888 gen_maddm_h(TCGv ret_low
, TCGv ret_high
, TCGv r1_low
, TCGv r1_high
, TCGv r2
,
889 TCGv r3
, uint32_t n
, uint32_t mode
)
891 TCGv temp
= tcg_const_i32(n
);
892 TCGv_i64 temp64
= tcg_temp_new_i64();
893 TCGv_i64 temp64_2
= tcg_temp_new_i64();
894 TCGv_i64 temp64_3
= tcg_temp_new_i64();
897 GEN_HELPER_LL(mulm_h
, temp64
, r2
, r3
, temp
);
900 GEN_HELPER_LU(mulm_h
, temp64
, r2
, r3
, temp
);
903 GEN_HELPER_UL(mulm_h
, temp64
, r2
, r3
, temp
);
906 GEN_HELPER_UU(mulm_h
, temp64
, r2
, r3
, temp
);
909 tcg_gen_concat_i32_i64(temp64_2
, r1_low
, r1_high
);
910 gen_add64_d(temp64_3
, temp64_2
, temp64
);
911 /* write back result */
912 tcg_gen_extr_i64_i32(ret_low
, ret_high
, temp64_3
);
915 tcg_temp_free_i64(temp64
);
916 tcg_temp_free_i64(temp64_2
);
917 tcg_temp_free_i64(temp64_3
);
921 gen_maddms_h(TCGv ret_low
, TCGv ret_high
, TCGv r1_low
, TCGv r1_high
, TCGv r2
,
922 TCGv r3
, uint32_t n
, uint32_t mode
)
924 TCGv temp
= tcg_const_i32(n
);
925 TCGv_i64 temp64
= tcg_temp_new_i64();
926 TCGv_i64 temp64_2
= tcg_temp_new_i64();
929 GEN_HELPER_LL(mulm_h
, temp64
, r2
, r3
, temp
);
932 GEN_HELPER_LU(mulm_h
, temp64
, r2
, r3
, temp
);
935 GEN_HELPER_UL(mulm_h
, temp64
, r2
, r3
, temp
);
938 GEN_HELPER_UU(mulm_h
, temp64
, r2
, r3
, temp
);
941 tcg_gen_concat_i32_i64(temp64_2
, r1_low
, r1_high
);
942 gen_helper_add64_ssov(temp64
, cpu_env
, temp64_2
, temp64
);
943 tcg_gen_extr_i64_i32(ret_low
, ret_high
, temp64
);
946 tcg_temp_free_i64(temp64
);
947 tcg_temp_free_i64(temp64_2
);
951 gen_maddr64_h(TCGv ret
, TCGv r1_low
, TCGv r1_high
, TCGv r2
, TCGv r3
, uint32_t n
,
954 TCGv temp
= tcg_const_i32(n
);
955 TCGv_i64 temp64
= tcg_temp_new_i64();
958 GEN_HELPER_LL(mul_h
, temp64
, r2
, r3
, temp
);
961 GEN_HELPER_LU(mul_h
, temp64
, r2
, r3
, temp
);
964 GEN_HELPER_UL(mul_h
, temp64
, r2
, r3
, temp
);
967 GEN_HELPER_UU(mul_h
, temp64
, r2
, r3
, temp
);
970 gen_helper_addr_h(ret
, cpu_env
, temp64
, r1_low
, r1_high
);
973 tcg_temp_free_i64(temp64
);
977 gen_maddr32_h(TCGv ret
, TCGv r1
, TCGv r2
, TCGv r3
, uint32_t n
, uint32_t mode
)
979 TCGv temp
= tcg_temp_new();
980 TCGv temp2
= tcg_temp_new();
982 tcg_gen_andi_tl(temp2
, r1
, 0xffff0000);
983 tcg_gen_shli_tl(temp
, r1
, 16);
984 gen_maddr64_h(ret
, temp
, temp2
, r2
, r3
, n
, mode
);
987 tcg_temp_free(temp2
);
991 gen_maddsur32_h(TCGv ret
, TCGv r1
, TCGv r2
, TCGv r3
, uint32_t n
, uint32_t mode
)
993 TCGv temp
= tcg_const_i32(n
);
994 TCGv temp2
= tcg_temp_new();
995 TCGv_i64 temp64
= tcg_temp_new_i64();
998 GEN_HELPER_LL(mul_h
, temp64
, r2
, r3
, temp
);
1001 GEN_HELPER_LU(mul_h
, temp64
, r2
, r3
, temp
);
1004 GEN_HELPER_UL(mul_h
, temp64
, r2
, r3
, temp
);
1007 GEN_HELPER_UU(mul_h
, temp64
, r2
, r3
, temp
);
1010 tcg_gen_andi_tl(temp2
, r1
, 0xffff0000);
1011 tcg_gen_shli_tl(temp
, r1
, 16);
1012 gen_helper_addsur_h(ret
, cpu_env
, temp64
, temp
, temp2
);
1014 tcg_temp_free(temp
);
1015 tcg_temp_free(temp2
);
1016 tcg_temp_free_i64(temp64
);
1021 gen_maddr64s_h(TCGv ret
, TCGv r1_low
, TCGv r1_high
, TCGv r2
, TCGv r3
,
1022 uint32_t n
, uint32_t mode
)
1024 TCGv temp
= tcg_const_i32(n
);
1025 TCGv_i64 temp64
= tcg_temp_new_i64();
1028 GEN_HELPER_LL(mul_h
, temp64
, r2
, r3
, temp
);
1031 GEN_HELPER_LU(mul_h
, temp64
, r2
, r3
, temp
);
1034 GEN_HELPER_UL(mul_h
, temp64
, r2
, r3
, temp
);
1037 GEN_HELPER_UU(mul_h
, temp64
, r2
, r3
, temp
);
1040 gen_helper_addr_h_ssov(ret
, cpu_env
, temp64
, r1_low
, r1_high
);
1042 tcg_temp_free(temp
);
1043 tcg_temp_free_i64(temp64
);
1047 gen_maddr32s_h(TCGv ret
, TCGv r1
, TCGv r2
, TCGv r3
, uint32_t n
, uint32_t mode
)
1049 TCGv temp
= tcg_temp_new();
1050 TCGv temp2
= tcg_temp_new();
1052 tcg_gen_andi_tl(temp2
, r1
, 0xffff0000);
1053 tcg_gen_shli_tl(temp
, r1
, 16);
1054 gen_maddr64s_h(ret
, temp
, temp2
, r2
, r3
, n
, mode
);
1056 tcg_temp_free(temp
);
1057 tcg_temp_free(temp2
);
1061 gen_maddsur32s_h(TCGv ret
, TCGv r1
, TCGv r2
, TCGv r3
, uint32_t n
, uint32_t mode
)
1063 TCGv temp
= tcg_const_i32(n
);
1064 TCGv temp2
= tcg_temp_new();
1065 TCGv_i64 temp64
= tcg_temp_new_i64();
1068 GEN_HELPER_LL(mul_h
, temp64
, r2
, r3
, temp
);
1071 GEN_HELPER_LU(mul_h
, temp64
, r2
, r3
, temp
);
1074 GEN_HELPER_UL(mul_h
, temp64
, r2
, r3
, temp
);
1077 GEN_HELPER_UU(mul_h
, temp64
, r2
, r3
, temp
);
1080 tcg_gen_andi_tl(temp2
, r1
, 0xffff0000);
1081 tcg_gen_shli_tl(temp
, r1
, 16);
1082 gen_helper_addsur_h_ssov(ret
, cpu_env
, temp64
, temp
, temp2
);
1084 tcg_temp_free(temp
);
1085 tcg_temp_free(temp2
);
1086 tcg_temp_free_i64(temp64
);
1090 gen_maddr_q(TCGv ret
, TCGv r1
, TCGv r2
, TCGv r3
, uint32_t n
)
1092 TCGv temp
= tcg_const_i32(n
);
1093 gen_helper_maddr_q(ret
, cpu_env
, r1
, r2
, r3
, temp
);
1094 tcg_temp_free(temp
);
1098 gen_maddrs_q(TCGv ret
, TCGv r1
, TCGv r2
, TCGv r3
, uint32_t n
)
1100 TCGv temp
= tcg_const_i32(n
);
1101 gen_helper_maddr_q_ssov(ret
, cpu_env
, r1
, r2
, r3
, temp
);
1102 tcg_temp_free(temp
);
1106 gen_madd32_q(TCGv ret
, TCGv arg1
, TCGv arg2
, TCGv arg3
, uint32_t n
,
1107 uint32_t up_shift
, CPUTriCoreState
*env
)
1109 TCGv temp
= tcg_temp_new();
1110 TCGv temp2
= tcg_temp_new();
1111 TCGv temp3
= tcg_temp_new();
1112 TCGv_i64 t1
= tcg_temp_new_i64();
1113 TCGv_i64 t2
= tcg_temp_new_i64();
1114 TCGv_i64 t3
= tcg_temp_new_i64();
1116 tcg_gen_ext_i32_i64(t2
, arg2
);
1117 tcg_gen_ext_i32_i64(t3
, arg3
);
1119 tcg_gen_mul_i64(t2
, t2
, t3
);
1120 tcg_gen_shli_i64(t2
, t2
, n
);
1122 tcg_gen_ext_i32_i64(t1
, arg1
);
1123 tcg_gen_sari_i64(t2
, t2
, up_shift
);
1125 tcg_gen_add_i64(t3
, t1
, t2
);
1126 tcg_gen_extrl_i64_i32(temp3
, t3
);
1128 tcg_gen_setcondi_i64(TCG_COND_GT
, t1
, t3
, 0x7fffffffLL
);
1129 tcg_gen_setcondi_i64(TCG_COND_LT
, t2
, t3
, -0x80000000LL
);
1130 tcg_gen_or_i64(t1
, t1
, t2
);
1131 tcg_gen_extrl_i64_i32(cpu_PSW_V
, t1
);
1132 tcg_gen_shli_tl(cpu_PSW_V
, cpu_PSW_V
, 31);
1133 /* We produce an overflow on the host if the mul before was
1134 (0x80000000 * 0x80000000) << 1). If this is the
1135 case, we negate the ovf. */
1137 tcg_gen_setcondi_tl(TCG_COND_EQ
, temp
, arg2
, 0x80000000);
1138 tcg_gen_setcond_tl(TCG_COND_EQ
, temp2
, arg2
, arg3
);
1139 tcg_gen_and_tl(temp
, temp
, temp2
);
1140 tcg_gen_shli_tl(temp
, temp
, 31);
1141 /* negate v bit, if special condition */
1142 tcg_gen_xor_tl(cpu_PSW_V
, cpu_PSW_V
, temp
);
1145 tcg_gen_or_tl(cpu_PSW_SV
, cpu_PSW_SV
, cpu_PSW_V
);
1146 /* Calc AV/SAV bits */
1147 tcg_gen_add_tl(cpu_PSW_AV
, temp3
, temp3
);
1148 tcg_gen_xor_tl(cpu_PSW_AV
, temp3
, cpu_PSW_AV
);
1150 tcg_gen_or_tl(cpu_PSW_SAV
, cpu_PSW_SAV
, cpu_PSW_AV
);
1151 /* write back result */
1152 tcg_gen_mov_tl(ret
, temp3
);
1154 tcg_temp_free(temp
);
1155 tcg_temp_free(temp2
);
1156 tcg_temp_free(temp3
);
1157 tcg_temp_free_i64(t1
);
1158 tcg_temp_free_i64(t2
);
1159 tcg_temp_free_i64(t3
);
1163 gen_m16add32_q(TCGv ret
, TCGv arg1
, TCGv arg2
, TCGv arg3
, uint32_t n
)
1165 TCGv temp
= tcg_temp_new();
1166 TCGv temp2
= tcg_temp_new();
1168 tcg_gen_mul_tl(temp
, arg2
, arg3
);
1169 } else { /* n is expected to be 1 */
1170 tcg_gen_mul_tl(temp
, arg2
, arg3
);
1171 tcg_gen_shli_tl(temp
, temp
, 1);
1172 /* catch special case r1 = r2 = 0x8000 */
1173 tcg_gen_setcondi_tl(TCG_COND_EQ
, temp2
, temp
, 0x80000000);
1174 tcg_gen_sub_tl(temp
, temp
, temp2
);
1176 gen_add_d(ret
, arg1
, temp
);
1178 tcg_temp_free(temp
);
1179 tcg_temp_free(temp2
);
1183 gen_m16adds32_q(TCGv ret
, TCGv arg1
, TCGv arg2
, TCGv arg3
, uint32_t n
)
1185 TCGv temp
= tcg_temp_new();
1186 TCGv temp2
= tcg_temp_new();
1188 tcg_gen_mul_tl(temp
, arg2
, arg3
);
1189 } else { /* n is expected to be 1 */
1190 tcg_gen_mul_tl(temp
, arg2
, arg3
);
1191 tcg_gen_shli_tl(temp
, temp
, 1);
1192 /* catch special case r1 = r2 = 0x8000 */
1193 tcg_gen_setcondi_tl(TCG_COND_EQ
, temp2
, temp
, 0x80000000);
1194 tcg_gen_sub_tl(temp
, temp
, temp2
);
1196 gen_adds(ret
, arg1
, temp
);
1198 tcg_temp_free(temp
);
1199 tcg_temp_free(temp2
);
1203 gen_m16add64_q(TCGv rl
, TCGv rh
, TCGv arg1_low
, TCGv arg1_high
, TCGv arg2
,
1204 TCGv arg3
, uint32_t n
)
1206 TCGv temp
= tcg_temp_new();
1207 TCGv temp2
= tcg_temp_new();
1208 TCGv_i64 t1
= tcg_temp_new_i64();
1209 TCGv_i64 t2
= tcg_temp_new_i64();
1210 TCGv_i64 t3
= tcg_temp_new_i64();
1213 tcg_gen_mul_tl(temp
, arg2
, arg3
);
1214 } else { /* n is expected to be 1 */
1215 tcg_gen_mul_tl(temp
, arg2
, arg3
);
1216 tcg_gen_shli_tl(temp
, temp
, 1);
1217 /* catch special case r1 = r2 = 0x8000 */
1218 tcg_gen_setcondi_tl(TCG_COND_EQ
, temp2
, temp
, 0x80000000);
1219 tcg_gen_sub_tl(temp
, temp
, temp2
);
1221 tcg_gen_ext_i32_i64(t2
, temp
);
1222 tcg_gen_shli_i64(t2
, t2
, 16);
1223 tcg_gen_concat_i32_i64(t1
, arg1_low
, arg1_high
);
1224 gen_add64_d(t3
, t1
, t2
);
1225 /* write back result */
1226 tcg_gen_extr_i64_i32(rl
, rh
, t3
);
1228 tcg_temp_free_i64(t1
);
1229 tcg_temp_free_i64(t2
);
1230 tcg_temp_free_i64(t3
);
1231 tcg_temp_free(temp
);
1232 tcg_temp_free(temp2
);
1236 gen_m16adds64_q(TCGv rl
, TCGv rh
, TCGv arg1_low
, TCGv arg1_high
, TCGv arg2
,
1237 TCGv arg3
, uint32_t n
)
1239 TCGv temp
= tcg_temp_new();
1240 TCGv temp2
= tcg_temp_new();
1241 TCGv_i64 t1
= tcg_temp_new_i64();
1242 TCGv_i64 t2
= tcg_temp_new_i64();
1245 tcg_gen_mul_tl(temp
, arg2
, arg3
);
1246 } else { /* n is expected to be 1 */
1247 tcg_gen_mul_tl(temp
, arg2
, arg3
);
1248 tcg_gen_shli_tl(temp
, temp
, 1);
1249 /* catch special case r1 = r2 = 0x8000 */
1250 tcg_gen_setcondi_tl(TCG_COND_EQ
, temp2
, temp
, 0x80000000);
1251 tcg_gen_sub_tl(temp
, temp
, temp2
);
1253 tcg_gen_ext_i32_i64(t2
, temp
);
1254 tcg_gen_shli_i64(t2
, t2
, 16);
1255 tcg_gen_concat_i32_i64(t1
, arg1_low
, arg1_high
);
1257 gen_helper_add64_ssov(t1
, cpu_env
, t1
, t2
);
1258 tcg_gen_extr_i64_i32(rl
, rh
, t1
);
1260 tcg_temp_free(temp
);
1261 tcg_temp_free(temp2
);
1262 tcg_temp_free_i64(t1
);
1263 tcg_temp_free_i64(t2
);
1267 gen_madd64_q(TCGv rl
, TCGv rh
, TCGv arg1_low
, TCGv arg1_high
, TCGv arg2
,
1268 TCGv arg3
, uint32_t n
, CPUTriCoreState
*env
)
1270 TCGv_i64 t1
= tcg_temp_new_i64();
1271 TCGv_i64 t2
= tcg_temp_new_i64();
1272 TCGv_i64 t3
= tcg_temp_new_i64();
1273 TCGv_i64 t4
= tcg_temp_new_i64();
1276 tcg_gen_concat_i32_i64(t1
, arg1_low
, arg1_high
);
1277 tcg_gen_ext_i32_i64(t2
, arg2
);
1278 tcg_gen_ext_i32_i64(t3
, arg3
);
1280 tcg_gen_mul_i64(t2
, t2
, t3
);
1282 tcg_gen_shli_i64(t2
, t2
, 1);
1284 tcg_gen_add_i64(t4
, t1
, t2
);
1286 tcg_gen_xor_i64(t3
, t4
, t1
);
1287 tcg_gen_xor_i64(t2
, t1
, t2
);
1288 tcg_gen_andc_i64(t3
, t3
, t2
);
1289 tcg_gen_extrh_i64_i32(cpu_PSW_V
, t3
);
1290 /* We produce an overflow on the host if the mul before was
1291 (0x80000000 * 0x80000000) << 1). If this is the
1292 case, we negate the ovf. */
1294 temp
= tcg_temp_new();
1295 temp2
= tcg_temp_new();
1296 tcg_gen_setcondi_tl(TCG_COND_EQ
, temp
, arg2
, 0x80000000);
1297 tcg_gen_setcond_tl(TCG_COND_EQ
, temp2
, arg2
, arg3
);
1298 tcg_gen_and_tl(temp
, temp
, temp2
);
1299 tcg_gen_shli_tl(temp
, temp
, 31);
1300 /* negate v bit, if special condition */
1301 tcg_gen_xor_tl(cpu_PSW_V
, cpu_PSW_V
, temp
);
1303 tcg_temp_free(temp
);
1304 tcg_temp_free(temp2
);
1306 /* write back result */
1307 tcg_gen_extr_i64_i32(rl
, rh
, t4
);
1309 tcg_gen_or_tl(cpu_PSW_SV
, cpu_PSW_SV
, cpu_PSW_V
);
1310 /* Calc AV/SAV bits */
1311 tcg_gen_add_tl(cpu_PSW_AV
, rh
, rh
);
1312 tcg_gen_xor_tl(cpu_PSW_AV
, rh
, cpu_PSW_AV
);
1314 tcg_gen_or_tl(cpu_PSW_SAV
, cpu_PSW_SAV
, cpu_PSW_AV
);
1316 tcg_temp_free_i64(t1
);
1317 tcg_temp_free_i64(t2
);
1318 tcg_temp_free_i64(t3
);
1319 tcg_temp_free_i64(t4
);
1323 gen_madds32_q(TCGv ret
, TCGv arg1
, TCGv arg2
, TCGv arg3
, uint32_t n
,
1326 TCGv_i64 t1
= tcg_temp_new_i64();
1327 TCGv_i64 t2
= tcg_temp_new_i64();
1328 TCGv_i64 t3
= tcg_temp_new_i64();
1330 tcg_gen_ext_i32_i64(t1
, arg1
);
1331 tcg_gen_ext_i32_i64(t2
, arg2
);
1332 tcg_gen_ext_i32_i64(t3
, arg3
);
1334 tcg_gen_mul_i64(t2
, t2
, t3
);
1335 tcg_gen_sari_i64(t2
, t2
, up_shift
- n
);
1337 gen_helper_madd32_q_add_ssov(ret
, cpu_env
, t1
, t2
);
1339 tcg_temp_free_i64(t1
);
1340 tcg_temp_free_i64(t2
);
1341 tcg_temp_free_i64(t3
);
1345 gen_madds64_q(TCGv rl
, TCGv rh
, TCGv arg1_low
, TCGv arg1_high
, TCGv arg2
,
1346 TCGv arg3
, uint32_t n
)
1348 TCGv_i64 r1
= tcg_temp_new_i64();
1349 TCGv temp
= tcg_const_i32(n
);
1351 tcg_gen_concat_i32_i64(r1
, arg1_low
, arg1_high
);
1352 gen_helper_madd64_q_ssov(r1
, cpu_env
, r1
, arg2
, arg3
, temp
);
1353 tcg_gen_extr_i64_i32(rl
, rh
, r1
);
1355 tcg_temp_free_i64(r1
);
1356 tcg_temp_free(temp
);
1358 /* ret = r2 - (r1 * r3); */
1359 static inline void gen_msub32_d(TCGv ret
, TCGv r1
, TCGv r2
, TCGv r3
)
1361 TCGv_i64 t1
= tcg_temp_new_i64();
1362 TCGv_i64 t2
= tcg_temp_new_i64();
1363 TCGv_i64 t3
= tcg_temp_new_i64();
1365 tcg_gen_ext_i32_i64(t1
, r1
);
1366 tcg_gen_ext_i32_i64(t2
, r2
);
1367 tcg_gen_ext_i32_i64(t3
, r3
);
1369 tcg_gen_mul_i64(t1
, t1
, t3
);
1370 tcg_gen_sub_i64(t1
, t2
, t1
);
1372 tcg_gen_extrl_i64_i32(ret
, t1
);
1375 tcg_gen_setcondi_i64(TCG_COND_GT
, t3
, t1
, 0x7fffffffLL
);
1376 /* result < -0x80000000 */
1377 tcg_gen_setcondi_i64(TCG_COND_LT
, t2
, t1
, -0x80000000LL
);
1378 tcg_gen_or_i64(t2
, t2
, t3
);
1379 tcg_gen_extrl_i64_i32(cpu_PSW_V
, t2
);
1380 tcg_gen_shli_tl(cpu_PSW_V
, cpu_PSW_V
, 31);
1383 tcg_gen_or_tl(cpu_PSW_SV
, cpu_PSW_SV
, cpu_PSW_V
);
1384 /* Calc AV/SAV bits */
1385 tcg_gen_add_tl(cpu_PSW_AV
, ret
, ret
);
1386 tcg_gen_xor_tl(cpu_PSW_AV
, ret
, cpu_PSW_AV
);
1388 tcg_gen_or_tl(cpu_PSW_SAV
, cpu_PSW_SAV
, cpu_PSW_AV
);
1390 tcg_temp_free_i64(t1
);
1391 tcg_temp_free_i64(t2
);
1392 tcg_temp_free_i64(t3
);
1395 static inline void gen_msubi32_d(TCGv ret
, TCGv r1
, TCGv r2
, int32_t con
)
1397 TCGv temp
= tcg_const_i32(con
);
1398 gen_msub32_d(ret
, r1
, r2
, temp
);
1399 tcg_temp_free(temp
);
1403 gen_msub64_d(TCGv ret_low
, TCGv ret_high
, TCGv r1
, TCGv r2_low
, TCGv r2_high
,
1406 TCGv t1
= tcg_temp_new();
1407 TCGv t2
= tcg_temp_new();
1408 TCGv t3
= tcg_temp_new();
1409 TCGv t4
= tcg_temp_new();
1411 tcg_gen_muls2_tl(t1
, t2
, r1
, r3
);
1412 /* only the sub can overflow */
1413 tcg_gen_sub2_tl(t3
, t4
, r2_low
, r2_high
, t1
, t2
);
1415 tcg_gen_xor_tl(cpu_PSW_V
, t4
, r2_high
);
1416 tcg_gen_xor_tl(t1
, r2_high
, t2
);
1417 tcg_gen_and_tl(cpu_PSW_V
, cpu_PSW_V
, t1
);
1419 tcg_gen_or_tl(cpu_PSW_SV
, cpu_PSW_SV
, cpu_PSW_V
);
1420 /* Calc AV/SAV bits */
1421 tcg_gen_add_tl(cpu_PSW_AV
, t4
, t4
);
1422 tcg_gen_xor_tl(cpu_PSW_AV
, t4
, cpu_PSW_AV
);
1424 tcg_gen_or_tl(cpu_PSW_SAV
, cpu_PSW_SAV
, cpu_PSW_AV
);
1425 /* write back the result */
1426 tcg_gen_mov_tl(ret_low
, t3
);
1427 tcg_gen_mov_tl(ret_high
, t4
);
1436 gen_msubi64_d(TCGv ret_low
, TCGv ret_high
, TCGv r1
, TCGv r2_low
, TCGv r2_high
,
1439 TCGv temp
= tcg_const_i32(con
);
1440 gen_msub64_d(ret_low
, ret_high
, r1
, r2_low
, r2_high
, temp
);
1441 tcg_temp_free(temp
);
1445 gen_msubu64_d(TCGv ret_low
, TCGv ret_high
, TCGv r1
, TCGv r2_low
, TCGv r2_high
,
1448 TCGv_i64 t1
= tcg_temp_new_i64();
1449 TCGv_i64 t2
= tcg_temp_new_i64();
1450 TCGv_i64 t3
= tcg_temp_new_i64();
1452 tcg_gen_extu_i32_i64(t1
, r1
);
1453 tcg_gen_concat_i32_i64(t2
, r2_low
, r2_high
);
1454 tcg_gen_extu_i32_i64(t3
, r3
);
1456 tcg_gen_mul_i64(t1
, t1
, t3
);
1457 tcg_gen_sub_i64(t3
, t2
, t1
);
1458 tcg_gen_extr_i64_i32(ret_low
, ret_high
, t3
);
1459 /* calc V bit, only the sub can overflow, if t1 > t2 */
1460 tcg_gen_setcond_i64(TCG_COND_GTU
, t1
, t1
, t2
);
1461 tcg_gen_extrl_i64_i32(cpu_PSW_V
, t1
);
1462 tcg_gen_shli_tl(cpu_PSW_V
, cpu_PSW_V
, 31);
1464 tcg_gen_or_tl(cpu_PSW_SV
, cpu_PSW_SV
, cpu_PSW_V
);
1465 /* Calc AV/SAV bits */
1466 tcg_gen_add_tl(cpu_PSW_AV
, ret_high
, ret_high
);
1467 tcg_gen_xor_tl(cpu_PSW_AV
, ret_high
, cpu_PSW_AV
);
1469 tcg_gen_or_tl(cpu_PSW_SAV
, cpu_PSW_SAV
, cpu_PSW_AV
);
1471 tcg_temp_free_i64(t1
);
1472 tcg_temp_free_i64(t2
);
1473 tcg_temp_free_i64(t3
);
1477 gen_msubui64_d(TCGv ret_low
, TCGv ret_high
, TCGv r1
, TCGv r2_low
, TCGv r2_high
,
1480 TCGv temp
= tcg_const_i32(con
);
1481 gen_msubu64_d(ret_low
, ret_high
, r1
, r2_low
, r2_high
, temp
);
1482 tcg_temp_free(temp
);
1485 static inline void gen_addi_d(TCGv ret
, TCGv r1
, target_ulong r2
)
1487 TCGv temp
= tcg_const_i32(r2
);
1488 gen_add_d(ret
, r1
, temp
);
1489 tcg_temp_free(temp
);
1491 /* calculate the carry bit too */
1492 static inline void gen_add_CC(TCGv ret
, TCGv r1
, TCGv r2
)
1494 TCGv t0
= tcg_temp_new_i32();
1495 TCGv result
= tcg_temp_new_i32();
1497 tcg_gen_movi_tl(t0
, 0);
1498 /* Addition and set C/V/SV bits */
1499 tcg_gen_add2_i32(result
, cpu_PSW_C
, r1
, t0
, r2
, t0
);
1501 tcg_gen_xor_tl(cpu_PSW_V
, result
, r1
);
1502 tcg_gen_xor_tl(t0
, r1
, r2
);
1503 tcg_gen_andc_tl(cpu_PSW_V
, cpu_PSW_V
, t0
);
1505 tcg_gen_or_tl(cpu_PSW_SV
, cpu_PSW_SV
, cpu_PSW_V
);
1506 /* Calc AV/SAV bits */
1507 tcg_gen_add_tl(cpu_PSW_AV
, result
, result
);
1508 tcg_gen_xor_tl(cpu_PSW_AV
, result
, cpu_PSW_AV
);
1510 tcg_gen_or_tl(cpu_PSW_SAV
, cpu_PSW_SAV
, cpu_PSW_AV
);
1511 /* write back result */
1512 tcg_gen_mov_tl(ret
, result
);
1514 tcg_temp_free(result
);
1518 static inline void gen_addi_CC(TCGv ret
, TCGv r1
, int32_t con
)
1520 TCGv temp
= tcg_const_i32(con
);
1521 gen_add_CC(ret
, r1
, temp
);
1522 tcg_temp_free(temp
);
1525 static inline void gen_addc_CC(TCGv ret
, TCGv r1
, TCGv r2
)
1527 TCGv carry
= tcg_temp_new_i32();
1528 TCGv t0
= tcg_temp_new_i32();
1529 TCGv result
= tcg_temp_new_i32();
1531 tcg_gen_movi_tl(t0
, 0);
1532 tcg_gen_setcondi_tl(TCG_COND_NE
, carry
, cpu_PSW_C
, 0);
1533 /* Addition, carry and set C/V/SV bits */
1534 tcg_gen_add2_i32(result
, cpu_PSW_C
, r1
, t0
, carry
, t0
);
1535 tcg_gen_add2_i32(result
, cpu_PSW_C
, result
, cpu_PSW_C
, r2
, t0
);
1537 tcg_gen_xor_tl(cpu_PSW_V
, result
, r1
);
1538 tcg_gen_xor_tl(t0
, r1
, r2
);
1539 tcg_gen_andc_tl(cpu_PSW_V
, cpu_PSW_V
, t0
);
1541 tcg_gen_or_tl(cpu_PSW_SV
, cpu_PSW_SV
, cpu_PSW_V
);
1542 /* Calc AV/SAV bits */
1543 tcg_gen_add_tl(cpu_PSW_AV
, result
, result
);
1544 tcg_gen_xor_tl(cpu_PSW_AV
, result
, cpu_PSW_AV
);
1546 tcg_gen_or_tl(cpu_PSW_SAV
, cpu_PSW_SAV
, cpu_PSW_AV
);
1547 /* write back result */
1548 tcg_gen_mov_tl(ret
, result
);
1550 tcg_temp_free(result
);
1552 tcg_temp_free(carry
);
1555 static inline void gen_addci_CC(TCGv ret
, TCGv r1
, int32_t con
)
1557 TCGv temp
= tcg_const_i32(con
);
1558 gen_addc_CC(ret
, r1
, temp
);
1559 tcg_temp_free(temp
);
1562 static inline void gen_cond_add(TCGCond cond
, TCGv r1
, TCGv r2
, TCGv r3
,
1565 TCGv temp
= tcg_temp_new();
1566 TCGv temp2
= tcg_temp_new();
1567 TCGv result
= tcg_temp_new();
1568 TCGv mask
= tcg_temp_new();
1569 TCGv t0
= tcg_const_i32(0);
1571 /* create mask for sticky bits */
1572 tcg_gen_setcond_tl(cond
, mask
, r4
, t0
);
1573 tcg_gen_shli_tl(mask
, mask
, 31);
1575 tcg_gen_add_tl(result
, r1
, r2
);
1577 tcg_gen_xor_tl(temp
, result
, r1
);
1578 tcg_gen_xor_tl(temp2
, r1
, r2
);
1579 tcg_gen_andc_tl(temp
, temp
, temp2
);
1580 tcg_gen_movcond_tl(cond
, cpu_PSW_V
, r4
, t0
, temp
, cpu_PSW_V
);
1582 tcg_gen_and_tl(temp
, temp
, mask
);
1583 tcg_gen_or_tl(cpu_PSW_SV
, temp
, cpu_PSW_SV
);
1585 tcg_gen_add_tl(temp
, result
, result
);
1586 tcg_gen_xor_tl(temp
, temp
, result
);
1587 tcg_gen_movcond_tl(cond
, cpu_PSW_AV
, r4
, t0
, temp
, cpu_PSW_AV
);
1589 tcg_gen_and_tl(temp
, temp
, mask
);
1590 tcg_gen_or_tl(cpu_PSW_SAV
, temp
, cpu_PSW_SAV
);
1591 /* write back result */
1592 tcg_gen_movcond_tl(cond
, r3
, r4
, t0
, result
, r1
);
1595 tcg_temp_free(temp
);
1596 tcg_temp_free(temp2
);
1597 tcg_temp_free(result
);
1598 tcg_temp_free(mask
);
1601 static inline void gen_condi_add(TCGCond cond
, TCGv r1
, int32_t r2
,
1604 TCGv temp
= tcg_const_i32(r2
);
1605 gen_cond_add(cond
, r1
, temp
, r3
, r4
);
1606 tcg_temp_free(temp
);
1609 static inline void gen_sub_d(TCGv ret
, TCGv r1
, TCGv r2
)
1611 TCGv temp
= tcg_temp_new_i32();
1612 TCGv result
= tcg_temp_new_i32();
1614 tcg_gen_sub_tl(result
, r1
, r2
);
1616 tcg_gen_xor_tl(cpu_PSW_V
, result
, r1
);
1617 tcg_gen_xor_tl(temp
, r1
, r2
);
1618 tcg_gen_and_tl(cpu_PSW_V
, cpu_PSW_V
, temp
);
1620 tcg_gen_or_tl(cpu_PSW_SV
, cpu_PSW_SV
, cpu_PSW_V
);
1622 tcg_gen_add_tl(cpu_PSW_AV
, result
, result
);
1623 tcg_gen_xor_tl(cpu_PSW_AV
, result
, cpu_PSW_AV
);
1625 tcg_gen_or_tl(cpu_PSW_SAV
, cpu_PSW_SAV
, cpu_PSW_AV
);
1626 /* write back result */
1627 tcg_gen_mov_tl(ret
, result
);
1629 tcg_temp_free(temp
);
1630 tcg_temp_free(result
);
1634 gen_sub64_d(TCGv_i64 ret
, TCGv_i64 r1
, TCGv_i64 r2
)
1636 TCGv temp
= tcg_temp_new();
1637 TCGv_i64 t0
= tcg_temp_new_i64();
1638 TCGv_i64 t1
= tcg_temp_new_i64();
1639 TCGv_i64 result
= tcg_temp_new_i64();
1641 tcg_gen_sub_i64(result
, r1
, r2
);
1643 tcg_gen_xor_i64(t1
, result
, r1
);
1644 tcg_gen_xor_i64(t0
, r1
, r2
);
1645 tcg_gen_and_i64(t1
, t1
, t0
);
1646 tcg_gen_extrh_i64_i32(cpu_PSW_V
, t1
);
1648 tcg_gen_or_tl(cpu_PSW_SV
, cpu_PSW_SV
, cpu_PSW_V
);
1649 /* calc AV/SAV bits */
1650 tcg_gen_extrh_i64_i32(temp
, result
);
1651 tcg_gen_add_tl(cpu_PSW_AV
, temp
, temp
);
1652 tcg_gen_xor_tl(cpu_PSW_AV
, temp
, cpu_PSW_AV
);
1654 tcg_gen_or_tl(cpu_PSW_SAV
, cpu_PSW_SAV
, cpu_PSW_AV
);
1655 /* write back result */
1656 tcg_gen_mov_i64(ret
, result
);
1658 tcg_temp_free(temp
);
1659 tcg_temp_free_i64(result
);
1660 tcg_temp_free_i64(t0
);
1661 tcg_temp_free_i64(t1
);
1664 static inline void gen_sub_CC(TCGv ret
, TCGv r1
, TCGv r2
)
1666 TCGv result
= tcg_temp_new();
1667 TCGv temp
= tcg_temp_new();
1669 tcg_gen_sub_tl(result
, r1
, r2
);
1671 tcg_gen_setcond_tl(TCG_COND_GEU
, cpu_PSW_C
, r1
, r2
);
1673 tcg_gen_xor_tl(cpu_PSW_V
, result
, r1
);
1674 tcg_gen_xor_tl(temp
, r1
, r2
);
1675 tcg_gen_and_tl(cpu_PSW_V
, cpu_PSW_V
, temp
);
1677 tcg_gen_or_tl(cpu_PSW_SV
, cpu_PSW_SV
, cpu_PSW_V
);
1679 tcg_gen_add_tl(cpu_PSW_AV
, result
, result
);
1680 tcg_gen_xor_tl(cpu_PSW_AV
, result
, cpu_PSW_AV
);
1682 tcg_gen_or_tl(cpu_PSW_SAV
, cpu_PSW_SAV
, cpu_PSW_AV
);
1683 /* write back result */
1684 tcg_gen_mov_tl(ret
, result
);
1686 tcg_temp_free(result
);
1687 tcg_temp_free(temp
);
1690 static inline void gen_subc_CC(TCGv ret
, TCGv r1
, TCGv r2
)
1692 TCGv temp
= tcg_temp_new();
1693 tcg_gen_not_tl(temp
, r2
);
1694 gen_addc_CC(ret
, r1
, temp
);
1695 tcg_temp_free(temp
);
1698 static inline void gen_cond_sub(TCGCond cond
, TCGv r1
, TCGv r2
, TCGv r3
,
1701 TCGv temp
= tcg_temp_new();
1702 TCGv temp2
= tcg_temp_new();
1703 TCGv result
= tcg_temp_new();
1704 TCGv mask
= tcg_temp_new();
1705 TCGv t0
= tcg_const_i32(0);
1707 /* create mask for sticky bits */
1708 tcg_gen_setcond_tl(cond
, mask
, r4
, t0
);
1709 tcg_gen_shli_tl(mask
, mask
, 31);
1711 tcg_gen_sub_tl(result
, r1
, r2
);
1713 tcg_gen_xor_tl(temp
, result
, r1
);
1714 tcg_gen_xor_tl(temp2
, r1
, r2
);
1715 tcg_gen_and_tl(temp
, temp
, temp2
);
1716 tcg_gen_movcond_tl(cond
, cpu_PSW_V
, r4
, t0
, temp
, cpu_PSW_V
);
1718 tcg_gen_and_tl(temp
, temp
, mask
);
1719 tcg_gen_or_tl(cpu_PSW_SV
, temp
, cpu_PSW_SV
);
1721 tcg_gen_add_tl(temp
, result
, result
);
1722 tcg_gen_xor_tl(temp
, temp
, result
);
1723 tcg_gen_movcond_tl(cond
, cpu_PSW_AV
, r4
, t0
, temp
, cpu_PSW_AV
);
1725 tcg_gen_and_tl(temp
, temp
, mask
);
1726 tcg_gen_or_tl(cpu_PSW_SAV
, temp
, cpu_PSW_SAV
);
1727 /* write back result */
1728 tcg_gen_movcond_tl(cond
, r3
, r4
, t0
, result
, r1
);
1731 tcg_temp_free(temp
);
1732 tcg_temp_free(temp2
);
1733 tcg_temp_free(result
);
1734 tcg_temp_free(mask
);
1738 gen_msub_h(TCGv ret_low
, TCGv ret_high
, TCGv r1_low
, TCGv r1_high
, TCGv r2
,
1739 TCGv r3
, uint32_t n
, uint32_t mode
)
1741 TCGv temp
= tcg_const_i32(n
);
1742 TCGv temp2
= tcg_temp_new();
1743 TCGv_i64 temp64
= tcg_temp_new_i64();
1746 GEN_HELPER_LL(mul_h
, temp64
, r2
, r3
, temp
);
1749 GEN_HELPER_LU(mul_h
, temp64
, r2
, r3
, temp
);
1752 GEN_HELPER_UL(mul_h
, temp64
, r2
, r3
, temp
);
1755 GEN_HELPER_UU(mul_h
, temp64
, r2
, r3
, temp
);
1758 tcg_gen_extr_i64_i32(temp
, temp2
, temp64
);
1759 gen_addsub64_h(ret_low
, ret_high
, r1_low
, r1_high
, temp
, temp2
,
1760 tcg_gen_sub_tl
, tcg_gen_sub_tl
);
1761 tcg_temp_free(temp
);
1762 tcg_temp_free(temp2
);
1763 tcg_temp_free_i64(temp64
);
1767 gen_msubs_h(TCGv ret_low
, TCGv ret_high
, TCGv r1_low
, TCGv r1_high
, TCGv r2
,
1768 TCGv r3
, uint32_t n
, uint32_t mode
)
1770 TCGv temp
= tcg_const_i32(n
);
1771 TCGv temp2
= tcg_temp_new();
1772 TCGv temp3
= tcg_temp_new();
1773 TCGv_i64 temp64
= tcg_temp_new_i64();
1777 GEN_HELPER_LL(mul_h
, temp64
, r2
, r3
, temp
);
1780 GEN_HELPER_LU(mul_h
, temp64
, r2
, r3
, temp
);
1783 GEN_HELPER_UL(mul_h
, temp64
, r2
, r3
, temp
);
1786 GEN_HELPER_UU(mul_h
, temp64
, r2
, r3
, temp
);
1789 tcg_gen_extr_i64_i32(temp
, temp2
, temp64
);
1790 gen_subs(ret_low
, r1_low
, temp
);
1791 tcg_gen_mov_tl(temp
, cpu_PSW_V
);
1792 tcg_gen_mov_tl(temp3
, cpu_PSW_AV
);
1793 gen_subs(ret_high
, r1_high
, temp2
);
1794 /* combine v bits */
1795 tcg_gen_or_tl(cpu_PSW_V
, cpu_PSW_V
, temp
);
1796 /* combine av bits */
1797 tcg_gen_or_tl(cpu_PSW_AV
, cpu_PSW_AV
, temp3
);
1799 tcg_temp_free(temp
);
1800 tcg_temp_free(temp2
);
1801 tcg_temp_free(temp3
);
1802 tcg_temp_free_i64(temp64
);
1806 gen_msubm_h(TCGv ret_low
, TCGv ret_high
, TCGv r1_low
, TCGv r1_high
, TCGv r2
,
1807 TCGv r3
, uint32_t n
, uint32_t mode
)
1809 TCGv temp
= tcg_const_i32(n
);
1810 TCGv_i64 temp64
= tcg_temp_new_i64();
1811 TCGv_i64 temp64_2
= tcg_temp_new_i64();
1812 TCGv_i64 temp64_3
= tcg_temp_new_i64();
1815 GEN_HELPER_LL(mulm_h
, temp64
, r2
, r3
, temp
);
1818 GEN_HELPER_LU(mulm_h
, temp64
, r2
, r3
, temp
);
1821 GEN_HELPER_UL(mulm_h
, temp64
, r2
, r3
, temp
);
1824 GEN_HELPER_UU(mulm_h
, temp64
, r2
, r3
, temp
);
1827 tcg_gen_concat_i32_i64(temp64_2
, r1_low
, r1_high
);
1828 gen_sub64_d(temp64_3
, temp64_2
, temp64
);
1829 /* write back result */
1830 tcg_gen_extr_i64_i32(ret_low
, ret_high
, temp64_3
);
1832 tcg_temp_free(temp
);
1833 tcg_temp_free_i64(temp64
);
1834 tcg_temp_free_i64(temp64_2
);
1835 tcg_temp_free_i64(temp64_3
);
1839 gen_msubms_h(TCGv ret_low
, TCGv ret_high
, TCGv r1_low
, TCGv r1_high
, TCGv r2
,
1840 TCGv r3
, uint32_t n
, uint32_t mode
)
1842 TCGv temp
= tcg_const_i32(n
);
1843 TCGv_i64 temp64
= tcg_temp_new_i64();
1844 TCGv_i64 temp64_2
= tcg_temp_new_i64();
1847 GEN_HELPER_LL(mulm_h
, temp64
, r2
, r3
, temp
);
1850 GEN_HELPER_LU(mulm_h
, temp64
, r2
, r3
, temp
);
1853 GEN_HELPER_UL(mulm_h
, temp64
, r2
, r3
, temp
);
1856 GEN_HELPER_UU(mulm_h
, temp64
, r2
, r3
, temp
);
1859 tcg_gen_concat_i32_i64(temp64_2
, r1_low
, r1_high
);
1860 gen_helper_sub64_ssov(temp64
, cpu_env
, temp64_2
, temp64
);
1861 tcg_gen_extr_i64_i32(ret_low
, ret_high
, temp64
);
1863 tcg_temp_free(temp
);
1864 tcg_temp_free_i64(temp64
);
1865 tcg_temp_free_i64(temp64_2
);
1869 gen_msubr64_h(TCGv ret
, TCGv r1_low
, TCGv r1_high
, TCGv r2
, TCGv r3
, uint32_t n
,
1872 TCGv temp
= tcg_const_i32(n
);
1873 TCGv_i64 temp64
= tcg_temp_new_i64();
1876 GEN_HELPER_LL(mul_h
, temp64
, r2
, r3
, temp
);
1879 GEN_HELPER_LU(mul_h
, temp64
, r2
, r3
, temp
);
1882 GEN_HELPER_UL(mul_h
, temp64
, r2
, r3
, temp
);
1885 GEN_HELPER_UU(mul_h
, temp64
, r2
, r3
, temp
);
1888 gen_helper_subr_h(ret
, cpu_env
, temp64
, r1_low
, r1_high
);
1890 tcg_temp_free(temp
);
1891 tcg_temp_free_i64(temp64
);
1895 gen_msubr32_h(TCGv ret
, TCGv r1
, TCGv r2
, TCGv r3
, uint32_t n
, uint32_t mode
)
1897 TCGv temp
= tcg_temp_new();
1898 TCGv temp2
= tcg_temp_new();
1900 tcg_gen_andi_tl(temp2
, r1
, 0xffff0000);
1901 tcg_gen_shli_tl(temp
, r1
, 16);
1902 gen_msubr64_h(ret
, temp
, temp2
, r2
, r3
, n
, mode
);
1904 tcg_temp_free(temp
);
1905 tcg_temp_free(temp2
);
1909 gen_msubr64s_h(TCGv ret
, TCGv r1_low
, TCGv r1_high
, TCGv r2
, TCGv r3
,
1910 uint32_t n
, uint32_t mode
)
1912 TCGv temp
= tcg_const_i32(n
);
1913 TCGv_i64 temp64
= tcg_temp_new_i64();
1916 GEN_HELPER_LL(mul_h
, temp64
, r2
, r3
, temp
);
1919 GEN_HELPER_LU(mul_h
, temp64
, r2
, r3
, temp
);
1922 GEN_HELPER_UL(mul_h
, temp64
, r2
, r3
, temp
);
1925 GEN_HELPER_UU(mul_h
, temp64
, r2
, r3
, temp
);
1928 gen_helper_subr_h_ssov(ret
, cpu_env
, temp64
, r1_low
, r1_high
);
1930 tcg_temp_free(temp
);
1931 tcg_temp_free_i64(temp64
);
1935 gen_msubr32s_h(TCGv ret
, TCGv r1
, TCGv r2
, TCGv r3
, uint32_t n
, uint32_t mode
)
1937 TCGv temp
= tcg_temp_new();
1938 TCGv temp2
= tcg_temp_new();
1940 tcg_gen_andi_tl(temp2
, r1
, 0xffff0000);
1941 tcg_gen_shli_tl(temp
, r1
, 16);
1942 gen_msubr64s_h(ret
, temp
, temp2
, r2
, r3
, n
, mode
);
1944 tcg_temp_free(temp
);
1945 tcg_temp_free(temp2
);
1949 gen_msubr_q(TCGv ret
, TCGv r1
, TCGv r2
, TCGv r3
, uint32_t n
)
1951 TCGv temp
= tcg_const_i32(n
);
1952 gen_helper_msubr_q(ret
, cpu_env
, r1
, r2
, r3
, temp
);
1953 tcg_temp_free(temp
);
1957 gen_msubrs_q(TCGv ret
, TCGv r1
, TCGv r2
, TCGv r3
, uint32_t n
)
1959 TCGv temp
= tcg_const_i32(n
);
1960 gen_helper_msubr_q_ssov(ret
, cpu_env
, r1
, r2
, r3
, temp
);
1961 tcg_temp_free(temp
);
1965 gen_msub32_q(TCGv ret
, TCGv arg1
, TCGv arg2
, TCGv arg3
, uint32_t n
,
1966 uint32_t up_shift
, CPUTriCoreState
*env
)
1968 TCGv temp
= tcg_temp_new();
1969 TCGv temp2
= tcg_temp_new();
1970 TCGv temp3
= tcg_temp_new();
1971 TCGv_i64 t1
= tcg_temp_new_i64();
1972 TCGv_i64 t2
= tcg_temp_new_i64();
1973 TCGv_i64 t3
= tcg_temp_new_i64();
1974 TCGv_i64 t4
= tcg_temp_new_i64();
1976 tcg_gen_ext_i32_i64(t2
, arg2
);
1977 tcg_gen_ext_i32_i64(t3
, arg3
);
1979 tcg_gen_mul_i64(t2
, t2
, t3
);
1981 tcg_gen_ext_i32_i64(t1
, arg1
);
1982 /* if we shift part of the fraction out, we need to round up */
1983 tcg_gen_andi_i64(t4
, t2
, (1ll << (up_shift
- n
)) - 1);
1984 tcg_gen_setcondi_i64(TCG_COND_NE
, t4
, t4
, 0);
1985 tcg_gen_sari_i64(t2
, t2
, up_shift
- n
);
1986 tcg_gen_add_i64(t2
, t2
, t4
);
1988 tcg_gen_sub_i64(t3
, t1
, t2
);
1989 tcg_gen_extrl_i64_i32(temp3
, t3
);
1991 tcg_gen_setcondi_i64(TCG_COND_GT
, t1
, t3
, 0x7fffffffLL
);
1992 tcg_gen_setcondi_i64(TCG_COND_LT
, t2
, t3
, -0x80000000LL
);
1993 tcg_gen_or_i64(t1
, t1
, t2
);
1994 tcg_gen_extrl_i64_i32(cpu_PSW_V
, t1
);
1995 tcg_gen_shli_tl(cpu_PSW_V
, cpu_PSW_V
, 31);
1997 tcg_gen_or_tl(cpu_PSW_SV
, cpu_PSW_SV
, cpu_PSW_V
);
1998 /* Calc AV/SAV bits */
1999 tcg_gen_add_tl(cpu_PSW_AV
, temp3
, temp3
);
2000 tcg_gen_xor_tl(cpu_PSW_AV
, temp3
, cpu_PSW_AV
);
2002 tcg_gen_or_tl(cpu_PSW_SAV
, cpu_PSW_SAV
, cpu_PSW_AV
);
2003 /* write back result */
2004 tcg_gen_mov_tl(ret
, temp3
);
2006 tcg_temp_free(temp
);
2007 tcg_temp_free(temp2
);
2008 tcg_temp_free(temp3
);
2009 tcg_temp_free_i64(t1
);
2010 tcg_temp_free_i64(t2
);
2011 tcg_temp_free_i64(t3
);
2012 tcg_temp_free_i64(t4
);
2016 gen_m16sub32_q(TCGv ret
, TCGv arg1
, TCGv arg2
, TCGv arg3
, uint32_t n
)
2018 TCGv temp
= tcg_temp_new();
2019 TCGv temp2
= tcg_temp_new();
2021 tcg_gen_mul_tl(temp
, arg2
, arg3
);
2022 } else { /* n is expected to be 1 */
2023 tcg_gen_mul_tl(temp
, arg2
, arg3
);
2024 tcg_gen_shli_tl(temp
, temp
, 1);
2025 /* catch special case r1 = r2 = 0x8000 */
2026 tcg_gen_setcondi_tl(TCG_COND_EQ
, temp2
, temp
, 0x80000000);
2027 tcg_gen_sub_tl(temp
, temp
, temp2
);
2029 gen_sub_d(ret
, arg1
, temp
);
2031 tcg_temp_free(temp
);
2032 tcg_temp_free(temp2
);
2036 gen_m16subs32_q(TCGv ret
, TCGv arg1
, TCGv arg2
, TCGv arg3
, uint32_t n
)
2038 TCGv temp
= tcg_temp_new();
2039 TCGv temp2
= tcg_temp_new();
2041 tcg_gen_mul_tl(temp
, arg2
, arg3
);
2042 } else { /* n is expected to be 1 */
2043 tcg_gen_mul_tl(temp
, arg2
, arg3
);
2044 tcg_gen_shli_tl(temp
, temp
, 1);
2045 /* catch special case r1 = r2 = 0x8000 */
2046 tcg_gen_setcondi_tl(TCG_COND_EQ
, temp2
, temp
, 0x80000000);
2047 tcg_gen_sub_tl(temp
, temp
, temp2
);
2049 gen_subs(ret
, arg1
, temp
);
2051 tcg_temp_free(temp
);
2052 tcg_temp_free(temp2
);
2056 gen_m16sub64_q(TCGv rl
, TCGv rh
, TCGv arg1_low
, TCGv arg1_high
, TCGv arg2
,
2057 TCGv arg3
, uint32_t n
)
2059 TCGv temp
= tcg_temp_new();
2060 TCGv temp2
= tcg_temp_new();
2061 TCGv_i64 t1
= tcg_temp_new_i64();
2062 TCGv_i64 t2
= tcg_temp_new_i64();
2063 TCGv_i64 t3
= tcg_temp_new_i64();
2066 tcg_gen_mul_tl(temp
, arg2
, arg3
);
2067 } else { /* n is expected to be 1 */
2068 tcg_gen_mul_tl(temp
, arg2
, arg3
);
2069 tcg_gen_shli_tl(temp
, temp
, 1);
2070 /* catch special case r1 = r2 = 0x8000 */
2071 tcg_gen_setcondi_tl(TCG_COND_EQ
, temp2
, temp
, 0x80000000);
2072 tcg_gen_sub_tl(temp
, temp
, temp2
);
2074 tcg_gen_ext_i32_i64(t2
, temp
);
2075 tcg_gen_shli_i64(t2
, t2
, 16);
2076 tcg_gen_concat_i32_i64(t1
, arg1_low
, arg1_high
);
2077 gen_sub64_d(t3
, t1
, t2
);
2078 /* write back result */
2079 tcg_gen_extr_i64_i32(rl
, rh
, t3
);
2081 tcg_temp_free_i64(t1
);
2082 tcg_temp_free_i64(t2
);
2083 tcg_temp_free_i64(t3
);
2084 tcg_temp_free(temp
);
2085 tcg_temp_free(temp2
);
2089 gen_m16subs64_q(TCGv rl
, TCGv rh
, TCGv arg1_low
, TCGv arg1_high
, TCGv arg2
,
2090 TCGv arg3
, uint32_t n
)
2092 TCGv temp
= tcg_temp_new();
2093 TCGv temp2
= tcg_temp_new();
2094 TCGv_i64 t1
= tcg_temp_new_i64();
2095 TCGv_i64 t2
= tcg_temp_new_i64();
2098 tcg_gen_mul_tl(temp
, arg2
, arg3
);
2099 } else { /* n is expected to be 1 */
2100 tcg_gen_mul_tl(temp
, arg2
, arg3
);
2101 tcg_gen_shli_tl(temp
, temp
, 1);
2102 /* catch special case r1 = r2 = 0x8000 */
2103 tcg_gen_setcondi_tl(TCG_COND_EQ
, temp2
, temp
, 0x80000000);
2104 tcg_gen_sub_tl(temp
, temp
, temp2
);
2106 tcg_gen_ext_i32_i64(t2
, temp
);
2107 tcg_gen_shli_i64(t2
, t2
, 16);
2108 tcg_gen_concat_i32_i64(t1
, arg1_low
, arg1_high
);
2110 gen_helper_sub64_ssov(t1
, cpu_env
, t1
, t2
);
2111 tcg_gen_extr_i64_i32(rl
, rh
, t1
);
2113 tcg_temp_free(temp
);
2114 tcg_temp_free(temp2
);
2115 tcg_temp_free_i64(t1
);
2116 tcg_temp_free_i64(t2
);
2120 gen_msub64_q(TCGv rl
, TCGv rh
, TCGv arg1_low
, TCGv arg1_high
, TCGv arg2
,
2121 TCGv arg3
, uint32_t n
, CPUTriCoreState
*env
)
2123 TCGv_i64 t1
= tcg_temp_new_i64();
2124 TCGv_i64 t2
= tcg_temp_new_i64();
2125 TCGv_i64 t3
= tcg_temp_new_i64();
2126 TCGv_i64 t4
= tcg_temp_new_i64();
2129 tcg_gen_concat_i32_i64(t1
, arg1_low
, arg1_high
);
2130 tcg_gen_ext_i32_i64(t2
, arg2
);
2131 tcg_gen_ext_i32_i64(t3
, arg3
);
2133 tcg_gen_mul_i64(t2
, t2
, t3
);
2135 tcg_gen_shli_i64(t2
, t2
, 1);
2137 tcg_gen_sub_i64(t4
, t1
, t2
);
2139 tcg_gen_xor_i64(t3
, t4
, t1
);
2140 tcg_gen_xor_i64(t2
, t1
, t2
);
2141 tcg_gen_and_i64(t3
, t3
, t2
);
2142 tcg_gen_extrh_i64_i32(cpu_PSW_V
, t3
);
2143 /* We produce an overflow on the host if the mul before was
2144 (0x80000000 * 0x80000000) << 1). If this is the
2145 case, we negate the ovf. */
2147 temp
= tcg_temp_new();
2148 temp2
= tcg_temp_new();
2149 tcg_gen_setcondi_tl(TCG_COND_EQ
, temp
, arg2
, 0x80000000);
2150 tcg_gen_setcond_tl(TCG_COND_EQ
, temp2
, arg2
, arg3
);
2151 tcg_gen_and_tl(temp
, temp
, temp2
);
2152 tcg_gen_shli_tl(temp
, temp
, 31);
2153 /* negate v bit, if special condition */
2154 tcg_gen_xor_tl(cpu_PSW_V
, cpu_PSW_V
, temp
);
2156 tcg_temp_free(temp
);
2157 tcg_temp_free(temp2
);
2159 /* write back result */
2160 tcg_gen_extr_i64_i32(rl
, rh
, t4
);
2162 tcg_gen_or_tl(cpu_PSW_SV
, cpu_PSW_SV
, cpu_PSW_V
);
2163 /* Calc AV/SAV bits */
2164 tcg_gen_add_tl(cpu_PSW_AV
, rh
, rh
);
2165 tcg_gen_xor_tl(cpu_PSW_AV
, rh
, cpu_PSW_AV
);
2167 tcg_gen_or_tl(cpu_PSW_SAV
, cpu_PSW_SAV
, cpu_PSW_AV
);
2169 tcg_temp_free_i64(t1
);
2170 tcg_temp_free_i64(t2
);
2171 tcg_temp_free_i64(t3
);
2172 tcg_temp_free_i64(t4
);
2176 gen_msubs32_q(TCGv ret
, TCGv arg1
, TCGv arg2
, TCGv arg3
, uint32_t n
,
2179 TCGv_i64 t1
= tcg_temp_new_i64();
2180 TCGv_i64 t2
= tcg_temp_new_i64();
2181 TCGv_i64 t3
= tcg_temp_new_i64();
2182 TCGv_i64 t4
= tcg_temp_new_i64();
2184 tcg_gen_ext_i32_i64(t1
, arg1
);
2185 tcg_gen_ext_i32_i64(t2
, arg2
);
2186 tcg_gen_ext_i32_i64(t3
, arg3
);
2188 tcg_gen_mul_i64(t2
, t2
, t3
);
2189 /* if we shift part of the fraction out, we need to round up */
2190 tcg_gen_andi_i64(t4
, t2
, (1ll << (up_shift
- n
)) - 1);
2191 tcg_gen_setcondi_i64(TCG_COND_NE
, t4
, t4
, 0);
2192 tcg_gen_sari_i64(t3
, t2
, up_shift
- n
);
2193 tcg_gen_add_i64(t3
, t3
, t4
);
2195 gen_helper_msub32_q_sub_ssov(ret
, cpu_env
, t1
, t3
);
2197 tcg_temp_free_i64(t1
);
2198 tcg_temp_free_i64(t2
);
2199 tcg_temp_free_i64(t3
);
2200 tcg_temp_free_i64(t4
);
2204 gen_msubs64_q(TCGv rl
, TCGv rh
, TCGv arg1_low
, TCGv arg1_high
, TCGv arg2
,
2205 TCGv arg3
, uint32_t n
)
2207 TCGv_i64 r1
= tcg_temp_new_i64();
2208 TCGv temp
= tcg_const_i32(n
);
2210 tcg_gen_concat_i32_i64(r1
, arg1_low
, arg1_high
);
2211 gen_helper_msub64_q_ssov(r1
, cpu_env
, r1
, arg2
, arg3
, temp
);
2212 tcg_gen_extr_i64_i32(rl
, rh
, r1
);
2214 tcg_temp_free_i64(r1
);
2215 tcg_temp_free(temp
);
2219 gen_msubad_h(TCGv ret_low
, TCGv ret_high
, TCGv r1_low
, TCGv r1_high
, TCGv r2
,
2220 TCGv r3
, uint32_t n
, uint32_t mode
)
2222 TCGv temp
= tcg_const_i32(n
);
2223 TCGv temp2
= tcg_temp_new();
2224 TCGv_i64 temp64
= tcg_temp_new_i64();
2227 GEN_HELPER_LL(mul_h
, temp64
, r2
, r3
, temp
);
2230 GEN_HELPER_LU(mul_h
, temp64
, r2
, r3
, temp
);
2233 GEN_HELPER_UL(mul_h
, temp64
, r2
, r3
, temp
);
2236 GEN_HELPER_UU(mul_h
, temp64
, r2
, r3
, temp
);
2239 tcg_gen_extr_i64_i32(temp
, temp2
, temp64
);
2240 gen_addsub64_h(ret_low
, ret_high
, r1_low
, r1_high
, temp
, temp2
,
2241 tcg_gen_add_tl
, tcg_gen_sub_tl
);
2242 tcg_temp_free(temp
);
2243 tcg_temp_free(temp2
);
2244 tcg_temp_free_i64(temp64
);
2248 gen_msubadm_h(TCGv ret_low
, TCGv ret_high
, TCGv r1_low
, TCGv r1_high
, TCGv r2
,
2249 TCGv r3
, uint32_t n
, uint32_t mode
)
2251 TCGv temp
= tcg_const_i32(n
);
2252 TCGv_i64 temp64
= tcg_temp_new_i64();
2253 TCGv_i64 temp64_2
= tcg_temp_new_i64();
2254 TCGv_i64 temp64_3
= tcg_temp_new_i64();
2257 GEN_HELPER_LL(mul_h
, temp64
, r2
, r3
, temp
);
2260 GEN_HELPER_LU(mul_h
, temp64
, r2
, r3
, temp
);
2263 GEN_HELPER_UL(mul_h
, temp64
, r2
, r3
, temp
);
2266 GEN_HELPER_UU(mul_h
, temp64
, r2
, r3
, temp
);
2269 tcg_gen_concat_i32_i64(temp64_3
, r1_low
, r1_high
);
2270 tcg_gen_sari_i64(temp64_2
, temp64
, 32); /* high */
2271 tcg_gen_ext32s_i64(temp64
, temp64
); /* low */
2272 tcg_gen_sub_i64(temp64
, temp64_2
, temp64
);
2273 tcg_gen_shli_i64(temp64
, temp64
, 16);
2275 gen_sub64_d(temp64_2
, temp64_3
, temp64
);
2276 /* write back result */
2277 tcg_gen_extr_i64_i32(ret_low
, ret_high
, temp64_2
);
2279 tcg_temp_free(temp
);
2280 tcg_temp_free_i64(temp64
);
2281 tcg_temp_free_i64(temp64_2
);
2282 tcg_temp_free_i64(temp64_3
);
2286 gen_msubadr32_h(TCGv ret
, TCGv r1
, TCGv r2
, TCGv r3
, uint32_t n
, uint32_t mode
)
2288 TCGv temp
= tcg_const_i32(n
);
2289 TCGv temp2
= tcg_temp_new();
2290 TCGv_i64 temp64
= tcg_temp_new_i64();
2293 GEN_HELPER_LL(mul_h
, temp64
, r2
, r3
, temp
);
2296 GEN_HELPER_LU(mul_h
, temp64
, r2
, r3
, temp
);
2299 GEN_HELPER_UL(mul_h
, temp64
, r2
, r3
, temp
);
2302 GEN_HELPER_UU(mul_h
, temp64
, r2
, r3
, temp
);
2305 tcg_gen_andi_tl(temp2
, r1
, 0xffff0000);
2306 tcg_gen_shli_tl(temp
, r1
, 16);
2307 gen_helper_subadr_h(ret
, cpu_env
, temp64
, temp
, temp2
);
2309 tcg_temp_free(temp
);
2310 tcg_temp_free(temp2
);
2311 tcg_temp_free_i64(temp64
);
2315 gen_msubads_h(TCGv ret_low
, TCGv ret_high
, TCGv r1_low
, TCGv r1_high
, TCGv r2
,
2316 TCGv r3
, uint32_t n
, uint32_t mode
)
2318 TCGv temp
= tcg_const_i32(n
);
2319 TCGv temp2
= tcg_temp_new();
2320 TCGv temp3
= tcg_temp_new();
2321 TCGv_i64 temp64
= tcg_temp_new_i64();
2325 GEN_HELPER_LL(mul_h
, temp64
, r2
, r3
, temp
);
2328 GEN_HELPER_LU(mul_h
, temp64
, r2
, r3
, temp
);
2331 GEN_HELPER_UL(mul_h
, temp64
, r2
, r3
, temp
);
2334 GEN_HELPER_UU(mul_h
, temp64
, r2
, r3
, temp
);
2337 tcg_gen_extr_i64_i32(temp
, temp2
, temp64
);
2338 gen_adds(ret_low
, r1_low
, temp
);
2339 tcg_gen_mov_tl(temp
, cpu_PSW_V
);
2340 tcg_gen_mov_tl(temp3
, cpu_PSW_AV
);
2341 gen_subs(ret_high
, r1_high
, temp2
);
2342 /* combine v bits */
2343 tcg_gen_or_tl(cpu_PSW_V
, cpu_PSW_V
, temp
);
2344 /* combine av bits */
2345 tcg_gen_or_tl(cpu_PSW_AV
, cpu_PSW_AV
, temp3
);
2347 tcg_temp_free(temp
);
2348 tcg_temp_free(temp2
);
2349 tcg_temp_free(temp3
);
2350 tcg_temp_free_i64(temp64
);
2354 gen_msubadms_h(TCGv ret_low
, TCGv ret_high
, TCGv r1_low
, TCGv r1_high
, TCGv r2
,
2355 TCGv r3
, uint32_t n
, uint32_t mode
)
2357 TCGv temp
= tcg_const_i32(n
);
2358 TCGv_i64 temp64
= tcg_temp_new_i64();
2359 TCGv_i64 temp64_2
= tcg_temp_new_i64();
2363 GEN_HELPER_LL(mul_h
, temp64
, r2
, r3
, temp
);
2366 GEN_HELPER_LU(mul_h
, temp64
, r2
, r3
, temp
);
2369 GEN_HELPER_UL(mul_h
, temp64
, r2
, r3
, temp
);
2372 GEN_HELPER_UU(mul_h
, temp64
, r2
, r3
, temp
);
2375 tcg_gen_sari_i64(temp64_2
, temp64
, 32); /* high */
2376 tcg_gen_ext32s_i64(temp64
, temp64
); /* low */
2377 tcg_gen_sub_i64(temp64
, temp64_2
, temp64
);
2378 tcg_gen_shli_i64(temp64
, temp64
, 16);
2379 tcg_gen_concat_i32_i64(temp64_2
, r1_low
, r1_high
);
2381 gen_helper_sub64_ssov(temp64
, cpu_env
, temp64_2
, temp64
);
2382 tcg_gen_extr_i64_i32(ret_low
, ret_high
, temp64
);
2384 tcg_temp_free(temp
);
2385 tcg_temp_free_i64(temp64
);
2386 tcg_temp_free_i64(temp64_2
);
2390 gen_msubadr32s_h(TCGv ret
, TCGv r1
, TCGv r2
, TCGv r3
, uint32_t n
, uint32_t mode
)
2392 TCGv temp
= tcg_const_i32(n
);
2393 TCGv temp2
= tcg_temp_new();
2394 TCGv_i64 temp64
= tcg_temp_new_i64();
2397 GEN_HELPER_LL(mul_h
, temp64
, r2
, r3
, temp
);
2400 GEN_HELPER_LU(mul_h
, temp64
, r2
, r3
, temp
);
2403 GEN_HELPER_UL(mul_h
, temp64
, r2
, r3
, temp
);
2406 GEN_HELPER_UU(mul_h
, temp64
, r2
, r3
, temp
);
2409 tcg_gen_andi_tl(temp2
, r1
, 0xffff0000);
2410 tcg_gen_shli_tl(temp
, r1
, 16);
2411 gen_helper_subadr_h_ssov(ret
, cpu_env
, temp64
, temp
, temp2
);
2413 tcg_temp_free(temp
);
2414 tcg_temp_free(temp2
);
2415 tcg_temp_free_i64(temp64
);
2418 static inline void gen_abs(TCGv ret
, TCGv r1
)
2420 TCGv temp
= tcg_temp_new();
2421 TCGv t0
= tcg_const_i32(0);
2423 tcg_gen_neg_tl(temp
, r1
);
2424 tcg_gen_movcond_tl(TCG_COND_GE
, ret
, r1
, t0
, r1
, temp
);
2425 /* overflow can only happen, if r1 = 0x80000000 */
2426 tcg_gen_setcondi_tl(TCG_COND_EQ
, cpu_PSW_V
, r1
, 0x80000000);
2427 tcg_gen_shli_tl(cpu_PSW_V
, cpu_PSW_V
, 31);
2429 tcg_gen_or_tl(cpu_PSW_SV
, cpu_PSW_SV
, cpu_PSW_V
);
2431 tcg_gen_add_tl(cpu_PSW_AV
, ret
, ret
);
2432 tcg_gen_xor_tl(cpu_PSW_AV
, ret
, cpu_PSW_AV
);
2434 tcg_gen_or_tl(cpu_PSW_SAV
, cpu_PSW_SAV
, cpu_PSW_AV
);
2436 tcg_temp_free(temp
);
2440 static inline void gen_absdif(TCGv ret
, TCGv r1
, TCGv r2
)
2442 TCGv temp
= tcg_temp_new_i32();
2443 TCGv result
= tcg_temp_new_i32();
2445 tcg_gen_sub_tl(result
, r1
, r2
);
2446 tcg_gen_sub_tl(temp
, r2
, r1
);
2447 tcg_gen_movcond_tl(TCG_COND_GT
, result
, r1
, r2
, result
, temp
);
2450 tcg_gen_xor_tl(cpu_PSW_V
, result
, r1
);
2451 tcg_gen_xor_tl(temp
, result
, r2
);
2452 tcg_gen_movcond_tl(TCG_COND_GT
, cpu_PSW_V
, r1
, r2
, cpu_PSW_V
, temp
);
2453 tcg_gen_xor_tl(temp
, r1
, r2
);
2454 tcg_gen_and_tl(cpu_PSW_V
, cpu_PSW_V
, temp
);
2456 tcg_gen_or_tl(cpu_PSW_SV
, cpu_PSW_SV
, cpu_PSW_V
);
2458 tcg_gen_add_tl(cpu_PSW_AV
, result
, result
);
2459 tcg_gen_xor_tl(cpu_PSW_AV
, result
, cpu_PSW_AV
);
2461 tcg_gen_or_tl(cpu_PSW_SAV
, cpu_PSW_SAV
, cpu_PSW_AV
);
2462 /* write back result */
2463 tcg_gen_mov_tl(ret
, result
);
2465 tcg_temp_free(temp
);
2466 tcg_temp_free(result
);
2469 static inline void gen_absdifi(TCGv ret
, TCGv r1
, int32_t con
)
2471 TCGv temp
= tcg_const_i32(con
);
2472 gen_absdif(ret
, r1
, temp
);
2473 tcg_temp_free(temp
);
2476 static inline void gen_absdifsi(TCGv ret
, TCGv r1
, int32_t con
)
2478 TCGv temp
= tcg_const_i32(con
);
2479 gen_helper_absdif_ssov(ret
, cpu_env
, r1
, temp
);
2480 tcg_temp_free(temp
);
2483 static inline void gen_mul_i32s(TCGv ret
, TCGv r1
, TCGv r2
)
2485 TCGv high
= tcg_temp_new();
2486 TCGv low
= tcg_temp_new();
2488 tcg_gen_muls2_tl(low
, high
, r1
, r2
);
2489 tcg_gen_mov_tl(ret
, low
);
2491 tcg_gen_sari_tl(low
, low
, 31);
2492 tcg_gen_setcond_tl(TCG_COND_NE
, cpu_PSW_V
, high
, low
);
2493 tcg_gen_shli_tl(cpu_PSW_V
, cpu_PSW_V
, 31);
2495 tcg_gen_or_tl(cpu_PSW_SV
, cpu_PSW_SV
, cpu_PSW_V
);
2497 tcg_gen_add_tl(cpu_PSW_AV
, ret
, ret
);
2498 tcg_gen_xor_tl(cpu_PSW_AV
, ret
, cpu_PSW_AV
);
2500 tcg_gen_or_tl(cpu_PSW_SAV
, cpu_PSW_SAV
, cpu_PSW_AV
);
2502 tcg_temp_free(high
);
2506 static inline void gen_muli_i32s(TCGv ret
, TCGv r1
, int32_t con
)
2508 TCGv temp
= tcg_const_i32(con
);
2509 gen_mul_i32s(ret
, r1
, temp
);
2510 tcg_temp_free(temp
);
2513 static inline void gen_mul_i64s(TCGv ret_low
, TCGv ret_high
, TCGv r1
, TCGv r2
)
2515 tcg_gen_muls2_tl(ret_low
, ret_high
, r1
, r2
);
2517 tcg_gen_movi_tl(cpu_PSW_V
, 0);
2519 tcg_gen_or_tl(cpu_PSW_SV
, cpu_PSW_SV
, cpu_PSW_V
);
2521 tcg_gen_add_tl(cpu_PSW_AV
, ret_high
, ret_high
);
2522 tcg_gen_xor_tl(cpu_PSW_AV
, ret_high
, cpu_PSW_AV
);
2524 tcg_gen_or_tl(cpu_PSW_SAV
, cpu_PSW_SAV
, cpu_PSW_AV
);
2527 static inline void gen_muli_i64s(TCGv ret_low
, TCGv ret_high
, TCGv r1
,
2530 TCGv temp
= tcg_const_i32(con
);
2531 gen_mul_i64s(ret_low
, ret_high
, r1
, temp
);
2532 tcg_temp_free(temp
);
2535 static inline void gen_mul_i64u(TCGv ret_low
, TCGv ret_high
, TCGv r1
, TCGv r2
)
2537 tcg_gen_mulu2_tl(ret_low
, ret_high
, r1
, r2
);
2539 tcg_gen_movi_tl(cpu_PSW_V
, 0);
2541 tcg_gen_or_tl(cpu_PSW_SV
, cpu_PSW_SV
, cpu_PSW_V
);
2543 tcg_gen_add_tl(cpu_PSW_AV
, ret_high
, ret_high
);
2544 tcg_gen_xor_tl(cpu_PSW_AV
, ret_high
, cpu_PSW_AV
);
2546 tcg_gen_or_tl(cpu_PSW_SAV
, cpu_PSW_SAV
, cpu_PSW_AV
);
2549 static inline void gen_muli_i64u(TCGv ret_low
, TCGv ret_high
, TCGv r1
,
2552 TCGv temp
= tcg_const_i32(con
);
2553 gen_mul_i64u(ret_low
, ret_high
, r1
, temp
);
2554 tcg_temp_free(temp
);
2557 static inline void gen_mulsi_i32(TCGv ret
, TCGv r1
, int32_t con
)
2559 TCGv temp
= tcg_const_i32(con
);
2560 gen_helper_mul_ssov(ret
, cpu_env
, r1
, temp
);
2561 tcg_temp_free(temp
);
2564 static inline void gen_mulsui_i32(TCGv ret
, TCGv r1
, int32_t con
)
2566 TCGv temp
= tcg_const_i32(con
);
2567 gen_helper_mul_suov(ret
, cpu_env
, r1
, temp
);
2568 tcg_temp_free(temp
);
2570 /* gen_maddsi_32(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9); */
2571 static inline void gen_maddsi_32(TCGv ret
, TCGv r1
, TCGv r2
, int32_t con
)
2573 TCGv temp
= tcg_const_i32(con
);
2574 gen_helper_madd32_ssov(ret
, cpu_env
, r1
, r2
, temp
);
2575 tcg_temp_free(temp
);
2578 static inline void gen_maddsui_32(TCGv ret
, TCGv r1
, TCGv r2
, int32_t con
)
2580 TCGv temp
= tcg_const_i32(con
);
2581 gen_helper_madd32_suov(ret
, cpu_env
, r1
, r2
, temp
);
2582 tcg_temp_free(temp
);
2586 gen_mul_q(TCGv rl
, TCGv rh
, TCGv arg1
, TCGv arg2
, uint32_t n
, uint32_t up_shift
)
2588 TCGv temp
= tcg_temp_new();
2589 TCGv_i64 temp_64
= tcg_temp_new_i64();
2590 TCGv_i64 temp2_64
= tcg_temp_new_i64();
2593 if (up_shift
== 32) {
2594 tcg_gen_muls2_tl(rh
, rl
, arg1
, arg2
);
2595 } else if (up_shift
== 16) {
2596 tcg_gen_ext_i32_i64(temp_64
, arg1
);
2597 tcg_gen_ext_i32_i64(temp2_64
, arg2
);
2599 tcg_gen_mul_i64(temp_64
, temp_64
, temp2_64
);
2600 tcg_gen_shri_i64(temp_64
, temp_64
, up_shift
);
2601 tcg_gen_extr_i64_i32(rl
, rh
, temp_64
);
2603 tcg_gen_muls2_tl(rl
, rh
, arg1
, arg2
);
2606 tcg_gen_movi_tl(cpu_PSW_V
, 0);
2607 } else { /* n is expected to be 1 */
2608 tcg_gen_ext_i32_i64(temp_64
, arg1
);
2609 tcg_gen_ext_i32_i64(temp2_64
, arg2
);
2611 tcg_gen_mul_i64(temp_64
, temp_64
, temp2_64
);
2613 if (up_shift
== 0) {
2614 tcg_gen_shli_i64(temp_64
, temp_64
, 1);
2616 tcg_gen_shri_i64(temp_64
, temp_64
, up_shift
- 1);
2618 tcg_gen_extr_i64_i32(rl
, rh
, temp_64
);
2619 /* overflow only occurs if r1 = r2 = 0x8000 */
2620 if (up_shift
== 0) {/* result is 64 bit */
2621 tcg_gen_setcondi_tl(TCG_COND_EQ
, cpu_PSW_V
, rh
,
2623 } else { /* result is 32 bit */
2624 tcg_gen_setcondi_tl(TCG_COND_EQ
, cpu_PSW_V
, rl
,
2627 tcg_gen_shli_tl(cpu_PSW_V
, cpu_PSW_V
, 31);
2628 /* calc sv overflow bit */
2629 tcg_gen_or_tl(cpu_PSW_SV
, cpu_PSW_SV
, cpu_PSW_V
);
2631 /* calc av overflow bit */
2632 if (up_shift
== 0) {
2633 tcg_gen_add_tl(cpu_PSW_AV
, rh
, rh
);
2634 tcg_gen_xor_tl(cpu_PSW_AV
, rh
, cpu_PSW_AV
);
2636 tcg_gen_add_tl(cpu_PSW_AV
, rl
, rl
);
2637 tcg_gen_xor_tl(cpu_PSW_AV
, rl
, cpu_PSW_AV
);
2639 /* calc sav overflow bit */
2640 tcg_gen_or_tl(cpu_PSW_SAV
, cpu_PSW_SAV
, cpu_PSW_AV
);
2641 tcg_temp_free(temp
);
2642 tcg_temp_free_i64(temp_64
);
2643 tcg_temp_free_i64(temp2_64
);
2647 gen_mul_q_16(TCGv ret
, TCGv arg1
, TCGv arg2
, uint32_t n
)
2649 TCGv temp
= tcg_temp_new();
2651 tcg_gen_mul_tl(ret
, arg1
, arg2
);
2652 } else { /* n is expected to be 1 */
2653 tcg_gen_mul_tl(ret
, arg1
, arg2
);
2654 tcg_gen_shli_tl(ret
, ret
, 1);
2655 /* catch special case r1 = r2 = 0x8000 */
2656 tcg_gen_setcondi_tl(TCG_COND_EQ
, temp
, ret
, 0x80000000);
2657 tcg_gen_sub_tl(ret
, ret
, temp
);
2660 tcg_gen_movi_tl(cpu_PSW_V
, 0);
2661 /* calc av overflow bit */
2662 tcg_gen_add_tl(cpu_PSW_AV
, ret
, ret
);
2663 tcg_gen_xor_tl(cpu_PSW_AV
, ret
, cpu_PSW_AV
);
2664 /* calc sav overflow bit */
2665 tcg_gen_or_tl(cpu_PSW_SAV
, cpu_PSW_SAV
, cpu_PSW_AV
);
2667 tcg_temp_free(temp
);
2670 static void gen_mulr_q(TCGv ret
, TCGv arg1
, TCGv arg2
, uint32_t n
)
2672 TCGv temp
= tcg_temp_new();
2674 tcg_gen_mul_tl(ret
, arg1
, arg2
);
2675 tcg_gen_addi_tl(ret
, ret
, 0x8000);
2677 tcg_gen_mul_tl(ret
, arg1
, arg2
);
2678 tcg_gen_shli_tl(ret
, ret
, 1);
2679 tcg_gen_addi_tl(ret
, ret
, 0x8000);
2680 /* catch special case r1 = r2 = 0x8000 */
2681 tcg_gen_setcondi_tl(TCG_COND_EQ
, temp
, ret
, 0x80008000);
2682 tcg_gen_muli_tl(temp
, temp
, 0x8001);
2683 tcg_gen_sub_tl(ret
, ret
, temp
);
2686 tcg_gen_movi_tl(cpu_PSW_V
, 0);
2687 /* calc av overflow bit */
2688 tcg_gen_add_tl(cpu_PSW_AV
, ret
, ret
);
2689 tcg_gen_xor_tl(cpu_PSW_AV
, ret
, cpu_PSW_AV
);
2690 /* calc sav overflow bit */
2691 tcg_gen_or_tl(cpu_PSW_SAV
, cpu_PSW_SAV
, cpu_PSW_AV
);
2692 /* cut halfword off */
2693 tcg_gen_andi_tl(ret
, ret
, 0xffff0000);
2695 tcg_temp_free(temp
);
2699 gen_madds_64(TCGv ret_low
, TCGv ret_high
, TCGv r1
, TCGv r2_low
, TCGv r2_high
,
2702 TCGv_i64 temp64
= tcg_temp_new_i64();
2703 tcg_gen_concat_i32_i64(temp64
, r2_low
, r2_high
);
2704 gen_helper_madd64_ssov(temp64
, cpu_env
, r1
, temp64
, r3
);
2705 tcg_gen_extr_i64_i32(ret_low
, ret_high
, temp64
);
2706 tcg_temp_free_i64(temp64
);
2710 gen_maddsi_64(TCGv ret_low
, TCGv ret_high
, TCGv r1
, TCGv r2_low
, TCGv r2_high
,
2713 TCGv temp
= tcg_const_i32(con
);
2714 gen_madds_64(ret_low
, ret_high
, r1
, r2_low
, r2_high
, temp
);
2715 tcg_temp_free(temp
);
2719 gen_maddsu_64(TCGv ret_low
, TCGv ret_high
, TCGv r1
, TCGv r2_low
, TCGv r2_high
,
2722 TCGv_i64 temp64
= tcg_temp_new_i64();
2723 tcg_gen_concat_i32_i64(temp64
, r2_low
, r2_high
);
2724 gen_helper_madd64_suov(temp64
, cpu_env
, r1
, temp64
, r3
);
2725 tcg_gen_extr_i64_i32(ret_low
, ret_high
, temp64
);
2726 tcg_temp_free_i64(temp64
);
2730 gen_maddsui_64(TCGv ret_low
, TCGv ret_high
, TCGv r1
, TCGv r2_low
, TCGv r2_high
,
2733 TCGv temp
= tcg_const_i32(con
);
2734 gen_maddsu_64(ret_low
, ret_high
, r1
, r2_low
, r2_high
, temp
);
2735 tcg_temp_free(temp
);
2738 static inline void gen_msubsi_32(TCGv ret
, TCGv r1
, TCGv r2
, int32_t con
)
2740 TCGv temp
= tcg_const_i32(con
);
2741 gen_helper_msub32_ssov(ret
, cpu_env
, r1
, r2
, temp
);
2742 tcg_temp_free(temp
);
2745 static inline void gen_msubsui_32(TCGv ret
, TCGv r1
, TCGv r2
, int32_t con
)
2747 TCGv temp
= tcg_const_i32(con
);
2748 gen_helper_msub32_suov(ret
, cpu_env
, r1
, r2
, temp
);
2749 tcg_temp_free(temp
);
2753 gen_msubs_64(TCGv ret_low
, TCGv ret_high
, TCGv r1
, TCGv r2_low
, TCGv r2_high
,
2756 TCGv_i64 temp64
= tcg_temp_new_i64();
2757 tcg_gen_concat_i32_i64(temp64
, r2_low
, r2_high
);
2758 gen_helper_msub64_ssov(temp64
, cpu_env
, r1
, temp64
, r3
);
2759 tcg_gen_extr_i64_i32(ret_low
, ret_high
, temp64
);
2760 tcg_temp_free_i64(temp64
);
2764 gen_msubsi_64(TCGv ret_low
, TCGv ret_high
, TCGv r1
, TCGv r2_low
, TCGv r2_high
,
2767 TCGv temp
= tcg_const_i32(con
);
2768 gen_msubs_64(ret_low
, ret_high
, r1
, r2_low
, r2_high
, temp
);
2769 tcg_temp_free(temp
);
2773 gen_msubsu_64(TCGv ret_low
, TCGv ret_high
, TCGv r1
, TCGv r2_low
, TCGv r2_high
,
2776 TCGv_i64 temp64
= tcg_temp_new_i64();
2777 tcg_gen_concat_i32_i64(temp64
, r2_low
, r2_high
);
2778 gen_helper_msub64_suov(temp64
, cpu_env
, r1
, temp64
, r3
);
2779 tcg_gen_extr_i64_i32(ret_low
, ret_high
, temp64
);
2780 tcg_temp_free_i64(temp64
);
2784 gen_msubsui_64(TCGv ret_low
, TCGv ret_high
, TCGv r1
, TCGv r2_low
, TCGv r2_high
,
2787 TCGv temp
= tcg_const_i32(con
);
2788 gen_msubsu_64(ret_low
, ret_high
, r1
, r2_low
, r2_high
, temp
);
2789 tcg_temp_free(temp
);
2792 static void gen_saturate(TCGv ret
, TCGv arg
, int32_t up
, int32_t low
)
2794 TCGv sat_neg
= tcg_const_i32(low
);
2795 TCGv temp
= tcg_const_i32(up
);
2797 /* sat_neg = (arg < low ) ? low : arg; */
2798 tcg_gen_movcond_tl(TCG_COND_LT
, sat_neg
, arg
, sat_neg
, sat_neg
, arg
);
2800 /* ret = (sat_neg > up ) ? up : sat_neg; */
2801 tcg_gen_movcond_tl(TCG_COND_GT
, ret
, sat_neg
, temp
, temp
, sat_neg
);
2803 tcg_temp_free(sat_neg
);
2804 tcg_temp_free(temp
);
2807 static void gen_saturate_u(TCGv ret
, TCGv arg
, int32_t up
)
2809 TCGv temp
= tcg_const_i32(up
);
2810 /* sat_neg = (arg > up ) ? up : arg; */
2811 tcg_gen_movcond_tl(TCG_COND_GTU
, ret
, arg
, temp
, temp
, arg
);
2812 tcg_temp_free(temp
);
2815 static void gen_shi(TCGv ret
, TCGv r1
, int32_t shift_count
)
2817 if (shift_count
== -32) {
2818 tcg_gen_movi_tl(ret
, 0);
2819 } else if (shift_count
>= 0) {
2820 tcg_gen_shli_tl(ret
, r1
, shift_count
);
2822 tcg_gen_shri_tl(ret
, r1
, -shift_count
);
2826 static void gen_sh_hi(TCGv ret
, TCGv r1
, int32_t shiftcount
)
2828 TCGv temp_low
, temp_high
;
2830 if (shiftcount
== -16) {
2831 tcg_gen_movi_tl(ret
, 0);
2833 temp_high
= tcg_temp_new();
2834 temp_low
= tcg_temp_new();
2836 tcg_gen_andi_tl(temp_low
, r1
, 0xffff);
2837 tcg_gen_andi_tl(temp_high
, r1
, 0xffff0000);
2838 gen_shi(temp_low
, temp_low
, shiftcount
);
2839 gen_shi(ret
, temp_high
, shiftcount
);
2840 tcg_gen_deposit_tl(ret
, ret
, temp_low
, 0, 16);
2842 tcg_temp_free(temp_low
);
2843 tcg_temp_free(temp_high
);
2847 static void gen_shaci(TCGv ret
, TCGv r1
, int32_t shift_count
)
2849 uint32_t msk
, msk_start
;
2850 TCGv temp
= tcg_temp_new();
2851 TCGv temp2
= tcg_temp_new();
2852 TCGv t_0
= tcg_const_i32(0);
2854 if (shift_count
== 0) {
2855 /* Clear PSW.C and PSW.V */
2856 tcg_gen_movi_tl(cpu_PSW_C
, 0);
2857 tcg_gen_mov_tl(cpu_PSW_V
, cpu_PSW_C
);
2858 tcg_gen_mov_tl(ret
, r1
);
2859 } else if (shift_count
== -32) {
2861 tcg_gen_mov_tl(cpu_PSW_C
, r1
);
2862 /* fill ret completely with sign bit */
2863 tcg_gen_sari_tl(ret
, r1
, 31);
2865 tcg_gen_movi_tl(cpu_PSW_V
, 0);
2866 } else if (shift_count
> 0) {
2867 TCGv t_max
= tcg_const_i32(0x7FFFFFFF >> shift_count
);
2868 TCGv t_min
= tcg_const_i32(((int32_t) -0x80000000) >> shift_count
);
2871 msk_start
= 32 - shift_count
;
2872 msk
= ((1 << shift_count
) - 1) << msk_start
;
2873 tcg_gen_andi_tl(cpu_PSW_C
, r1
, msk
);
2874 /* calc v/sv bits */
2875 tcg_gen_setcond_tl(TCG_COND_GT
, temp
, r1
, t_max
);
2876 tcg_gen_setcond_tl(TCG_COND_LT
, temp2
, r1
, t_min
);
2877 tcg_gen_or_tl(cpu_PSW_V
, temp
, temp2
);
2878 tcg_gen_shli_tl(cpu_PSW_V
, cpu_PSW_V
, 31);
2880 tcg_gen_or_tl(cpu_PSW_SV
, cpu_PSW_V
, cpu_PSW_SV
);
2882 tcg_gen_shli_tl(ret
, r1
, shift_count
);
2884 tcg_temp_free(t_max
);
2885 tcg_temp_free(t_min
);
2888 tcg_gen_movi_tl(cpu_PSW_V
, 0);
2890 msk
= (1 << -shift_count
) - 1;
2891 tcg_gen_andi_tl(cpu_PSW_C
, r1
, msk
);
2893 tcg_gen_sari_tl(ret
, r1
, -shift_count
);
2895 /* calc av overflow bit */
2896 tcg_gen_add_tl(cpu_PSW_AV
, ret
, ret
);
2897 tcg_gen_xor_tl(cpu_PSW_AV
, ret
, cpu_PSW_AV
);
2898 /* calc sav overflow bit */
2899 tcg_gen_or_tl(cpu_PSW_SAV
, cpu_PSW_SAV
, cpu_PSW_AV
);
2901 tcg_temp_free(temp
);
2902 tcg_temp_free(temp2
);
2906 static void gen_shas(TCGv ret
, TCGv r1
, TCGv r2
)
2908 gen_helper_sha_ssov(ret
, cpu_env
, r1
, r2
);
2911 static void gen_shasi(TCGv ret
, TCGv r1
, int32_t con
)
2913 TCGv temp
= tcg_const_i32(con
);
2914 gen_shas(ret
, r1
, temp
);
2915 tcg_temp_free(temp
);
2918 static void gen_sha_hi(TCGv ret
, TCGv r1
, int32_t shift_count
)
2922 if (shift_count
== 0) {
2923 tcg_gen_mov_tl(ret
, r1
);
2924 } else if (shift_count
> 0) {
2925 low
= tcg_temp_new();
2926 high
= tcg_temp_new();
2928 tcg_gen_andi_tl(high
, r1
, 0xffff0000);
2929 tcg_gen_shli_tl(low
, r1
, shift_count
);
2930 tcg_gen_shli_tl(ret
, high
, shift_count
);
2931 tcg_gen_deposit_tl(ret
, ret
, low
, 0, 16);
2934 tcg_temp_free(high
);
2936 low
= tcg_temp_new();
2937 high
= tcg_temp_new();
2939 tcg_gen_ext16s_tl(low
, r1
);
2940 tcg_gen_sari_tl(low
, low
, -shift_count
);
2941 tcg_gen_sari_tl(ret
, r1
, -shift_count
);
2942 tcg_gen_deposit_tl(ret
, ret
, low
, 0, 16);
2945 tcg_temp_free(high
);
2950 /* ret = {ret[30:0], (r1 cond r2)}; */
2951 static void gen_sh_cond(int cond
, TCGv ret
, TCGv r1
, TCGv r2
)
2953 TCGv temp
= tcg_temp_new();
2954 TCGv temp2
= tcg_temp_new();
2956 tcg_gen_shli_tl(temp
, ret
, 1);
2957 tcg_gen_setcond_tl(cond
, temp2
, r1
, r2
);
2958 tcg_gen_or_tl(ret
, temp
, temp2
);
2960 tcg_temp_free(temp
);
2961 tcg_temp_free(temp2
);
2964 static void gen_sh_condi(int cond
, TCGv ret
, TCGv r1
, int32_t con
)
2966 TCGv temp
= tcg_const_i32(con
);
2967 gen_sh_cond(cond
, ret
, r1
, temp
);
2968 tcg_temp_free(temp
);
2971 static inline void gen_adds(TCGv ret
, TCGv r1
, TCGv r2
)
2973 gen_helper_add_ssov(ret
, cpu_env
, r1
, r2
);
2976 static inline void gen_addsi(TCGv ret
, TCGv r1
, int32_t con
)
2978 TCGv temp
= tcg_const_i32(con
);
2979 gen_helper_add_ssov(ret
, cpu_env
, r1
, temp
);
2980 tcg_temp_free(temp
);
2983 static inline void gen_addsui(TCGv ret
, TCGv r1
, int32_t con
)
2985 TCGv temp
= tcg_const_i32(con
);
2986 gen_helper_add_suov(ret
, cpu_env
, r1
, temp
);
2987 tcg_temp_free(temp
);
2990 static inline void gen_subs(TCGv ret
, TCGv r1
, TCGv r2
)
2992 gen_helper_sub_ssov(ret
, cpu_env
, r1
, r2
);
2995 static inline void gen_subsu(TCGv ret
, TCGv r1
, TCGv r2
)
2997 gen_helper_sub_suov(ret
, cpu_env
, r1
, r2
);
3000 static inline void gen_bit_2op(TCGv ret
, TCGv r1
, TCGv r2
,
3002 void(*op1
)(TCGv
, TCGv
, TCGv
),
3003 void(*op2
)(TCGv
, TCGv
, TCGv
))
3007 temp1
= tcg_temp_new();
3008 temp2
= tcg_temp_new();
3010 tcg_gen_shri_tl(temp2
, r2
, pos2
);
3011 tcg_gen_shri_tl(temp1
, r1
, pos1
);
3013 (*op1
)(temp1
, temp1
, temp2
);
3014 (*op2
)(temp1
, ret
, temp1
);
3016 tcg_gen_deposit_tl(ret
, ret
, temp1
, 0, 1);
3018 tcg_temp_free(temp1
);
3019 tcg_temp_free(temp2
);
3022 /* ret = r1[pos1] op1 r2[pos2]; */
3023 static inline void gen_bit_1op(TCGv ret
, TCGv r1
, TCGv r2
,
3025 void(*op1
)(TCGv
, TCGv
, TCGv
))
3029 temp1
= tcg_temp_new();
3030 temp2
= tcg_temp_new();
3032 tcg_gen_shri_tl(temp2
, r2
, pos2
);
3033 tcg_gen_shri_tl(temp1
, r1
, pos1
);
3035 (*op1
)(ret
, temp1
, temp2
);
3037 tcg_gen_andi_tl(ret
, ret
, 0x1);
3039 tcg_temp_free(temp1
);
3040 tcg_temp_free(temp2
);
3043 static inline void gen_accumulating_cond(int cond
, TCGv ret
, TCGv r1
, TCGv r2
,
3044 void(*op
)(TCGv
, TCGv
, TCGv
))
3046 TCGv temp
= tcg_temp_new();
3047 TCGv temp2
= tcg_temp_new();
3048 /* temp = (arg1 cond arg2 )*/
3049 tcg_gen_setcond_tl(cond
, temp
, r1
, r2
);
3051 tcg_gen_andi_tl(temp2
, ret
, 0x1);
3052 /* temp = temp insn temp2 */
3053 (*op
)(temp
, temp
, temp2
);
3054 /* ret = {ret[31:1], temp} */
3055 tcg_gen_deposit_tl(ret
, ret
, temp
, 0, 1);
3057 tcg_temp_free(temp
);
3058 tcg_temp_free(temp2
);
3062 gen_accumulating_condi(int cond
, TCGv ret
, TCGv r1
, int32_t con
,
3063 void(*op
)(TCGv
, TCGv
, TCGv
))
3065 TCGv temp
= tcg_const_i32(con
);
3066 gen_accumulating_cond(cond
, ret
, r1
, temp
, op
);
3067 tcg_temp_free(temp
);
3070 /* ret = (r1 cond r2) ? 0xFFFFFFFF ? 0x00000000;*/
3071 static inline void gen_cond_w(TCGCond cond
, TCGv ret
, TCGv r1
, TCGv r2
)
3073 tcg_gen_setcond_tl(cond
, ret
, r1
, r2
);
3074 tcg_gen_neg_tl(ret
, ret
);
3077 static inline void gen_eqany_bi(TCGv ret
, TCGv r1
, int32_t con
)
3079 TCGv b0
= tcg_temp_new();
3080 TCGv b1
= tcg_temp_new();
3081 TCGv b2
= tcg_temp_new();
3082 TCGv b3
= tcg_temp_new();
3085 tcg_gen_andi_tl(b0
, r1
, 0xff);
3086 tcg_gen_setcondi_tl(TCG_COND_EQ
, b0
, b0
, con
& 0xff);
3089 tcg_gen_andi_tl(b1
, r1
, 0xff00);
3090 tcg_gen_setcondi_tl(TCG_COND_EQ
, b1
, b1
, con
& 0xff00);
3093 tcg_gen_andi_tl(b2
, r1
, 0xff0000);
3094 tcg_gen_setcondi_tl(TCG_COND_EQ
, b2
, b2
, con
& 0xff0000);
3097 tcg_gen_andi_tl(b3
, r1
, 0xff000000);
3098 tcg_gen_setcondi_tl(TCG_COND_EQ
, b3
, b3
, con
& 0xff000000);
3101 tcg_gen_or_tl(ret
, b0
, b1
);
3102 tcg_gen_or_tl(ret
, ret
, b2
);
3103 tcg_gen_or_tl(ret
, ret
, b3
);
3111 static inline void gen_eqany_hi(TCGv ret
, TCGv r1
, int32_t con
)
3113 TCGv h0
= tcg_temp_new();
3114 TCGv h1
= tcg_temp_new();
3117 tcg_gen_andi_tl(h0
, r1
, 0xffff);
3118 tcg_gen_setcondi_tl(TCG_COND_EQ
, h0
, h0
, con
& 0xffff);
3121 tcg_gen_andi_tl(h1
, r1
, 0xffff0000);
3122 tcg_gen_setcondi_tl(TCG_COND_EQ
, h1
, h1
, con
& 0xffff0000);
3125 tcg_gen_or_tl(ret
, h0
, h1
);
3130 /* mask = ((1 << width) -1) << pos;
3131 ret = (r1 & ~mask) | (r2 << pos) & mask); */
3132 static inline void gen_insert(TCGv ret
, TCGv r1
, TCGv r2
, TCGv width
, TCGv pos
)
3134 TCGv mask
= tcg_temp_new();
3135 TCGv temp
= tcg_temp_new();
3136 TCGv temp2
= tcg_temp_new();
3138 tcg_gen_movi_tl(mask
, 1);
3139 tcg_gen_shl_tl(mask
, mask
, width
);
3140 tcg_gen_subi_tl(mask
, mask
, 1);
3141 tcg_gen_shl_tl(mask
, mask
, pos
);
3143 tcg_gen_shl_tl(temp
, r2
, pos
);
3144 tcg_gen_and_tl(temp
, temp
, mask
);
3145 tcg_gen_andc_tl(temp2
, r1
, mask
);
3146 tcg_gen_or_tl(ret
, temp
, temp2
);
3148 tcg_temp_free(mask
);
3149 tcg_temp_free(temp
);
3150 tcg_temp_free(temp2
);
3153 static inline void gen_bsplit(TCGv rl
, TCGv rh
, TCGv r1
)
3155 TCGv_i64 temp
= tcg_temp_new_i64();
3157 gen_helper_bsplit(temp
, r1
);
3158 tcg_gen_extr_i64_i32(rl
, rh
, temp
);
3160 tcg_temp_free_i64(temp
);
3163 static inline void gen_unpack(TCGv rl
, TCGv rh
, TCGv r1
)
3165 TCGv_i64 temp
= tcg_temp_new_i64();
3167 gen_helper_unpack(temp
, r1
);
3168 tcg_gen_extr_i64_i32(rl
, rh
, temp
);
3170 tcg_temp_free_i64(temp
);
3174 gen_dvinit_b(CPUTriCoreState
*env
, TCGv rl
, TCGv rh
, TCGv r1
, TCGv r2
)
3176 TCGv_i64 ret
= tcg_temp_new_i64();
3178 if (!tricore_feature(env
, TRICORE_FEATURE_131
)) {
3179 gen_helper_dvinit_b_13(ret
, cpu_env
, r1
, r2
);
3181 gen_helper_dvinit_b_131(ret
, cpu_env
, r1
, r2
);
3183 tcg_gen_extr_i64_i32(rl
, rh
, ret
);
3185 tcg_temp_free_i64(ret
);
3189 gen_dvinit_h(CPUTriCoreState
*env
, TCGv rl
, TCGv rh
, TCGv r1
, TCGv r2
)
3191 TCGv_i64 ret
= tcg_temp_new_i64();
3193 if (!tricore_feature(env
, TRICORE_FEATURE_131
)) {
3194 gen_helper_dvinit_h_13(ret
, cpu_env
, r1
, r2
);
3196 gen_helper_dvinit_h_131(ret
, cpu_env
, r1
, r2
);
3198 tcg_gen_extr_i64_i32(rl
, rh
, ret
);
3200 tcg_temp_free_i64(ret
);
3203 static void gen_calc_usb_mul_h(TCGv arg_low
, TCGv arg_high
)
3205 TCGv temp
= tcg_temp_new();
3207 tcg_gen_add_tl(temp
, arg_low
, arg_low
);
3208 tcg_gen_xor_tl(temp
, temp
, arg_low
);
3209 tcg_gen_add_tl(cpu_PSW_AV
, arg_high
, arg_high
);
3210 tcg_gen_xor_tl(cpu_PSW_AV
, cpu_PSW_AV
, arg_high
);
3211 tcg_gen_or_tl(cpu_PSW_AV
, cpu_PSW_AV
, temp
);
3213 tcg_gen_or_tl(cpu_PSW_SAV
, cpu_PSW_SAV
, cpu_PSW_AV
);
3214 tcg_gen_movi_tl(cpu_PSW_V
, 0);
3215 tcg_temp_free(temp
);
3218 static void gen_calc_usb_mulr_h(TCGv arg
)
3220 TCGv temp
= tcg_temp_new();
3222 tcg_gen_add_tl(temp
, arg
, arg
);
3223 tcg_gen_xor_tl(temp
, temp
, arg
);
3224 tcg_gen_shli_tl(cpu_PSW_AV
, temp
, 16);
3225 tcg_gen_or_tl(cpu_PSW_AV
, cpu_PSW_AV
, temp
);
3227 tcg_gen_or_tl(cpu_PSW_SAV
, cpu_PSW_SAV
, cpu_PSW_AV
);
3229 tcg_gen_movi_tl(cpu_PSW_V
, 0);
3230 tcg_temp_free(temp
);
3233 /* helpers for generating program flow micro-ops */
3235 static inline void gen_save_pc(target_ulong pc
)
3237 tcg_gen_movi_tl(cpu_PC
, pc
);
3240 static inline bool use_goto_tb(DisasContext
*ctx
, target_ulong dest
)
3242 if (unlikely(ctx
->singlestep_enabled
)) {
3246 #ifndef CONFIG_USER_ONLY
3247 return (ctx
->tb
->pc
& TARGET_PAGE_MASK
) == (dest
& TARGET_PAGE_MASK
);
3253 static inline void gen_goto_tb(DisasContext
*ctx
, int n
, target_ulong dest
)
3255 if (use_goto_tb(ctx
, dest
)) {
3258 tcg_gen_exit_tb((uintptr_t)ctx
->tb
+ n
);
3261 if (ctx
->singlestep_enabled
) {
3262 /* raise exception debug */
3268 static void generate_trap(DisasContext
*ctx
, int class, int tin
)
3270 TCGv_i32 classtemp
= tcg_const_i32(class);
3271 TCGv_i32 tintemp
= tcg_const_i32(tin
);
3273 gen_save_pc(ctx
->pc
);
3274 gen_helper_raise_exception_sync(cpu_env
, classtemp
, tintemp
);
3275 ctx
->bstate
= BS_EXCP
;
3277 tcg_temp_free(classtemp
);
3278 tcg_temp_free(tintemp
);
3281 static inline void gen_branch_cond(DisasContext
*ctx
, TCGCond cond
, TCGv r1
,
3282 TCGv r2
, int16_t address
)
3284 TCGLabel
*jumpLabel
= gen_new_label();
3285 tcg_gen_brcond_tl(cond
, r1
, r2
, jumpLabel
);
3287 gen_goto_tb(ctx
, 1, ctx
->next_pc
);
3289 gen_set_label(jumpLabel
);
3290 gen_goto_tb(ctx
, 0, ctx
->pc
+ address
* 2);
3293 static inline void gen_branch_condi(DisasContext
*ctx
, TCGCond cond
, TCGv r1
,
3294 int r2
, int16_t address
)
3296 TCGv temp
= tcg_const_i32(r2
);
3297 gen_branch_cond(ctx
, cond
, r1
, temp
, address
);
3298 tcg_temp_free(temp
);
3301 static void gen_loop(DisasContext
*ctx
, int r1
, int32_t offset
)
3303 TCGLabel
*l1
= gen_new_label();
3305 tcg_gen_subi_tl(cpu_gpr_a
[r1
], cpu_gpr_a
[r1
], 1);
3306 tcg_gen_brcondi_tl(TCG_COND_EQ
, cpu_gpr_a
[r1
], -1, l1
);
3307 gen_goto_tb(ctx
, 1, ctx
->pc
+ offset
);
3309 gen_goto_tb(ctx
, 0, ctx
->next_pc
);
3312 static void gen_fcall_save_ctx(DisasContext
*ctx
)
3314 TCGv temp
= tcg_temp_new();
3316 tcg_gen_addi_tl(temp
, cpu_gpr_a
[10], -4);
3317 tcg_gen_qemu_st_tl(cpu_gpr_a
[11], temp
, ctx
->mem_idx
, MO_LESL
);
3318 tcg_gen_movi_tl(cpu_gpr_a
[11], ctx
->next_pc
);
3319 tcg_gen_mov_tl(cpu_gpr_a
[10], temp
);
3321 tcg_temp_free(temp
);
3324 static void gen_fret(DisasContext
*ctx
)
3326 TCGv temp
= tcg_temp_new();
3328 tcg_gen_andi_tl(temp
, cpu_gpr_a
[11], ~0x1);
3329 tcg_gen_qemu_ld_tl(cpu_gpr_a
[11], cpu_gpr_a
[10], ctx
->mem_idx
, MO_LESL
);
3330 tcg_gen_addi_tl(cpu_gpr_a
[10], cpu_gpr_a
[10], 4);
3331 tcg_gen_mov_tl(cpu_PC
, temp
);
3333 ctx
->bstate
= BS_BRANCH
;
3335 tcg_temp_free(temp
);
3338 static void gen_compute_branch(DisasContext
*ctx
, uint32_t opc
, int r1
,
3339 int r2
, int32_t constant
, int32_t offset
)
3345 /* SB-format jumps */
3348 gen_goto_tb(ctx
, 0, ctx
->pc
+ offset
* 2);
3350 case OPC1_32_B_CALL
:
3351 case OPC1_16_SB_CALL
:
3352 gen_helper_1arg(call
, ctx
->next_pc
);
3353 gen_goto_tb(ctx
, 0, ctx
->pc
+ offset
* 2);
3356 gen_branch_condi(ctx
, TCG_COND_EQ
, cpu_gpr_d
[15], 0, offset
);
3358 case OPC1_16_SB_JNZ
:
3359 gen_branch_condi(ctx
, TCG_COND_NE
, cpu_gpr_d
[15], 0, offset
);
3361 /* SBC-format jumps */
3362 case OPC1_16_SBC_JEQ
:
3363 gen_branch_condi(ctx
, TCG_COND_EQ
, cpu_gpr_d
[15], constant
, offset
);
3365 case OPC1_16_SBC_JEQ2
:
3366 gen_branch_condi(ctx
, TCG_COND_EQ
, cpu_gpr_d
[15], constant
,
3369 case OPC1_16_SBC_JNE
:
3370 gen_branch_condi(ctx
, TCG_COND_NE
, cpu_gpr_d
[15], constant
, offset
);
3372 case OPC1_16_SBC_JNE2
:
3373 gen_branch_condi(ctx
, TCG_COND_NE
, cpu_gpr_d
[15],
3374 constant
, offset
+ 16);
3376 /* SBRN-format jumps */
3377 case OPC1_16_SBRN_JZ_T
:
3378 temp
= tcg_temp_new();
3379 tcg_gen_andi_tl(temp
, cpu_gpr_d
[15], 0x1u
<< constant
);
3380 gen_branch_condi(ctx
, TCG_COND_EQ
, temp
, 0, offset
);
3381 tcg_temp_free(temp
);
3383 case OPC1_16_SBRN_JNZ_T
:
3384 temp
= tcg_temp_new();
3385 tcg_gen_andi_tl(temp
, cpu_gpr_d
[15], 0x1u
<< constant
);
3386 gen_branch_condi(ctx
, TCG_COND_NE
, temp
, 0, offset
);
3387 tcg_temp_free(temp
);
3389 /* SBR-format jumps */
3390 case OPC1_16_SBR_JEQ
:
3391 gen_branch_cond(ctx
, TCG_COND_EQ
, cpu_gpr_d
[r1
], cpu_gpr_d
[15],
3394 case OPC1_16_SBR_JNE
:
3395 gen_branch_cond(ctx
, TCG_COND_NE
, cpu_gpr_d
[r1
], cpu_gpr_d
[15],
3398 case OPC1_16_SBR_JNZ
:
3399 gen_branch_condi(ctx
, TCG_COND_NE
, cpu_gpr_d
[r1
], 0, offset
);
3401 case OPC1_16_SBR_JNZ_A
:
3402 gen_branch_condi(ctx
, TCG_COND_NE
, cpu_gpr_a
[r1
], 0, offset
);
3404 case OPC1_16_SBR_JGEZ
:
3405 gen_branch_condi(ctx
, TCG_COND_GE
, cpu_gpr_d
[r1
], 0, offset
);
3407 case OPC1_16_SBR_JGTZ
:
3408 gen_branch_condi(ctx
, TCG_COND_GT
, cpu_gpr_d
[r1
], 0, offset
);
3410 case OPC1_16_SBR_JLEZ
:
3411 gen_branch_condi(ctx
, TCG_COND_LE
, cpu_gpr_d
[r1
], 0, offset
);
3413 case OPC1_16_SBR_JLTZ
:
3414 gen_branch_condi(ctx
, TCG_COND_LT
, cpu_gpr_d
[r1
], 0, offset
);
3416 case OPC1_16_SBR_JZ
:
3417 gen_branch_condi(ctx
, TCG_COND_EQ
, cpu_gpr_d
[r1
], 0, offset
);
3419 case OPC1_16_SBR_JZ_A
:
3420 gen_branch_condi(ctx
, TCG_COND_EQ
, cpu_gpr_a
[r1
], 0, offset
);
3422 case OPC1_16_SBR_LOOP
:
3423 gen_loop(ctx
, r1
, offset
* 2 - 32);
3425 /* SR-format jumps */
3427 tcg_gen_andi_tl(cpu_PC
, cpu_gpr_a
[r1
], 0xfffffffe);
3430 case OPC2_32_SYS_RET
:
3431 case OPC2_16_SR_RET
:
3432 gen_helper_ret(cpu_env
);
3436 case OPC1_32_B_CALLA
:
3437 gen_helper_1arg(call
, ctx
->next_pc
);
3438 gen_goto_tb(ctx
, 0, EA_B_ABSOLUT(offset
));
3440 case OPC1_32_B_FCALL
:
3441 gen_fcall_save_ctx(ctx
);
3442 gen_goto_tb(ctx
, 0, ctx
->pc
+ offset
* 2);
3444 case OPC1_32_B_FCALLA
:
3445 gen_fcall_save_ctx(ctx
);
3446 gen_goto_tb(ctx
, 0, EA_B_ABSOLUT(offset
));
3449 tcg_gen_movi_tl(cpu_gpr_a
[11], ctx
->next_pc
);
3452 gen_goto_tb(ctx
, 0, EA_B_ABSOLUT(offset
));
3455 tcg_gen_movi_tl(cpu_gpr_a
[11], ctx
->next_pc
);
3456 gen_goto_tb(ctx
, 0, ctx
->pc
+ offset
* 2);
3459 case OPCM_32_BRC_EQ_NEQ
:
3460 if (MASK_OP_BRC_OP2(ctx
->opcode
) == OPC2_32_BRC_JEQ
) {
3461 gen_branch_condi(ctx
, TCG_COND_EQ
, cpu_gpr_d
[r1
], constant
, offset
);
3463 gen_branch_condi(ctx
, TCG_COND_NE
, cpu_gpr_d
[r1
], constant
, offset
);
3466 case OPCM_32_BRC_GE
:
3467 if (MASK_OP_BRC_OP2(ctx
->opcode
) == OP2_32_BRC_JGE
) {
3468 gen_branch_condi(ctx
, TCG_COND_GE
, cpu_gpr_d
[r1
], constant
, offset
);
3470 constant
= MASK_OP_BRC_CONST4(ctx
->opcode
);
3471 gen_branch_condi(ctx
, TCG_COND_GEU
, cpu_gpr_d
[r1
], constant
,
3475 case OPCM_32_BRC_JLT
:
3476 if (MASK_OP_BRC_OP2(ctx
->opcode
) == OPC2_32_BRC_JLT
) {
3477 gen_branch_condi(ctx
, TCG_COND_LT
, cpu_gpr_d
[r1
], constant
, offset
);
3479 constant
= MASK_OP_BRC_CONST4(ctx
->opcode
);
3480 gen_branch_condi(ctx
, TCG_COND_LTU
, cpu_gpr_d
[r1
], constant
,
3484 case OPCM_32_BRC_JNE
:
3485 temp
= tcg_temp_new();
3486 if (MASK_OP_BRC_OP2(ctx
->opcode
) == OPC2_32_BRC_JNED
) {
3487 tcg_gen_mov_tl(temp
, cpu_gpr_d
[r1
]);
3488 /* subi is unconditional */
3489 tcg_gen_subi_tl(cpu_gpr_d
[r1
], cpu_gpr_d
[r1
], 1);
3490 gen_branch_condi(ctx
, TCG_COND_NE
, temp
, constant
, offset
);
3492 tcg_gen_mov_tl(temp
, cpu_gpr_d
[r1
]);
3493 /* addi is unconditional */
3494 tcg_gen_addi_tl(cpu_gpr_d
[r1
], cpu_gpr_d
[r1
], 1);
3495 gen_branch_condi(ctx
, TCG_COND_NE
, temp
, constant
, offset
);
3497 tcg_temp_free(temp
);
3500 case OPCM_32_BRN_JTT
:
3501 n
= MASK_OP_BRN_N(ctx
->opcode
);
3503 temp
= tcg_temp_new();
3504 tcg_gen_andi_tl(temp
, cpu_gpr_d
[r1
], (1 << n
));
3506 if (MASK_OP_BRN_OP2(ctx
->opcode
) == OPC2_32_BRN_JNZ_T
) {
3507 gen_branch_condi(ctx
, TCG_COND_NE
, temp
, 0, offset
);
3509 gen_branch_condi(ctx
, TCG_COND_EQ
, temp
, 0, offset
);
3511 tcg_temp_free(temp
);
3514 case OPCM_32_BRR_EQ_NEQ
:
3515 if (MASK_OP_BRR_OP2(ctx
->opcode
) == OPC2_32_BRR_JEQ
) {
3516 gen_branch_cond(ctx
, TCG_COND_EQ
, cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
3519 gen_branch_cond(ctx
, TCG_COND_NE
, cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
3523 case OPCM_32_BRR_ADDR_EQ_NEQ
:
3524 if (MASK_OP_BRR_OP2(ctx
->opcode
) == OPC2_32_BRR_JEQ_A
) {
3525 gen_branch_cond(ctx
, TCG_COND_EQ
, cpu_gpr_a
[r1
], cpu_gpr_a
[r2
],
3528 gen_branch_cond(ctx
, TCG_COND_NE
, cpu_gpr_a
[r1
], cpu_gpr_a
[r2
],
3532 case OPCM_32_BRR_GE
:
3533 if (MASK_OP_BRR_OP2(ctx
->opcode
) == OPC2_32_BRR_JGE
) {
3534 gen_branch_cond(ctx
, TCG_COND_GE
, cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
3537 gen_branch_cond(ctx
, TCG_COND_GEU
, cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
3541 case OPCM_32_BRR_JLT
:
3542 if (MASK_OP_BRR_OP2(ctx
->opcode
) == OPC2_32_BRR_JLT
) {
3543 gen_branch_cond(ctx
, TCG_COND_LT
, cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
3546 gen_branch_cond(ctx
, TCG_COND_LTU
, cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
3550 case OPCM_32_BRR_LOOP
:
3551 if (MASK_OP_BRR_OP2(ctx
->opcode
) == OPC2_32_BRR_LOOP
) {
3552 gen_loop(ctx
, r2
, offset
* 2);
3554 /* OPC2_32_BRR_LOOPU */
3555 gen_goto_tb(ctx
, 0, ctx
->pc
+ offset
* 2);
3558 case OPCM_32_BRR_JNE
:
3559 temp
= tcg_temp_new();
3560 temp2
= tcg_temp_new();
3561 if (MASK_OP_BRC_OP2(ctx
->opcode
) == OPC2_32_BRR_JNED
) {
3562 tcg_gen_mov_tl(temp
, cpu_gpr_d
[r1
]);
3563 /* also save r2, in case of r1 == r2, so r2 is not decremented */
3564 tcg_gen_mov_tl(temp2
, cpu_gpr_d
[r2
]);
3565 /* subi is unconditional */
3566 tcg_gen_subi_tl(cpu_gpr_d
[r1
], cpu_gpr_d
[r1
], 1);
3567 gen_branch_cond(ctx
, TCG_COND_NE
, temp
, temp2
, offset
);
3569 tcg_gen_mov_tl(temp
, cpu_gpr_d
[r1
]);
3570 /* also save r2, in case of r1 == r2, so r2 is not decremented */
3571 tcg_gen_mov_tl(temp2
, cpu_gpr_d
[r2
]);
3572 /* addi is unconditional */
3573 tcg_gen_addi_tl(cpu_gpr_d
[r1
], cpu_gpr_d
[r1
], 1);
3574 gen_branch_cond(ctx
, TCG_COND_NE
, temp
, temp2
, offset
);
3576 tcg_temp_free(temp
);
3577 tcg_temp_free(temp2
);
3579 case OPCM_32_BRR_JNZ
:
3580 if (MASK_OP_BRR_OP2(ctx
->opcode
) == OPC2_32_BRR_JNZ_A
) {
3581 gen_branch_condi(ctx
, TCG_COND_NE
, cpu_gpr_a
[r1
], 0, offset
);
3583 gen_branch_condi(ctx
, TCG_COND_EQ
, cpu_gpr_a
[r1
], 0, offset
);
3587 generate_trap(ctx
, TRAPC_INSN_ERR
, TIN2_IOPC
);
3589 ctx
->bstate
= BS_BRANCH
;
3594 * Functions for decoding instructions
3597 static void decode_src_opc(CPUTriCoreState
*env
, DisasContext
*ctx
, int op1
)
3603 r1
= MASK_OP_SRC_S1D(ctx
->opcode
);
3604 const4
= MASK_OP_SRC_CONST4_SEXT(ctx
->opcode
);
3607 case OPC1_16_SRC_ADD
:
3608 gen_addi_d(cpu_gpr_d
[r1
], cpu_gpr_d
[r1
], const4
);
3610 case OPC1_16_SRC_ADD_A15
:
3611 gen_addi_d(cpu_gpr_d
[r1
], cpu_gpr_d
[15], const4
);
3613 case OPC1_16_SRC_ADD_15A
:
3614 gen_addi_d(cpu_gpr_d
[15], cpu_gpr_d
[r1
], const4
);
3616 case OPC1_16_SRC_ADD_A
:
3617 tcg_gen_addi_tl(cpu_gpr_a
[r1
], cpu_gpr_a
[r1
], const4
);
3619 case OPC1_16_SRC_CADD
:
3620 gen_condi_add(TCG_COND_NE
, cpu_gpr_d
[r1
], const4
, cpu_gpr_d
[r1
],
3623 case OPC1_16_SRC_CADDN
:
3624 gen_condi_add(TCG_COND_EQ
, cpu_gpr_d
[r1
], const4
, cpu_gpr_d
[r1
],
3627 case OPC1_16_SRC_CMOV
:
3628 temp
= tcg_const_tl(0);
3629 temp2
= tcg_const_tl(const4
);
3630 tcg_gen_movcond_tl(TCG_COND_NE
, cpu_gpr_d
[r1
], cpu_gpr_d
[15], temp
,
3631 temp2
, cpu_gpr_d
[r1
]);
3632 tcg_temp_free(temp
);
3633 tcg_temp_free(temp2
);
3635 case OPC1_16_SRC_CMOVN
:
3636 temp
= tcg_const_tl(0);
3637 temp2
= tcg_const_tl(const4
);
3638 tcg_gen_movcond_tl(TCG_COND_EQ
, cpu_gpr_d
[r1
], cpu_gpr_d
[15], temp
,
3639 temp2
, cpu_gpr_d
[r1
]);
3640 tcg_temp_free(temp
);
3641 tcg_temp_free(temp2
);
3643 case OPC1_16_SRC_EQ
:
3644 tcg_gen_setcondi_tl(TCG_COND_EQ
, cpu_gpr_d
[15], cpu_gpr_d
[r1
],
3647 case OPC1_16_SRC_LT
:
3648 tcg_gen_setcondi_tl(TCG_COND_LT
, cpu_gpr_d
[15], cpu_gpr_d
[r1
],
3651 case OPC1_16_SRC_MOV
:
3652 tcg_gen_movi_tl(cpu_gpr_d
[r1
], const4
);
3654 case OPC1_16_SRC_MOV_A
:
3655 const4
= MASK_OP_SRC_CONST4(ctx
->opcode
);
3656 tcg_gen_movi_tl(cpu_gpr_a
[r1
], const4
);
3658 case OPC1_16_SRC_MOV_E
:
3659 if (tricore_feature(env
, TRICORE_FEATURE_16
)) {
3660 tcg_gen_movi_tl(cpu_gpr_d
[r1
], const4
);
3661 tcg_gen_sari_tl(cpu_gpr_d
[r1
+1], cpu_gpr_d
[r1
], 31);
3663 generate_trap(ctx
, TRAPC_INSN_ERR
, TIN2_IOPC
);
3666 case OPC1_16_SRC_SH
:
3667 gen_shi(cpu_gpr_d
[r1
], cpu_gpr_d
[r1
], const4
);
3669 case OPC1_16_SRC_SHA
:
3670 gen_shaci(cpu_gpr_d
[r1
], cpu_gpr_d
[r1
], const4
);
3673 generate_trap(ctx
, TRAPC_INSN_ERR
, TIN2_IOPC
);
3677 static void decode_srr_opc(DisasContext
*ctx
, int op1
)
3682 r1
= MASK_OP_SRR_S1D(ctx
->opcode
);
3683 r2
= MASK_OP_SRR_S2(ctx
->opcode
);
3686 case OPC1_16_SRR_ADD
:
3687 gen_add_d(cpu_gpr_d
[r1
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
3689 case OPC1_16_SRR_ADD_A15
:
3690 gen_add_d(cpu_gpr_d
[r1
], cpu_gpr_d
[15], cpu_gpr_d
[r2
]);
3692 case OPC1_16_SRR_ADD_15A
:
3693 gen_add_d(cpu_gpr_d
[15], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
3695 case OPC1_16_SRR_ADD_A
:
3696 tcg_gen_add_tl(cpu_gpr_a
[r1
], cpu_gpr_a
[r1
], cpu_gpr_a
[r2
]);
3698 case OPC1_16_SRR_ADDS
:
3699 gen_adds(cpu_gpr_d
[r1
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
3701 case OPC1_16_SRR_AND
:
3702 tcg_gen_and_tl(cpu_gpr_d
[r1
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
3704 case OPC1_16_SRR_CMOV
:
3705 temp
= tcg_const_tl(0);
3706 tcg_gen_movcond_tl(TCG_COND_NE
, cpu_gpr_d
[r1
], cpu_gpr_d
[15], temp
,
3707 cpu_gpr_d
[r2
], cpu_gpr_d
[r1
]);
3708 tcg_temp_free(temp
);
3710 case OPC1_16_SRR_CMOVN
:
3711 temp
= tcg_const_tl(0);
3712 tcg_gen_movcond_tl(TCG_COND_EQ
, cpu_gpr_d
[r1
], cpu_gpr_d
[15], temp
,
3713 cpu_gpr_d
[r2
], cpu_gpr_d
[r1
]);
3714 tcg_temp_free(temp
);
3716 case OPC1_16_SRR_EQ
:
3717 tcg_gen_setcond_tl(TCG_COND_EQ
, cpu_gpr_d
[15], cpu_gpr_d
[r1
],
3720 case OPC1_16_SRR_LT
:
3721 tcg_gen_setcond_tl(TCG_COND_LT
, cpu_gpr_d
[15], cpu_gpr_d
[r1
],
3724 case OPC1_16_SRR_MOV
:
3725 tcg_gen_mov_tl(cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
3727 case OPC1_16_SRR_MOV_A
:
3728 tcg_gen_mov_tl(cpu_gpr_a
[r1
], cpu_gpr_d
[r2
]);
3730 case OPC1_16_SRR_MOV_AA
:
3731 tcg_gen_mov_tl(cpu_gpr_a
[r1
], cpu_gpr_a
[r2
]);
3733 case OPC1_16_SRR_MOV_D
:
3734 tcg_gen_mov_tl(cpu_gpr_d
[r1
], cpu_gpr_a
[r2
]);
3736 case OPC1_16_SRR_MUL
:
3737 gen_mul_i32s(cpu_gpr_d
[r1
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
3739 case OPC1_16_SRR_OR
:
3740 tcg_gen_or_tl(cpu_gpr_d
[r1
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
3742 case OPC1_16_SRR_SUB
:
3743 gen_sub_d(cpu_gpr_d
[r1
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
3745 case OPC1_16_SRR_SUB_A15B
:
3746 gen_sub_d(cpu_gpr_d
[r1
], cpu_gpr_d
[15], cpu_gpr_d
[r2
]);
3748 case OPC1_16_SRR_SUB_15AB
:
3749 gen_sub_d(cpu_gpr_d
[15], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
3751 case OPC1_16_SRR_SUBS
:
3752 gen_subs(cpu_gpr_d
[r1
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
3754 case OPC1_16_SRR_XOR
:
3755 tcg_gen_xor_tl(cpu_gpr_d
[r1
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
3758 generate_trap(ctx
, TRAPC_INSN_ERR
, TIN2_IOPC
);
3762 static void decode_ssr_opc(DisasContext
*ctx
, int op1
)
3766 r1
= MASK_OP_SSR_S1(ctx
->opcode
);
3767 r2
= MASK_OP_SSR_S2(ctx
->opcode
);
3770 case OPC1_16_SSR_ST_A
:
3771 tcg_gen_qemu_st_tl(cpu_gpr_a
[r1
], cpu_gpr_a
[r2
], ctx
->mem_idx
, MO_LEUL
);
3773 case OPC1_16_SSR_ST_A_POSTINC
:
3774 tcg_gen_qemu_st_tl(cpu_gpr_a
[r1
], cpu_gpr_a
[r2
], ctx
->mem_idx
, MO_LEUL
);
3775 tcg_gen_addi_tl(cpu_gpr_a
[r2
], cpu_gpr_a
[r2
], 4);
3777 case OPC1_16_SSR_ST_B
:
3778 tcg_gen_qemu_st_tl(cpu_gpr_d
[r1
], cpu_gpr_a
[r2
], ctx
->mem_idx
, MO_UB
);
3780 case OPC1_16_SSR_ST_B_POSTINC
:
3781 tcg_gen_qemu_st_tl(cpu_gpr_d
[r1
], cpu_gpr_a
[r2
], ctx
->mem_idx
, MO_UB
);
3782 tcg_gen_addi_tl(cpu_gpr_a
[r2
], cpu_gpr_a
[r2
], 1);
3784 case OPC1_16_SSR_ST_H
:
3785 tcg_gen_qemu_st_tl(cpu_gpr_d
[r1
], cpu_gpr_a
[r2
], ctx
->mem_idx
, MO_LEUW
);
3787 case OPC1_16_SSR_ST_H_POSTINC
:
3788 tcg_gen_qemu_st_tl(cpu_gpr_d
[r1
], cpu_gpr_a
[r2
], ctx
->mem_idx
, MO_LEUW
);
3789 tcg_gen_addi_tl(cpu_gpr_a
[r2
], cpu_gpr_a
[r2
], 2);
3791 case OPC1_16_SSR_ST_W
:
3792 tcg_gen_qemu_st_tl(cpu_gpr_d
[r1
], cpu_gpr_a
[r2
], ctx
->mem_idx
, MO_LEUL
);
3794 case OPC1_16_SSR_ST_W_POSTINC
:
3795 tcg_gen_qemu_st_tl(cpu_gpr_d
[r1
], cpu_gpr_a
[r2
], ctx
->mem_idx
, MO_LEUL
);
3796 tcg_gen_addi_tl(cpu_gpr_a
[r2
], cpu_gpr_a
[r2
], 4);
3799 generate_trap(ctx
, TRAPC_INSN_ERR
, TIN2_IOPC
);
3803 static void decode_sc_opc(DisasContext
*ctx
, int op1
)
3807 const16
= MASK_OP_SC_CONST8(ctx
->opcode
);
3810 case OPC1_16_SC_AND
:
3811 tcg_gen_andi_tl(cpu_gpr_d
[15], cpu_gpr_d
[15], const16
);
3813 case OPC1_16_SC_BISR
:
3814 gen_helper_1arg(bisr
, const16
& 0xff);
3816 case OPC1_16_SC_LD_A
:
3817 gen_offset_ld(ctx
, cpu_gpr_a
[15], cpu_gpr_a
[10], const16
* 4, MO_LESL
);
3819 case OPC1_16_SC_LD_W
:
3820 gen_offset_ld(ctx
, cpu_gpr_d
[15], cpu_gpr_a
[10], const16
* 4, MO_LESL
);
3822 case OPC1_16_SC_MOV
:
3823 tcg_gen_movi_tl(cpu_gpr_d
[15], const16
);
3826 tcg_gen_ori_tl(cpu_gpr_d
[15], cpu_gpr_d
[15], const16
);
3828 case OPC1_16_SC_ST_A
:
3829 gen_offset_st(ctx
, cpu_gpr_a
[15], cpu_gpr_a
[10], const16
* 4, MO_LESL
);
3831 case OPC1_16_SC_ST_W
:
3832 gen_offset_st(ctx
, cpu_gpr_d
[15], cpu_gpr_a
[10], const16
* 4, MO_LESL
);
3834 case OPC1_16_SC_SUB_A
:
3835 tcg_gen_subi_tl(cpu_gpr_a
[10], cpu_gpr_a
[10], const16
);
3838 generate_trap(ctx
, TRAPC_INSN_ERR
, TIN2_IOPC
);
3842 static void decode_slr_opc(DisasContext
*ctx
, int op1
)
3846 r1
= MASK_OP_SLR_D(ctx
->opcode
);
3847 r2
= MASK_OP_SLR_S2(ctx
->opcode
);
3851 case OPC1_16_SLR_LD_A
:
3852 tcg_gen_qemu_ld_tl(cpu_gpr_a
[r1
], cpu_gpr_a
[r2
], ctx
->mem_idx
, MO_LESL
);
3854 case OPC1_16_SLR_LD_A_POSTINC
:
3855 tcg_gen_qemu_ld_tl(cpu_gpr_a
[r1
], cpu_gpr_a
[r2
], ctx
->mem_idx
, MO_LESL
);
3856 tcg_gen_addi_tl(cpu_gpr_a
[r2
], cpu_gpr_a
[r2
], 4);
3858 case OPC1_16_SLR_LD_BU
:
3859 tcg_gen_qemu_ld_tl(cpu_gpr_d
[r1
], cpu_gpr_a
[r2
], ctx
->mem_idx
, MO_UB
);
3861 case OPC1_16_SLR_LD_BU_POSTINC
:
3862 tcg_gen_qemu_ld_tl(cpu_gpr_d
[r1
], cpu_gpr_a
[r2
], ctx
->mem_idx
, MO_UB
);
3863 tcg_gen_addi_tl(cpu_gpr_a
[r2
], cpu_gpr_a
[r2
], 1);
3865 case OPC1_16_SLR_LD_H
:
3866 tcg_gen_qemu_ld_tl(cpu_gpr_d
[r1
], cpu_gpr_a
[r2
], ctx
->mem_idx
, MO_LESW
);
3868 case OPC1_16_SLR_LD_H_POSTINC
:
3869 tcg_gen_qemu_ld_tl(cpu_gpr_d
[r1
], cpu_gpr_a
[r2
], ctx
->mem_idx
, MO_LESW
);
3870 tcg_gen_addi_tl(cpu_gpr_a
[r2
], cpu_gpr_a
[r2
], 2);
3872 case OPC1_16_SLR_LD_W
:
3873 tcg_gen_qemu_ld_tl(cpu_gpr_d
[r1
], cpu_gpr_a
[r2
], ctx
->mem_idx
, MO_LESL
);
3875 case OPC1_16_SLR_LD_W_POSTINC
:
3876 tcg_gen_qemu_ld_tl(cpu_gpr_d
[r1
], cpu_gpr_a
[r2
], ctx
->mem_idx
, MO_LESL
);
3877 tcg_gen_addi_tl(cpu_gpr_a
[r2
], cpu_gpr_a
[r2
], 4);
3880 generate_trap(ctx
, TRAPC_INSN_ERR
, TIN2_IOPC
);
3884 static void decode_sro_opc(DisasContext
*ctx
, int op1
)
3889 r2
= MASK_OP_SRO_S2(ctx
->opcode
);
3890 address
= MASK_OP_SRO_OFF4(ctx
->opcode
);
3894 case OPC1_16_SRO_LD_A
:
3895 gen_offset_ld(ctx
, cpu_gpr_a
[15], cpu_gpr_a
[r2
], address
* 4, MO_LESL
);
3897 case OPC1_16_SRO_LD_BU
:
3898 gen_offset_ld(ctx
, cpu_gpr_d
[15], cpu_gpr_a
[r2
], address
, MO_UB
);
3900 case OPC1_16_SRO_LD_H
:
3901 gen_offset_ld(ctx
, cpu_gpr_d
[15], cpu_gpr_a
[r2
], address
, MO_LESW
);
3903 case OPC1_16_SRO_LD_W
:
3904 gen_offset_ld(ctx
, cpu_gpr_d
[15], cpu_gpr_a
[r2
], address
* 4, MO_LESL
);
3906 case OPC1_16_SRO_ST_A
:
3907 gen_offset_st(ctx
, cpu_gpr_a
[15], cpu_gpr_a
[r2
], address
* 4, MO_LESL
);
3909 case OPC1_16_SRO_ST_B
:
3910 gen_offset_st(ctx
, cpu_gpr_d
[15], cpu_gpr_a
[r2
], address
, MO_UB
);
3912 case OPC1_16_SRO_ST_H
:
3913 gen_offset_st(ctx
, cpu_gpr_d
[15], cpu_gpr_a
[r2
], address
* 2, MO_LESW
);
3915 case OPC1_16_SRO_ST_W
:
3916 gen_offset_st(ctx
, cpu_gpr_d
[15], cpu_gpr_a
[r2
], address
* 4, MO_LESL
);
3919 generate_trap(ctx
, TRAPC_INSN_ERR
, TIN2_IOPC
);
3923 static void decode_sr_system(CPUTriCoreState
*env
, DisasContext
*ctx
)
3926 op2
= MASK_OP_SR_OP2(ctx
->opcode
);
3929 case OPC2_16_SR_NOP
:
3931 case OPC2_16_SR_RET
:
3932 gen_compute_branch(ctx
, op2
, 0, 0, 0, 0);
3934 case OPC2_16_SR_RFE
:
3935 gen_helper_rfe(cpu_env
);
3937 ctx
->bstate
= BS_BRANCH
;
3939 case OPC2_16_SR_DEBUG
:
3940 /* raise EXCP_DEBUG */
3942 case OPC2_16_SR_FRET
:
3946 generate_trap(ctx
, TRAPC_INSN_ERR
, TIN2_IOPC
);
3950 static void decode_sr_accu(CPUTriCoreState
*env
, DisasContext
*ctx
)
3956 r1
= MASK_OP_SR_S1D(ctx
->opcode
);
3957 op2
= MASK_OP_SR_OP2(ctx
->opcode
);
3960 case OPC2_16_SR_RSUB
:
3961 /* overflow only if r1 = -0x80000000 */
3962 temp
= tcg_const_i32(-0x80000000);
3964 tcg_gen_setcond_tl(TCG_COND_EQ
, cpu_PSW_V
, cpu_gpr_d
[r1
], temp
);
3965 tcg_gen_shli_tl(cpu_PSW_V
, cpu_PSW_V
, 31);
3967 tcg_gen_or_tl(cpu_PSW_SV
, cpu_PSW_SV
, cpu_PSW_V
);
3969 tcg_gen_neg_tl(cpu_gpr_d
[r1
], cpu_gpr_d
[r1
]);
3971 tcg_gen_add_tl(cpu_PSW_AV
, cpu_gpr_d
[r1
], cpu_gpr_d
[r1
]);
3972 tcg_gen_xor_tl(cpu_PSW_AV
, cpu_gpr_d
[r1
], cpu_PSW_AV
);
3974 tcg_gen_or_tl(cpu_PSW_SAV
, cpu_PSW_SAV
, cpu_PSW_AV
);
3975 tcg_temp_free(temp
);
3977 case OPC2_16_SR_SAT_B
:
3978 gen_saturate(cpu_gpr_d
[r1
], cpu_gpr_d
[r1
], 0x7f, -0x80);
3980 case OPC2_16_SR_SAT_BU
:
3981 gen_saturate_u(cpu_gpr_d
[r1
], cpu_gpr_d
[r1
], 0xff);
3983 case OPC2_16_SR_SAT_H
:
3984 gen_saturate(cpu_gpr_d
[r1
], cpu_gpr_d
[r1
], 0x7fff, -0x8000);
3986 case OPC2_16_SR_SAT_HU
:
3987 gen_saturate_u(cpu_gpr_d
[r1
], cpu_gpr_d
[r1
], 0xffff);
3990 generate_trap(ctx
, TRAPC_INSN_ERR
, TIN2_IOPC
);
3994 static void decode_16Bit_opc(CPUTriCoreState
*env
, DisasContext
*ctx
)
4002 op1
= MASK_OP_MAJOR(ctx
->opcode
);
4004 /* handle ADDSC.A opcode only being 6 bit long */
4005 if (unlikely((op1
& 0x3f) == OPC1_16_SRRS_ADDSC_A
)) {
4006 op1
= OPC1_16_SRRS_ADDSC_A
;
4010 case OPC1_16_SRC_ADD
:
4011 case OPC1_16_SRC_ADD_A15
:
4012 case OPC1_16_SRC_ADD_15A
:
4013 case OPC1_16_SRC_ADD_A
:
4014 case OPC1_16_SRC_CADD
:
4015 case OPC1_16_SRC_CADDN
:
4016 case OPC1_16_SRC_CMOV
:
4017 case OPC1_16_SRC_CMOVN
:
4018 case OPC1_16_SRC_EQ
:
4019 case OPC1_16_SRC_LT
:
4020 case OPC1_16_SRC_MOV
:
4021 case OPC1_16_SRC_MOV_A
:
4022 case OPC1_16_SRC_MOV_E
:
4023 case OPC1_16_SRC_SH
:
4024 case OPC1_16_SRC_SHA
:
4025 decode_src_opc(env
, ctx
, op1
);
4028 case OPC1_16_SRR_ADD
:
4029 case OPC1_16_SRR_ADD_A15
:
4030 case OPC1_16_SRR_ADD_15A
:
4031 case OPC1_16_SRR_ADD_A
:
4032 case OPC1_16_SRR_ADDS
:
4033 case OPC1_16_SRR_AND
:
4034 case OPC1_16_SRR_CMOV
:
4035 case OPC1_16_SRR_CMOVN
:
4036 case OPC1_16_SRR_EQ
:
4037 case OPC1_16_SRR_LT
:
4038 case OPC1_16_SRR_MOV
:
4039 case OPC1_16_SRR_MOV_A
:
4040 case OPC1_16_SRR_MOV_AA
:
4041 case OPC1_16_SRR_MOV_D
:
4042 case OPC1_16_SRR_MUL
:
4043 case OPC1_16_SRR_OR
:
4044 case OPC1_16_SRR_SUB
:
4045 case OPC1_16_SRR_SUB_A15B
:
4046 case OPC1_16_SRR_SUB_15AB
:
4047 case OPC1_16_SRR_SUBS
:
4048 case OPC1_16_SRR_XOR
:
4049 decode_srr_opc(ctx
, op1
);
4052 case OPC1_16_SSR_ST_A
:
4053 case OPC1_16_SSR_ST_A_POSTINC
:
4054 case OPC1_16_SSR_ST_B
:
4055 case OPC1_16_SSR_ST_B_POSTINC
:
4056 case OPC1_16_SSR_ST_H
:
4057 case OPC1_16_SSR_ST_H_POSTINC
:
4058 case OPC1_16_SSR_ST_W
:
4059 case OPC1_16_SSR_ST_W_POSTINC
:
4060 decode_ssr_opc(ctx
, op1
);
4063 case OPC1_16_SRRS_ADDSC_A
:
4064 r2
= MASK_OP_SRRS_S2(ctx
->opcode
);
4065 r1
= MASK_OP_SRRS_S1D(ctx
->opcode
);
4066 const16
= MASK_OP_SRRS_N(ctx
->opcode
);
4067 temp
= tcg_temp_new();
4068 tcg_gen_shli_tl(temp
, cpu_gpr_d
[15], const16
);
4069 tcg_gen_add_tl(cpu_gpr_a
[r1
], cpu_gpr_a
[r2
], temp
);
4070 tcg_temp_free(temp
);
4073 case OPC1_16_SLRO_LD_A
:
4074 r1
= MASK_OP_SLRO_D(ctx
->opcode
);
4075 const16
= MASK_OP_SLRO_OFF4(ctx
->opcode
);
4076 gen_offset_ld(ctx
, cpu_gpr_a
[r1
], cpu_gpr_a
[15], const16
* 4, MO_LESL
);
4078 case OPC1_16_SLRO_LD_BU
:
4079 r1
= MASK_OP_SLRO_D(ctx
->opcode
);
4080 const16
= MASK_OP_SLRO_OFF4(ctx
->opcode
);
4081 gen_offset_ld(ctx
, cpu_gpr_d
[r1
], cpu_gpr_a
[15], const16
, MO_UB
);
4083 case OPC1_16_SLRO_LD_H
:
4084 r1
= MASK_OP_SLRO_D(ctx
->opcode
);
4085 const16
= MASK_OP_SLRO_OFF4(ctx
->opcode
);
4086 gen_offset_ld(ctx
, cpu_gpr_d
[r1
], cpu_gpr_a
[15], const16
* 2, MO_LESW
);
4088 case OPC1_16_SLRO_LD_W
:
4089 r1
= MASK_OP_SLRO_D(ctx
->opcode
);
4090 const16
= MASK_OP_SLRO_OFF4(ctx
->opcode
);
4091 gen_offset_ld(ctx
, cpu_gpr_d
[r1
], cpu_gpr_a
[15], const16
* 4, MO_LESL
);
4094 case OPC1_16_SB_CALL
:
4096 case OPC1_16_SB_JNZ
:
4098 address
= MASK_OP_SB_DISP8_SEXT(ctx
->opcode
);
4099 gen_compute_branch(ctx
, op1
, 0, 0, 0, address
);
4102 case OPC1_16_SBC_JEQ
:
4103 case OPC1_16_SBC_JNE
:
4104 address
= MASK_OP_SBC_DISP4(ctx
->opcode
);
4105 const16
= MASK_OP_SBC_CONST4_SEXT(ctx
->opcode
);
4106 gen_compute_branch(ctx
, op1
, 0, 0, const16
, address
);
4108 case OPC1_16_SBC_JEQ2
:
4109 case OPC1_16_SBC_JNE2
:
4110 if (tricore_feature(env
, TRICORE_FEATURE_16
)) {
4111 address
= MASK_OP_SBC_DISP4(ctx
->opcode
);
4112 const16
= MASK_OP_SBC_CONST4_SEXT(ctx
->opcode
);
4113 gen_compute_branch(ctx
, op1
, 0, 0, const16
, address
);
4115 generate_trap(ctx
, TRAPC_INSN_ERR
, TIN2_IOPC
);
4119 case OPC1_16_SBRN_JNZ_T
:
4120 case OPC1_16_SBRN_JZ_T
:
4121 address
= MASK_OP_SBRN_DISP4(ctx
->opcode
);
4122 const16
= MASK_OP_SBRN_N(ctx
->opcode
);
4123 gen_compute_branch(ctx
, op1
, 0, 0, const16
, address
);
4126 case OPC1_16_SBR_JEQ
:
4127 case OPC1_16_SBR_JGEZ
:
4128 case OPC1_16_SBR_JGTZ
:
4129 case OPC1_16_SBR_JLEZ
:
4130 case OPC1_16_SBR_JLTZ
:
4131 case OPC1_16_SBR_JNE
:
4132 case OPC1_16_SBR_JNZ
:
4133 case OPC1_16_SBR_JNZ_A
:
4134 case OPC1_16_SBR_JZ
:
4135 case OPC1_16_SBR_JZ_A
:
4136 case OPC1_16_SBR_LOOP
:
4137 r1
= MASK_OP_SBR_S2(ctx
->opcode
);
4138 address
= MASK_OP_SBR_DISP4(ctx
->opcode
);
4139 gen_compute_branch(ctx
, op1
, r1
, 0, 0, address
);
4142 case OPC1_16_SC_AND
:
4143 case OPC1_16_SC_BISR
:
4144 case OPC1_16_SC_LD_A
:
4145 case OPC1_16_SC_LD_W
:
4146 case OPC1_16_SC_MOV
:
4148 case OPC1_16_SC_ST_A
:
4149 case OPC1_16_SC_ST_W
:
4150 case OPC1_16_SC_SUB_A
:
4151 decode_sc_opc(ctx
, op1
);
4154 case OPC1_16_SLR_LD_A
:
4155 case OPC1_16_SLR_LD_A_POSTINC
:
4156 case OPC1_16_SLR_LD_BU
:
4157 case OPC1_16_SLR_LD_BU_POSTINC
:
4158 case OPC1_16_SLR_LD_H
:
4159 case OPC1_16_SLR_LD_H_POSTINC
:
4160 case OPC1_16_SLR_LD_W
:
4161 case OPC1_16_SLR_LD_W_POSTINC
:
4162 decode_slr_opc(ctx
, op1
);
4165 case OPC1_16_SRO_LD_A
:
4166 case OPC1_16_SRO_LD_BU
:
4167 case OPC1_16_SRO_LD_H
:
4168 case OPC1_16_SRO_LD_W
:
4169 case OPC1_16_SRO_ST_A
:
4170 case OPC1_16_SRO_ST_B
:
4171 case OPC1_16_SRO_ST_H
:
4172 case OPC1_16_SRO_ST_W
:
4173 decode_sro_opc(ctx
, op1
);
4176 case OPC1_16_SSRO_ST_A
:
4177 r1
= MASK_OP_SSRO_S1(ctx
->opcode
);
4178 const16
= MASK_OP_SSRO_OFF4(ctx
->opcode
);
4179 gen_offset_st(ctx
, cpu_gpr_a
[r1
], cpu_gpr_a
[15], const16
* 4, MO_LESL
);
4181 case OPC1_16_SSRO_ST_B
:
4182 r1
= MASK_OP_SSRO_S1(ctx
->opcode
);
4183 const16
= MASK_OP_SSRO_OFF4(ctx
->opcode
);
4184 gen_offset_st(ctx
, cpu_gpr_d
[r1
], cpu_gpr_a
[15], const16
, MO_UB
);
4186 case OPC1_16_SSRO_ST_H
:
4187 r1
= MASK_OP_SSRO_S1(ctx
->opcode
);
4188 const16
= MASK_OP_SSRO_OFF4(ctx
->opcode
);
4189 gen_offset_st(ctx
, cpu_gpr_d
[r1
], cpu_gpr_a
[15], const16
* 2, MO_LESW
);
4191 case OPC1_16_SSRO_ST_W
:
4192 r1
= MASK_OP_SSRO_S1(ctx
->opcode
);
4193 const16
= MASK_OP_SSRO_OFF4(ctx
->opcode
);
4194 gen_offset_st(ctx
, cpu_gpr_d
[r1
], cpu_gpr_a
[15], const16
* 4, MO_LESL
);
4197 case OPCM_16_SR_SYSTEM
:
4198 decode_sr_system(env
, ctx
);
4200 case OPCM_16_SR_ACCU
:
4201 decode_sr_accu(env
, ctx
);
4204 r1
= MASK_OP_SR_S1D(ctx
->opcode
);
4205 gen_compute_branch(ctx
, op1
, r1
, 0, 0, 0);
4207 case OPC1_16_SR_NOT
:
4208 r1
= MASK_OP_SR_S1D(ctx
->opcode
);
4209 tcg_gen_not_tl(cpu_gpr_d
[r1
], cpu_gpr_d
[r1
]);
4212 generate_trap(ctx
, TRAPC_INSN_ERR
, TIN2_IOPC
);
4217 * 32 bit instructions
4221 static void decode_abs_ldw(CPUTriCoreState
*env
, DisasContext
*ctx
)
4228 r1
= MASK_OP_ABS_S1D(ctx
->opcode
);
4229 address
= MASK_OP_ABS_OFF18(ctx
->opcode
);
4230 op2
= MASK_OP_ABS_OP2(ctx
->opcode
);
4232 temp
= tcg_const_i32(EA_ABS_FORMAT(address
));
4235 case OPC2_32_ABS_LD_A
:
4236 tcg_gen_qemu_ld_tl(cpu_gpr_a
[r1
], temp
, ctx
->mem_idx
, MO_LESL
);
4238 case OPC2_32_ABS_LD_D
:
4240 gen_ld_2regs_64(cpu_gpr_d
[r1
+1], cpu_gpr_d
[r1
], temp
, ctx
);
4242 case OPC2_32_ABS_LD_DA
:
4244 gen_ld_2regs_64(cpu_gpr_a
[r1
+1], cpu_gpr_a
[r1
], temp
, ctx
);
4246 case OPC2_32_ABS_LD_W
:
4247 tcg_gen_qemu_ld_tl(cpu_gpr_d
[r1
], temp
, ctx
->mem_idx
, MO_LESL
);
4250 generate_trap(ctx
, TRAPC_INSN_ERR
, TIN2_IOPC
);
4253 tcg_temp_free(temp
);
4256 static void decode_abs_ldb(CPUTriCoreState
*env
, DisasContext
*ctx
)
4263 r1
= MASK_OP_ABS_S1D(ctx
->opcode
);
4264 address
= MASK_OP_ABS_OFF18(ctx
->opcode
);
4265 op2
= MASK_OP_ABS_OP2(ctx
->opcode
);
4267 temp
= tcg_const_i32(EA_ABS_FORMAT(address
));
4270 case OPC2_32_ABS_LD_B
:
4271 tcg_gen_qemu_ld_tl(cpu_gpr_d
[r1
], temp
, ctx
->mem_idx
, MO_SB
);
4273 case OPC2_32_ABS_LD_BU
:
4274 tcg_gen_qemu_ld_tl(cpu_gpr_d
[r1
], temp
, ctx
->mem_idx
, MO_UB
);
4276 case OPC2_32_ABS_LD_H
:
4277 tcg_gen_qemu_ld_tl(cpu_gpr_d
[r1
], temp
, ctx
->mem_idx
, MO_LESW
);
4279 case OPC2_32_ABS_LD_HU
:
4280 tcg_gen_qemu_ld_tl(cpu_gpr_d
[r1
], temp
, ctx
->mem_idx
, MO_LEUW
);
4283 generate_trap(ctx
, TRAPC_INSN_ERR
, TIN2_IOPC
);
4286 tcg_temp_free(temp
);
4289 static void decode_abs_ldst_swap(CPUTriCoreState
*env
, DisasContext
*ctx
)
4296 r1
= MASK_OP_ABS_S1D(ctx
->opcode
);
4297 address
= MASK_OP_ABS_OFF18(ctx
->opcode
);
4298 op2
= MASK_OP_ABS_OP2(ctx
->opcode
);
4300 temp
= tcg_const_i32(EA_ABS_FORMAT(address
));
4303 case OPC2_32_ABS_LDMST
:
4304 gen_ldmst(ctx
, r1
, temp
);
4306 case OPC2_32_ABS_SWAP_W
:
4307 gen_swap(ctx
, r1
, temp
);
4310 generate_trap(ctx
, TRAPC_INSN_ERR
, TIN2_IOPC
);
4313 tcg_temp_free(temp
);
4316 static void decode_abs_ldst_context(CPUTriCoreState
*env
, DisasContext
*ctx
)
4321 off18
= MASK_OP_ABS_OFF18(ctx
->opcode
);
4322 op2
= MASK_OP_ABS_OP2(ctx
->opcode
);
4325 case OPC2_32_ABS_LDLCX
:
4326 gen_helper_1arg(ldlcx
, EA_ABS_FORMAT(off18
));
4328 case OPC2_32_ABS_LDUCX
:
4329 gen_helper_1arg(lducx
, EA_ABS_FORMAT(off18
));
4331 case OPC2_32_ABS_STLCX
:
4332 gen_helper_1arg(stlcx
, EA_ABS_FORMAT(off18
));
4334 case OPC2_32_ABS_STUCX
:
4335 gen_helper_1arg(stucx
, EA_ABS_FORMAT(off18
));
4338 generate_trap(ctx
, TRAPC_INSN_ERR
, TIN2_IOPC
);
4342 static void decode_abs_store(CPUTriCoreState
*env
, DisasContext
*ctx
)
4349 r1
= MASK_OP_ABS_S1D(ctx
->opcode
);
4350 address
= MASK_OP_ABS_OFF18(ctx
->opcode
);
4351 op2
= MASK_OP_ABS_OP2(ctx
->opcode
);
4353 temp
= tcg_const_i32(EA_ABS_FORMAT(address
));
4356 case OPC2_32_ABS_ST_A
:
4357 tcg_gen_qemu_st_tl(cpu_gpr_a
[r1
], temp
, ctx
->mem_idx
, MO_LESL
);
4359 case OPC2_32_ABS_ST_D
:
4361 gen_st_2regs_64(cpu_gpr_d
[r1
+1], cpu_gpr_d
[r1
], temp
, ctx
);
4363 case OPC2_32_ABS_ST_DA
:
4365 gen_st_2regs_64(cpu_gpr_a
[r1
+1], cpu_gpr_a
[r1
], temp
, ctx
);
4367 case OPC2_32_ABS_ST_W
:
4368 tcg_gen_qemu_st_tl(cpu_gpr_d
[r1
], temp
, ctx
->mem_idx
, MO_LESL
);
4371 generate_trap(ctx
, TRAPC_INSN_ERR
, TIN2_IOPC
);
4373 tcg_temp_free(temp
);
4376 static void decode_abs_storeb_h(CPUTriCoreState
*env
, DisasContext
*ctx
)
4383 r1
= MASK_OP_ABS_S1D(ctx
->opcode
);
4384 address
= MASK_OP_ABS_OFF18(ctx
->opcode
);
4385 op2
= MASK_OP_ABS_OP2(ctx
->opcode
);
4387 temp
= tcg_const_i32(EA_ABS_FORMAT(address
));
4390 case OPC2_32_ABS_ST_B
:
4391 tcg_gen_qemu_st_tl(cpu_gpr_d
[r1
], temp
, ctx
->mem_idx
, MO_UB
);
4393 case OPC2_32_ABS_ST_H
:
4394 tcg_gen_qemu_st_tl(cpu_gpr_d
[r1
], temp
, ctx
->mem_idx
, MO_LEUW
);
4397 generate_trap(ctx
, TRAPC_INSN_ERR
, TIN2_IOPC
);
4399 tcg_temp_free(temp
);
4404 static void decode_bit_andacc(CPUTriCoreState
*env
, DisasContext
*ctx
)
4410 r1
= MASK_OP_BIT_S1(ctx
->opcode
);
4411 r2
= MASK_OP_BIT_S2(ctx
->opcode
);
4412 r3
= MASK_OP_BIT_D(ctx
->opcode
);
4413 pos1
= MASK_OP_BIT_POS1(ctx
->opcode
);
4414 pos2
= MASK_OP_BIT_POS2(ctx
->opcode
);
4415 op2
= MASK_OP_BIT_OP2(ctx
->opcode
);
4419 case OPC2_32_BIT_AND_AND_T
:
4420 gen_bit_2op(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
4421 pos1
, pos2
, &tcg_gen_and_tl
, &tcg_gen_and_tl
);
4423 case OPC2_32_BIT_AND_ANDN_T
:
4424 gen_bit_2op(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
4425 pos1
, pos2
, &tcg_gen_andc_tl
, &tcg_gen_and_tl
);
4427 case OPC2_32_BIT_AND_NOR_T
:
4428 if (TCG_TARGET_HAS_andc_i32
) {
4429 gen_bit_2op(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
4430 pos1
, pos2
, &tcg_gen_or_tl
, &tcg_gen_andc_tl
);
4432 gen_bit_2op(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
4433 pos1
, pos2
, &tcg_gen_nor_tl
, &tcg_gen_and_tl
);
4436 case OPC2_32_BIT_AND_OR_T
:
4437 gen_bit_2op(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
4438 pos1
, pos2
, &tcg_gen_or_tl
, &tcg_gen_and_tl
);
4441 generate_trap(ctx
, TRAPC_INSN_ERR
, TIN2_IOPC
);
4445 static void decode_bit_logical_t(CPUTriCoreState
*env
, DisasContext
*ctx
)
4450 r1
= MASK_OP_BIT_S1(ctx
->opcode
);
4451 r2
= MASK_OP_BIT_S2(ctx
->opcode
);
4452 r3
= MASK_OP_BIT_D(ctx
->opcode
);
4453 pos1
= MASK_OP_BIT_POS1(ctx
->opcode
);
4454 pos2
= MASK_OP_BIT_POS2(ctx
->opcode
);
4455 op2
= MASK_OP_BIT_OP2(ctx
->opcode
);
4458 case OPC2_32_BIT_AND_T
:
4459 gen_bit_1op(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
4460 pos1
, pos2
, &tcg_gen_and_tl
);
4462 case OPC2_32_BIT_ANDN_T
:
4463 gen_bit_1op(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
4464 pos1
, pos2
, &tcg_gen_andc_tl
);
4466 case OPC2_32_BIT_NOR_T
:
4467 gen_bit_1op(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
4468 pos1
, pos2
, &tcg_gen_nor_tl
);
4470 case OPC2_32_BIT_OR_T
:
4471 gen_bit_1op(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
4472 pos1
, pos2
, &tcg_gen_or_tl
);
4475 generate_trap(ctx
, TRAPC_INSN_ERR
, TIN2_IOPC
);
4479 static void decode_bit_insert(CPUTriCoreState
*env
, DisasContext
*ctx
)
4485 op2
= MASK_OP_BIT_OP2(ctx
->opcode
);
4486 r1
= MASK_OP_BIT_S1(ctx
->opcode
);
4487 r2
= MASK_OP_BIT_S2(ctx
->opcode
);
4488 r3
= MASK_OP_BIT_D(ctx
->opcode
);
4489 pos1
= MASK_OP_BIT_POS1(ctx
->opcode
);
4490 pos2
= MASK_OP_BIT_POS2(ctx
->opcode
);
4492 temp
= tcg_temp_new();
4494 tcg_gen_shri_tl(temp
, cpu_gpr_d
[r2
], pos2
);
4495 if (op2
== OPC2_32_BIT_INSN_T
) {
4496 tcg_gen_not_tl(temp
, temp
);
4498 tcg_gen_deposit_tl(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], temp
, pos1
, 1);
4499 tcg_temp_free(temp
);
4502 static void decode_bit_logical_t2(CPUTriCoreState
*env
, DisasContext
*ctx
)
4509 op2
= MASK_OP_BIT_OP2(ctx
->opcode
);
4510 r1
= MASK_OP_BIT_S1(ctx
->opcode
);
4511 r2
= MASK_OP_BIT_S2(ctx
->opcode
);
4512 r3
= MASK_OP_BIT_D(ctx
->opcode
);
4513 pos1
= MASK_OP_BIT_POS1(ctx
->opcode
);
4514 pos2
= MASK_OP_BIT_POS2(ctx
->opcode
);
4517 case OPC2_32_BIT_NAND_T
:
4518 gen_bit_1op(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
4519 pos1
, pos2
, &tcg_gen_nand_tl
);
4521 case OPC2_32_BIT_ORN_T
:
4522 gen_bit_1op(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
4523 pos1
, pos2
, &tcg_gen_orc_tl
);
4525 case OPC2_32_BIT_XNOR_T
:
4526 gen_bit_1op(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
4527 pos1
, pos2
, &tcg_gen_eqv_tl
);
4529 case OPC2_32_BIT_XOR_T
:
4530 gen_bit_1op(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
4531 pos1
, pos2
, &tcg_gen_xor_tl
);
4534 generate_trap(ctx
, TRAPC_INSN_ERR
, TIN2_IOPC
);
4538 static void decode_bit_orand(CPUTriCoreState
*env
, DisasContext
*ctx
)
4545 op2
= MASK_OP_BIT_OP2(ctx
->opcode
);
4546 r1
= MASK_OP_BIT_S1(ctx
->opcode
);
4547 r2
= MASK_OP_BIT_S2(ctx
->opcode
);
4548 r3
= MASK_OP_BIT_D(ctx
->opcode
);
4549 pos1
= MASK_OP_BIT_POS1(ctx
->opcode
);
4550 pos2
= MASK_OP_BIT_POS2(ctx
->opcode
);
4553 case OPC2_32_BIT_OR_AND_T
:
4554 gen_bit_2op(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
4555 pos1
, pos2
, &tcg_gen_and_tl
, &tcg_gen_or_tl
);
4557 case OPC2_32_BIT_OR_ANDN_T
:
4558 gen_bit_2op(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
4559 pos1
, pos2
, &tcg_gen_andc_tl
, &tcg_gen_or_tl
);
4561 case OPC2_32_BIT_OR_NOR_T
:
4562 if (TCG_TARGET_HAS_orc_i32
) {
4563 gen_bit_2op(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
4564 pos1
, pos2
, &tcg_gen_or_tl
, &tcg_gen_orc_tl
);
4566 gen_bit_2op(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
4567 pos1
, pos2
, &tcg_gen_nor_tl
, &tcg_gen_or_tl
);
4570 case OPC2_32_BIT_OR_OR_T
:
4571 gen_bit_2op(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
4572 pos1
, pos2
, &tcg_gen_or_tl
, &tcg_gen_or_tl
);
4575 generate_trap(ctx
, TRAPC_INSN_ERR
, TIN2_IOPC
);
4579 static void decode_bit_sh_logic1(CPUTriCoreState
*env
, DisasContext
*ctx
)
4586 op2
= MASK_OP_BIT_OP2(ctx
->opcode
);
4587 r1
= MASK_OP_BIT_S1(ctx
->opcode
);
4588 r2
= MASK_OP_BIT_S2(ctx
->opcode
);
4589 r3
= MASK_OP_BIT_D(ctx
->opcode
);
4590 pos1
= MASK_OP_BIT_POS1(ctx
->opcode
);
4591 pos2
= MASK_OP_BIT_POS2(ctx
->opcode
);
4593 temp
= tcg_temp_new();
4596 case OPC2_32_BIT_SH_AND_T
:
4597 gen_bit_1op(temp
, cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
4598 pos1
, pos2
, &tcg_gen_and_tl
);
4600 case OPC2_32_BIT_SH_ANDN_T
:
4601 gen_bit_1op(temp
, cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
4602 pos1
, pos2
, &tcg_gen_andc_tl
);
4604 case OPC2_32_BIT_SH_NOR_T
:
4605 gen_bit_1op(temp
, cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
4606 pos1
, pos2
, &tcg_gen_nor_tl
);
4608 case OPC2_32_BIT_SH_OR_T
:
4609 gen_bit_1op(temp
, cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
4610 pos1
, pos2
, &tcg_gen_or_tl
);
4613 generate_trap(ctx
, TRAPC_INSN_ERR
, TIN2_IOPC
);
4615 tcg_gen_shli_tl(cpu_gpr_d
[r3
], cpu_gpr_d
[r3
], 1);
4616 tcg_gen_add_tl(cpu_gpr_d
[r3
], cpu_gpr_d
[r3
], temp
);
4617 tcg_temp_free(temp
);
4620 static void decode_bit_sh_logic2(CPUTriCoreState
*env
, DisasContext
*ctx
)
4627 op2
= MASK_OP_BIT_OP2(ctx
->opcode
);
4628 r1
= MASK_OP_BIT_S1(ctx
->opcode
);
4629 r2
= MASK_OP_BIT_S2(ctx
->opcode
);
4630 r3
= MASK_OP_BIT_D(ctx
->opcode
);
4631 pos1
= MASK_OP_BIT_POS1(ctx
->opcode
);
4632 pos2
= MASK_OP_BIT_POS2(ctx
->opcode
);
4634 temp
= tcg_temp_new();
4637 case OPC2_32_BIT_SH_NAND_T
:
4638 gen_bit_1op(temp
, cpu_gpr_d
[r1
] , cpu_gpr_d
[r2
] ,
4639 pos1
, pos2
, &tcg_gen_nand_tl
);
4641 case OPC2_32_BIT_SH_ORN_T
:
4642 gen_bit_1op(temp
, cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
4643 pos1
, pos2
, &tcg_gen_orc_tl
);
4645 case OPC2_32_BIT_SH_XNOR_T
:
4646 gen_bit_1op(temp
, cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
4647 pos1
, pos2
, &tcg_gen_eqv_tl
);
4649 case OPC2_32_BIT_SH_XOR_T
:
4650 gen_bit_1op(temp
, cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
4651 pos1
, pos2
, &tcg_gen_xor_tl
);
4654 generate_trap(ctx
, TRAPC_INSN_ERR
, TIN2_IOPC
);
4656 tcg_gen_shli_tl(cpu_gpr_d
[r3
], cpu_gpr_d
[r3
], 1);
4657 tcg_gen_add_tl(cpu_gpr_d
[r3
], cpu_gpr_d
[r3
], temp
);
4658 tcg_temp_free(temp
);
4664 static void decode_bo_addrmode_post_pre_base(CPUTriCoreState
*env
,
4672 r1
= MASK_OP_BO_S1D(ctx
->opcode
);
4673 r2
= MASK_OP_BO_S2(ctx
->opcode
);
4674 off10
= MASK_OP_BO_OFF10_SEXT(ctx
->opcode
);
4675 op2
= MASK_OP_BO_OP2(ctx
->opcode
);
4678 case OPC2_32_BO_CACHEA_WI_SHORTOFF
:
4679 case OPC2_32_BO_CACHEA_W_SHORTOFF
:
4680 case OPC2_32_BO_CACHEA_I_SHORTOFF
:
4681 /* instruction to access the cache */
4683 case OPC2_32_BO_CACHEA_WI_POSTINC
:
4684 case OPC2_32_BO_CACHEA_W_POSTINC
:
4685 case OPC2_32_BO_CACHEA_I_POSTINC
:
4686 /* instruction to access the cache, but we still need to handle
4687 the addressing mode */
4688 tcg_gen_addi_tl(cpu_gpr_a
[r2
], cpu_gpr_a
[r2
], off10
);
4690 case OPC2_32_BO_CACHEA_WI_PREINC
:
4691 case OPC2_32_BO_CACHEA_W_PREINC
:
4692 case OPC2_32_BO_CACHEA_I_PREINC
:
4693 /* instruction to access the cache, but we still need to handle
4694 the addressing mode */
4695 tcg_gen_addi_tl(cpu_gpr_a
[r2
], cpu_gpr_a
[r2
], off10
);
4697 case OPC2_32_BO_CACHEI_WI_SHORTOFF
:
4698 case OPC2_32_BO_CACHEI_W_SHORTOFF
:
4699 if (!tricore_feature(env
, TRICORE_FEATURE_131
)) {
4700 generate_trap(ctx
, TRAPC_INSN_ERR
, TIN2_IOPC
);
4703 case OPC2_32_BO_CACHEI_W_POSTINC
:
4704 case OPC2_32_BO_CACHEI_WI_POSTINC
:
4705 if (tricore_feature(env
, TRICORE_FEATURE_131
)) {
4706 tcg_gen_addi_tl(cpu_gpr_a
[r2
], cpu_gpr_a
[r2
], off10
);
4708 generate_trap(ctx
, TRAPC_INSN_ERR
, TIN2_IOPC
);
4711 case OPC2_32_BO_CACHEI_W_PREINC
:
4712 case OPC2_32_BO_CACHEI_WI_PREINC
:
4713 if (tricore_feature(env
, TRICORE_FEATURE_131
)) {
4714 tcg_gen_addi_tl(cpu_gpr_a
[r2
], cpu_gpr_a
[r2
], off10
);
4716 generate_trap(ctx
, TRAPC_INSN_ERR
, TIN2_IOPC
);
4719 case OPC2_32_BO_ST_A_SHORTOFF
:
4720 gen_offset_st(ctx
, cpu_gpr_a
[r1
], cpu_gpr_a
[r2
], off10
, MO_LESL
);
4722 case OPC2_32_BO_ST_A_POSTINC
:
4723 tcg_gen_qemu_st_tl(cpu_gpr_a
[r1
], cpu_gpr_a
[r2
], ctx
->mem_idx
,
4725 tcg_gen_addi_tl(cpu_gpr_a
[r2
], cpu_gpr_a
[r2
], off10
);
4727 case OPC2_32_BO_ST_A_PREINC
:
4728 gen_st_preincr(ctx
, cpu_gpr_a
[r1
], cpu_gpr_a
[r2
], off10
, MO_LESL
);
4730 case OPC2_32_BO_ST_B_SHORTOFF
:
4731 gen_offset_st(ctx
, cpu_gpr_d
[r1
], cpu_gpr_a
[r2
], off10
, MO_UB
);
4733 case OPC2_32_BO_ST_B_POSTINC
:
4734 tcg_gen_qemu_st_tl(cpu_gpr_d
[r1
], cpu_gpr_a
[r2
], ctx
->mem_idx
,
4736 tcg_gen_addi_tl(cpu_gpr_a
[r2
], cpu_gpr_a
[r2
], off10
);
4738 case OPC2_32_BO_ST_B_PREINC
:
4739 gen_st_preincr(ctx
, cpu_gpr_d
[r1
], cpu_gpr_a
[r2
], off10
, MO_UB
);
4741 case OPC2_32_BO_ST_D_SHORTOFF
:
4743 gen_offset_st_2regs(cpu_gpr_d
[r1
+1], cpu_gpr_d
[r1
], cpu_gpr_a
[r2
],
4746 case OPC2_32_BO_ST_D_POSTINC
:
4748 gen_st_2regs_64(cpu_gpr_d
[r1
+1], cpu_gpr_d
[r1
], cpu_gpr_a
[r2
], ctx
);
4749 tcg_gen_addi_tl(cpu_gpr_a
[r2
], cpu_gpr_a
[r2
], off10
);
4751 case OPC2_32_BO_ST_D_PREINC
:
4753 temp
= tcg_temp_new();
4754 tcg_gen_addi_tl(temp
, cpu_gpr_a
[r2
], off10
);
4755 gen_st_2regs_64(cpu_gpr_d
[r1
+1], cpu_gpr_d
[r1
], temp
, ctx
);
4756 tcg_gen_mov_tl(cpu_gpr_a
[r2
], temp
);
4757 tcg_temp_free(temp
);
4759 case OPC2_32_BO_ST_DA_SHORTOFF
:
4761 gen_offset_st_2regs(cpu_gpr_a
[r1
+1], cpu_gpr_a
[r1
], cpu_gpr_a
[r2
],
4764 case OPC2_32_BO_ST_DA_POSTINC
:
4766 gen_st_2regs_64(cpu_gpr_a
[r1
+1], cpu_gpr_a
[r1
], cpu_gpr_a
[r2
], ctx
);
4767 tcg_gen_addi_tl(cpu_gpr_a
[r2
], cpu_gpr_a
[r2
], off10
);
4769 case OPC2_32_BO_ST_DA_PREINC
:
4771 temp
= tcg_temp_new();
4772 tcg_gen_addi_tl(temp
, cpu_gpr_a
[r2
], off10
);
4773 gen_st_2regs_64(cpu_gpr_a
[r1
+1], cpu_gpr_a
[r1
], temp
, ctx
);
4774 tcg_gen_mov_tl(cpu_gpr_a
[r2
], temp
);
4775 tcg_temp_free(temp
);
4777 case OPC2_32_BO_ST_H_SHORTOFF
:
4778 gen_offset_st(ctx
, cpu_gpr_d
[r1
], cpu_gpr_a
[r2
], off10
, MO_LEUW
);
4780 case OPC2_32_BO_ST_H_POSTINC
:
4781 tcg_gen_qemu_st_tl(cpu_gpr_d
[r1
], cpu_gpr_a
[r2
], ctx
->mem_idx
,
4783 tcg_gen_addi_tl(cpu_gpr_a
[r2
], cpu_gpr_a
[r2
], off10
);
4785 case OPC2_32_BO_ST_H_PREINC
:
4786 gen_st_preincr(ctx
, cpu_gpr_d
[r1
], cpu_gpr_a
[r2
], off10
, MO_LEUW
);
4788 case OPC2_32_BO_ST_Q_SHORTOFF
:
4789 temp
= tcg_temp_new();
4790 tcg_gen_shri_tl(temp
, cpu_gpr_d
[r1
], 16);
4791 gen_offset_st(ctx
, temp
, cpu_gpr_a
[r2
], off10
, MO_LEUW
);
4792 tcg_temp_free(temp
);
4794 case OPC2_32_BO_ST_Q_POSTINC
:
4795 temp
= tcg_temp_new();
4796 tcg_gen_shri_tl(temp
, cpu_gpr_d
[r1
], 16);
4797 tcg_gen_qemu_st_tl(temp
, cpu_gpr_a
[r2
], ctx
->mem_idx
,
4799 tcg_gen_addi_tl(cpu_gpr_a
[r2
], cpu_gpr_a
[r2
], off10
);
4800 tcg_temp_free(temp
);
4802 case OPC2_32_BO_ST_Q_PREINC
:
4803 temp
= tcg_temp_new();
4804 tcg_gen_shri_tl(temp
, cpu_gpr_d
[r1
], 16);
4805 gen_st_preincr(ctx
, temp
, cpu_gpr_a
[r2
], off10
, MO_LEUW
);
4806 tcg_temp_free(temp
);
4808 case OPC2_32_BO_ST_W_SHORTOFF
:
4809 gen_offset_st(ctx
, cpu_gpr_d
[r1
], cpu_gpr_a
[r2
], off10
, MO_LEUL
);
4811 case OPC2_32_BO_ST_W_POSTINC
:
4812 tcg_gen_qemu_st_tl(cpu_gpr_d
[r1
], cpu_gpr_a
[r2
], ctx
->mem_idx
,
4814 tcg_gen_addi_tl(cpu_gpr_a
[r2
], cpu_gpr_a
[r2
], off10
);
4816 case OPC2_32_BO_ST_W_PREINC
:
4817 gen_st_preincr(ctx
, cpu_gpr_d
[r1
], cpu_gpr_a
[r2
], off10
, MO_LEUL
);
4820 generate_trap(ctx
, TRAPC_INSN_ERR
, TIN2_IOPC
);
4824 static void decode_bo_addrmode_bitreverse_circular(CPUTriCoreState
*env
,
4830 TCGv temp
, temp2
, temp3
;
4832 r1
= MASK_OP_BO_S1D(ctx
->opcode
);
4833 r2
= MASK_OP_BO_S2(ctx
->opcode
);
4834 off10
= MASK_OP_BO_OFF10_SEXT(ctx
->opcode
);
4835 op2
= MASK_OP_BO_OP2(ctx
->opcode
);
4837 temp
= tcg_temp_new();
4838 temp2
= tcg_temp_new();
4839 temp3
= tcg_const_i32(off10
);
4841 tcg_gen_ext16u_tl(temp
, cpu_gpr_a
[r2
+1]);
4842 tcg_gen_add_tl(temp2
, cpu_gpr_a
[r2
], temp
);
4845 case OPC2_32_BO_CACHEA_WI_BR
:
4846 case OPC2_32_BO_CACHEA_W_BR
:
4847 case OPC2_32_BO_CACHEA_I_BR
:
4848 gen_helper_br_update(cpu_gpr_a
[r2
+1], cpu_gpr_a
[r2
+1]);
4850 case OPC2_32_BO_CACHEA_WI_CIRC
:
4851 case OPC2_32_BO_CACHEA_W_CIRC
:
4852 case OPC2_32_BO_CACHEA_I_CIRC
:
4853 gen_helper_circ_update(cpu_gpr_a
[r2
+1], cpu_gpr_a
[r2
+1], temp3
);
4855 case OPC2_32_BO_ST_A_BR
:
4856 tcg_gen_qemu_st_tl(cpu_gpr_a
[r1
], temp2
, ctx
->mem_idx
, MO_LEUL
);
4857 gen_helper_br_update(cpu_gpr_a
[r2
+1], cpu_gpr_a
[r2
+1]);
4859 case OPC2_32_BO_ST_A_CIRC
:
4860 tcg_gen_qemu_st_tl(cpu_gpr_a
[r1
], temp2
, ctx
->mem_idx
, MO_LEUL
);
4861 gen_helper_circ_update(cpu_gpr_a
[r2
+1], cpu_gpr_a
[r2
+1], temp3
);
4863 case OPC2_32_BO_ST_B_BR
:
4864 tcg_gen_qemu_st_tl(cpu_gpr_d
[r1
], temp2
, ctx
->mem_idx
, MO_UB
);
4865 gen_helper_br_update(cpu_gpr_a
[r2
+1], cpu_gpr_a
[r2
+1]);
4867 case OPC2_32_BO_ST_B_CIRC
:
4868 tcg_gen_qemu_st_tl(cpu_gpr_d
[r1
], temp2
, ctx
->mem_idx
, MO_UB
);
4869 gen_helper_circ_update(cpu_gpr_a
[r2
+1], cpu_gpr_a
[r2
+1], temp3
);
4871 case OPC2_32_BO_ST_D_BR
:
4873 gen_st_2regs_64(cpu_gpr_d
[r1
+1], cpu_gpr_d
[r1
], temp2
, ctx
);
4874 gen_helper_br_update(cpu_gpr_a
[r2
+1], cpu_gpr_a
[r2
+1]);
4876 case OPC2_32_BO_ST_D_CIRC
:
4878 tcg_gen_qemu_st_tl(cpu_gpr_d
[r1
], temp2
, ctx
->mem_idx
, MO_LEUL
);
4879 tcg_gen_shri_tl(temp2
, cpu_gpr_a
[r2
+1], 16);
4880 tcg_gen_addi_tl(temp
, temp
, 4);
4881 tcg_gen_rem_tl(temp
, temp
, temp2
);
4882 tcg_gen_add_tl(temp2
, cpu_gpr_a
[r2
], temp
);
4883 tcg_gen_qemu_st_tl(cpu_gpr_d
[r1
+1], temp2
, ctx
->mem_idx
, MO_LEUL
);
4884 gen_helper_circ_update(cpu_gpr_a
[r2
+1], cpu_gpr_a
[r2
+1], temp3
);
4886 case OPC2_32_BO_ST_DA_BR
:
4888 gen_st_2regs_64(cpu_gpr_a
[r1
+1], cpu_gpr_a
[r1
], temp2
, ctx
);
4889 gen_helper_br_update(cpu_gpr_a
[r2
+1], cpu_gpr_a
[r2
+1]);
4891 case OPC2_32_BO_ST_DA_CIRC
:
4893 tcg_gen_qemu_st_tl(cpu_gpr_a
[r1
], temp2
, ctx
->mem_idx
, MO_LEUL
);
4894 tcg_gen_shri_tl(temp2
, cpu_gpr_a
[r2
+1], 16);
4895 tcg_gen_addi_tl(temp
, temp
, 4);
4896 tcg_gen_rem_tl(temp
, temp
, temp2
);
4897 tcg_gen_add_tl(temp2
, cpu_gpr_a
[r2
], temp
);
4898 tcg_gen_qemu_st_tl(cpu_gpr_a
[r1
+1], temp2
, ctx
->mem_idx
, MO_LEUL
);
4899 gen_helper_circ_update(cpu_gpr_a
[r2
+1], cpu_gpr_a
[r2
+1], temp3
);
4901 case OPC2_32_BO_ST_H_BR
:
4902 tcg_gen_qemu_st_tl(cpu_gpr_d
[r1
], temp2
, ctx
->mem_idx
, MO_LEUW
);
4903 gen_helper_br_update(cpu_gpr_a
[r2
+1], cpu_gpr_a
[r2
+1]);
4905 case OPC2_32_BO_ST_H_CIRC
:
4906 tcg_gen_qemu_st_tl(cpu_gpr_d
[r1
], temp2
, ctx
->mem_idx
, MO_LEUW
);
4907 gen_helper_circ_update(cpu_gpr_a
[r2
+1], cpu_gpr_a
[r2
+1], temp3
);
4909 case OPC2_32_BO_ST_Q_BR
:
4910 tcg_gen_shri_tl(temp
, cpu_gpr_d
[r1
], 16);
4911 tcg_gen_qemu_st_tl(temp
, temp2
, ctx
->mem_idx
, MO_LEUW
);
4912 gen_helper_br_update(cpu_gpr_a
[r2
+1], cpu_gpr_a
[r2
+1]);
4914 case OPC2_32_BO_ST_Q_CIRC
:
4915 tcg_gen_shri_tl(temp
, cpu_gpr_d
[r1
], 16);
4916 tcg_gen_qemu_st_tl(temp
, temp2
, ctx
->mem_idx
, MO_LEUW
);
4917 gen_helper_circ_update(cpu_gpr_a
[r2
+1], cpu_gpr_a
[r2
+1], temp3
);
4919 case OPC2_32_BO_ST_W_BR
:
4920 tcg_gen_qemu_st_tl(cpu_gpr_d
[r1
], temp2
, ctx
->mem_idx
, MO_LEUL
);
4921 gen_helper_br_update(cpu_gpr_a
[r2
+1], cpu_gpr_a
[r2
+1]);
4923 case OPC2_32_BO_ST_W_CIRC
:
4924 tcg_gen_qemu_st_tl(cpu_gpr_d
[r1
], temp2
, ctx
->mem_idx
, MO_LEUL
);
4925 gen_helper_circ_update(cpu_gpr_a
[r2
+1], cpu_gpr_a
[r2
+1], temp3
);
4928 generate_trap(ctx
, TRAPC_INSN_ERR
, TIN2_IOPC
);
4930 tcg_temp_free(temp
);
4931 tcg_temp_free(temp2
);
4932 tcg_temp_free(temp3
);
4935 static void decode_bo_addrmode_ld_post_pre_base(CPUTriCoreState
*env
,
4943 r1
= MASK_OP_BO_S1D(ctx
->opcode
);
4944 r2
= MASK_OP_BO_S2(ctx
->opcode
);
4945 off10
= MASK_OP_BO_OFF10_SEXT(ctx
->opcode
);
4946 op2
= MASK_OP_BO_OP2(ctx
->opcode
);
4949 case OPC2_32_BO_LD_A_SHORTOFF
:
4950 gen_offset_ld(ctx
, cpu_gpr_a
[r1
], cpu_gpr_a
[r2
], off10
, MO_LEUL
);
4952 case OPC2_32_BO_LD_A_POSTINC
:
4953 tcg_gen_qemu_ld_tl(cpu_gpr_a
[r1
], cpu_gpr_a
[r2
], ctx
->mem_idx
,
4955 tcg_gen_addi_tl(cpu_gpr_a
[r2
], cpu_gpr_a
[r2
], off10
);
4957 case OPC2_32_BO_LD_A_PREINC
:
4958 gen_ld_preincr(ctx
, cpu_gpr_a
[r1
], cpu_gpr_a
[r2
], off10
, MO_LEUL
);
4960 case OPC2_32_BO_LD_B_SHORTOFF
:
4961 gen_offset_ld(ctx
, cpu_gpr_d
[r1
], cpu_gpr_a
[r2
], off10
, MO_SB
);
4963 case OPC2_32_BO_LD_B_POSTINC
:
4964 tcg_gen_qemu_ld_tl(cpu_gpr_d
[r1
], cpu_gpr_a
[r2
], ctx
->mem_idx
,
4966 tcg_gen_addi_tl(cpu_gpr_a
[r2
], cpu_gpr_a
[r2
], off10
);
4968 case OPC2_32_BO_LD_B_PREINC
:
4969 gen_ld_preincr(ctx
, cpu_gpr_d
[r1
], cpu_gpr_a
[r2
], off10
, MO_SB
);
4971 case OPC2_32_BO_LD_BU_SHORTOFF
:
4972 gen_offset_ld(ctx
, cpu_gpr_d
[r1
], cpu_gpr_a
[r2
], off10
, MO_UB
);
4974 case OPC2_32_BO_LD_BU_POSTINC
:
4975 tcg_gen_qemu_ld_tl(cpu_gpr_d
[r1
], cpu_gpr_a
[r2
], ctx
->mem_idx
,
4977 tcg_gen_addi_tl(cpu_gpr_a
[r2
], cpu_gpr_a
[r2
], off10
);
4979 case OPC2_32_BO_LD_BU_PREINC
:
4980 gen_ld_preincr(ctx
, cpu_gpr_d
[r1
], cpu_gpr_a
[r2
], off10
, MO_SB
);
4982 case OPC2_32_BO_LD_D_SHORTOFF
:
4984 gen_offset_ld_2regs(cpu_gpr_d
[r1
+1], cpu_gpr_d
[r1
], cpu_gpr_a
[r2
],
4987 case OPC2_32_BO_LD_D_POSTINC
:
4989 gen_ld_2regs_64(cpu_gpr_d
[r1
+1], cpu_gpr_d
[r1
], cpu_gpr_a
[r2
], ctx
);
4990 tcg_gen_addi_tl(cpu_gpr_a
[r2
], cpu_gpr_a
[r2
], off10
);
4992 case OPC2_32_BO_LD_D_PREINC
:
4994 temp
= tcg_temp_new();
4995 tcg_gen_addi_tl(temp
, cpu_gpr_a
[r2
], off10
);
4996 gen_ld_2regs_64(cpu_gpr_d
[r1
+1], cpu_gpr_d
[r1
], temp
, ctx
);
4997 tcg_gen_mov_tl(cpu_gpr_a
[r2
], temp
);
4998 tcg_temp_free(temp
);
5000 case OPC2_32_BO_LD_DA_SHORTOFF
:
5002 gen_offset_ld_2regs(cpu_gpr_a
[r1
+1], cpu_gpr_a
[r1
], cpu_gpr_a
[r2
],
5005 case OPC2_32_BO_LD_DA_POSTINC
:
5007 gen_ld_2regs_64(cpu_gpr_a
[r1
+1], cpu_gpr_a
[r1
], cpu_gpr_a
[r2
], ctx
);
5008 tcg_gen_addi_tl(cpu_gpr_a
[r2
], cpu_gpr_a
[r2
], off10
);
5010 case OPC2_32_BO_LD_DA_PREINC
:
5012 temp
= tcg_temp_new();
5013 tcg_gen_addi_tl(temp
, cpu_gpr_a
[r2
], off10
);
5014 gen_ld_2regs_64(cpu_gpr_a
[r1
+1], cpu_gpr_a
[r1
], temp
, ctx
);
5015 tcg_gen_mov_tl(cpu_gpr_a
[r2
], temp
);
5016 tcg_temp_free(temp
);
5018 case OPC2_32_BO_LD_H_SHORTOFF
:
5019 gen_offset_ld(ctx
, cpu_gpr_d
[r1
], cpu_gpr_a
[r2
], off10
, MO_LESW
);
5021 case OPC2_32_BO_LD_H_POSTINC
:
5022 tcg_gen_qemu_ld_tl(cpu_gpr_d
[r1
], cpu_gpr_a
[r2
], ctx
->mem_idx
,
5024 tcg_gen_addi_tl(cpu_gpr_a
[r2
], cpu_gpr_a
[r2
], off10
);
5026 case OPC2_32_BO_LD_H_PREINC
:
5027 gen_ld_preincr(ctx
, cpu_gpr_d
[r1
], cpu_gpr_a
[r2
], off10
, MO_LESW
);
5029 case OPC2_32_BO_LD_HU_SHORTOFF
:
5030 gen_offset_ld(ctx
, cpu_gpr_d
[r1
], cpu_gpr_a
[r2
], off10
, MO_LEUW
);
5032 case OPC2_32_BO_LD_HU_POSTINC
:
5033 tcg_gen_qemu_ld_tl(cpu_gpr_d
[r1
], cpu_gpr_a
[r2
], ctx
->mem_idx
,
5035 tcg_gen_addi_tl(cpu_gpr_a
[r2
], cpu_gpr_a
[r2
], off10
);
5037 case OPC2_32_BO_LD_HU_PREINC
:
5038 gen_ld_preincr(ctx
, cpu_gpr_d
[r1
], cpu_gpr_a
[r2
], off10
, MO_LEUW
);
5040 case OPC2_32_BO_LD_Q_SHORTOFF
:
5041 gen_offset_ld(ctx
, cpu_gpr_d
[r1
], cpu_gpr_a
[r2
], off10
, MO_LEUW
);
5042 tcg_gen_shli_tl(cpu_gpr_d
[r1
], cpu_gpr_d
[r1
], 16);
5044 case OPC2_32_BO_LD_Q_POSTINC
:
5045 tcg_gen_qemu_ld_tl(cpu_gpr_d
[r1
], cpu_gpr_a
[r2
], ctx
->mem_idx
,
5047 tcg_gen_shli_tl(cpu_gpr_d
[r1
], cpu_gpr_d
[r1
], 16);
5048 tcg_gen_addi_tl(cpu_gpr_a
[r2
], cpu_gpr_a
[r2
], off10
);
5050 case OPC2_32_BO_LD_Q_PREINC
:
5051 gen_ld_preincr(ctx
, cpu_gpr_d
[r1
], cpu_gpr_a
[r2
], off10
, MO_LEUW
);
5052 tcg_gen_shli_tl(cpu_gpr_d
[r1
], cpu_gpr_d
[r1
], 16);
5054 case OPC2_32_BO_LD_W_SHORTOFF
:
5055 gen_offset_ld(ctx
, cpu_gpr_d
[r1
], cpu_gpr_a
[r2
], off10
, MO_LEUL
);
5057 case OPC2_32_BO_LD_W_POSTINC
:
5058 tcg_gen_qemu_ld_tl(cpu_gpr_d
[r1
], cpu_gpr_a
[r2
], ctx
->mem_idx
,
5060 tcg_gen_addi_tl(cpu_gpr_a
[r2
], cpu_gpr_a
[r2
], off10
);
5062 case OPC2_32_BO_LD_W_PREINC
:
5063 gen_ld_preincr(ctx
, cpu_gpr_d
[r1
], cpu_gpr_a
[r2
], off10
, MO_LEUL
);
5066 generate_trap(ctx
, TRAPC_INSN_ERR
, TIN2_IOPC
);
5070 static void decode_bo_addrmode_ld_bitreverse_circular(CPUTriCoreState
*env
,
5077 TCGv temp
, temp2
, temp3
;
5079 r1
= MASK_OP_BO_S1D(ctx
->opcode
);
5080 r2
= MASK_OP_BO_S2(ctx
->opcode
);
5081 off10
= MASK_OP_BO_OFF10_SEXT(ctx
->opcode
);
5082 op2
= MASK_OP_BO_OP2(ctx
->opcode
);
5084 temp
= tcg_temp_new();
5085 temp2
= tcg_temp_new();
5086 temp3
= tcg_const_i32(off10
);
5088 tcg_gen_ext16u_tl(temp
, cpu_gpr_a
[r2
+1]);
5089 tcg_gen_add_tl(temp2
, cpu_gpr_a
[r2
], temp
);
5093 case OPC2_32_BO_LD_A_BR
:
5094 tcg_gen_qemu_ld_tl(cpu_gpr_a
[r1
], temp2
, ctx
->mem_idx
, MO_LEUL
);
5095 gen_helper_br_update(cpu_gpr_a
[r2
+1], cpu_gpr_a
[r2
+1]);
5097 case OPC2_32_BO_LD_A_CIRC
:
5098 tcg_gen_qemu_ld_tl(cpu_gpr_a
[r1
], temp2
, ctx
->mem_idx
, MO_LEUL
);
5099 gen_helper_circ_update(cpu_gpr_a
[r2
+1], cpu_gpr_a
[r2
+1], temp3
);
5101 case OPC2_32_BO_LD_B_BR
:
5102 tcg_gen_qemu_ld_tl(cpu_gpr_d
[r1
], temp2
, ctx
->mem_idx
, MO_SB
);
5103 gen_helper_br_update(cpu_gpr_a
[r2
+1], cpu_gpr_a
[r2
+1]);
5105 case OPC2_32_BO_LD_B_CIRC
:
5106 tcg_gen_qemu_ld_tl(cpu_gpr_d
[r1
], temp2
, ctx
->mem_idx
, MO_SB
);
5107 gen_helper_circ_update(cpu_gpr_a
[r2
+1], cpu_gpr_a
[r2
+1], temp3
);
5109 case OPC2_32_BO_LD_BU_BR
:
5110 tcg_gen_qemu_ld_tl(cpu_gpr_d
[r1
], temp2
, ctx
->mem_idx
, MO_UB
);
5111 gen_helper_br_update(cpu_gpr_a
[r2
+1], cpu_gpr_a
[r2
+1]);
5113 case OPC2_32_BO_LD_BU_CIRC
:
5114 tcg_gen_qemu_ld_tl(cpu_gpr_d
[r1
], temp2
, ctx
->mem_idx
, MO_UB
);
5115 gen_helper_circ_update(cpu_gpr_a
[r2
+1], cpu_gpr_a
[r2
+1], temp3
);
5117 case OPC2_32_BO_LD_D_BR
:
5119 gen_ld_2regs_64(cpu_gpr_d
[r1
+1], cpu_gpr_d
[r1
], temp2
, ctx
);
5120 gen_helper_br_update(cpu_gpr_a
[r2
+1], cpu_gpr_a
[r2
+1]);
5122 case OPC2_32_BO_LD_D_CIRC
:
5124 tcg_gen_qemu_ld_tl(cpu_gpr_d
[r1
], temp2
, ctx
->mem_idx
, MO_LEUL
);
5125 tcg_gen_shri_tl(temp2
, cpu_gpr_a
[r2
+1], 16);
5126 tcg_gen_addi_tl(temp
, temp
, 4);
5127 tcg_gen_rem_tl(temp
, temp
, temp2
);
5128 tcg_gen_add_tl(temp2
, cpu_gpr_a
[r2
], temp
);
5129 tcg_gen_qemu_ld_tl(cpu_gpr_d
[r1
+1], temp2
, ctx
->mem_idx
, MO_LEUL
);
5130 gen_helper_circ_update(cpu_gpr_a
[r2
+1], cpu_gpr_a
[r2
+1], temp3
);
5132 case OPC2_32_BO_LD_DA_BR
:
5134 gen_ld_2regs_64(cpu_gpr_a
[r1
+1], cpu_gpr_a
[r1
], temp2
, ctx
);
5135 gen_helper_br_update(cpu_gpr_a
[r2
+1], cpu_gpr_a
[r2
+1]);
5137 case OPC2_32_BO_LD_DA_CIRC
:
5139 tcg_gen_qemu_ld_tl(cpu_gpr_a
[r1
], temp2
, ctx
->mem_idx
, MO_LEUL
);
5140 tcg_gen_shri_tl(temp2
, cpu_gpr_a
[r2
+1], 16);
5141 tcg_gen_addi_tl(temp
, temp
, 4);
5142 tcg_gen_rem_tl(temp
, temp
, temp2
);
5143 tcg_gen_add_tl(temp2
, cpu_gpr_a
[r2
], temp
);
5144 tcg_gen_qemu_ld_tl(cpu_gpr_a
[r1
+1], temp2
, ctx
->mem_idx
, MO_LEUL
);
5145 gen_helper_circ_update(cpu_gpr_a
[r2
+1], cpu_gpr_a
[r2
+1], temp3
);
5147 case OPC2_32_BO_LD_H_BR
:
5148 tcg_gen_qemu_ld_tl(cpu_gpr_d
[r1
], temp2
, ctx
->mem_idx
, MO_LESW
);
5149 gen_helper_br_update(cpu_gpr_a
[r2
+1], cpu_gpr_a
[r2
+1]);
5151 case OPC2_32_BO_LD_H_CIRC
:
5152 tcg_gen_qemu_ld_tl(cpu_gpr_d
[r1
], temp2
, ctx
->mem_idx
, MO_LESW
);
5153 gen_helper_circ_update(cpu_gpr_a
[r2
+1], cpu_gpr_a
[r2
+1], temp3
);
5155 case OPC2_32_BO_LD_HU_BR
:
5156 tcg_gen_qemu_ld_tl(cpu_gpr_d
[r1
], temp2
, ctx
->mem_idx
, MO_LEUW
);
5157 gen_helper_br_update(cpu_gpr_a
[r2
+1], cpu_gpr_a
[r2
+1]);
5159 case OPC2_32_BO_LD_HU_CIRC
:
5160 tcg_gen_qemu_ld_tl(cpu_gpr_d
[r1
], temp2
, ctx
->mem_idx
, MO_LEUW
);
5161 gen_helper_circ_update(cpu_gpr_a
[r2
+1], cpu_gpr_a
[r2
+1], temp3
);
5163 case OPC2_32_BO_LD_Q_BR
:
5164 tcg_gen_qemu_ld_tl(cpu_gpr_d
[r1
], temp2
, ctx
->mem_idx
, MO_LEUW
);
5165 tcg_gen_shli_tl(cpu_gpr_d
[r1
], cpu_gpr_d
[r1
], 16);
5166 gen_helper_br_update(cpu_gpr_a
[r2
+1], cpu_gpr_a
[r2
+1]);
5168 case OPC2_32_BO_LD_Q_CIRC
:
5169 tcg_gen_qemu_ld_tl(cpu_gpr_d
[r1
], temp2
, ctx
->mem_idx
, MO_LEUW
);
5170 tcg_gen_shli_tl(cpu_gpr_d
[r1
], cpu_gpr_d
[r1
], 16);
5171 gen_helper_circ_update(cpu_gpr_a
[r2
+1], cpu_gpr_a
[r2
+1], temp3
);
5173 case OPC2_32_BO_LD_W_BR
:
5174 tcg_gen_qemu_ld_tl(cpu_gpr_d
[r1
], temp2
, ctx
->mem_idx
, MO_LEUL
);
5175 gen_helper_br_update(cpu_gpr_a
[r2
+1], cpu_gpr_a
[r2
+1]);
5177 case OPC2_32_BO_LD_W_CIRC
:
5178 tcg_gen_qemu_ld_tl(cpu_gpr_d
[r1
], temp2
, ctx
->mem_idx
, MO_LEUL
);
5179 gen_helper_circ_update(cpu_gpr_a
[r2
+1], cpu_gpr_a
[r2
+1], temp3
);
5182 generate_trap(ctx
, TRAPC_INSN_ERR
, TIN2_IOPC
);
5184 tcg_temp_free(temp
);
5185 tcg_temp_free(temp2
);
5186 tcg_temp_free(temp3
);
5189 static void decode_bo_addrmode_stctx_post_pre_base(CPUTriCoreState
*env
,
5198 r1
= MASK_OP_BO_S1D(ctx
->opcode
);
5199 r2
= MASK_OP_BO_S2(ctx
->opcode
);
5200 off10
= MASK_OP_BO_OFF10_SEXT(ctx
->opcode
);
5201 op2
= MASK_OP_BO_OP2(ctx
->opcode
);
5204 temp
= tcg_temp_new();
5205 temp2
= tcg_temp_new();
5208 case OPC2_32_BO_LDLCX_SHORTOFF
:
5209 tcg_gen_addi_tl(temp
, cpu_gpr_a
[r2
], off10
);
5210 gen_helper_ldlcx(cpu_env
, temp
);
5212 case OPC2_32_BO_LDMST_SHORTOFF
:
5213 tcg_gen_addi_tl(temp
, cpu_gpr_a
[r2
], off10
);
5214 gen_ldmst(ctx
, r1
, temp
);
5216 case OPC2_32_BO_LDMST_POSTINC
:
5217 gen_ldmst(ctx
, r1
, cpu_gpr_a
[r2
]);
5218 tcg_gen_addi_tl(cpu_gpr_a
[r2
], cpu_gpr_a
[r2
], off10
);
5220 case OPC2_32_BO_LDMST_PREINC
:
5221 tcg_gen_addi_tl(cpu_gpr_a
[r2
], cpu_gpr_a
[r2
], off10
);
5222 gen_ldmst(ctx
, r1
, cpu_gpr_a
[r2
]);
5224 case OPC2_32_BO_LDUCX_SHORTOFF
:
5225 tcg_gen_addi_tl(temp
, cpu_gpr_a
[r2
], off10
);
5226 gen_helper_lducx(cpu_env
, temp
);
5228 case OPC2_32_BO_LEA_SHORTOFF
:
5229 tcg_gen_addi_tl(cpu_gpr_a
[r1
], cpu_gpr_a
[r2
], off10
);
5231 case OPC2_32_BO_STLCX_SHORTOFF
:
5232 tcg_gen_addi_tl(temp
, cpu_gpr_a
[r2
], off10
);
5233 gen_helper_stlcx(cpu_env
, temp
);
5235 case OPC2_32_BO_STUCX_SHORTOFF
:
5236 tcg_gen_addi_tl(temp
, cpu_gpr_a
[r2
], off10
);
5237 gen_helper_stucx(cpu_env
, temp
);
5239 case OPC2_32_BO_SWAP_W_SHORTOFF
:
5240 tcg_gen_addi_tl(temp
, cpu_gpr_a
[r2
], off10
);
5241 gen_swap(ctx
, r1
, temp
);
5243 case OPC2_32_BO_SWAP_W_POSTINC
:
5244 gen_swap(ctx
, r1
, cpu_gpr_a
[r2
]);
5245 tcg_gen_addi_tl(cpu_gpr_a
[r2
], cpu_gpr_a
[r2
], off10
);
5247 case OPC2_32_BO_SWAP_W_PREINC
:
5248 tcg_gen_addi_tl(cpu_gpr_a
[r2
], cpu_gpr_a
[r2
], off10
);
5249 gen_swap(ctx
, r1
, cpu_gpr_a
[r2
]);
5251 case OPC2_32_BO_CMPSWAP_W_SHORTOFF
:
5252 tcg_gen_addi_tl(temp
, cpu_gpr_a
[r2
], off10
);
5253 gen_cmpswap(ctx
, r1
, temp
);
5255 case OPC2_32_BO_CMPSWAP_W_POSTINC
:
5256 gen_cmpswap(ctx
, r1
, cpu_gpr_a
[r2
]);
5257 tcg_gen_addi_tl(cpu_gpr_a
[r2
], cpu_gpr_a
[r2
], off10
);
5259 case OPC2_32_BO_CMPSWAP_W_PREINC
:
5260 tcg_gen_addi_tl(cpu_gpr_a
[r2
], cpu_gpr_a
[r2
], off10
);
5261 gen_cmpswap(ctx
, r1
, cpu_gpr_a
[r2
]);
5263 case OPC2_32_BO_SWAPMSK_W_SHORTOFF
:
5264 tcg_gen_addi_tl(temp
, cpu_gpr_a
[r2
], off10
);
5265 gen_swapmsk(ctx
, r1
, temp
);
5267 case OPC2_32_BO_SWAPMSK_W_POSTINC
:
5268 gen_swapmsk(ctx
, r1
, cpu_gpr_a
[r2
]);
5269 tcg_gen_addi_tl(cpu_gpr_a
[r2
], cpu_gpr_a
[r2
], off10
);
5271 case OPC2_32_BO_SWAPMSK_W_PREINC
:
5272 tcg_gen_addi_tl(cpu_gpr_a
[r2
], cpu_gpr_a
[r2
], off10
);
5273 gen_swapmsk(ctx
, r1
, cpu_gpr_a
[r2
]);
5276 generate_trap(ctx
, TRAPC_INSN_ERR
, TIN2_IOPC
);
5278 tcg_temp_free(temp
);
5279 tcg_temp_free(temp2
);
5282 static void decode_bo_addrmode_ldmst_bitreverse_circular(CPUTriCoreState
*env
,
5289 TCGv temp
, temp2
, temp3
;
5291 r1
= MASK_OP_BO_S1D(ctx
->opcode
);
5292 r2
= MASK_OP_BO_S2(ctx
->opcode
);
5293 off10
= MASK_OP_BO_OFF10_SEXT(ctx
->opcode
);
5294 op2
= MASK_OP_BO_OP2(ctx
->opcode
);
5296 temp
= tcg_temp_new();
5297 temp2
= tcg_temp_new();
5298 temp3
= tcg_const_i32(off10
);
5300 tcg_gen_ext16u_tl(temp
, cpu_gpr_a
[r2
+1]);
5301 tcg_gen_add_tl(temp2
, cpu_gpr_a
[r2
], temp
);
5304 case OPC2_32_BO_LDMST_BR
:
5305 gen_ldmst(ctx
, r1
, temp2
);
5306 gen_helper_br_update(cpu_gpr_a
[r2
+1], cpu_gpr_a
[r2
+1]);
5308 case OPC2_32_BO_LDMST_CIRC
:
5309 gen_ldmst(ctx
, r1
, temp2
);
5310 gen_helper_circ_update(cpu_gpr_a
[r2
+1], cpu_gpr_a
[r2
+1], temp3
);
5312 case OPC2_32_BO_SWAP_W_BR
:
5313 gen_swap(ctx
, r1
, temp2
);
5314 gen_helper_br_update(cpu_gpr_a
[r2
+1], cpu_gpr_a
[r2
+1]);
5316 case OPC2_32_BO_SWAP_W_CIRC
:
5317 gen_swap(ctx
, r1
, temp2
);
5318 gen_helper_circ_update(cpu_gpr_a
[r2
+1], cpu_gpr_a
[r2
+1], temp3
);
5320 case OPC2_32_BO_CMPSWAP_W_BR
:
5321 gen_cmpswap(ctx
, r1
, temp2
);
5322 gen_helper_br_update(cpu_gpr_a
[r2
+1], cpu_gpr_a
[r2
+1]);
5324 case OPC2_32_BO_CMPSWAP_W_CIRC
:
5325 gen_cmpswap(ctx
, r1
, temp2
);
5326 gen_helper_circ_update(cpu_gpr_a
[r2
+1], cpu_gpr_a
[r2
+1], temp3
);
5328 case OPC2_32_BO_SWAPMSK_W_BR
:
5329 gen_swapmsk(ctx
, r1
, temp2
);
5330 gen_helper_br_update(cpu_gpr_a
[r2
+1], cpu_gpr_a
[r2
+1]);
5332 case OPC2_32_BO_SWAPMSK_W_CIRC
:
5333 gen_swapmsk(ctx
, r1
, temp2
);
5334 gen_helper_circ_update(cpu_gpr_a
[r2
+1], cpu_gpr_a
[r2
+1], temp3
);
5337 generate_trap(ctx
, TRAPC_INSN_ERR
, TIN2_IOPC
);
5340 tcg_temp_free(temp
);
5341 tcg_temp_free(temp2
);
5342 tcg_temp_free(temp3
);
5345 static void decode_bol_opc(CPUTriCoreState
*env
, DisasContext
*ctx
, int32_t op1
)
5351 r1
= MASK_OP_BOL_S1D(ctx
->opcode
);
5352 r2
= MASK_OP_BOL_S2(ctx
->opcode
);
5353 address
= MASK_OP_BOL_OFF16_SEXT(ctx
->opcode
);
5356 case OPC1_32_BOL_LD_A_LONGOFF
:
5357 temp
= tcg_temp_new();
5358 tcg_gen_addi_tl(temp
, cpu_gpr_a
[r2
], address
);
5359 tcg_gen_qemu_ld_tl(cpu_gpr_a
[r1
], temp
, ctx
->mem_idx
, MO_LEUL
);
5360 tcg_temp_free(temp
);
5362 case OPC1_32_BOL_LD_W_LONGOFF
:
5363 temp
= tcg_temp_new();
5364 tcg_gen_addi_tl(temp
, cpu_gpr_a
[r2
], address
);
5365 tcg_gen_qemu_ld_tl(cpu_gpr_d
[r1
], temp
, ctx
->mem_idx
, MO_LEUL
);
5366 tcg_temp_free(temp
);
5368 case OPC1_32_BOL_LEA_LONGOFF
:
5369 tcg_gen_addi_tl(cpu_gpr_a
[r1
], cpu_gpr_a
[r2
], address
);
5371 case OPC1_32_BOL_ST_A_LONGOFF
:
5372 if (tricore_feature(env
, TRICORE_FEATURE_16
)) {
5373 gen_offset_st(ctx
, cpu_gpr_a
[r1
], cpu_gpr_a
[r2
], address
, MO_LEUL
);
5375 generate_trap(ctx
, TRAPC_INSN_ERR
, TIN2_IOPC
);
5378 case OPC1_32_BOL_ST_W_LONGOFF
:
5379 gen_offset_st(ctx
, cpu_gpr_d
[r1
], cpu_gpr_a
[r2
], address
, MO_LEUL
);
5381 case OPC1_32_BOL_LD_B_LONGOFF
:
5382 if (tricore_feature(env
, TRICORE_FEATURE_16
)) {
5383 gen_offset_ld(ctx
, cpu_gpr_d
[r1
], cpu_gpr_a
[r2
], address
, MO_SB
);
5385 generate_trap(ctx
, TRAPC_INSN_ERR
, TIN2_IOPC
);
5388 case OPC1_32_BOL_LD_BU_LONGOFF
:
5389 if (tricore_feature(env
, TRICORE_FEATURE_16
)) {
5390 gen_offset_ld(ctx
, cpu_gpr_d
[r1
], cpu_gpr_a
[r2
], address
, MO_UB
);
5392 generate_trap(ctx
, TRAPC_INSN_ERR
, TIN2_IOPC
);
5395 case OPC1_32_BOL_LD_H_LONGOFF
:
5396 if (tricore_feature(env
, TRICORE_FEATURE_16
)) {
5397 gen_offset_ld(ctx
, cpu_gpr_d
[r1
], cpu_gpr_a
[r2
], address
, MO_LESW
);
5399 generate_trap(ctx
, TRAPC_INSN_ERR
, TIN2_IOPC
);
5402 case OPC1_32_BOL_LD_HU_LONGOFF
:
5403 if (tricore_feature(env
, TRICORE_FEATURE_16
)) {
5404 gen_offset_ld(ctx
, cpu_gpr_d
[r1
], cpu_gpr_a
[r2
], address
, MO_LEUW
);
5406 generate_trap(ctx
, TRAPC_INSN_ERR
, TIN2_IOPC
);
5409 case OPC1_32_BOL_ST_B_LONGOFF
:
5410 if (tricore_feature(env
, TRICORE_FEATURE_16
)) {
5411 gen_offset_st(ctx
, cpu_gpr_d
[r1
], cpu_gpr_a
[r2
], address
, MO_SB
);
5413 generate_trap(ctx
, TRAPC_INSN_ERR
, TIN2_IOPC
);
5416 case OPC1_32_BOL_ST_H_LONGOFF
:
5417 if (tricore_feature(env
, TRICORE_FEATURE_16
)) {
5418 gen_offset_st(ctx
, cpu_gpr_d
[r1
], cpu_gpr_a
[r2
], address
, MO_LESW
);
5420 generate_trap(ctx
, TRAPC_INSN_ERR
, TIN2_IOPC
);
5424 generate_trap(ctx
, TRAPC_INSN_ERR
, TIN2_IOPC
);
5429 static void decode_rc_logical_shift(CPUTriCoreState
*env
, DisasContext
*ctx
)
5436 r2
= MASK_OP_RC_D(ctx
->opcode
);
5437 r1
= MASK_OP_RC_S1(ctx
->opcode
);
5438 const9
= MASK_OP_RC_CONST9(ctx
->opcode
);
5439 op2
= MASK_OP_RC_OP2(ctx
->opcode
);
5441 temp
= tcg_temp_new();
5444 case OPC2_32_RC_AND
:
5445 tcg_gen_andi_tl(cpu_gpr_d
[r2
], cpu_gpr_d
[r1
], const9
);
5447 case OPC2_32_RC_ANDN
:
5448 tcg_gen_andi_tl(cpu_gpr_d
[r2
], cpu_gpr_d
[r1
], ~const9
);
5450 case OPC2_32_RC_NAND
:
5451 tcg_gen_movi_tl(temp
, const9
);
5452 tcg_gen_nand_tl(cpu_gpr_d
[r2
], cpu_gpr_d
[r1
], temp
);
5454 case OPC2_32_RC_NOR
:
5455 tcg_gen_movi_tl(temp
, const9
);
5456 tcg_gen_nor_tl(cpu_gpr_d
[r2
], cpu_gpr_d
[r1
], temp
);
5459 tcg_gen_ori_tl(cpu_gpr_d
[r2
], cpu_gpr_d
[r1
], const9
);
5461 case OPC2_32_RC_ORN
:
5462 tcg_gen_ori_tl(cpu_gpr_d
[r2
], cpu_gpr_d
[r1
], ~const9
);
5465 const9
= sextract32(const9
, 0, 6);
5466 gen_shi(cpu_gpr_d
[r2
], cpu_gpr_d
[r1
], const9
);
5468 case OPC2_32_RC_SH_H
:
5469 const9
= sextract32(const9
, 0, 5);
5470 gen_sh_hi(cpu_gpr_d
[r2
], cpu_gpr_d
[r1
], const9
);
5472 case OPC2_32_RC_SHA
:
5473 const9
= sextract32(const9
, 0, 6);
5474 gen_shaci(cpu_gpr_d
[r2
], cpu_gpr_d
[r1
], const9
);
5476 case OPC2_32_RC_SHA_H
:
5477 const9
= sextract32(const9
, 0, 5);
5478 gen_sha_hi(cpu_gpr_d
[r2
], cpu_gpr_d
[r1
], const9
);
5480 case OPC2_32_RC_SHAS
:
5481 gen_shasi(cpu_gpr_d
[r2
], cpu_gpr_d
[r1
], const9
);
5483 case OPC2_32_RC_XNOR
:
5484 tcg_gen_xori_tl(cpu_gpr_d
[r2
], cpu_gpr_d
[r1
], const9
);
5485 tcg_gen_not_tl(cpu_gpr_d
[r2
], cpu_gpr_d
[r2
]);
5487 case OPC2_32_RC_XOR
:
5488 tcg_gen_xori_tl(cpu_gpr_d
[r2
], cpu_gpr_d
[r1
], const9
);
5491 generate_trap(ctx
, TRAPC_INSN_ERR
, TIN2_IOPC
);
5493 tcg_temp_free(temp
);
5496 static void decode_rc_accumulator(CPUTriCoreState
*env
, DisasContext
*ctx
)
5504 r2
= MASK_OP_RC_D(ctx
->opcode
);
5505 r1
= MASK_OP_RC_S1(ctx
->opcode
);
5506 const9
= MASK_OP_RC_CONST9_SEXT(ctx
->opcode
);
5508 op2
= MASK_OP_RC_OP2(ctx
->opcode
);
5510 temp
= tcg_temp_new();
5513 case OPC2_32_RC_ABSDIF
:
5514 gen_absdifi(cpu_gpr_d
[r2
], cpu_gpr_d
[r1
], const9
);
5516 case OPC2_32_RC_ABSDIFS
:
5517 gen_absdifsi(cpu_gpr_d
[r2
], cpu_gpr_d
[r1
], const9
);
5519 case OPC2_32_RC_ADD
:
5520 gen_addi_d(cpu_gpr_d
[r2
], cpu_gpr_d
[r1
], const9
);
5522 case OPC2_32_RC_ADDC
:
5523 gen_addci_CC(cpu_gpr_d
[r2
], cpu_gpr_d
[r1
], const9
);
5525 case OPC2_32_RC_ADDS
:
5526 gen_addsi(cpu_gpr_d
[r2
], cpu_gpr_d
[r1
], const9
);
5528 case OPC2_32_RC_ADDS_U
:
5529 gen_addsui(cpu_gpr_d
[r2
], cpu_gpr_d
[r1
], const9
);
5531 case OPC2_32_RC_ADDX
:
5532 gen_addi_CC(cpu_gpr_d
[r2
], cpu_gpr_d
[r1
], const9
);
5534 case OPC2_32_RC_AND_EQ
:
5535 gen_accumulating_condi(TCG_COND_EQ
, cpu_gpr_d
[r2
], cpu_gpr_d
[r1
],
5536 const9
, &tcg_gen_and_tl
);
5538 case OPC2_32_RC_AND_GE
:
5539 gen_accumulating_condi(TCG_COND_GE
, cpu_gpr_d
[r2
], cpu_gpr_d
[r1
],
5540 const9
, &tcg_gen_and_tl
);
5542 case OPC2_32_RC_AND_GE_U
:
5543 const9
= MASK_OP_RC_CONST9(ctx
->opcode
);
5544 gen_accumulating_condi(TCG_COND_GEU
, cpu_gpr_d
[r2
], cpu_gpr_d
[r1
],
5545 const9
, &tcg_gen_and_tl
);
5547 case OPC2_32_RC_AND_LT
:
5548 gen_accumulating_condi(TCG_COND_LT
, cpu_gpr_d
[r2
], cpu_gpr_d
[r1
],
5549 const9
, &tcg_gen_and_tl
);
5551 case OPC2_32_RC_AND_LT_U
:
5552 const9
= MASK_OP_RC_CONST9(ctx
->opcode
);
5553 gen_accumulating_condi(TCG_COND_LTU
, cpu_gpr_d
[r2
], cpu_gpr_d
[r1
],
5554 const9
, &tcg_gen_and_tl
);
5556 case OPC2_32_RC_AND_NE
:
5557 gen_accumulating_condi(TCG_COND_NE
, cpu_gpr_d
[r2
], cpu_gpr_d
[r1
],
5558 const9
, &tcg_gen_and_tl
);
5561 tcg_gen_setcondi_tl(TCG_COND_EQ
, cpu_gpr_d
[r2
], cpu_gpr_d
[r1
], const9
);
5563 case OPC2_32_RC_EQANY_B
:
5564 gen_eqany_bi(cpu_gpr_d
[r2
], cpu_gpr_d
[r1
], const9
);
5566 case OPC2_32_RC_EQANY_H
:
5567 gen_eqany_hi(cpu_gpr_d
[r2
], cpu_gpr_d
[r1
], const9
);
5570 tcg_gen_setcondi_tl(TCG_COND_GE
, cpu_gpr_d
[r2
], cpu_gpr_d
[r1
], const9
);
5572 case OPC2_32_RC_GE_U
:
5573 const9
= MASK_OP_RC_CONST9(ctx
->opcode
);
5574 tcg_gen_setcondi_tl(TCG_COND_GEU
, cpu_gpr_d
[r2
], cpu_gpr_d
[r1
], const9
);
5577 tcg_gen_setcondi_tl(TCG_COND_LT
, cpu_gpr_d
[r2
], cpu_gpr_d
[r1
], const9
);
5579 case OPC2_32_RC_LT_U
:
5580 const9
= MASK_OP_RC_CONST9(ctx
->opcode
);
5581 tcg_gen_setcondi_tl(TCG_COND_LTU
, cpu_gpr_d
[r2
], cpu_gpr_d
[r1
], const9
);
5583 case OPC2_32_RC_MAX
:
5584 tcg_gen_movi_tl(temp
, const9
);
5585 tcg_gen_movcond_tl(TCG_COND_GT
, cpu_gpr_d
[r2
], cpu_gpr_d
[r1
], temp
,
5586 cpu_gpr_d
[r1
], temp
);
5588 case OPC2_32_RC_MAX_U
:
5589 tcg_gen_movi_tl(temp
, MASK_OP_RC_CONST9(ctx
->opcode
));
5590 tcg_gen_movcond_tl(TCG_COND_GTU
, cpu_gpr_d
[r2
], cpu_gpr_d
[r1
], temp
,
5591 cpu_gpr_d
[r1
], temp
);
5593 case OPC2_32_RC_MIN
:
5594 tcg_gen_movi_tl(temp
, const9
);
5595 tcg_gen_movcond_tl(TCG_COND_LT
, cpu_gpr_d
[r2
], cpu_gpr_d
[r1
], temp
,
5596 cpu_gpr_d
[r1
], temp
);
5598 case OPC2_32_RC_MIN_U
:
5599 tcg_gen_movi_tl(temp
, MASK_OP_RC_CONST9(ctx
->opcode
));
5600 tcg_gen_movcond_tl(TCG_COND_LTU
, cpu_gpr_d
[r2
], cpu_gpr_d
[r1
], temp
,
5601 cpu_gpr_d
[r1
], temp
);
5604 tcg_gen_setcondi_tl(TCG_COND_NE
, cpu_gpr_d
[r2
], cpu_gpr_d
[r1
], const9
);
5606 case OPC2_32_RC_OR_EQ
:
5607 gen_accumulating_condi(TCG_COND_EQ
, cpu_gpr_d
[r2
], cpu_gpr_d
[r1
],
5608 const9
, &tcg_gen_or_tl
);
5610 case OPC2_32_RC_OR_GE
:
5611 gen_accumulating_condi(TCG_COND_GE
, cpu_gpr_d
[r2
], cpu_gpr_d
[r1
],
5612 const9
, &tcg_gen_or_tl
);
5614 case OPC2_32_RC_OR_GE_U
:
5615 const9
= MASK_OP_RC_CONST9(ctx
->opcode
);
5616 gen_accumulating_condi(TCG_COND_GEU
, cpu_gpr_d
[r2
], cpu_gpr_d
[r1
],
5617 const9
, &tcg_gen_or_tl
);
5619 case OPC2_32_RC_OR_LT
:
5620 gen_accumulating_condi(TCG_COND_LT
, cpu_gpr_d
[r2
], cpu_gpr_d
[r1
],
5621 const9
, &tcg_gen_or_tl
);
5623 case OPC2_32_RC_OR_LT_U
:
5624 const9
= MASK_OP_RC_CONST9(ctx
->opcode
);
5625 gen_accumulating_condi(TCG_COND_LTU
, cpu_gpr_d
[r2
], cpu_gpr_d
[r1
],
5626 const9
, &tcg_gen_or_tl
);
5628 case OPC2_32_RC_OR_NE
:
5629 gen_accumulating_condi(TCG_COND_NE
, cpu_gpr_d
[r2
], cpu_gpr_d
[r1
],
5630 const9
, &tcg_gen_or_tl
);
5632 case OPC2_32_RC_RSUB
:
5633 tcg_gen_movi_tl(temp
, const9
);
5634 gen_sub_d(cpu_gpr_d
[r2
], temp
, cpu_gpr_d
[r1
]);
5636 case OPC2_32_RC_RSUBS
:
5637 tcg_gen_movi_tl(temp
, const9
);
5638 gen_subs(cpu_gpr_d
[r2
], temp
, cpu_gpr_d
[r1
]);
5640 case OPC2_32_RC_RSUBS_U
:
5641 tcg_gen_movi_tl(temp
, const9
);
5642 gen_subsu(cpu_gpr_d
[r2
], temp
, cpu_gpr_d
[r1
]);
5644 case OPC2_32_RC_SH_EQ
:
5645 gen_sh_condi(TCG_COND_EQ
, cpu_gpr_d
[r2
], cpu_gpr_d
[r1
], const9
);
5647 case OPC2_32_RC_SH_GE
:
5648 gen_sh_condi(TCG_COND_GE
, cpu_gpr_d
[r2
], cpu_gpr_d
[r1
], const9
);
5650 case OPC2_32_RC_SH_GE_U
:
5651 const9
= MASK_OP_RC_CONST9(ctx
->opcode
);
5652 gen_sh_condi(TCG_COND_GEU
, cpu_gpr_d
[r2
], cpu_gpr_d
[r1
], const9
);
5654 case OPC2_32_RC_SH_LT
:
5655 gen_sh_condi(TCG_COND_LT
, cpu_gpr_d
[r2
], cpu_gpr_d
[r1
], const9
);
5657 case OPC2_32_RC_SH_LT_U
:
5658 const9
= MASK_OP_RC_CONST9(ctx
->opcode
);
5659 gen_sh_condi(TCG_COND_LTU
, cpu_gpr_d
[r2
], cpu_gpr_d
[r1
], const9
);
5661 case OPC2_32_RC_SH_NE
:
5662 gen_sh_condi(TCG_COND_NE
, cpu_gpr_d
[r2
], cpu_gpr_d
[r1
], const9
);
5664 case OPC2_32_RC_XOR_EQ
:
5665 gen_accumulating_condi(TCG_COND_EQ
, cpu_gpr_d
[r2
], cpu_gpr_d
[r1
],
5666 const9
, &tcg_gen_xor_tl
);
5668 case OPC2_32_RC_XOR_GE
:
5669 gen_accumulating_condi(TCG_COND_GE
, cpu_gpr_d
[r2
], cpu_gpr_d
[r1
],
5670 const9
, &tcg_gen_xor_tl
);
5672 case OPC2_32_RC_XOR_GE_U
:
5673 const9
= MASK_OP_RC_CONST9(ctx
->opcode
);
5674 gen_accumulating_condi(TCG_COND_GEU
, cpu_gpr_d
[r2
], cpu_gpr_d
[r1
],
5675 const9
, &tcg_gen_xor_tl
);
5677 case OPC2_32_RC_XOR_LT
:
5678 gen_accumulating_condi(TCG_COND_LT
, cpu_gpr_d
[r2
], cpu_gpr_d
[r1
],
5679 const9
, &tcg_gen_xor_tl
);
5681 case OPC2_32_RC_XOR_LT_U
:
5682 const9
= MASK_OP_RC_CONST9(ctx
->opcode
);
5683 gen_accumulating_condi(TCG_COND_LTU
, cpu_gpr_d
[r2
], cpu_gpr_d
[r1
],
5684 const9
, &tcg_gen_xor_tl
);
5686 case OPC2_32_RC_XOR_NE
:
5687 gen_accumulating_condi(TCG_COND_NE
, cpu_gpr_d
[r2
], cpu_gpr_d
[r1
],
5688 const9
, &tcg_gen_xor_tl
);
5691 generate_trap(ctx
, TRAPC_INSN_ERR
, TIN2_IOPC
);
5693 tcg_temp_free(temp
);
5696 static void decode_rc_serviceroutine(CPUTriCoreState
*env
, DisasContext
*ctx
)
5701 op2
= MASK_OP_RC_OP2(ctx
->opcode
);
5702 const9
= MASK_OP_RC_CONST9(ctx
->opcode
);
5705 case OPC2_32_RC_BISR
:
5706 gen_helper_1arg(bisr
, const9
);
5708 case OPC2_32_RC_SYSCALL
:
5709 /* TODO: Add exception generation */
5712 generate_trap(ctx
, TRAPC_INSN_ERR
, TIN2_IOPC
);
5716 static void decode_rc_mul(CPUTriCoreState
*env
, DisasContext
*ctx
)
5722 r2
= MASK_OP_RC_D(ctx
->opcode
);
5723 r1
= MASK_OP_RC_S1(ctx
->opcode
);
5724 const9
= MASK_OP_RC_CONST9_SEXT(ctx
->opcode
);
5726 op2
= MASK_OP_RC_OP2(ctx
->opcode
);
5729 case OPC2_32_RC_MUL_32
:
5730 gen_muli_i32s(cpu_gpr_d
[r2
], cpu_gpr_d
[r1
], const9
);
5732 case OPC2_32_RC_MUL_64
:
5734 gen_muli_i64s(cpu_gpr_d
[r2
], cpu_gpr_d
[r2
+1], cpu_gpr_d
[r1
], const9
);
5736 case OPC2_32_RC_MULS_32
:
5737 gen_mulsi_i32(cpu_gpr_d
[r2
], cpu_gpr_d
[r1
], const9
);
5739 case OPC2_32_RC_MUL_U_64
:
5740 const9
= MASK_OP_RC_CONST9(ctx
->opcode
);
5742 gen_muli_i64u(cpu_gpr_d
[r2
], cpu_gpr_d
[r2
+1], cpu_gpr_d
[r1
], const9
);
5744 case OPC2_32_RC_MULS_U_32
:
5745 const9
= MASK_OP_RC_CONST9(ctx
->opcode
);
5746 gen_mulsui_i32(cpu_gpr_d
[r2
], cpu_gpr_d
[r1
], const9
);
5749 generate_trap(ctx
, TRAPC_INSN_ERR
, TIN2_IOPC
);
5754 static void decode_rcpw_insert(CPUTriCoreState
*env
, DisasContext
*ctx
)
5758 int32_t pos
, width
, const4
;
5762 op2
= MASK_OP_RCPW_OP2(ctx
->opcode
);
5763 r1
= MASK_OP_RCPW_S1(ctx
->opcode
);
5764 r2
= MASK_OP_RCPW_D(ctx
->opcode
);
5765 const4
= MASK_OP_RCPW_CONST4(ctx
->opcode
);
5766 width
= MASK_OP_RCPW_WIDTH(ctx
->opcode
);
5767 pos
= MASK_OP_RCPW_POS(ctx
->opcode
);
5770 case OPC2_32_RCPW_IMASK
:
5772 /* if pos + width > 31 undefined result */
5773 if (pos
+ width
<= 31) {
5774 tcg_gen_movi_tl(cpu_gpr_d
[r2
+1], ((1u << width
) - 1) << pos
);
5775 tcg_gen_movi_tl(cpu_gpr_d
[r2
], (const4
<< pos
));
5778 case OPC2_32_RCPW_INSERT
:
5779 /* if pos + width > 32 undefined result */
5780 if (pos
+ width
<= 32) {
5781 temp
= tcg_const_i32(const4
);
5782 tcg_gen_deposit_tl(cpu_gpr_d
[r2
], cpu_gpr_d
[r1
], temp
, pos
, width
);
5783 tcg_temp_free(temp
);
5787 generate_trap(ctx
, TRAPC_INSN_ERR
, TIN2_IOPC
);
5793 static void decode_rcrw_insert(CPUTriCoreState
*env
, DisasContext
*ctx
)
5797 int32_t width
, const4
;
5799 TCGv temp
, temp2
, temp3
;
5801 op2
= MASK_OP_RCRW_OP2(ctx
->opcode
);
5802 r1
= MASK_OP_RCRW_S1(ctx
->opcode
);
5803 r3
= MASK_OP_RCRW_S3(ctx
->opcode
);
5804 r4
= MASK_OP_RCRW_D(ctx
->opcode
);
5805 width
= MASK_OP_RCRW_WIDTH(ctx
->opcode
);
5806 const4
= MASK_OP_RCRW_CONST4(ctx
->opcode
);
5808 temp
= tcg_temp_new();
5809 temp2
= tcg_temp_new();
5812 case OPC2_32_RCRW_IMASK
:
5813 tcg_gen_andi_tl(temp
, cpu_gpr_d
[r4
], 0x1f);
5814 tcg_gen_movi_tl(temp2
, (1 << width
) - 1);
5815 tcg_gen_shl_tl(cpu_gpr_d
[r3
+ 1], temp2
, temp
);
5816 tcg_gen_movi_tl(temp2
, const4
);
5817 tcg_gen_shl_tl(cpu_gpr_d
[r3
], temp2
, temp
);
5819 case OPC2_32_RCRW_INSERT
:
5820 temp3
= tcg_temp_new();
5822 tcg_gen_movi_tl(temp
, width
);
5823 tcg_gen_movi_tl(temp2
, const4
);
5824 tcg_gen_andi_tl(temp3
, cpu_gpr_d
[r4
], 0x1f);
5825 gen_insert(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], temp2
, temp
, temp3
);
5827 tcg_temp_free(temp3
);
5830 generate_trap(ctx
, TRAPC_INSN_ERR
, TIN2_IOPC
);
5832 tcg_temp_free(temp
);
5833 tcg_temp_free(temp2
);
5838 static void decode_rcr_cond_select(CPUTriCoreState
*env
, DisasContext
*ctx
)
5846 op2
= MASK_OP_RCR_OP2(ctx
->opcode
);
5847 r1
= MASK_OP_RCR_S1(ctx
->opcode
);
5848 const9
= MASK_OP_RCR_CONST9_SEXT(ctx
->opcode
);
5849 r3
= MASK_OP_RCR_S3(ctx
->opcode
);
5850 r4
= MASK_OP_RCR_D(ctx
->opcode
);
5853 case OPC2_32_RCR_CADD
:
5854 gen_condi_add(TCG_COND_NE
, cpu_gpr_d
[r1
], const9
, cpu_gpr_d
[r3
],
5857 case OPC2_32_RCR_CADDN
:
5858 gen_condi_add(TCG_COND_EQ
, cpu_gpr_d
[r1
], const9
, cpu_gpr_d
[r3
],
5861 case OPC2_32_RCR_SEL
:
5862 temp
= tcg_const_i32(0);
5863 temp2
= tcg_const_i32(const9
);
5864 tcg_gen_movcond_tl(TCG_COND_NE
, cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], temp
,
5865 cpu_gpr_d
[r1
], temp2
);
5866 tcg_temp_free(temp
);
5867 tcg_temp_free(temp2
);
5869 case OPC2_32_RCR_SELN
:
5870 temp
= tcg_const_i32(0);
5871 temp2
= tcg_const_i32(const9
);
5872 tcg_gen_movcond_tl(TCG_COND_EQ
, cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], temp
,
5873 cpu_gpr_d
[r1
], temp2
);
5874 tcg_temp_free(temp
);
5875 tcg_temp_free(temp2
);
5878 generate_trap(ctx
, TRAPC_INSN_ERR
, TIN2_IOPC
);
5882 static void decode_rcr_madd(CPUTriCoreState
*env
, DisasContext
*ctx
)
5889 op2
= MASK_OP_RCR_OP2(ctx
->opcode
);
5890 r1
= MASK_OP_RCR_S1(ctx
->opcode
);
5891 const9
= MASK_OP_RCR_CONST9_SEXT(ctx
->opcode
);
5892 r3
= MASK_OP_RCR_S3(ctx
->opcode
);
5893 r4
= MASK_OP_RCR_D(ctx
->opcode
);
5896 case OPC2_32_RCR_MADD_32
:
5897 gen_maddi32_d(cpu_gpr_d
[r4
], cpu_gpr_d
[r1
], cpu_gpr_d
[r3
], const9
);
5899 case OPC2_32_RCR_MADD_64
:
5902 gen_maddi64_d(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r1
],
5903 cpu_gpr_d
[r3
], cpu_gpr_d
[r3
+1], const9
);
5905 case OPC2_32_RCR_MADDS_32
:
5906 gen_maddsi_32(cpu_gpr_d
[r4
], cpu_gpr_d
[r1
], cpu_gpr_d
[r3
], const9
);
5908 case OPC2_32_RCR_MADDS_64
:
5911 gen_maddsi_64(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r1
],
5912 cpu_gpr_d
[r3
], cpu_gpr_d
[r3
+1], const9
);
5914 case OPC2_32_RCR_MADD_U_64
:
5917 const9
= MASK_OP_RCR_CONST9(ctx
->opcode
);
5918 gen_maddui64_d(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r1
],
5919 cpu_gpr_d
[r3
], cpu_gpr_d
[r3
+1], const9
);
5921 case OPC2_32_RCR_MADDS_U_32
:
5922 const9
= MASK_OP_RCR_CONST9(ctx
->opcode
);
5923 gen_maddsui_32(cpu_gpr_d
[r4
], cpu_gpr_d
[r1
], cpu_gpr_d
[r3
], const9
);
5925 case OPC2_32_RCR_MADDS_U_64
:
5928 const9
= MASK_OP_RCR_CONST9(ctx
->opcode
);
5929 gen_maddsui_64(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r1
],
5930 cpu_gpr_d
[r3
], cpu_gpr_d
[r3
+1], const9
);
5933 generate_trap(ctx
, TRAPC_INSN_ERR
, TIN2_IOPC
);
5937 static void decode_rcr_msub(CPUTriCoreState
*env
, DisasContext
*ctx
)
5944 op2
= MASK_OP_RCR_OP2(ctx
->opcode
);
5945 r1
= MASK_OP_RCR_S1(ctx
->opcode
);
5946 const9
= MASK_OP_RCR_CONST9_SEXT(ctx
->opcode
);
5947 r3
= MASK_OP_RCR_S3(ctx
->opcode
);
5948 r4
= MASK_OP_RCR_D(ctx
->opcode
);
5951 case OPC2_32_RCR_MSUB_32
:
5952 gen_msubi32_d(cpu_gpr_d
[r4
], cpu_gpr_d
[r1
], cpu_gpr_d
[r3
], const9
);
5954 case OPC2_32_RCR_MSUB_64
:
5957 gen_msubi64_d(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r1
],
5958 cpu_gpr_d
[r3
], cpu_gpr_d
[r3
+1], const9
);
5960 case OPC2_32_RCR_MSUBS_32
:
5961 gen_msubsi_32(cpu_gpr_d
[r4
], cpu_gpr_d
[r1
], cpu_gpr_d
[r3
], const9
);
5963 case OPC2_32_RCR_MSUBS_64
:
5966 gen_msubsi_64(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r1
],
5967 cpu_gpr_d
[r3
], cpu_gpr_d
[r3
+1], const9
);
5969 case OPC2_32_RCR_MSUB_U_64
:
5972 const9
= MASK_OP_RCR_CONST9(ctx
->opcode
);
5973 gen_msubui64_d(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r1
],
5974 cpu_gpr_d
[r3
], cpu_gpr_d
[r3
+1], const9
);
5976 case OPC2_32_RCR_MSUBS_U_32
:
5977 const9
= MASK_OP_RCR_CONST9(ctx
->opcode
);
5978 gen_msubsui_32(cpu_gpr_d
[r4
], cpu_gpr_d
[r1
], cpu_gpr_d
[r3
], const9
);
5980 case OPC2_32_RCR_MSUBS_U_64
:
5983 const9
= MASK_OP_RCR_CONST9(ctx
->opcode
);
5984 gen_msubsui_64(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r1
],
5985 cpu_gpr_d
[r3
], cpu_gpr_d
[r3
+1], const9
);
5988 generate_trap(ctx
, TRAPC_INSN_ERR
, TIN2_IOPC
);
5994 static void decode_rlc_opc(CPUTriCoreState
*env
, DisasContext
*ctx
,
6000 const16
= MASK_OP_RLC_CONST16_SEXT(ctx
->opcode
);
6001 r1
= MASK_OP_RLC_S1(ctx
->opcode
);
6002 r2
= MASK_OP_RLC_D(ctx
->opcode
);
6005 case OPC1_32_RLC_ADDI
:
6006 gen_addi_d(cpu_gpr_d
[r2
], cpu_gpr_d
[r1
], const16
);
6008 case OPC1_32_RLC_ADDIH
:
6009 gen_addi_d(cpu_gpr_d
[r2
], cpu_gpr_d
[r1
], const16
<< 16);
6011 case OPC1_32_RLC_ADDIH_A
:
6012 tcg_gen_addi_tl(cpu_gpr_a
[r2
], cpu_gpr_a
[r1
], const16
<< 16);
6014 case OPC1_32_RLC_MFCR
:
6015 const16
= MASK_OP_RLC_CONST16(ctx
->opcode
);
6016 gen_mfcr(env
, cpu_gpr_d
[r2
], const16
);
6018 case OPC1_32_RLC_MOV
:
6019 tcg_gen_movi_tl(cpu_gpr_d
[r2
], const16
);
6021 case OPC1_32_RLC_MOV_64
:
6022 if (tricore_feature(env
, TRICORE_FEATURE_16
)) {
6024 tcg_gen_movi_tl(cpu_gpr_d
[r2
], const16
);
6025 tcg_gen_movi_tl(cpu_gpr_d
[r2
+1], const16
>> 15);
6027 generate_trap(ctx
, TRAPC_INSN_ERR
, TIN2_IOPC
);
6030 case OPC1_32_RLC_MOV_U
:
6031 const16
= MASK_OP_RLC_CONST16(ctx
->opcode
);
6032 tcg_gen_movi_tl(cpu_gpr_d
[r2
], const16
);
6034 case OPC1_32_RLC_MOV_H
:
6035 tcg_gen_movi_tl(cpu_gpr_d
[r2
], const16
<< 16);
6037 case OPC1_32_RLC_MOVH_A
:
6038 tcg_gen_movi_tl(cpu_gpr_a
[r2
], const16
<< 16);
6040 case OPC1_32_RLC_MTCR
:
6041 const16
= MASK_OP_RLC_CONST16(ctx
->opcode
);
6042 gen_mtcr(env
, ctx
, cpu_gpr_d
[r1
], const16
);
6045 generate_trap(ctx
, TRAPC_INSN_ERR
, TIN2_IOPC
);
6050 static void decode_rr_accumulator(CPUTriCoreState
*env
, DisasContext
*ctx
)
6057 r3
= MASK_OP_RR_D(ctx
->opcode
);
6058 r2
= MASK_OP_RR_S2(ctx
->opcode
);
6059 r1
= MASK_OP_RR_S1(ctx
->opcode
);
6060 op2
= MASK_OP_RR_OP2(ctx
->opcode
);
6063 case OPC2_32_RR_ABS
:
6064 gen_abs(cpu_gpr_d
[r3
], cpu_gpr_d
[r2
]);
6066 case OPC2_32_RR_ABS_B
:
6067 gen_helper_abs_b(cpu_gpr_d
[r3
], cpu_env
, cpu_gpr_d
[r2
]);
6069 case OPC2_32_RR_ABS_H
:
6070 gen_helper_abs_h(cpu_gpr_d
[r3
], cpu_env
, cpu_gpr_d
[r2
]);
6072 case OPC2_32_RR_ABSDIF
:
6073 gen_absdif(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
6075 case OPC2_32_RR_ABSDIF_B
:
6076 gen_helper_absdif_b(cpu_gpr_d
[r3
], cpu_env
, cpu_gpr_d
[r1
],
6079 case OPC2_32_RR_ABSDIF_H
:
6080 gen_helper_absdif_h(cpu_gpr_d
[r3
], cpu_env
, cpu_gpr_d
[r1
],
6083 case OPC2_32_RR_ABSDIFS
:
6084 gen_helper_absdif_ssov(cpu_gpr_d
[r3
], cpu_env
, cpu_gpr_d
[r1
],
6087 case OPC2_32_RR_ABSDIFS_H
:
6088 gen_helper_absdif_h_ssov(cpu_gpr_d
[r3
], cpu_env
, cpu_gpr_d
[r1
],
6091 case OPC2_32_RR_ABSS
:
6092 gen_helper_abs_ssov(cpu_gpr_d
[r3
], cpu_env
, cpu_gpr_d
[r2
]);
6094 case OPC2_32_RR_ABSS_H
:
6095 gen_helper_abs_h_ssov(cpu_gpr_d
[r3
], cpu_env
, cpu_gpr_d
[r2
]);
6097 case OPC2_32_RR_ADD
:
6098 gen_add_d(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
6100 case OPC2_32_RR_ADD_B
:
6101 gen_helper_add_b(cpu_gpr_d
[r3
], cpu_env
, cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
6103 case OPC2_32_RR_ADD_H
:
6104 gen_helper_add_h(cpu_gpr_d
[r3
], cpu_env
, cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
6106 case OPC2_32_RR_ADDC
:
6107 gen_addc_CC(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
6109 case OPC2_32_RR_ADDS
:
6110 gen_adds(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
6112 case OPC2_32_RR_ADDS_H
:
6113 gen_helper_add_h_ssov(cpu_gpr_d
[r3
], cpu_env
, cpu_gpr_d
[r1
],
6116 case OPC2_32_RR_ADDS_HU
:
6117 gen_helper_add_h_suov(cpu_gpr_d
[r3
], cpu_env
, cpu_gpr_d
[r1
],
6120 case OPC2_32_RR_ADDS_U
:
6121 gen_helper_add_suov(cpu_gpr_d
[r3
], cpu_env
, cpu_gpr_d
[r1
],
6124 case OPC2_32_RR_ADDX
:
6125 gen_add_CC(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
6127 case OPC2_32_RR_AND_EQ
:
6128 gen_accumulating_cond(TCG_COND_EQ
, cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
6129 cpu_gpr_d
[r2
], &tcg_gen_and_tl
);
6131 case OPC2_32_RR_AND_GE
:
6132 gen_accumulating_cond(TCG_COND_GE
, cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
6133 cpu_gpr_d
[r2
], &tcg_gen_and_tl
);
6135 case OPC2_32_RR_AND_GE_U
:
6136 gen_accumulating_cond(TCG_COND_GEU
, cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
6137 cpu_gpr_d
[r2
], &tcg_gen_and_tl
);
6139 case OPC2_32_RR_AND_LT
:
6140 gen_accumulating_cond(TCG_COND_LT
, cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
6141 cpu_gpr_d
[r2
], &tcg_gen_and_tl
);
6143 case OPC2_32_RR_AND_LT_U
:
6144 gen_accumulating_cond(TCG_COND_LTU
, cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
6145 cpu_gpr_d
[r2
], &tcg_gen_and_tl
);
6147 case OPC2_32_RR_AND_NE
:
6148 gen_accumulating_cond(TCG_COND_NE
, cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
6149 cpu_gpr_d
[r2
], &tcg_gen_and_tl
);
6152 tcg_gen_setcond_tl(TCG_COND_EQ
, cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
6155 case OPC2_32_RR_EQ_B
:
6156 gen_helper_eq_b(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
6158 case OPC2_32_RR_EQ_H
:
6159 gen_helper_eq_h(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
6161 case OPC2_32_RR_EQ_W
:
6162 gen_cond_w(TCG_COND_EQ
, cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
6164 case OPC2_32_RR_EQANY_B
:
6165 gen_helper_eqany_b(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
6167 case OPC2_32_RR_EQANY_H
:
6168 gen_helper_eqany_h(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
6171 tcg_gen_setcond_tl(TCG_COND_GE
, cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
6174 case OPC2_32_RR_GE_U
:
6175 tcg_gen_setcond_tl(TCG_COND_GEU
, cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
6179 tcg_gen_setcond_tl(TCG_COND_LT
, cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
6182 case OPC2_32_RR_LT_U
:
6183 tcg_gen_setcond_tl(TCG_COND_LTU
, cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
6186 case OPC2_32_RR_LT_B
:
6187 gen_helper_lt_b(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
6189 case OPC2_32_RR_LT_BU
:
6190 gen_helper_lt_bu(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
6192 case OPC2_32_RR_LT_H
:
6193 gen_helper_lt_h(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
6195 case OPC2_32_RR_LT_HU
:
6196 gen_helper_lt_hu(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
6198 case OPC2_32_RR_LT_W
:
6199 gen_cond_w(TCG_COND_LT
, cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
6201 case OPC2_32_RR_LT_WU
:
6202 gen_cond_w(TCG_COND_LTU
, cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
6204 case OPC2_32_RR_MAX
:
6205 tcg_gen_movcond_tl(TCG_COND_GT
, cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
6206 cpu_gpr_d
[r2
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
6208 case OPC2_32_RR_MAX_U
:
6209 tcg_gen_movcond_tl(TCG_COND_GTU
, cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
6210 cpu_gpr_d
[r2
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
6212 case OPC2_32_RR_MAX_B
:
6213 gen_helper_max_b(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
6215 case OPC2_32_RR_MAX_BU
:
6216 gen_helper_max_bu(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
6218 case OPC2_32_RR_MAX_H
:
6219 gen_helper_max_h(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
6221 case OPC2_32_RR_MAX_HU
:
6222 gen_helper_max_hu(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
6224 case OPC2_32_RR_MIN
:
6225 tcg_gen_movcond_tl(TCG_COND_LT
, cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
6226 cpu_gpr_d
[r2
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
6228 case OPC2_32_RR_MIN_U
:
6229 tcg_gen_movcond_tl(TCG_COND_LTU
, cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
6230 cpu_gpr_d
[r2
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
6232 case OPC2_32_RR_MIN_B
:
6233 gen_helper_min_b(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
6235 case OPC2_32_RR_MIN_BU
:
6236 gen_helper_min_bu(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
6238 case OPC2_32_RR_MIN_H
:
6239 gen_helper_min_h(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
6241 case OPC2_32_RR_MIN_HU
:
6242 gen_helper_min_hu(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
6244 case OPC2_32_RR_MOV
:
6245 tcg_gen_mov_tl(cpu_gpr_d
[r3
], cpu_gpr_d
[r2
]);
6247 case OPC2_32_RR_MOV_64
:
6248 if (tricore_feature(env
, TRICORE_FEATURE_16
)) {
6249 temp
= tcg_temp_new();
6252 tcg_gen_mov_tl(temp
, cpu_gpr_d
[r1
]);
6253 tcg_gen_mov_tl(cpu_gpr_d
[r3
], cpu_gpr_d
[r2
]);
6254 tcg_gen_mov_tl(cpu_gpr_d
[r3
+ 1], temp
);
6256 tcg_temp_free(temp
);
6258 generate_trap(ctx
, TRAPC_INSN_ERR
, TIN2_IOPC
);
6262 tcg_gen_setcond_tl(TCG_COND_NE
, cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
6265 case OPC2_32_RR_OR_EQ
:
6266 gen_accumulating_cond(TCG_COND_EQ
, cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
6267 cpu_gpr_d
[r2
], &tcg_gen_or_tl
);
6269 case OPC2_32_RR_OR_GE
:
6270 gen_accumulating_cond(TCG_COND_GE
, cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
6271 cpu_gpr_d
[r2
], &tcg_gen_or_tl
);
6273 case OPC2_32_RR_OR_GE_U
:
6274 gen_accumulating_cond(TCG_COND_GEU
, cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
6275 cpu_gpr_d
[r2
], &tcg_gen_or_tl
);
6277 case OPC2_32_RR_OR_LT
:
6278 gen_accumulating_cond(TCG_COND_LT
, cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
6279 cpu_gpr_d
[r2
], &tcg_gen_or_tl
);
6281 case OPC2_32_RR_OR_LT_U
:
6282 gen_accumulating_cond(TCG_COND_LTU
, cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
6283 cpu_gpr_d
[r2
], &tcg_gen_or_tl
);
6285 case OPC2_32_RR_OR_NE
:
6286 gen_accumulating_cond(TCG_COND_NE
, cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
6287 cpu_gpr_d
[r2
], &tcg_gen_or_tl
);
6289 case OPC2_32_RR_SAT_B
:
6290 gen_saturate(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], 0x7f, -0x80);
6292 case OPC2_32_RR_SAT_BU
:
6293 gen_saturate_u(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], 0xff);
6295 case OPC2_32_RR_SAT_H
:
6296 gen_saturate(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], 0x7fff, -0x8000);
6298 case OPC2_32_RR_SAT_HU
:
6299 gen_saturate_u(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], 0xffff);
6301 case OPC2_32_RR_SH_EQ
:
6302 gen_sh_cond(TCG_COND_EQ
, cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
6305 case OPC2_32_RR_SH_GE
:
6306 gen_sh_cond(TCG_COND_GE
, cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
6309 case OPC2_32_RR_SH_GE_U
:
6310 gen_sh_cond(TCG_COND_GEU
, cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
6313 case OPC2_32_RR_SH_LT
:
6314 gen_sh_cond(TCG_COND_LT
, cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
6317 case OPC2_32_RR_SH_LT_U
:
6318 gen_sh_cond(TCG_COND_LTU
, cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
6321 case OPC2_32_RR_SH_NE
:
6322 gen_sh_cond(TCG_COND_NE
, cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
6325 case OPC2_32_RR_SUB
:
6326 gen_sub_d(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
6328 case OPC2_32_RR_SUB_B
:
6329 gen_helper_sub_b(cpu_gpr_d
[r3
], cpu_env
, cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
6331 case OPC2_32_RR_SUB_H
:
6332 gen_helper_sub_h(cpu_gpr_d
[r3
], cpu_env
, cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
6334 case OPC2_32_RR_SUBC
:
6335 gen_subc_CC(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
6337 case OPC2_32_RR_SUBS
:
6338 gen_subs(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
6340 case OPC2_32_RR_SUBS_U
:
6341 gen_subsu(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
6343 case OPC2_32_RR_SUBS_H
:
6344 gen_helper_sub_h_ssov(cpu_gpr_d
[r3
], cpu_env
, cpu_gpr_d
[r1
],
6347 case OPC2_32_RR_SUBS_HU
:
6348 gen_helper_sub_h_suov(cpu_gpr_d
[r3
], cpu_env
, cpu_gpr_d
[r1
],
6351 case OPC2_32_RR_SUBX
:
6352 gen_sub_CC(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
6354 case OPC2_32_RR_XOR_EQ
:
6355 gen_accumulating_cond(TCG_COND_EQ
, cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
6356 cpu_gpr_d
[r2
], &tcg_gen_xor_tl
);
6358 case OPC2_32_RR_XOR_GE
:
6359 gen_accumulating_cond(TCG_COND_GE
, cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
6360 cpu_gpr_d
[r2
], &tcg_gen_xor_tl
);
6362 case OPC2_32_RR_XOR_GE_U
:
6363 gen_accumulating_cond(TCG_COND_GEU
, cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
6364 cpu_gpr_d
[r2
], &tcg_gen_xor_tl
);
6366 case OPC2_32_RR_XOR_LT
:
6367 gen_accumulating_cond(TCG_COND_LT
, cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
6368 cpu_gpr_d
[r2
], &tcg_gen_xor_tl
);
6370 case OPC2_32_RR_XOR_LT_U
:
6371 gen_accumulating_cond(TCG_COND_LTU
, cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
6372 cpu_gpr_d
[r2
], &tcg_gen_xor_tl
);
6374 case OPC2_32_RR_XOR_NE
:
6375 gen_accumulating_cond(TCG_COND_NE
, cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
6376 cpu_gpr_d
[r2
], &tcg_gen_xor_tl
);
6379 generate_trap(ctx
, TRAPC_INSN_ERR
, TIN2_IOPC
);
6383 static void decode_rr_logical_shift(CPUTriCoreState
*env
, DisasContext
*ctx
)
6389 r3
= MASK_OP_RR_D(ctx
->opcode
);
6390 r2
= MASK_OP_RR_S2(ctx
->opcode
);
6391 r1
= MASK_OP_RR_S1(ctx
->opcode
);
6393 temp
= tcg_temp_new();
6394 op2
= MASK_OP_RR_OP2(ctx
->opcode
);
6397 case OPC2_32_RR_AND
:
6398 tcg_gen_and_tl(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
6400 case OPC2_32_RR_ANDN
:
6401 tcg_gen_andc_tl(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
6403 case OPC2_32_RR_CLO
:
6404 tcg_gen_not_tl(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
]);
6405 tcg_gen_clzi_tl(cpu_gpr_d
[r3
], cpu_gpr_d
[r3
], TARGET_LONG_BITS
);
6407 case OPC2_32_RR_CLO_H
:
6408 gen_helper_clo_h(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
]);
6410 case OPC2_32_RR_CLS
:
6411 tcg_gen_clrsb_tl(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
]);
6413 case OPC2_32_RR_CLS_H
:
6414 gen_helper_cls_h(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
]);
6416 case OPC2_32_RR_CLZ
:
6417 tcg_gen_clzi_tl(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], TARGET_LONG_BITS
);
6419 case OPC2_32_RR_CLZ_H
:
6420 gen_helper_clz_h(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
]);
6422 case OPC2_32_RR_NAND
:
6423 tcg_gen_nand_tl(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
6425 case OPC2_32_RR_NOR
:
6426 tcg_gen_nor_tl(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
6429 tcg_gen_or_tl(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
6431 case OPC2_32_RR_ORN
:
6432 tcg_gen_orc_tl(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
6435 gen_helper_sh(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
6437 case OPC2_32_RR_SH_H
:
6438 gen_helper_sh_h(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
6440 case OPC2_32_RR_SHA
:
6441 gen_helper_sha(cpu_gpr_d
[r3
], cpu_env
, cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
6443 case OPC2_32_RR_SHA_H
:
6444 gen_helper_sha_h(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
6446 case OPC2_32_RR_SHAS
:
6447 gen_shas(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
6449 case OPC2_32_RR_XNOR
:
6450 tcg_gen_eqv_tl(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
6452 case OPC2_32_RR_XOR
:
6453 tcg_gen_xor_tl(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
6456 generate_trap(ctx
, TRAPC_INSN_ERR
, TIN2_IOPC
);
6458 tcg_temp_free(temp
);
6461 static void decode_rr_address(CPUTriCoreState
*env
, DisasContext
*ctx
)
6467 op2
= MASK_OP_RR_OP2(ctx
->opcode
);
6468 r3
= MASK_OP_RR_D(ctx
->opcode
);
6469 r2
= MASK_OP_RR_S2(ctx
->opcode
);
6470 r1
= MASK_OP_RR_S1(ctx
->opcode
);
6471 n
= MASK_OP_RR_N(ctx
->opcode
);
6474 case OPC2_32_RR_ADD_A
:
6475 tcg_gen_add_tl(cpu_gpr_a
[r3
], cpu_gpr_a
[r1
], cpu_gpr_a
[r2
]);
6477 case OPC2_32_RR_ADDSC_A
:
6478 temp
= tcg_temp_new();
6479 tcg_gen_shli_tl(temp
, cpu_gpr_d
[r1
], n
);
6480 tcg_gen_add_tl(cpu_gpr_a
[r3
], cpu_gpr_a
[r2
], temp
);
6481 tcg_temp_free(temp
);
6483 case OPC2_32_RR_ADDSC_AT
:
6484 temp
= tcg_temp_new();
6485 tcg_gen_sari_tl(temp
, cpu_gpr_d
[r1
], 3);
6486 tcg_gen_add_tl(temp
, cpu_gpr_a
[r2
], temp
);
6487 tcg_gen_andi_tl(cpu_gpr_a
[r3
], temp
, 0xFFFFFFFC);
6488 tcg_temp_free(temp
);
6490 case OPC2_32_RR_EQ_A
:
6491 tcg_gen_setcond_tl(TCG_COND_EQ
, cpu_gpr_d
[r3
], cpu_gpr_a
[r1
],
6494 case OPC2_32_RR_EQZ
:
6495 tcg_gen_setcondi_tl(TCG_COND_EQ
, cpu_gpr_d
[r3
], cpu_gpr_a
[r1
], 0);
6497 case OPC2_32_RR_GE_A
:
6498 tcg_gen_setcond_tl(TCG_COND_GEU
, cpu_gpr_d
[r3
], cpu_gpr_a
[r1
],
6501 case OPC2_32_RR_LT_A
:
6502 tcg_gen_setcond_tl(TCG_COND_LTU
, cpu_gpr_d
[r3
], cpu_gpr_a
[r1
],
6505 case OPC2_32_RR_MOV_A
:
6506 tcg_gen_mov_tl(cpu_gpr_a
[r3
], cpu_gpr_d
[r2
]);
6508 case OPC2_32_RR_MOV_AA
:
6509 tcg_gen_mov_tl(cpu_gpr_a
[r3
], cpu_gpr_a
[r2
]);
6511 case OPC2_32_RR_MOV_D
:
6512 tcg_gen_mov_tl(cpu_gpr_d
[r3
], cpu_gpr_a
[r2
]);
6514 case OPC2_32_RR_NE_A
:
6515 tcg_gen_setcond_tl(TCG_COND_NE
, cpu_gpr_d
[r3
], cpu_gpr_a
[r1
],
6518 case OPC2_32_RR_NEZ_A
:
6519 tcg_gen_setcondi_tl(TCG_COND_NE
, cpu_gpr_d
[r3
], cpu_gpr_a
[r1
], 0);
6521 case OPC2_32_RR_SUB_A
:
6522 tcg_gen_sub_tl(cpu_gpr_a
[r3
], cpu_gpr_a
[r1
], cpu_gpr_a
[r2
]);
6525 generate_trap(ctx
, TRAPC_INSN_ERR
, TIN2_IOPC
);
6529 static void decode_rr_idirect(CPUTriCoreState
*env
, DisasContext
*ctx
)
6534 op2
= MASK_OP_RR_OP2(ctx
->opcode
);
6535 r1
= MASK_OP_RR_S1(ctx
->opcode
);
6539 tcg_gen_andi_tl(cpu_PC
, cpu_gpr_a
[r1
], ~0x1);
6541 case OPC2_32_RR_JLI
:
6542 tcg_gen_movi_tl(cpu_gpr_a
[11], ctx
->next_pc
);
6543 tcg_gen_andi_tl(cpu_PC
, cpu_gpr_a
[r1
], ~0x1);
6545 case OPC2_32_RR_CALLI
:
6546 gen_helper_1arg(call
, ctx
->next_pc
);
6547 tcg_gen_andi_tl(cpu_PC
, cpu_gpr_a
[r1
], ~0x1);
6549 case OPC2_32_RR_FCALLI
:
6550 gen_fcall_save_ctx(ctx
);
6551 tcg_gen_andi_tl(cpu_PC
, cpu_gpr_a
[r1
], ~0x1);
6554 generate_trap(ctx
, TRAPC_INSN_ERR
, TIN2_IOPC
);
6557 ctx
->bstate
= BS_BRANCH
;
6560 static void decode_rr_divide(CPUTriCoreState
*env
, DisasContext
*ctx
)
6565 TCGv temp
, temp2
, temp3
;
6567 op2
= MASK_OP_RR_OP2(ctx
->opcode
);
6568 r3
= MASK_OP_RR_D(ctx
->opcode
);
6569 r2
= MASK_OP_RR_S2(ctx
->opcode
);
6570 r1
= MASK_OP_RR_S1(ctx
->opcode
);
6573 case OPC2_32_RR_BMERGE
:
6574 gen_helper_bmerge(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
6576 case OPC2_32_RR_BSPLIT
:
6578 gen_bsplit(cpu_gpr_d
[r3
], cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
]);
6580 case OPC2_32_RR_DVINIT_B
:
6582 gen_dvinit_b(env
, cpu_gpr_d
[r3
], cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
],
6585 case OPC2_32_RR_DVINIT_BU
:
6586 temp
= tcg_temp_new();
6587 temp2
= tcg_temp_new();
6588 temp3
= tcg_temp_new();
6590 tcg_gen_shri_tl(temp3
, cpu_gpr_d
[r1
], 8);
6592 tcg_gen_movi_tl(cpu_PSW_AV
, 0);
6593 if (!tricore_feature(env
, TRICORE_FEATURE_131
)) {
6594 /* overflow = (abs(D[r3+1]) >= abs(D[r2])) */
6595 tcg_gen_neg_tl(temp
, temp3
);
6596 /* use cpu_PSW_AV to compare against 0 */
6597 tcg_gen_movcond_tl(TCG_COND_LT
, temp
, temp3
, cpu_PSW_AV
,
6599 tcg_gen_neg_tl(temp2
, cpu_gpr_d
[r2
]);
6600 tcg_gen_movcond_tl(TCG_COND_LT
, temp2
, cpu_gpr_d
[r2
], cpu_PSW_AV
,
6601 temp2
, cpu_gpr_d
[r2
]);
6602 tcg_gen_setcond_tl(TCG_COND_GE
, cpu_PSW_V
, temp
, temp2
);
6604 /* overflow = (D[b] == 0) */
6605 tcg_gen_setcondi_tl(TCG_COND_EQ
, cpu_PSW_V
, cpu_gpr_d
[r2
], 0);
6607 tcg_gen_shli_tl(cpu_PSW_V
, cpu_PSW_V
, 31);
6609 tcg_gen_or_tl(cpu_PSW_SV
, cpu_PSW_SV
, cpu_PSW_V
);
6611 tcg_gen_shli_tl(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], 24);
6612 tcg_gen_mov_tl(cpu_gpr_d
[r3
+1], temp3
);
6614 tcg_temp_free(temp
);
6615 tcg_temp_free(temp2
);
6616 tcg_temp_free(temp3
);
6618 case OPC2_32_RR_DVINIT_H
:
6620 gen_dvinit_h(env
, cpu_gpr_d
[r3
], cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
],
6623 case OPC2_32_RR_DVINIT_HU
:
6624 temp
= tcg_temp_new();
6625 temp2
= tcg_temp_new();
6626 temp3
= tcg_temp_new();
6628 tcg_gen_shri_tl(temp3
, cpu_gpr_d
[r1
], 16);
6630 tcg_gen_movi_tl(cpu_PSW_AV
, 0);
6631 if (!tricore_feature(env
, TRICORE_FEATURE_131
)) {
6632 /* overflow = (abs(D[r3+1]) >= abs(D[r2])) */
6633 tcg_gen_neg_tl(temp
, temp3
);
6634 /* use cpu_PSW_AV to compare against 0 */
6635 tcg_gen_movcond_tl(TCG_COND_LT
, temp
, temp3
, cpu_PSW_AV
,
6637 tcg_gen_neg_tl(temp2
, cpu_gpr_d
[r2
]);
6638 tcg_gen_movcond_tl(TCG_COND_LT
, temp2
, cpu_gpr_d
[r2
], cpu_PSW_AV
,
6639 temp2
, cpu_gpr_d
[r2
]);
6640 tcg_gen_setcond_tl(TCG_COND_GE
, cpu_PSW_V
, temp
, temp2
);
6642 /* overflow = (D[b] == 0) */
6643 tcg_gen_setcondi_tl(TCG_COND_EQ
, cpu_PSW_V
, cpu_gpr_d
[r2
], 0);
6645 tcg_gen_shli_tl(cpu_PSW_V
, cpu_PSW_V
, 31);
6647 tcg_gen_or_tl(cpu_PSW_SV
, cpu_PSW_SV
, cpu_PSW_V
);
6649 tcg_gen_shli_tl(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], 16);
6650 tcg_gen_mov_tl(cpu_gpr_d
[r3
+1], temp3
);
6651 tcg_temp_free(temp
);
6652 tcg_temp_free(temp2
);
6653 tcg_temp_free(temp3
);
6655 case OPC2_32_RR_DVINIT
:
6656 temp
= tcg_temp_new();
6657 temp2
= tcg_temp_new();
6659 /* overflow = ((D[b] == 0) ||
6660 ((D[b] == 0xFFFFFFFF) && (D[a] == 0x80000000))) */
6661 tcg_gen_setcondi_tl(TCG_COND_EQ
, temp
, cpu_gpr_d
[r2
], 0xffffffff);
6662 tcg_gen_setcondi_tl(TCG_COND_EQ
, temp2
, cpu_gpr_d
[r1
], 0x80000000);
6663 tcg_gen_and_tl(temp
, temp
, temp2
);
6664 tcg_gen_setcondi_tl(TCG_COND_EQ
, temp2
, cpu_gpr_d
[r2
], 0);
6665 tcg_gen_or_tl(cpu_PSW_V
, temp
, temp2
);
6666 tcg_gen_shli_tl(cpu_PSW_V
, cpu_PSW_V
, 31);
6668 tcg_gen_or_tl(cpu_PSW_SV
, cpu_PSW_SV
, cpu_PSW_V
);
6670 tcg_gen_movi_tl(cpu_PSW_AV
, 0);
6672 tcg_gen_mov_tl(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
]);
6673 /* sign extend to high reg */
6674 tcg_gen_sari_tl(cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], 31);
6675 tcg_temp_free(temp
);
6676 tcg_temp_free(temp2
);
6678 case OPC2_32_RR_DVINIT_U
:
6679 /* overflow = (D[b] == 0) */
6680 tcg_gen_setcondi_tl(TCG_COND_EQ
, cpu_PSW_V
, cpu_gpr_d
[r2
], 0);
6681 tcg_gen_shli_tl(cpu_PSW_V
, cpu_PSW_V
, 31);
6683 tcg_gen_or_tl(cpu_PSW_SV
, cpu_PSW_SV
, cpu_PSW_V
);
6685 tcg_gen_movi_tl(cpu_PSW_AV
, 0);
6687 tcg_gen_mov_tl(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
]);
6688 /* zero extend to high reg*/
6689 tcg_gen_movi_tl(cpu_gpr_d
[r3
+1], 0);
6691 case OPC2_32_RR_PARITY
:
6692 gen_helper_parity(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
]);
6694 case OPC2_32_RR_UNPACK
:
6696 gen_unpack(cpu_gpr_d
[r3
], cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
]);
6698 case OPC2_32_RR_CRC32
:
6699 if (tricore_feature(env
, TRICORE_FEATURE_161
)) {
6700 gen_helper_crc32(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
6702 generate_trap(ctx
, TRAPC_INSN_ERR
, TIN2_IOPC
);
6705 case OPC2_32_RR_DIV
:
6706 if (tricore_feature(env
, TRICORE_FEATURE_16
)) {
6707 GEN_HELPER_RR(divide
, cpu_gpr_d
[r3
], cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
],
6710 generate_trap(ctx
, TRAPC_INSN_ERR
, TIN2_IOPC
);
6713 case OPC2_32_RR_DIV_U
:
6714 if (tricore_feature(env
, TRICORE_FEATURE_16
)) {
6715 GEN_HELPER_RR(divide_u
, cpu_gpr_d
[r3
], cpu_gpr_d
[r3
+1],
6716 cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
6718 generate_trap(ctx
, TRAPC_INSN_ERR
, TIN2_IOPC
);
6721 case OPC2_32_RR_MUL_F
:
6722 gen_helper_fmul(cpu_gpr_d
[r3
], cpu_env
, cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
6724 case OPC2_32_RR_DIV_F
:
6725 gen_helper_fdiv(cpu_gpr_d
[r3
], cpu_env
, cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
6727 case OPC2_32_RR_CMP_F
:
6728 gen_helper_fcmp(cpu_gpr_d
[r3
], cpu_env
, cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
6730 case OPC2_32_RR_FTOI
:
6731 gen_helper_ftoi(cpu_gpr_d
[r3
], cpu_env
, cpu_gpr_d
[r1
]);
6733 case OPC2_32_RR_ITOF
:
6734 gen_helper_itof(cpu_gpr_d
[r3
], cpu_env
, cpu_gpr_d
[r1
]);
6736 case OPC2_32_RR_FTOUZ
:
6737 gen_helper_ftouz(cpu_gpr_d
[r3
], cpu_env
, cpu_gpr_d
[r1
]);
6739 case OPC2_32_RR_UPDFL
:
6740 gen_helper_updfl(cpu_env
, cpu_gpr_d
[r1
]);
6743 generate_trap(ctx
, TRAPC_INSN_ERR
, TIN2_IOPC
);
6748 static void decode_rr1_mul(CPUTriCoreState
*env
, DisasContext
*ctx
)
6756 r1
= MASK_OP_RR1_S1(ctx
->opcode
);
6757 r2
= MASK_OP_RR1_S2(ctx
->opcode
);
6758 r3
= MASK_OP_RR1_D(ctx
->opcode
);
6759 n
= tcg_const_i32(MASK_OP_RR1_N(ctx
->opcode
));
6760 op2
= MASK_OP_RR1_OP2(ctx
->opcode
);
6763 case OPC2_32_RR1_MUL_H_32_LL
:
6764 temp64
= tcg_temp_new_i64();
6766 GEN_HELPER_LL(mul_h
, temp64
, cpu_gpr_d
[r1
], cpu_gpr_d
[r2
], n
);
6767 tcg_gen_extr_i64_i32(cpu_gpr_d
[r3
], cpu_gpr_d
[r3
+1], temp64
);
6768 gen_calc_usb_mul_h(cpu_gpr_d
[r3
], cpu_gpr_d
[r3
+1]);
6769 tcg_temp_free_i64(temp64
);
6771 case OPC2_32_RR1_MUL_H_32_LU
:
6772 temp64
= tcg_temp_new_i64();
6774 GEN_HELPER_LU(mul_h
, temp64
, cpu_gpr_d
[r1
], cpu_gpr_d
[r2
], n
);
6775 tcg_gen_extr_i64_i32(cpu_gpr_d
[r3
], cpu_gpr_d
[r3
+1], temp64
);
6776 gen_calc_usb_mul_h(cpu_gpr_d
[r3
], cpu_gpr_d
[r3
+1]);
6777 tcg_temp_free_i64(temp64
);
6779 case OPC2_32_RR1_MUL_H_32_UL
:
6780 temp64
= tcg_temp_new_i64();
6782 GEN_HELPER_UL(mul_h
, temp64
, cpu_gpr_d
[r1
], cpu_gpr_d
[r2
], n
);
6783 tcg_gen_extr_i64_i32(cpu_gpr_d
[r3
], cpu_gpr_d
[r3
+1], temp64
);
6784 gen_calc_usb_mul_h(cpu_gpr_d
[r3
], cpu_gpr_d
[r3
+1]);
6785 tcg_temp_free_i64(temp64
);
6787 case OPC2_32_RR1_MUL_H_32_UU
:
6788 temp64
= tcg_temp_new_i64();
6790 GEN_HELPER_UU(mul_h
, temp64
, cpu_gpr_d
[r1
], cpu_gpr_d
[r2
], n
);
6791 tcg_gen_extr_i64_i32(cpu_gpr_d
[r3
], cpu_gpr_d
[r3
+1], temp64
);
6792 gen_calc_usb_mul_h(cpu_gpr_d
[r3
], cpu_gpr_d
[r3
+1]);
6793 tcg_temp_free_i64(temp64
);
6795 case OPC2_32_RR1_MULM_H_64_LL
:
6796 temp64
= tcg_temp_new_i64();
6798 GEN_HELPER_LL(mulm_h
, temp64
, cpu_gpr_d
[r1
], cpu_gpr_d
[r2
], n
);
6799 tcg_gen_extr_i64_i32(cpu_gpr_d
[r3
], cpu_gpr_d
[r3
+1], temp64
);
6801 tcg_gen_movi_tl(cpu_PSW_V
, 0);
6803 tcg_gen_mov_tl(cpu_PSW_AV
, cpu_PSW_V
);
6804 tcg_temp_free_i64(temp64
);
6806 case OPC2_32_RR1_MULM_H_64_LU
:
6807 temp64
= tcg_temp_new_i64();
6809 GEN_HELPER_LU(mulm_h
, temp64
, cpu_gpr_d
[r1
], cpu_gpr_d
[r2
], n
);
6810 tcg_gen_extr_i64_i32(cpu_gpr_d
[r3
], cpu_gpr_d
[r3
+1], temp64
);
6812 tcg_gen_movi_tl(cpu_PSW_V
, 0);
6814 tcg_gen_mov_tl(cpu_PSW_AV
, cpu_PSW_V
);
6815 tcg_temp_free_i64(temp64
);
6817 case OPC2_32_RR1_MULM_H_64_UL
:
6818 temp64
= tcg_temp_new_i64();
6820 GEN_HELPER_UL(mulm_h
, temp64
, cpu_gpr_d
[r1
], cpu_gpr_d
[r2
], n
);
6821 tcg_gen_extr_i64_i32(cpu_gpr_d
[r3
], cpu_gpr_d
[r3
+1], temp64
);
6823 tcg_gen_movi_tl(cpu_PSW_V
, 0);
6825 tcg_gen_mov_tl(cpu_PSW_AV
, cpu_PSW_V
);
6826 tcg_temp_free_i64(temp64
);
6828 case OPC2_32_RR1_MULM_H_64_UU
:
6829 temp64
= tcg_temp_new_i64();
6831 GEN_HELPER_UU(mulm_h
, temp64
, cpu_gpr_d
[r1
], cpu_gpr_d
[r2
], n
);
6832 tcg_gen_extr_i64_i32(cpu_gpr_d
[r3
], cpu_gpr_d
[r3
+1], temp64
);
6834 tcg_gen_movi_tl(cpu_PSW_V
, 0);
6836 tcg_gen_mov_tl(cpu_PSW_AV
, cpu_PSW_V
);
6837 tcg_temp_free_i64(temp64
);
6840 case OPC2_32_RR1_MULR_H_16_LL
:
6841 GEN_HELPER_LL(mulr_h
, cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
], n
);
6842 gen_calc_usb_mulr_h(cpu_gpr_d
[r3
]);
6844 case OPC2_32_RR1_MULR_H_16_LU
:
6845 GEN_HELPER_LU(mulr_h
, cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
], n
);
6846 gen_calc_usb_mulr_h(cpu_gpr_d
[r3
]);
6848 case OPC2_32_RR1_MULR_H_16_UL
:
6849 GEN_HELPER_UL(mulr_h
, cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
], n
);
6850 gen_calc_usb_mulr_h(cpu_gpr_d
[r3
]);
6852 case OPC2_32_RR1_MULR_H_16_UU
:
6853 GEN_HELPER_UU(mulr_h
, cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
], n
);
6854 gen_calc_usb_mulr_h(cpu_gpr_d
[r3
]);
6857 generate_trap(ctx
, TRAPC_INSN_ERR
, TIN2_IOPC
);
6862 static void decode_rr1_mulq(CPUTriCoreState
*env
, DisasContext
*ctx
)
6870 r1
= MASK_OP_RR1_S1(ctx
->opcode
);
6871 r2
= MASK_OP_RR1_S2(ctx
->opcode
);
6872 r3
= MASK_OP_RR1_D(ctx
->opcode
);
6873 n
= MASK_OP_RR1_N(ctx
->opcode
);
6874 op2
= MASK_OP_RR1_OP2(ctx
->opcode
);
6876 temp
= tcg_temp_new();
6877 temp2
= tcg_temp_new();
6880 case OPC2_32_RR1_MUL_Q_32
:
6881 gen_mul_q(cpu_gpr_d
[r3
], temp
, cpu_gpr_d
[r1
], cpu_gpr_d
[r2
], n
, 32);
6883 case OPC2_32_RR1_MUL_Q_64
:
6885 gen_mul_q(cpu_gpr_d
[r3
], cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
6888 case OPC2_32_RR1_MUL_Q_32_L
:
6889 tcg_gen_ext16s_tl(temp
, cpu_gpr_d
[r2
]);
6890 gen_mul_q(cpu_gpr_d
[r3
], temp
, cpu_gpr_d
[r1
], temp
, n
, 16);
6892 case OPC2_32_RR1_MUL_Q_64_L
:
6894 tcg_gen_ext16s_tl(temp
, cpu_gpr_d
[r2
]);
6895 gen_mul_q(cpu_gpr_d
[r3
], cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], temp
, n
, 0);
6897 case OPC2_32_RR1_MUL_Q_32_U
:
6898 tcg_gen_sari_tl(temp
, cpu_gpr_d
[r2
], 16);
6899 gen_mul_q(cpu_gpr_d
[r3
], temp
, cpu_gpr_d
[r1
], temp
, n
, 16);
6901 case OPC2_32_RR1_MUL_Q_64_U
:
6903 tcg_gen_sari_tl(temp
, cpu_gpr_d
[r2
], 16);
6904 gen_mul_q(cpu_gpr_d
[r3
], cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], temp
, n
, 0);
6906 case OPC2_32_RR1_MUL_Q_32_LL
:
6907 tcg_gen_ext16s_tl(temp
, cpu_gpr_d
[r1
]);
6908 tcg_gen_ext16s_tl(temp2
, cpu_gpr_d
[r2
]);
6909 gen_mul_q_16(cpu_gpr_d
[r3
], temp
, temp2
, n
);
6911 case OPC2_32_RR1_MUL_Q_32_UU
:
6912 tcg_gen_sari_tl(temp
, cpu_gpr_d
[r1
], 16);
6913 tcg_gen_sari_tl(temp2
, cpu_gpr_d
[r2
], 16);
6914 gen_mul_q_16(cpu_gpr_d
[r3
], temp
, temp2
, n
);
6916 case OPC2_32_RR1_MULR_Q_32_L
:
6917 tcg_gen_ext16s_tl(temp
, cpu_gpr_d
[r1
]);
6918 tcg_gen_ext16s_tl(temp2
, cpu_gpr_d
[r2
]);
6919 gen_mulr_q(cpu_gpr_d
[r3
], temp
, temp2
, n
);
6921 case OPC2_32_RR1_MULR_Q_32_U
:
6922 tcg_gen_sari_tl(temp
, cpu_gpr_d
[r1
], 16);
6923 tcg_gen_sari_tl(temp2
, cpu_gpr_d
[r2
], 16);
6924 gen_mulr_q(cpu_gpr_d
[r3
], temp
, temp2
, n
);
6927 generate_trap(ctx
, TRAPC_INSN_ERR
, TIN2_IOPC
);
6929 tcg_temp_free(temp
);
6930 tcg_temp_free(temp2
);
6934 static void decode_rr2_mul(CPUTriCoreState
*env
, DisasContext
*ctx
)
6939 op2
= MASK_OP_RR2_OP2(ctx
->opcode
);
6940 r1
= MASK_OP_RR2_S1(ctx
->opcode
);
6941 r2
= MASK_OP_RR2_S2(ctx
->opcode
);
6942 r3
= MASK_OP_RR2_D(ctx
->opcode
);
6944 case OPC2_32_RR2_MUL_32
:
6945 gen_mul_i32s(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
6947 case OPC2_32_RR2_MUL_64
:
6949 gen_mul_i64s(cpu_gpr_d
[r3
], cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
],
6952 case OPC2_32_RR2_MULS_32
:
6953 gen_helper_mul_ssov(cpu_gpr_d
[r3
], cpu_env
, cpu_gpr_d
[r1
],
6956 case OPC2_32_RR2_MUL_U_64
:
6958 gen_mul_i64u(cpu_gpr_d
[r3
], cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
],
6961 case OPC2_32_RR2_MULS_U_32
:
6962 gen_helper_mul_suov(cpu_gpr_d
[r3
], cpu_env
, cpu_gpr_d
[r1
],
6966 generate_trap(ctx
, TRAPC_INSN_ERR
, TIN2_IOPC
);
6971 static void decode_rrpw_extract_insert(CPUTriCoreState
*env
, DisasContext
*ctx
)
6977 op2
= MASK_OP_RRPW_OP2(ctx
->opcode
);
6978 r1
= MASK_OP_RRPW_S1(ctx
->opcode
);
6979 r2
= MASK_OP_RRPW_S2(ctx
->opcode
);
6980 r3
= MASK_OP_RRPW_D(ctx
->opcode
);
6981 pos
= MASK_OP_RRPW_POS(ctx
->opcode
);
6982 width
= MASK_OP_RRPW_WIDTH(ctx
->opcode
);
6985 case OPC2_32_RRPW_EXTR
:
6986 if (pos
+ width
<= 31) {
6987 /* optimize special cases */
6988 if ((pos
== 0) && (width
== 8)) {
6989 tcg_gen_ext8s_tl(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
]);
6990 } else if ((pos
== 0) && (width
== 16)) {
6991 tcg_gen_ext16s_tl(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
]);
6993 tcg_gen_shli_tl(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], 32 - pos
- width
);
6994 tcg_gen_sari_tl(cpu_gpr_d
[r3
], cpu_gpr_d
[r3
], 32 - width
);
6998 case OPC2_32_RRPW_EXTR_U
:
7000 tcg_gen_movi_tl(cpu_gpr_d
[r3
], 0);
7002 tcg_gen_shri_tl(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], pos
);
7003 tcg_gen_andi_tl(cpu_gpr_d
[r3
], cpu_gpr_d
[r3
], ~0u >> (32-width
));
7006 case OPC2_32_RRPW_IMASK
:
7008 if (pos
+ width
<= 31) {
7009 tcg_gen_movi_tl(cpu_gpr_d
[r3
+1], ((1u << width
) - 1) << pos
);
7010 tcg_gen_shli_tl(cpu_gpr_d
[r3
], cpu_gpr_d
[r2
], pos
);
7013 case OPC2_32_RRPW_INSERT
:
7014 if (pos
+ width
<= 31) {
7015 tcg_gen_deposit_tl(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
7020 generate_trap(ctx
, TRAPC_INSN_ERR
, TIN2_IOPC
);
7025 static void decode_rrr_cond_select(CPUTriCoreState
*env
, DisasContext
*ctx
)
7031 op2
= MASK_OP_RRR_OP2(ctx
->opcode
);
7032 r1
= MASK_OP_RRR_S1(ctx
->opcode
);
7033 r2
= MASK_OP_RRR_S2(ctx
->opcode
);
7034 r3
= MASK_OP_RRR_S3(ctx
->opcode
);
7035 r4
= MASK_OP_RRR_D(ctx
->opcode
);
7038 case OPC2_32_RRR_CADD
:
7039 gen_cond_add(TCG_COND_NE
, cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
7040 cpu_gpr_d
[r4
], cpu_gpr_d
[r3
]);
7042 case OPC2_32_RRR_CADDN
:
7043 gen_cond_add(TCG_COND_EQ
, cpu_gpr_d
[r1
], cpu_gpr_d
[r2
], cpu_gpr_d
[r4
],
7046 case OPC2_32_RRR_CSUB
:
7047 gen_cond_sub(TCG_COND_NE
, cpu_gpr_d
[r1
], cpu_gpr_d
[r2
], cpu_gpr_d
[r4
],
7050 case OPC2_32_RRR_CSUBN
:
7051 gen_cond_sub(TCG_COND_EQ
, cpu_gpr_d
[r1
], cpu_gpr_d
[r2
], cpu_gpr_d
[r4
],
7054 case OPC2_32_RRR_SEL
:
7055 temp
= tcg_const_i32(0);
7056 tcg_gen_movcond_tl(TCG_COND_NE
, cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], temp
,
7057 cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
7058 tcg_temp_free(temp
);
7060 case OPC2_32_RRR_SELN
:
7061 temp
= tcg_const_i32(0);
7062 tcg_gen_movcond_tl(TCG_COND_EQ
, cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], temp
,
7063 cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
7064 tcg_temp_free(temp
);
7067 generate_trap(ctx
, TRAPC_INSN_ERR
, TIN2_IOPC
);
7071 static void decode_rrr_divide(CPUTriCoreState
*env
, DisasContext
*ctx
)
7077 op2
= MASK_OP_RRR_OP2(ctx
->opcode
);
7078 r1
= MASK_OP_RRR_S1(ctx
->opcode
);
7079 r2
= MASK_OP_RRR_S2(ctx
->opcode
);
7080 r3
= MASK_OP_RRR_S3(ctx
->opcode
);
7081 r4
= MASK_OP_RRR_D(ctx
->opcode
);
7084 case OPC2_32_RRR_DVADJ
:
7087 GEN_HELPER_RRR(dvadj
, cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
7088 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r2
]);
7090 case OPC2_32_RRR_DVSTEP
:
7093 GEN_HELPER_RRR(dvstep
, cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
7094 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r2
]);
7096 case OPC2_32_RRR_DVSTEP_U
:
7099 GEN_HELPER_RRR(dvstep_u
, cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
7100 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r2
]);
7102 case OPC2_32_RRR_IXMAX
:
7105 GEN_HELPER_RRR(ixmax
, cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
7106 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r2
]);
7108 case OPC2_32_RRR_IXMAX_U
:
7111 GEN_HELPER_RRR(ixmax_u
, cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
7112 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r2
]);
7114 case OPC2_32_RRR_IXMIN
:
7117 GEN_HELPER_RRR(ixmin
, cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
7118 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r2
]);
7120 case OPC2_32_RRR_IXMIN_U
:
7123 GEN_HELPER_RRR(ixmin_u
, cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
7124 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r2
]);
7126 case OPC2_32_RRR_PACK
:
7128 gen_helper_pack(cpu_gpr_d
[r4
], cpu_PSW_C
, cpu_gpr_d
[r3
],
7129 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
]);
7131 case OPC2_32_RRR_ADD_F
:
7132 gen_helper_fadd(cpu_gpr_d
[r4
], cpu_env
, cpu_gpr_d
[r1
], cpu_gpr_d
[r3
]);
7134 case OPC2_32_RRR_SUB_F
:
7135 gen_helper_fsub(cpu_gpr_d
[r4
], cpu_env
, cpu_gpr_d
[r1
], cpu_gpr_d
[r3
]);
7137 case OPC2_32_RRR_MADD_F
:
7138 gen_helper_fmadd(cpu_gpr_d
[r4
], cpu_env
, cpu_gpr_d
[r1
],
7139 cpu_gpr_d
[r2
], cpu_gpr_d
[r3
]);
7141 case OPC2_32_RRR_MSUB_F
:
7142 gen_helper_fmsub(cpu_gpr_d
[r4
], cpu_env
, cpu_gpr_d
[r1
],
7143 cpu_gpr_d
[r2
], cpu_gpr_d
[r3
]);
7146 generate_trap(ctx
, TRAPC_INSN_ERR
, TIN2_IOPC
);
7151 static void decode_rrr2_madd(CPUTriCoreState
*env
, DisasContext
*ctx
)
7154 uint32_t r1
, r2
, r3
, r4
;
7156 op2
= MASK_OP_RRR2_OP2(ctx
->opcode
);
7157 r1
= MASK_OP_RRR2_S1(ctx
->opcode
);
7158 r2
= MASK_OP_RRR2_S2(ctx
->opcode
);
7159 r3
= MASK_OP_RRR2_S3(ctx
->opcode
);
7160 r4
= MASK_OP_RRR2_D(ctx
->opcode
);
7162 case OPC2_32_RRR2_MADD_32
:
7163 gen_madd32_d(cpu_gpr_d
[r4
], cpu_gpr_d
[r1
], cpu_gpr_d
[r3
],
7166 case OPC2_32_RRR2_MADD_64
:
7169 gen_madd64_d(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r1
],
7170 cpu_gpr_d
[r3
], cpu_gpr_d
[r3
+1], cpu_gpr_d
[r2
]);
7172 case OPC2_32_RRR2_MADDS_32
:
7173 gen_helper_madd32_ssov(cpu_gpr_d
[r4
], cpu_env
, cpu_gpr_d
[r1
],
7174 cpu_gpr_d
[r3
], cpu_gpr_d
[r2
]);
7176 case OPC2_32_RRR2_MADDS_64
:
7179 gen_madds_64(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r1
],
7180 cpu_gpr_d
[r3
], cpu_gpr_d
[r3
+1], cpu_gpr_d
[r2
]);
7182 case OPC2_32_RRR2_MADD_U_64
:
7185 gen_maddu64_d(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r1
],
7186 cpu_gpr_d
[r3
], cpu_gpr_d
[r3
+1], cpu_gpr_d
[r2
]);
7188 case OPC2_32_RRR2_MADDS_U_32
:
7189 gen_helper_madd32_suov(cpu_gpr_d
[r4
], cpu_env
, cpu_gpr_d
[r1
],
7190 cpu_gpr_d
[r3
], cpu_gpr_d
[r2
]);
7192 case OPC2_32_RRR2_MADDS_U_64
:
7195 gen_maddsu_64(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r1
],
7196 cpu_gpr_d
[r3
], cpu_gpr_d
[r3
+1], cpu_gpr_d
[r2
]);
7199 generate_trap(ctx
, TRAPC_INSN_ERR
, TIN2_IOPC
);
7203 static void decode_rrr2_msub(CPUTriCoreState
*env
, DisasContext
*ctx
)
7206 uint32_t r1
, r2
, r3
, r4
;
7208 op2
= MASK_OP_RRR2_OP2(ctx
->opcode
);
7209 r1
= MASK_OP_RRR2_S1(ctx
->opcode
);
7210 r2
= MASK_OP_RRR2_S2(ctx
->opcode
);
7211 r3
= MASK_OP_RRR2_S3(ctx
->opcode
);
7212 r4
= MASK_OP_RRR2_D(ctx
->opcode
);
7215 case OPC2_32_RRR2_MSUB_32
:
7216 gen_msub32_d(cpu_gpr_d
[r4
], cpu_gpr_d
[r1
], cpu_gpr_d
[r3
],
7219 case OPC2_32_RRR2_MSUB_64
:
7222 gen_msub64_d(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r1
],
7223 cpu_gpr_d
[r3
], cpu_gpr_d
[r3
+1], cpu_gpr_d
[r2
]);
7225 case OPC2_32_RRR2_MSUBS_32
:
7226 gen_helper_msub32_ssov(cpu_gpr_d
[r4
], cpu_env
, cpu_gpr_d
[r1
],
7227 cpu_gpr_d
[r3
], cpu_gpr_d
[r2
]);
7229 case OPC2_32_RRR2_MSUBS_64
:
7232 gen_msubs_64(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r1
],
7233 cpu_gpr_d
[r3
], cpu_gpr_d
[r3
+1], cpu_gpr_d
[r2
]);
7235 case OPC2_32_RRR2_MSUB_U_64
:
7236 gen_msubu64_d(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r1
],
7237 cpu_gpr_d
[r3
], cpu_gpr_d
[r3
+1], cpu_gpr_d
[r2
]);
7239 case OPC2_32_RRR2_MSUBS_U_32
:
7240 gen_helper_msub32_suov(cpu_gpr_d
[r4
], cpu_env
, cpu_gpr_d
[r1
],
7241 cpu_gpr_d
[r3
], cpu_gpr_d
[r2
]);
7243 case OPC2_32_RRR2_MSUBS_U_64
:
7246 gen_msubsu_64(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r1
],
7247 cpu_gpr_d
[r3
], cpu_gpr_d
[r3
+1], cpu_gpr_d
[r2
]);
7250 generate_trap(ctx
, TRAPC_INSN_ERR
, TIN2_IOPC
);
7255 static void decode_rrr1_madd(CPUTriCoreState
*env
, DisasContext
*ctx
)
7258 uint32_t r1
, r2
, r3
, r4
, n
;
7260 op2
= MASK_OP_RRR1_OP2(ctx
->opcode
);
7261 r1
= MASK_OP_RRR1_S1(ctx
->opcode
);
7262 r2
= MASK_OP_RRR1_S2(ctx
->opcode
);
7263 r3
= MASK_OP_RRR1_S3(ctx
->opcode
);
7264 r4
= MASK_OP_RRR1_D(ctx
->opcode
);
7265 n
= MASK_OP_RRR1_N(ctx
->opcode
);
7268 case OPC2_32_RRR1_MADD_H_LL
:
7271 gen_madd_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
7272 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
], n
, MODE_LL
);
7274 case OPC2_32_RRR1_MADD_H_LU
:
7277 gen_madd_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
7278 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
], n
, MODE_LU
);
7280 case OPC2_32_RRR1_MADD_H_UL
:
7283 gen_madd_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
7284 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
], n
, MODE_UL
);
7286 case OPC2_32_RRR1_MADD_H_UU
:
7289 gen_madd_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
7290 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
], n
, MODE_UU
);
7292 case OPC2_32_RRR1_MADDS_H_LL
:
7295 gen_madds_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
7296 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
], n
, MODE_LL
);
7298 case OPC2_32_RRR1_MADDS_H_LU
:
7301 gen_madds_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
7302 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
], n
, MODE_LU
);
7304 case OPC2_32_RRR1_MADDS_H_UL
:
7307 gen_madds_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
7308 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
], n
, MODE_UL
);
7310 case OPC2_32_RRR1_MADDS_H_UU
:
7313 gen_madds_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
7314 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
], n
, MODE_UU
);
7316 case OPC2_32_RRR1_MADDM_H_LL
:
7319 gen_maddm_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
7320 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
], n
, MODE_LL
);
7322 case OPC2_32_RRR1_MADDM_H_LU
:
7325 gen_maddm_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
7326 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
], n
, MODE_LU
);
7328 case OPC2_32_RRR1_MADDM_H_UL
:
7331 gen_maddm_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
7332 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
], n
, MODE_UL
);
7334 case OPC2_32_RRR1_MADDM_H_UU
:
7337 gen_maddm_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
7338 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
], n
, MODE_UU
);
7340 case OPC2_32_RRR1_MADDMS_H_LL
:
7343 gen_maddms_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
7344 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
], n
, MODE_LL
);
7346 case OPC2_32_RRR1_MADDMS_H_LU
:
7349 gen_maddms_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
7350 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
], n
, MODE_LU
);
7352 case OPC2_32_RRR1_MADDMS_H_UL
:
7355 gen_maddms_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
7356 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
], n
, MODE_UL
);
7358 case OPC2_32_RRR1_MADDMS_H_UU
:
7361 gen_maddms_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
7362 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
], n
, MODE_UU
);
7364 case OPC2_32_RRR1_MADDR_H_LL
:
7365 gen_maddr32_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
7366 cpu_gpr_d
[r2
], n
, MODE_LL
);
7368 case OPC2_32_RRR1_MADDR_H_LU
:
7369 gen_maddr32_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
7370 cpu_gpr_d
[r2
], n
, MODE_LU
);
7372 case OPC2_32_RRR1_MADDR_H_UL
:
7373 gen_maddr32_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
7374 cpu_gpr_d
[r2
], n
, MODE_UL
);
7376 case OPC2_32_RRR1_MADDR_H_UU
:
7377 gen_maddr32_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
7378 cpu_gpr_d
[r2
], n
, MODE_UU
);
7380 case OPC2_32_RRR1_MADDRS_H_LL
:
7381 gen_maddr32s_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
7382 cpu_gpr_d
[r2
], n
, MODE_LL
);
7384 case OPC2_32_RRR1_MADDRS_H_LU
:
7385 gen_maddr32s_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
7386 cpu_gpr_d
[r2
], n
, MODE_LU
);
7388 case OPC2_32_RRR1_MADDRS_H_UL
:
7389 gen_maddr32s_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
7390 cpu_gpr_d
[r2
], n
, MODE_UL
);
7392 case OPC2_32_RRR1_MADDRS_H_UU
:
7393 gen_maddr32s_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
7394 cpu_gpr_d
[r2
], n
, MODE_UU
);
7397 generate_trap(ctx
, TRAPC_INSN_ERR
, TIN2_IOPC
);
7401 static void decode_rrr1_maddq_h(CPUTriCoreState
*env
, DisasContext
*ctx
)
7404 uint32_t r1
, r2
, r3
, r4
, n
;
7407 op2
= MASK_OP_RRR1_OP2(ctx
->opcode
);
7408 r1
= MASK_OP_RRR1_S1(ctx
->opcode
);
7409 r2
= MASK_OP_RRR1_S2(ctx
->opcode
);
7410 r3
= MASK_OP_RRR1_S3(ctx
->opcode
);
7411 r4
= MASK_OP_RRR1_D(ctx
->opcode
);
7412 n
= MASK_OP_RRR1_N(ctx
->opcode
);
7414 temp
= tcg_const_i32(n
);
7415 temp2
= tcg_temp_new();
7418 case OPC2_32_RRR1_MADD_Q_32
:
7419 gen_madd32_q(cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
7420 cpu_gpr_d
[r2
], n
, 32, env
);
7422 case OPC2_32_RRR1_MADD_Q_64
:
7425 gen_madd64_q(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
7426 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
7429 case OPC2_32_RRR1_MADD_Q_32_L
:
7430 tcg_gen_ext16s_tl(temp
, cpu_gpr_d
[r2
]);
7431 gen_madd32_q(cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
7434 case OPC2_32_RRR1_MADD_Q_64_L
:
7437 tcg_gen_ext16s_tl(temp
, cpu_gpr_d
[r2
]);
7438 gen_madd64_q(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
7439 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], temp
,
7442 case OPC2_32_RRR1_MADD_Q_32_U
:
7443 tcg_gen_sari_tl(temp
, cpu_gpr_d
[r2
], 16);
7444 gen_madd32_q(cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
7447 case OPC2_32_RRR1_MADD_Q_64_U
:
7450 tcg_gen_sari_tl(temp
, cpu_gpr_d
[r2
], 16);
7451 gen_madd64_q(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
7452 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], temp
,
7455 case OPC2_32_RRR1_MADD_Q_32_LL
:
7456 tcg_gen_ext16s_tl(temp
, cpu_gpr_d
[r1
]);
7457 tcg_gen_ext16s_tl(temp2
, cpu_gpr_d
[r2
]);
7458 gen_m16add32_q(cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], temp
, temp2
, n
);
7460 case OPC2_32_RRR1_MADD_Q_64_LL
:
7463 tcg_gen_ext16s_tl(temp
, cpu_gpr_d
[r1
]);
7464 tcg_gen_ext16s_tl(temp2
, cpu_gpr_d
[r2
]);
7465 gen_m16add64_q(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
7466 cpu_gpr_d
[r3
+1], temp
, temp2
, n
);
7468 case OPC2_32_RRR1_MADD_Q_32_UU
:
7469 tcg_gen_sari_tl(temp
, cpu_gpr_d
[r1
], 16);
7470 tcg_gen_sari_tl(temp2
, cpu_gpr_d
[r2
], 16);
7471 gen_m16add32_q(cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], temp
, temp2
, n
);
7473 case OPC2_32_RRR1_MADD_Q_64_UU
:
7476 tcg_gen_sari_tl(temp
, cpu_gpr_d
[r1
], 16);
7477 tcg_gen_sari_tl(temp2
, cpu_gpr_d
[r2
], 16);
7478 gen_m16add64_q(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
7479 cpu_gpr_d
[r3
+1], temp
, temp2
, n
);
7481 case OPC2_32_RRR1_MADDS_Q_32
:
7482 gen_madds32_q(cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
7483 cpu_gpr_d
[r2
], n
, 32);
7485 case OPC2_32_RRR1_MADDS_Q_64
:
7488 gen_madds64_q(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
7489 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
7492 case OPC2_32_RRR1_MADDS_Q_32_L
:
7493 tcg_gen_ext16s_tl(temp
, cpu_gpr_d
[r2
]);
7494 gen_madds32_q(cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
7497 case OPC2_32_RRR1_MADDS_Q_64_L
:
7500 tcg_gen_ext16s_tl(temp
, cpu_gpr_d
[r2
]);
7501 gen_madds64_q(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
7502 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], temp
,
7505 case OPC2_32_RRR1_MADDS_Q_32_U
:
7506 tcg_gen_sari_tl(temp
, cpu_gpr_d
[r2
], 16);
7507 gen_madds32_q(cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
7510 case OPC2_32_RRR1_MADDS_Q_64_U
:
7513 tcg_gen_sari_tl(temp
, cpu_gpr_d
[r2
], 16);
7514 gen_madds64_q(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
7515 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], temp
,
7518 case OPC2_32_RRR1_MADDS_Q_32_LL
:
7519 tcg_gen_ext16s_tl(temp
, cpu_gpr_d
[r1
]);
7520 tcg_gen_ext16s_tl(temp2
, cpu_gpr_d
[r2
]);
7521 gen_m16adds32_q(cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], temp
, temp2
, n
);
7523 case OPC2_32_RRR1_MADDS_Q_64_LL
:
7526 tcg_gen_ext16s_tl(temp
, cpu_gpr_d
[r1
]);
7527 tcg_gen_ext16s_tl(temp2
, cpu_gpr_d
[r2
]);
7528 gen_m16adds64_q(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
7529 cpu_gpr_d
[r3
+1], temp
, temp2
, n
);
7531 case OPC2_32_RRR1_MADDS_Q_32_UU
:
7532 tcg_gen_sari_tl(temp
, cpu_gpr_d
[r1
], 16);
7533 tcg_gen_sari_tl(temp2
, cpu_gpr_d
[r2
], 16);
7534 gen_m16adds32_q(cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], temp
, temp2
, n
);
7536 case OPC2_32_RRR1_MADDS_Q_64_UU
:
7539 tcg_gen_sari_tl(temp
, cpu_gpr_d
[r1
], 16);
7540 tcg_gen_sari_tl(temp2
, cpu_gpr_d
[r2
], 16);
7541 gen_m16adds64_q(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
7542 cpu_gpr_d
[r3
+1], temp
, temp2
, n
);
7544 case OPC2_32_RRR1_MADDR_H_64_UL
:
7546 gen_maddr64_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], cpu_gpr_d
[r3
+1],
7547 cpu_gpr_d
[r1
], cpu_gpr_d
[r2
], n
, 2);
7549 case OPC2_32_RRR1_MADDRS_H_64_UL
:
7551 gen_maddr64s_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], cpu_gpr_d
[r3
+1],
7552 cpu_gpr_d
[r1
], cpu_gpr_d
[r2
], n
, 2);
7554 case OPC2_32_RRR1_MADDR_Q_32_LL
:
7555 tcg_gen_ext16s_tl(temp
, cpu_gpr_d
[r1
]);
7556 tcg_gen_ext16s_tl(temp2
, cpu_gpr_d
[r2
]);
7557 gen_maddr_q(cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], temp
, temp2
, n
);
7559 case OPC2_32_RRR1_MADDR_Q_32_UU
:
7560 tcg_gen_sari_tl(temp
, cpu_gpr_d
[r1
], 16);
7561 tcg_gen_sari_tl(temp2
, cpu_gpr_d
[r2
], 16);
7562 gen_maddr_q(cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], temp
, temp2
, n
);
7564 case OPC2_32_RRR1_MADDRS_Q_32_LL
:
7565 tcg_gen_ext16s_tl(temp
, cpu_gpr_d
[r1
]);
7566 tcg_gen_ext16s_tl(temp2
, cpu_gpr_d
[r2
]);
7567 gen_maddrs_q(cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], temp
, temp2
, n
);
7569 case OPC2_32_RRR1_MADDRS_Q_32_UU
:
7570 tcg_gen_sari_tl(temp
, cpu_gpr_d
[r1
], 16);
7571 tcg_gen_sari_tl(temp2
, cpu_gpr_d
[r2
], 16);
7572 gen_maddrs_q(cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], temp
, temp2
, n
);
7575 generate_trap(ctx
, TRAPC_INSN_ERR
, TIN2_IOPC
);
7577 tcg_temp_free(temp
);
7578 tcg_temp_free(temp2
);
7581 static void decode_rrr1_maddsu_h(CPUTriCoreState
*env
, DisasContext
*ctx
)
7584 uint32_t r1
, r2
, r3
, r4
, n
;
7586 op2
= MASK_OP_RRR1_OP2(ctx
->opcode
);
7587 r1
= MASK_OP_RRR1_S1(ctx
->opcode
);
7588 r2
= MASK_OP_RRR1_S2(ctx
->opcode
);
7589 r3
= MASK_OP_RRR1_S3(ctx
->opcode
);
7590 r4
= MASK_OP_RRR1_D(ctx
->opcode
);
7591 n
= MASK_OP_RRR1_N(ctx
->opcode
);
7594 case OPC2_32_RRR1_MADDSU_H_32_LL
:
7597 gen_maddsu_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
7598 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
], n
, MODE_LL
);
7600 case OPC2_32_RRR1_MADDSU_H_32_LU
:
7603 gen_maddsu_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
7604 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
], n
, MODE_LU
);
7606 case OPC2_32_RRR1_MADDSU_H_32_UL
:
7609 gen_maddsu_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
7610 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
], n
, MODE_UL
);
7612 case OPC2_32_RRR1_MADDSU_H_32_UU
:
7615 gen_maddsu_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
7616 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
], n
, MODE_UU
);
7618 case OPC2_32_RRR1_MADDSUS_H_32_LL
:
7621 gen_maddsus_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
7622 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
7625 case OPC2_32_RRR1_MADDSUS_H_32_LU
:
7628 gen_maddsus_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
7629 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
7632 case OPC2_32_RRR1_MADDSUS_H_32_UL
:
7635 gen_maddsus_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
7636 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
7639 case OPC2_32_RRR1_MADDSUS_H_32_UU
:
7642 gen_maddsus_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
7643 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
7646 case OPC2_32_RRR1_MADDSUM_H_64_LL
:
7649 gen_maddsum_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
7650 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
7653 case OPC2_32_RRR1_MADDSUM_H_64_LU
:
7656 gen_maddsum_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
7657 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
7660 case OPC2_32_RRR1_MADDSUM_H_64_UL
:
7663 gen_maddsum_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
7664 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
7667 case OPC2_32_RRR1_MADDSUM_H_64_UU
:
7670 gen_maddsum_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
7671 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
7674 case OPC2_32_RRR1_MADDSUMS_H_64_LL
:
7677 gen_maddsums_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
7678 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
7681 case OPC2_32_RRR1_MADDSUMS_H_64_LU
:
7684 gen_maddsums_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
7685 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
7688 case OPC2_32_RRR1_MADDSUMS_H_64_UL
:
7691 gen_maddsums_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
7692 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
7695 case OPC2_32_RRR1_MADDSUMS_H_64_UU
:
7698 gen_maddsums_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
7699 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
7702 case OPC2_32_RRR1_MADDSUR_H_16_LL
:
7703 gen_maddsur32_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
7704 cpu_gpr_d
[r2
], n
, MODE_LL
);
7706 case OPC2_32_RRR1_MADDSUR_H_16_LU
:
7707 gen_maddsur32_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
7708 cpu_gpr_d
[r2
], n
, MODE_LU
);
7710 case OPC2_32_RRR1_MADDSUR_H_16_UL
:
7711 gen_maddsur32_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
7712 cpu_gpr_d
[r2
], n
, MODE_UL
);
7714 case OPC2_32_RRR1_MADDSUR_H_16_UU
:
7715 gen_maddsur32_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
7716 cpu_gpr_d
[r2
], n
, MODE_UU
);
7718 case OPC2_32_RRR1_MADDSURS_H_16_LL
:
7719 gen_maddsur32s_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
7720 cpu_gpr_d
[r2
], n
, MODE_LL
);
7722 case OPC2_32_RRR1_MADDSURS_H_16_LU
:
7723 gen_maddsur32s_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
7724 cpu_gpr_d
[r2
], n
, MODE_LU
);
7726 case OPC2_32_RRR1_MADDSURS_H_16_UL
:
7727 gen_maddsur32s_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
7728 cpu_gpr_d
[r2
], n
, MODE_UL
);
7730 case OPC2_32_RRR1_MADDSURS_H_16_UU
:
7731 gen_maddsur32s_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
7732 cpu_gpr_d
[r2
], n
, MODE_UU
);
7735 generate_trap(ctx
, TRAPC_INSN_ERR
, TIN2_IOPC
);
7739 static void decode_rrr1_msub(CPUTriCoreState
*env
, DisasContext
*ctx
)
7742 uint32_t r1
, r2
, r3
, r4
, n
;
7744 op2
= MASK_OP_RRR1_OP2(ctx
->opcode
);
7745 r1
= MASK_OP_RRR1_S1(ctx
->opcode
);
7746 r2
= MASK_OP_RRR1_S2(ctx
->opcode
);
7747 r3
= MASK_OP_RRR1_S3(ctx
->opcode
);
7748 r4
= MASK_OP_RRR1_D(ctx
->opcode
);
7749 n
= MASK_OP_RRR1_N(ctx
->opcode
);
7752 case OPC2_32_RRR1_MSUB_H_LL
:
7755 gen_msub_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
7756 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
], n
, MODE_LL
);
7758 case OPC2_32_RRR1_MSUB_H_LU
:
7761 gen_msub_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
7762 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
], n
, MODE_LU
);
7764 case OPC2_32_RRR1_MSUB_H_UL
:
7767 gen_msub_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
7768 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
], n
, MODE_UL
);
7770 case OPC2_32_RRR1_MSUB_H_UU
:
7773 gen_msub_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
7774 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
], n
, MODE_UU
);
7776 case OPC2_32_RRR1_MSUBS_H_LL
:
7779 gen_msubs_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
7780 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
], n
, MODE_LL
);
7782 case OPC2_32_RRR1_MSUBS_H_LU
:
7785 gen_msubs_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
7786 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
], n
, MODE_LU
);
7788 case OPC2_32_RRR1_MSUBS_H_UL
:
7791 gen_msubs_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
7792 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
], n
, MODE_UL
);
7794 case OPC2_32_RRR1_MSUBS_H_UU
:
7797 gen_msubs_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
7798 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
], n
, MODE_UU
);
7800 case OPC2_32_RRR1_MSUBM_H_LL
:
7803 gen_msubm_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
7804 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
], n
, MODE_LL
);
7806 case OPC2_32_RRR1_MSUBM_H_LU
:
7809 gen_msubm_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
7810 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
], n
, MODE_LU
);
7812 case OPC2_32_RRR1_MSUBM_H_UL
:
7815 gen_msubm_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
7816 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
], n
, MODE_UL
);
7818 case OPC2_32_RRR1_MSUBM_H_UU
:
7821 gen_msubm_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
7822 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
], n
, MODE_UU
);
7824 case OPC2_32_RRR1_MSUBMS_H_LL
:
7827 gen_msubms_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
7828 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
], n
, MODE_LL
);
7830 case OPC2_32_RRR1_MSUBMS_H_LU
:
7833 gen_msubms_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
7834 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
], n
, MODE_LU
);
7836 case OPC2_32_RRR1_MSUBMS_H_UL
:
7839 gen_msubms_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
7840 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
], n
, MODE_UL
);
7842 case OPC2_32_RRR1_MSUBMS_H_UU
:
7845 gen_msubms_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
7846 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
], n
, MODE_UU
);
7848 case OPC2_32_RRR1_MSUBR_H_LL
:
7849 gen_msubr32_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
7850 cpu_gpr_d
[r2
], n
, MODE_LL
);
7852 case OPC2_32_RRR1_MSUBR_H_LU
:
7853 gen_msubr32_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
7854 cpu_gpr_d
[r2
], n
, MODE_LU
);
7856 case OPC2_32_RRR1_MSUBR_H_UL
:
7857 gen_msubr32_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
7858 cpu_gpr_d
[r2
], n
, MODE_UL
);
7860 case OPC2_32_RRR1_MSUBR_H_UU
:
7861 gen_msubr32_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
7862 cpu_gpr_d
[r2
], n
, MODE_UU
);
7864 case OPC2_32_RRR1_MSUBRS_H_LL
:
7865 gen_msubr32s_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
7866 cpu_gpr_d
[r2
], n
, MODE_LL
);
7868 case OPC2_32_RRR1_MSUBRS_H_LU
:
7869 gen_msubr32s_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
7870 cpu_gpr_d
[r2
], n
, MODE_LU
);
7872 case OPC2_32_RRR1_MSUBRS_H_UL
:
7873 gen_msubr32s_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
7874 cpu_gpr_d
[r2
], n
, MODE_UL
);
7876 case OPC2_32_RRR1_MSUBRS_H_UU
:
7877 gen_msubr32s_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
7878 cpu_gpr_d
[r2
], n
, MODE_UU
);
7881 generate_trap(ctx
, TRAPC_INSN_ERR
, TIN2_IOPC
);
7885 static void decode_rrr1_msubq_h(CPUTriCoreState
*env
, DisasContext
*ctx
)
7888 uint32_t r1
, r2
, r3
, r4
, n
;
7891 op2
= MASK_OP_RRR1_OP2(ctx
->opcode
);
7892 r1
= MASK_OP_RRR1_S1(ctx
->opcode
);
7893 r2
= MASK_OP_RRR1_S2(ctx
->opcode
);
7894 r3
= MASK_OP_RRR1_S3(ctx
->opcode
);
7895 r4
= MASK_OP_RRR1_D(ctx
->opcode
);
7896 n
= MASK_OP_RRR1_N(ctx
->opcode
);
7898 temp
= tcg_const_i32(n
);
7899 temp2
= tcg_temp_new();
7902 case OPC2_32_RRR1_MSUB_Q_32
:
7903 gen_msub32_q(cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
7904 cpu_gpr_d
[r2
], n
, 32, env
);
7906 case OPC2_32_RRR1_MSUB_Q_64
:
7909 gen_msub64_q(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
7910 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
7913 case OPC2_32_RRR1_MSUB_Q_32_L
:
7914 tcg_gen_ext16s_tl(temp
, cpu_gpr_d
[r2
]);
7915 gen_msub32_q(cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
7918 case OPC2_32_RRR1_MSUB_Q_64_L
:
7921 tcg_gen_ext16s_tl(temp
, cpu_gpr_d
[r2
]);
7922 gen_msub64_q(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
7923 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], temp
,
7926 case OPC2_32_RRR1_MSUB_Q_32_U
:
7927 tcg_gen_sari_tl(temp
, cpu_gpr_d
[r2
], 16);
7928 gen_msub32_q(cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
7931 case OPC2_32_RRR1_MSUB_Q_64_U
:
7934 tcg_gen_sari_tl(temp
, cpu_gpr_d
[r2
], 16);
7935 gen_msub64_q(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
7936 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], temp
,
7939 case OPC2_32_RRR1_MSUB_Q_32_LL
:
7940 tcg_gen_ext16s_tl(temp
, cpu_gpr_d
[r1
]);
7941 tcg_gen_ext16s_tl(temp2
, cpu_gpr_d
[r2
]);
7942 gen_m16sub32_q(cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], temp
, temp2
, n
);
7944 case OPC2_32_RRR1_MSUB_Q_64_LL
:
7947 tcg_gen_ext16s_tl(temp
, cpu_gpr_d
[r1
]);
7948 tcg_gen_ext16s_tl(temp2
, cpu_gpr_d
[r2
]);
7949 gen_m16sub64_q(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
7950 cpu_gpr_d
[r3
+1], temp
, temp2
, n
);
7952 case OPC2_32_RRR1_MSUB_Q_32_UU
:
7953 tcg_gen_sari_tl(temp
, cpu_gpr_d
[r1
], 16);
7954 tcg_gen_sari_tl(temp2
, cpu_gpr_d
[r2
], 16);
7955 gen_m16sub32_q(cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], temp
, temp2
, n
);
7957 case OPC2_32_RRR1_MSUB_Q_64_UU
:
7960 tcg_gen_sari_tl(temp
, cpu_gpr_d
[r1
], 16);
7961 tcg_gen_sari_tl(temp2
, cpu_gpr_d
[r2
], 16);
7962 gen_m16sub64_q(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
7963 cpu_gpr_d
[r3
+1], temp
, temp2
, n
);
7965 case OPC2_32_RRR1_MSUBS_Q_32
:
7966 gen_msubs32_q(cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
7967 cpu_gpr_d
[r2
], n
, 32);
7969 case OPC2_32_RRR1_MSUBS_Q_64
:
7972 gen_msubs64_q(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
7973 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
7976 case OPC2_32_RRR1_MSUBS_Q_32_L
:
7977 tcg_gen_ext16s_tl(temp
, cpu_gpr_d
[r2
]);
7978 gen_msubs32_q(cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
7981 case OPC2_32_RRR1_MSUBS_Q_64_L
:
7984 tcg_gen_ext16s_tl(temp
, cpu_gpr_d
[r2
]);
7985 gen_msubs64_q(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
7986 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], temp
,
7989 case OPC2_32_RRR1_MSUBS_Q_32_U
:
7990 tcg_gen_sari_tl(temp
, cpu_gpr_d
[r2
], 16);
7991 gen_msubs32_q(cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
7994 case OPC2_32_RRR1_MSUBS_Q_64_U
:
7997 tcg_gen_sari_tl(temp
, cpu_gpr_d
[r2
], 16);
7998 gen_msubs64_q(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
7999 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], temp
,
8002 case OPC2_32_RRR1_MSUBS_Q_32_LL
:
8003 tcg_gen_ext16s_tl(temp
, cpu_gpr_d
[r1
]);
8004 tcg_gen_ext16s_tl(temp2
, cpu_gpr_d
[r2
]);
8005 gen_m16subs32_q(cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], temp
, temp2
, n
);
8007 case OPC2_32_RRR1_MSUBS_Q_64_LL
:
8010 tcg_gen_ext16s_tl(temp
, cpu_gpr_d
[r1
]);
8011 tcg_gen_ext16s_tl(temp2
, cpu_gpr_d
[r2
]);
8012 gen_m16subs64_q(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
8013 cpu_gpr_d
[r3
+1], temp
, temp2
, n
);
8015 case OPC2_32_RRR1_MSUBS_Q_32_UU
:
8016 tcg_gen_sari_tl(temp
, cpu_gpr_d
[r1
], 16);
8017 tcg_gen_sari_tl(temp2
, cpu_gpr_d
[r2
], 16);
8018 gen_m16subs32_q(cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], temp
, temp2
, n
);
8020 case OPC2_32_RRR1_MSUBS_Q_64_UU
:
8023 tcg_gen_sari_tl(temp
, cpu_gpr_d
[r1
], 16);
8024 tcg_gen_sari_tl(temp2
, cpu_gpr_d
[r2
], 16);
8025 gen_m16subs64_q(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
8026 cpu_gpr_d
[r3
+1], temp
, temp2
, n
);
8028 case OPC2_32_RRR1_MSUBR_H_64_UL
:
8030 gen_msubr64_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], cpu_gpr_d
[r3
+1],
8031 cpu_gpr_d
[r1
], cpu_gpr_d
[r2
], n
, 2);
8033 case OPC2_32_RRR1_MSUBRS_H_64_UL
:
8035 gen_msubr64s_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], cpu_gpr_d
[r3
+1],
8036 cpu_gpr_d
[r1
], cpu_gpr_d
[r2
], n
, 2);
8038 case OPC2_32_RRR1_MSUBR_Q_32_LL
:
8039 tcg_gen_ext16s_tl(temp
, cpu_gpr_d
[r1
]);
8040 tcg_gen_ext16s_tl(temp2
, cpu_gpr_d
[r2
]);
8041 gen_msubr_q(cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], temp
, temp2
, n
);
8043 case OPC2_32_RRR1_MSUBR_Q_32_UU
:
8044 tcg_gen_sari_tl(temp
, cpu_gpr_d
[r1
], 16);
8045 tcg_gen_sari_tl(temp2
, cpu_gpr_d
[r2
], 16);
8046 gen_msubr_q(cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], temp
, temp2
, n
);
8048 case OPC2_32_RRR1_MSUBRS_Q_32_LL
:
8049 tcg_gen_ext16s_tl(temp
, cpu_gpr_d
[r1
]);
8050 tcg_gen_ext16s_tl(temp2
, cpu_gpr_d
[r2
]);
8051 gen_msubrs_q(cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], temp
, temp2
, n
);
8053 case OPC2_32_RRR1_MSUBRS_Q_32_UU
:
8054 tcg_gen_sari_tl(temp
, cpu_gpr_d
[r1
], 16);
8055 tcg_gen_sari_tl(temp2
, cpu_gpr_d
[r2
], 16);
8056 gen_msubrs_q(cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], temp
, temp2
, n
);
8059 generate_trap(ctx
, TRAPC_INSN_ERR
, TIN2_IOPC
);
8061 tcg_temp_free(temp
);
8062 tcg_temp_free(temp2
);
8065 static void decode_rrr1_msubad_h(CPUTriCoreState
*env
, DisasContext
*ctx
)
8068 uint32_t r1
, r2
, r3
, r4
, n
;
8070 op2
= MASK_OP_RRR1_OP2(ctx
->opcode
);
8071 r1
= MASK_OP_RRR1_S1(ctx
->opcode
);
8072 r2
= MASK_OP_RRR1_S2(ctx
->opcode
);
8073 r3
= MASK_OP_RRR1_S3(ctx
->opcode
);
8074 r4
= MASK_OP_RRR1_D(ctx
->opcode
);
8075 n
= MASK_OP_RRR1_N(ctx
->opcode
);
8078 case OPC2_32_RRR1_MSUBAD_H_32_LL
:
8081 gen_msubad_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
8082 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
], n
, MODE_LL
);
8084 case OPC2_32_RRR1_MSUBAD_H_32_LU
:
8087 gen_msubad_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
8088 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
], n
, MODE_LU
);
8090 case OPC2_32_RRR1_MSUBAD_H_32_UL
:
8093 gen_msubad_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
8094 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
], n
, MODE_UL
);
8096 case OPC2_32_RRR1_MSUBAD_H_32_UU
:
8099 gen_msubad_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
8100 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
], n
, MODE_UU
);
8102 case OPC2_32_RRR1_MSUBADS_H_32_LL
:
8105 gen_msubads_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
8106 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
8109 case OPC2_32_RRR1_MSUBADS_H_32_LU
:
8112 gen_msubads_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
8113 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
8116 case OPC2_32_RRR1_MSUBADS_H_32_UL
:
8119 gen_msubads_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
8120 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
8123 case OPC2_32_RRR1_MSUBADS_H_32_UU
:
8126 gen_msubads_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
8127 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
8130 case OPC2_32_RRR1_MSUBADM_H_64_LL
:
8133 gen_msubadm_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
8134 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
8137 case OPC2_32_RRR1_MSUBADM_H_64_LU
:
8140 gen_msubadm_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
8141 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
8144 case OPC2_32_RRR1_MSUBADM_H_64_UL
:
8147 gen_msubadm_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
8148 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
8151 case OPC2_32_RRR1_MSUBADM_H_64_UU
:
8154 gen_msubadm_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
8155 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
8158 case OPC2_32_RRR1_MSUBADMS_H_64_LL
:
8161 gen_msubadms_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
8162 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
8165 case OPC2_32_RRR1_MSUBADMS_H_64_LU
:
8168 gen_msubadms_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
8169 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
8172 case OPC2_32_RRR1_MSUBADMS_H_64_UL
:
8175 gen_msubadms_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
8176 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
8179 case OPC2_32_RRR1_MSUBADMS_H_64_UU
:
8182 gen_msubadms_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
8183 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
8186 case OPC2_32_RRR1_MSUBADR_H_16_LL
:
8187 gen_msubadr32_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
8188 cpu_gpr_d
[r2
], n
, MODE_LL
);
8190 case OPC2_32_RRR1_MSUBADR_H_16_LU
:
8191 gen_msubadr32_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
8192 cpu_gpr_d
[r2
], n
, MODE_LU
);
8194 case OPC2_32_RRR1_MSUBADR_H_16_UL
:
8195 gen_msubadr32_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
8196 cpu_gpr_d
[r2
], n
, MODE_UL
);
8198 case OPC2_32_RRR1_MSUBADR_H_16_UU
:
8199 gen_msubadr32_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
8200 cpu_gpr_d
[r2
], n
, MODE_UU
);
8202 case OPC2_32_RRR1_MSUBADRS_H_16_LL
:
8203 gen_msubadr32s_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
8204 cpu_gpr_d
[r2
], n
, MODE_LL
);
8206 case OPC2_32_RRR1_MSUBADRS_H_16_LU
:
8207 gen_msubadr32s_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
8208 cpu_gpr_d
[r2
], n
, MODE_LU
);
8210 case OPC2_32_RRR1_MSUBADRS_H_16_UL
:
8211 gen_msubadr32s_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
8212 cpu_gpr_d
[r2
], n
, MODE_UL
);
8214 case OPC2_32_RRR1_MSUBADRS_H_16_UU
:
8215 gen_msubadr32s_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
8216 cpu_gpr_d
[r2
], n
, MODE_UU
);
8219 generate_trap(ctx
, TRAPC_INSN_ERR
, TIN2_IOPC
);
8224 static void decode_rrrr_extract_insert(CPUTriCoreState
*env
, DisasContext
*ctx
)
8228 TCGv tmp_width
, tmp_pos
;
8230 r1
= MASK_OP_RRRR_S1(ctx
->opcode
);
8231 r2
= MASK_OP_RRRR_S2(ctx
->opcode
);
8232 r3
= MASK_OP_RRRR_S3(ctx
->opcode
);
8233 r4
= MASK_OP_RRRR_D(ctx
->opcode
);
8234 op2
= MASK_OP_RRRR_OP2(ctx
->opcode
);
8236 tmp_pos
= tcg_temp_new();
8237 tmp_width
= tcg_temp_new();
8240 case OPC2_32_RRRR_DEXTR
:
8241 tcg_gen_andi_tl(tmp_pos
, cpu_gpr_d
[r3
], 0x1f);
8243 tcg_gen_rotl_tl(cpu_gpr_d
[r4
], cpu_gpr_d
[r1
], tmp_pos
);
8245 tcg_gen_shl_tl(tmp_width
, cpu_gpr_d
[r1
], tmp_pos
);
8246 tcg_gen_subfi_tl(tmp_pos
, 32, tmp_pos
);
8247 tcg_gen_shr_tl(tmp_pos
, cpu_gpr_d
[r2
], tmp_pos
);
8248 tcg_gen_or_tl(cpu_gpr_d
[r4
], tmp_width
, tmp_pos
);
8251 case OPC2_32_RRRR_EXTR
:
8252 case OPC2_32_RRRR_EXTR_U
:
8254 tcg_gen_andi_tl(tmp_width
, cpu_gpr_d
[r3
+1], 0x1f);
8255 tcg_gen_andi_tl(tmp_pos
, cpu_gpr_d
[r3
], 0x1f);
8256 tcg_gen_add_tl(tmp_pos
, tmp_pos
, tmp_width
);
8257 tcg_gen_subfi_tl(tmp_pos
, 32, tmp_pos
);
8258 tcg_gen_shl_tl(cpu_gpr_d
[r4
], cpu_gpr_d
[r1
], tmp_pos
);
8259 tcg_gen_subfi_tl(tmp_width
, 32, tmp_width
);
8260 if (op2
== OPC2_32_RRRR_EXTR
) {
8261 tcg_gen_sar_tl(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
], tmp_width
);
8263 tcg_gen_shr_tl(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
], tmp_width
);
8266 case OPC2_32_RRRR_INSERT
:
8268 tcg_gen_andi_tl(tmp_width
, cpu_gpr_d
[r3
+1], 0x1f);
8269 tcg_gen_andi_tl(tmp_pos
, cpu_gpr_d
[r3
], 0x1f);
8270 gen_insert(cpu_gpr_d
[r4
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
], tmp_width
,
8274 generate_trap(ctx
, TRAPC_INSN_ERR
, TIN2_IOPC
);
8276 tcg_temp_free(tmp_pos
);
8277 tcg_temp_free(tmp_width
);
8281 static void decode_rrrw_extract_insert(CPUTriCoreState
*env
, DisasContext
*ctx
)
8289 op2
= MASK_OP_RRRW_OP2(ctx
->opcode
);
8290 r1
= MASK_OP_RRRW_S1(ctx
->opcode
);
8291 r2
= MASK_OP_RRRW_S2(ctx
->opcode
);
8292 r3
= MASK_OP_RRRW_S3(ctx
->opcode
);
8293 r4
= MASK_OP_RRRW_D(ctx
->opcode
);
8294 width
= MASK_OP_RRRW_WIDTH(ctx
->opcode
);
8296 temp
= tcg_temp_new();
8299 case OPC2_32_RRRW_EXTR
:
8300 tcg_gen_andi_tl(temp
, cpu_gpr_d
[r3
], 0x1f);
8301 tcg_gen_addi_tl(temp
, temp
, width
);
8302 tcg_gen_subfi_tl(temp
, 32, temp
);
8303 tcg_gen_shl_tl(cpu_gpr_d
[r4
], cpu_gpr_d
[r1
], temp
);
8304 tcg_gen_sari_tl(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
], 32 - width
);
8306 case OPC2_32_RRRW_EXTR_U
:
8308 tcg_gen_movi_tl(cpu_gpr_d
[r4
], 0);
8310 tcg_gen_andi_tl(temp
, cpu_gpr_d
[r3
], 0x1f);
8311 tcg_gen_shr_tl(cpu_gpr_d
[r4
], cpu_gpr_d
[r1
], temp
);
8312 tcg_gen_andi_tl(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
], ~0u >> (32-width
));
8315 case OPC2_32_RRRW_IMASK
:
8316 temp2
= tcg_temp_new();
8318 tcg_gen_andi_tl(temp
, cpu_gpr_d
[r3
], 0x1f);
8319 tcg_gen_movi_tl(temp2
, (1 << width
) - 1);
8320 tcg_gen_shl_tl(temp2
, temp2
, temp
);
8321 tcg_gen_shl_tl(cpu_gpr_d
[r4
], cpu_gpr_d
[r2
], temp
);
8322 tcg_gen_mov_tl(cpu_gpr_d
[r4
+1], temp2
);
8324 tcg_temp_free(temp2
);
8326 case OPC2_32_RRRW_INSERT
:
8327 temp2
= tcg_temp_new();
8329 tcg_gen_movi_tl(temp
, width
);
8330 tcg_gen_andi_tl(temp2
, cpu_gpr_d
[r3
], 0x1f);
8331 gen_insert(cpu_gpr_d
[r4
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
], temp
, temp2
);
8333 tcg_temp_free(temp2
);
8336 generate_trap(ctx
, TRAPC_INSN_ERR
, TIN2_IOPC
);
8338 tcg_temp_free(temp
);
8342 static void decode_sys_interrupts(CPUTriCoreState
*env
, DisasContext
*ctx
)
8349 op2
= MASK_OP_SYS_OP2(ctx
->opcode
);
8350 r1
= MASK_OP_SYS_S1D(ctx
->opcode
);
8353 case OPC2_32_SYS_DEBUG
:
8354 /* raise EXCP_DEBUG */
8356 case OPC2_32_SYS_DISABLE
:
8357 tcg_gen_andi_tl(cpu_ICR
, cpu_ICR
, ~MASK_ICR_IE
);
8359 case OPC2_32_SYS_DSYNC
:
8361 case OPC2_32_SYS_ENABLE
:
8362 tcg_gen_ori_tl(cpu_ICR
, cpu_ICR
, MASK_ICR_IE
);
8364 case OPC2_32_SYS_ISYNC
:
8366 case OPC2_32_SYS_NOP
:
8368 case OPC2_32_SYS_RET
:
8369 gen_compute_branch(ctx
, op2
, 0, 0, 0, 0);
8371 case OPC2_32_SYS_FRET
:
8374 case OPC2_32_SYS_RFE
:
8375 gen_helper_rfe(cpu_env
);
8377 ctx
->bstate
= BS_BRANCH
;
8379 case OPC2_32_SYS_RFM
:
8380 if ((ctx
->hflags
& TRICORE_HFLAG_KUU
) == TRICORE_HFLAG_SM
) {
8381 tmp
= tcg_temp_new();
8382 l1
= gen_new_label();
8384 tcg_gen_ld32u_tl(tmp
, cpu_env
, offsetof(CPUTriCoreState
, DBGSR
));
8385 tcg_gen_andi_tl(tmp
, tmp
, MASK_DBGSR_DE
);
8386 tcg_gen_brcondi_tl(TCG_COND_NE
, tmp
, 1, l1
);
8387 gen_helper_rfm(cpu_env
);
8390 ctx
->bstate
= BS_BRANCH
;
8393 /* generate privilege trap */
8396 case OPC2_32_SYS_RSLCX
:
8397 gen_helper_rslcx(cpu_env
);
8399 case OPC2_32_SYS_SVLCX
:
8400 gen_helper_svlcx(cpu_env
);
8402 case OPC2_32_SYS_RESTORE
:
8403 if (tricore_feature(env
, TRICORE_FEATURE_16
)) {
8404 if ((ctx
->hflags
& TRICORE_HFLAG_KUU
) == TRICORE_HFLAG_SM
||
8405 (ctx
->hflags
& TRICORE_HFLAG_KUU
) == TRICORE_HFLAG_UM1
) {
8406 tcg_gen_deposit_tl(cpu_ICR
, cpu_ICR
, cpu_gpr_d
[r1
], 8, 1);
8407 } /* else raise privilege trap */
8409 generate_trap(ctx
, TRAPC_INSN_ERR
, TIN2_IOPC
);
8412 case OPC2_32_SYS_TRAPSV
:
8413 l1
= gen_new_label();
8414 tcg_gen_brcondi_tl(TCG_COND_GE
, cpu_PSW_SV
, 0, l1
);
8415 generate_trap(ctx
, TRAPC_ASSERT
, TIN5_SOVF
);
8418 case OPC2_32_SYS_TRAPV
:
8419 l1
= gen_new_label();
8420 tcg_gen_brcondi_tl(TCG_COND_GE
, cpu_PSW_V
, 0, l1
);
8421 generate_trap(ctx
, TRAPC_ASSERT
, TIN5_OVF
);
8425 generate_trap(ctx
, TRAPC_INSN_ERR
, TIN2_IOPC
);
8429 static void decode_32Bit_opc(CPUTriCoreState
*env
, DisasContext
*ctx
)
8433 int32_t address
, const16
;
8436 TCGv temp
, temp2
, temp3
;
8438 op1
= MASK_OP_MAJOR(ctx
->opcode
);
8440 /* handle JNZ.T opcode only being 7 bit long */
8441 if (unlikely((op1
& 0x7f) == OPCM_32_BRN_JTT
)) {
8442 op1
= OPCM_32_BRN_JTT
;
8447 case OPCM_32_ABS_LDW
:
8448 decode_abs_ldw(env
, ctx
);
8450 case OPCM_32_ABS_LDB
:
8451 decode_abs_ldb(env
, ctx
);
8453 case OPCM_32_ABS_LDMST_SWAP
:
8454 decode_abs_ldst_swap(env
, ctx
);
8456 case OPCM_32_ABS_LDST_CONTEXT
:
8457 decode_abs_ldst_context(env
, ctx
);
8459 case OPCM_32_ABS_STORE
:
8460 decode_abs_store(env
, ctx
);
8462 case OPCM_32_ABS_STOREB_H
:
8463 decode_abs_storeb_h(env
, ctx
);
8465 case OPC1_32_ABS_STOREQ
:
8466 address
= MASK_OP_ABS_OFF18(ctx
->opcode
);
8467 r1
= MASK_OP_ABS_S1D(ctx
->opcode
);
8468 temp
= tcg_const_i32(EA_ABS_FORMAT(address
));
8469 temp2
= tcg_temp_new();
8471 tcg_gen_shri_tl(temp2
, cpu_gpr_d
[r1
], 16);
8472 tcg_gen_qemu_st_tl(temp2
, temp
, ctx
->mem_idx
, MO_LEUW
);
8474 tcg_temp_free(temp2
);
8475 tcg_temp_free(temp
);
8477 case OPC1_32_ABS_LD_Q
:
8478 address
= MASK_OP_ABS_OFF18(ctx
->opcode
);
8479 r1
= MASK_OP_ABS_S1D(ctx
->opcode
);
8480 temp
= tcg_const_i32(EA_ABS_FORMAT(address
));
8482 tcg_gen_qemu_ld_tl(cpu_gpr_d
[r1
], temp
, ctx
->mem_idx
, MO_LEUW
);
8483 tcg_gen_shli_tl(cpu_gpr_d
[r1
], cpu_gpr_d
[r1
], 16);
8485 tcg_temp_free(temp
);
8487 case OPC1_32_ABS_LEA
:
8488 address
= MASK_OP_ABS_OFF18(ctx
->opcode
);
8489 r1
= MASK_OP_ABS_S1D(ctx
->opcode
);
8490 tcg_gen_movi_tl(cpu_gpr_a
[r1
], EA_ABS_FORMAT(address
));
8493 case OPC1_32_ABSB_ST_T
:
8494 address
= MASK_OP_ABS_OFF18(ctx
->opcode
);
8495 b
= MASK_OP_ABSB_B(ctx
->opcode
);
8496 bpos
= MASK_OP_ABSB_BPOS(ctx
->opcode
);
8498 temp
= tcg_const_i32(EA_ABS_FORMAT(address
));
8499 temp2
= tcg_temp_new();
8501 tcg_gen_qemu_ld_tl(temp2
, temp
, ctx
->mem_idx
, MO_UB
);
8502 tcg_gen_andi_tl(temp2
, temp2
, ~(0x1u
<< bpos
));
8503 tcg_gen_ori_tl(temp2
, temp2
, (b
<< bpos
));
8504 tcg_gen_qemu_st_tl(temp2
, temp
, ctx
->mem_idx
, MO_UB
);
8506 tcg_temp_free(temp
);
8507 tcg_temp_free(temp2
);
8510 case OPC1_32_B_CALL
:
8511 case OPC1_32_B_CALLA
:
8512 case OPC1_32_B_FCALL
:
8513 case OPC1_32_B_FCALLA
:
8518 address
= MASK_OP_B_DISP24_SEXT(ctx
->opcode
);
8519 gen_compute_branch(ctx
, op1
, 0, 0, 0, address
);
8522 case OPCM_32_BIT_ANDACC
:
8523 decode_bit_andacc(env
, ctx
);
8525 case OPCM_32_BIT_LOGICAL_T1
:
8526 decode_bit_logical_t(env
, ctx
);
8528 case OPCM_32_BIT_INSERT
:
8529 decode_bit_insert(env
, ctx
);
8531 case OPCM_32_BIT_LOGICAL_T2
:
8532 decode_bit_logical_t2(env
, ctx
);
8534 case OPCM_32_BIT_ORAND
:
8535 decode_bit_orand(env
, ctx
);
8537 case OPCM_32_BIT_SH_LOGIC1
:
8538 decode_bit_sh_logic1(env
, ctx
);
8540 case OPCM_32_BIT_SH_LOGIC2
:
8541 decode_bit_sh_logic2(env
, ctx
);
8544 case OPCM_32_BO_ADDRMODE_POST_PRE_BASE
:
8545 decode_bo_addrmode_post_pre_base(env
, ctx
);
8547 case OPCM_32_BO_ADDRMODE_BITREVERSE_CIRCULAR
:
8548 decode_bo_addrmode_bitreverse_circular(env
, ctx
);
8550 case OPCM_32_BO_ADDRMODE_LD_POST_PRE_BASE
:
8551 decode_bo_addrmode_ld_post_pre_base(env
, ctx
);
8553 case OPCM_32_BO_ADDRMODE_LD_BITREVERSE_CIRCULAR
:
8554 decode_bo_addrmode_ld_bitreverse_circular(env
, ctx
);
8556 case OPCM_32_BO_ADDRMODE_STCTX_POST_PRE_BASE
:
8557 decode_bo_addrmode_stctx_post_pre_base(env
, ctx
);
8559 case OPCM_32_BO_ADDRMODE_LDMST_BITREVERSE_CIRCULAR
:
8560 decode_bo_addrmode_ldmst_bitreverse_circular(env
, ctx
);
8563 case OPC1_32_BOL_LD_A_LONGOFF
:
8564 case OPC1_32_BOL_LD_W_LONGOFF
:
8565 case OPC1_32_BOL_LEA_LONGOFF
:
8566 case OPC1_32_BOL_ST_W_LONGOFF
:
8567 case OPC1_32_BOL_ST_A_LONGOFF
:
8568 case OPC1_32_BOL_LD_B_LONGOFF
:
8569 case OPC1_32_BOL_LD_BU_LONGOFF
:
8570 case OPC1_32_BOL_LD_H_LONGOFF
:
8571 case OPC1_32_BOL_LD_HU_LONGOFF
:
8572 case OPC1_32_BOL_ST_B_LONGOFF
:
8573 case OPC1_32_BOL_ST_H_LONGOFF
:
8574 decode_bol_opc(env
, ctx
, op1
);
8577 case OPCM_32_BRC_EQ_NEQ
:
8578 case OPCM_32_BRC_GE
:
8579 case OPCM_32_BRC_JLT
:
8580 case OPCM_32_BRC_JNE
:
8581 const4
= MASK_OP_BRC_CONST4_SEXT(ctx
->opcode
);
8582 address
= MASK_OP_BRC_DISP15_SEXT(ctx
->opcode
);
8583 r1
= MASK_OP_BRC_S1(ctx
->opcode
);
8584 gen_compute_branch(ctx
, op1
, r1
, 0, const4
, address
);
8587 case OPCM_32_BRN_JTT
:
8588 address
= MASK_OP_BRN_DISP15_SEXT(ctx
->opcode
);
8589 r1
= MASK_OP_BRN_S1(ctx
->opcode
);
8590 gen_compute_branch(ctx
, op1
, r1
, 0, 0, address
);
8593 case OPCM_32_BRR_EQ_NEQ
:
8594 case OPCM_32_BRR_ADDR_EQ_NEQ
:
8595 case OPCM_32_BRR_GE
:
8596 case OPCM_32_BRR_JLT
:
8597 case OPCM_32_BRR_JNE
:
8598 case OPCM_32_BRR_JNZ
:
8599 case OPCM_32_BRR_LOOP
:
8600 address
= MASK_OP_BRR_DISP15_SEXT(ctx
->opcode
);
8601 r2
= MASK_OP_BRR_S2(ctx
->opcode
);
8602 r1
= MASK_OP_BRR_S1(ctx
->opcode
);
8603 gen_compute_branch(ctx
, op1
, r1
, r2
, 0, address
);
8606 case OPCM_32_RC_LOGICAL_SHIFT
:
8607 decode_rc_logical_shift(env
, ctx
);
8609 case OPCM_32_RC_ACCUMULATOR
:
8610 decode_rc_accumulator(env
, ctx
);
8612 case OPCM_32_RC_SERVICEROUTINE
:
8613 decode_rc_serviceroutine(env
, ctx
);
8615 case OPCM_32_RC_MUL
:
8616 decode_rc_mul(env
, ctx
);
8619 case OPCM_32_RCPW_MASK_INSERT
:
8620 decode_rcpw_insert(env
, ctx
);
8623 case OPC1_32_RCRR_INSERT
:
8624 r1
= MASK_OP_RCRR_S1(ctx
->opcode
);
8625 r2
= MASK_OP_RCRR_S3(ctx
->opcode
);
8626 r3
= MASK_OP_RCRR_D(ctx
->opcode
);
8627 const16
= MASK_OP_RCRR_CONST4(ctx
->opcode
);
8628 temp
= tcg_const_i32(const16
);
8629 temp2
= tcg_temp_new(); /* width*/
8630 temp3
= tcg_temp_new(); /* pos */
8634 tcg_gen_andi_tl(temp2
, cpu_gpr_d
[r3
+1], 0x1f);
8635 tcg_gen_andi_tl(temp3
, cpu_gpr_d
[r3
], 0x1f);
8637 gen_insert(cpu_gpr_d
[r2
], cpu_gpr_d
[r1
], temp
, temp2
, temp3
);
8639 tcg_temp_free(temp
);
8640 tcg_temp_free(temp2
);
8641 tcg_temp_free(temp3
);
8644 case OPCM_32_RCRW_MASK_INSERT
:
8645 decode_rcrw_insert(env
, ctx
);
8648 case OPCM_32_RCR_COND_SELECT
:
8649 decode_rcr_cond_select(env
, ctx
);
8651 case OPCM_32_RCR_MADD
:
8652 decode_rcr_madd(env
, ctx
);
8654 case OPCM_32_RCR_MSUB
:
8655 decode_rcr_msub(env
, ctx
);
8658 case OPC1_32_RLC_ADDI
:
8659 case OPC1_32_RLC_ADDIH
:
8660 case OPC1_32_RLC_ADDIH_A
:
8661 case OPC1_32_RLC_MFCR
:
8662 case OPC1_32_RLC_MOV
:
8663 case OPC1_32_RLC_MOV_64
:
8664 case OPC1_32_RLC_MOV_U
:
8665 case OPC1_32_RLC_MOV_H
:
8666 case OPC1_32_RLC_MOVH_A
:
8667 case OPC1_32_RLC_MTCR
:
8668 decode_rlc_opc(env
, ctx
, op1
);
8671 case OPCM_32_RR_ACCUMULATOR
:
8672 decode_rr_accumulator(env
, ctx
);
8674 case OPCM_32_RR_LOGICAL_SHIFT
:
8675 decode_rr_logical_shift(env
, ctx
);
8677 case OPCM_32_RR_ADDRESS
:
8678 decode_rr_address(env
, ctx
);
8680 case OPCM_32_RR_IDIRECT
:
8681 decode_rr_idirect(env
, ctx
);
8683 case OPCM_32_RR_DIVIDE
:
8684 decode_rr_divide(env
, ctx
);
8687 case OPCM_32_RR1_MUL
:
8688 decode_rr1_mul(env
, ctx
);
8690 case OPCM_32_RR1_MULQ
:
8691 decode_rr1_mulq(env
, ctx
);
8694 case OPCM_32_RR2_MUL
:
8695 decode_rr2_mul(env
, ctx
);
8698 case OPCM_32_RRPW_EXTRACT_INSERT
:
8699 decode_rrpw_extract_insert(env
, ctx
);
8701 case OPC1_32_RRPW_DEXTR
:
8702 r1
= MASK_OP_RRPW_S1(ctx
->opcode
);
8703 r2
= MASK_OP_RRPW_S2(ctx
->opcode
);
8704 r3
= MASK_OP_RRPW_D(ctx
->opcode
);
8705 const16
= MASK_OP_RRPW_POS(ctx
->opcode
);
8707 tcg_gen_rotli_tl(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], const16
);
8709 temp
= tcg_temp_new();
8710 tcg_gen_shli_tl(temp
, cpu_gpr_d
[r1
], const16
);
8711 tcg_gen_shri_tl(cpu_gpr_d
[r3
], cpu_gpr_d
[r2
], 32 - const16
);
8712 tcg_gen_or_tl(cpu_gpr_d
[r3
], cpu_gpr_d
[r3
], temp
);
8713 tcg_temp_free(temp
);
8717 case OPCM_32_RRR_COND_SELECT
:
8718 decode_rrr_cond_select(env
, ctx
);
8720 case OPCM_32_RRR_DIVIDE
:
8721 decode_rrr_divide(env
, ctx
);
8724 case OPCM_32_RRR2_MADD
:
8725 decode_rrr2_madd(env
, ctx
);
8727 case OPCM_32_RRR2_MSUB
:
8728 decode_rrr2_msub(env
, ctx
);
8731 case OPCM_32_RRR1_MADD
:
8732 decode_rrr1_madd(env
, ctx
);
8734 case OPCM_32_RRR1_MADDQ_H
:
8735 decode_rrr1_maddq_h(env
, ctx
);
8737 case OPCM_32_RRR1_MADDSU_H
:
8738 decode_rrr1_maddsu_h(env
, ctx
);
8740 case OPCM_32_RRR1_MSUB_H
:
8741 decode_rrr1_msub(env
, ctx
);
8743 case OPCM_32_RRR1_MSUB_Q
:
8744 decode_rrr1_msubq_h(env
, ctx
);
8746 case OPCM_32_RRR1_MSUBAD_H
:
8747 decode_rrr1_msubad_h(env
, ctx
);
8750 case OPCM_32_RRRR_EXTRACT_INSERT
:
8751 decode_rrrr_extract_insert(env
, ctx
);
8754 case OPCM_32_RRRW_EXTRACT_INSERT
:
8755 decode_rrrw_extract_insert(env
, ctx
);
8758 case OPCM_32_SYS_INTERRUPTS
:
8759 decode_sys_interrupts(env
, ctx
);
8761 case OPC1_32_SYS_RSTV
:
8762 tcg_gen_movi_tl(cpu_PSW_V
, 0);
8763 tcg_gen_mov_tl(cpu_PSW_SV
, cpu_PSW_V
);
8764 tcg_gen_mov_tl(cpu_PSW_AV
, cpu_PSW_V
);
8765 tcg_gen_mov_tl(cpu_PSW_SAV
, cpu_PSW_V
);
8768 generate_trap(ctx
, TRAPC_INSN_ERR
, TIN2_IOPC
);
8772 static void decode_opc(CPUTriCoreState
*env
, DisasContext
*ctx
, int *is_branch
)
8774 /* 16-Bit Instruction */
8775 if ((ctx
->opcode
& 0x1) == 0) {
8776 ctx
->next_pc
= ctx
->pc
+ 2;
8777 decode_16Bit_opc(env
, ctx
);
8778 /* 32-Bit Instruction */
8780 ctx
->next_pc
= ctx
->pc
+ 4;
8781 decode_32Bit_opc(env
, ctx
);
8785 void gen_intermediate_code(CPUState
*cs
, struct TranslationBlock
*tb
)
8787 CPUTriCoreState
*env
= cs
->env_ptr
;
8789 target_ulong pc_start
;
8790 int num_insns
, max_insns
;
8793 max_insns
= tb
->cflags
& CF_COUNT_MASK
;
8794 if (max_insns
== 0) {
8795 max_insns
= CF_COUNT_MASK
;
8800 if (max_insns
> TCG_MAX_INSNS
) {
8801 max_insns
= TCG_MAX_INSNS
;
8808 ctx
.singlestep_enabled
= cs
->singlestep_enabled
;
8809 ctx
.bstate
= BS_NONE
;
8810 ctx
.mem_idx
= cpu_mmu_index(env
, false);
8812 tcg_clear_temp_count();
8814 while (ctx
.bstate
== BS_NONE
) {
8815 tcg_gen_insn_start(ctx
.pc
);
8818 ctx
.opcode
= cpu_ldl_code(env
, ctx
.pc
);
8819 decode_opc(env
, &ctx
, 0);
8821 if (num_insns
>= max_insns
|| tcg_op_buf_full()) {
8822 gen_save_pc(ctx
.next_pc
);
8826 ctx
.pc
= ctx
.next_pc
;
8829 gen_tb_end(tb
, num_insns
);
8830 tb
->size
= ctx
.pc
- pc_start
;
8831 tb
->icount
= num_insns
;
8833 if (tcg_check_temp_count()) {
8834 printf("LEAK at %08x\n", env
->PC
);
8838 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM
)
8839 && qemu_log_in_addr_range(pc_start
)) {
8841 qemu_log("IN: %s\n", lookup_symbol(pc_start
));
8842 log_target_disas(cs
, pc_start
, ctx
.pc
- pc_start
, 0);
8850 restore_state_to_opc(CPUTriCoreState
*env
, TranslationBlock
*tb
,
8861 void cpu_state_reset(CPUTriCoreState
*env
)
8863 /* Reset Regs to Default Value */
8868 static void tricore_tcg_init_csfr(void)
8870 cpu_PCXI
= tcg_global_mem_new(cpu_env
,
8871 offsetof(CPUTriCoreState
, PCXI
), "PCXI");
8872 cpu_PSW
= tcg_global_mem_new(cpu_env
,
8873 offsetof(CPUTriCoreState
, PSW
), "PSW");
8874 cpu_PC
= tcg_global_mem_new(cpu_env
,
8875 offsetof(CPUTriCoreState
, PC
), "PC");
8876 cpu_ICR
= tcg_global_mem_new(cpu_env
,
8877 offsetof(CPUTriCoreState
, ICR
), "ICR");
8880 void tricore_tcg_init(void)
8887 cpu_env
= tcg_global_reg_new_ptr(TCG_AREG0
, "env");
8888 tcg_ctx
.tcg_env
= cpu_env
;
8890 for (i
= 0 ; i
< 16 ; i
++) {
8891 cpu_gpr_a
[i
] = tcg_global_mem_new(cpu_env
,
8892 offsetof(CPUTriCoreState
, gpr_a
[i
]),
8895 for (i
= 0 ; i
< 16 ; i
++) {
8896 cpu_gpr_d
[i
] = tcg_global_mem_new(cpu_env
,
8897 offsetof(CPUTriCoreState
, gpr_d
[i
]),
8900 tricore_tcg_init_csfr();
8901 /* init PSW flag cache */
8902 cpu_PSW_C
= tcg_global_mem_new(cpu_env
,
8903 offsetof(CPUTriCoreState
, PSW_USB_C
),
8905 cpu_PSW_V
= tcg_global_mem_new(cpu_env
,
8906 offsetof(CPUTriCoreState
, PSW_USB_V
),
8908 cpu_PSW_SV
= tcg_global_mem_new(cpu_env
,
8909 offsetof(CPUTriCoreState
, PSW_USB_SV
),
8911 cpu_PSW_AV
= tcg_global_mem_new(cpu_env
,
8912 offsetof(CPUTriCoreState
, PSW_USB_AV
),
8914 cpu_PSW_SAV
= tcg_global_mem_new(cpu_env
,
8915 offsetof(CPUTriCoreState
, PSW_USB_SAV
),