2 * LatticeMico32 helper routines.
4 * Copyright (c) 2010 Michael Walle <michael@walle.cc>
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
27 #include "host-utils.h"
29 int cpu_lm32_handle_mmu_fault(CPUState
*env
, target_ulong address
, int rw
,
30 int mmu_idx
, int is_softmmu
)
34 address
&= TARGET_PAGE_MASK
;
36 if (env
->flags
& LM32_FLAG_IGNORE_MSB
) {
37 tlb_set_page(env
, address
, address
& 0x7fffffff, prot
, mmu_idx
,
40 tlb_set_page(env
, address
, address
, prot
, mmu_idx
, TARGET_PAGE_SIZE
);
46 target_phys_addr_t
cpu_get_phys_page_debug(CPUState
*env
, target_ulong addr
)
48 return addr
& TARGET_PAGE_MASK
;
51 void do_interrupt(CPUState
*env
)
53 qemu_log_mask(CPU_LOG_INT
,
54 "exception at pc=%x type=%x\n", env
->pc
, env
->exception_index
);
56 switch (env
->exception_index
) {
57 case EXCP_INSN_BUS_ERROR
:
58 case EXCP_DATA_BUS_ERROR
:
59 case EXCP_DIVIDE_BY_ZERO
:
62 /* non-debug exceptions */
63 env
->regs
[R_EA
] = env
->pc
;
64 env
->ie
|= (env
->ie
& IE_IE
) ? IE_EIE
: 0;
66 if (env
->dc
& DC_RE
) {
67 env
->pc
= env
->deba
+ (env
->exception_index
* 32);
69 env
->pc
= env
->eba
+ (env
->exception_index
* 32);
71 log_cpu_state_mask(CPU_LOG_INT
, env
, 0);
75 /* debug exceptions */
76 env
->regs
[R_BA
] = env
->pc
;
77 env
->ie
|= (env
->ie
& IE_IE
) ? IE_BIE
: 0;
79 env
->pc
= env
->deba
+ (env
->exception_index
* 32);
80 log_cpu_state_mask(CPU_LOG_INT
, env
, 0);
83 cpu_abort(env
, "unhandled exception type=%d\n",
84 env
->exception_index
);
92 uint8_t num_interrupts
;
93 uint8_t num_breakpoints
;
94 uint8_t num_watchpoints
;
98 static const LM32Def lm32_defs
[] = {
100 .name
= "lm32-basic",
102 .num_interrupts
= 32,
103 .num_breakpoints
= 4,
104 .num_watchpoints
= 4,
105 .features
= (LM32_FEATURE_SHIFT
106 | LM32_FEATURE_SIGN_EXTEND
107 | LM32_FEATURE_CYCLE_COUNT
),
110 .name
= "lm32-standard",
112 .num_interrupts
= 32,
113 .num_breakpoints
= 4,
114 .num_watchpoints
= 4,
115 .features
= (LM32_FEATURE_MULTIPLY
116 | LM32_FEATURE_DIVIDE
118 | LM32_FEATURE_SIGN_EXTEND
119 | LM32_FEATURE_I_CACHE
120 | LM32_FEATURE_CYCLE_COUNT
),
125 .num_interrupts
= 32,
126 .num_breakpoints
= 4,
127 .num_watchpoints
= 4,
128 .features
= (LM32_FEATURE_MULTIPLY
129 | LM32_FEATURE_DIVIDE
131 | LM32_FEATURE_SIGN_EXTEND
132 | LM32_FEATURE_I_CACHE
133 | LM32_FEATURE_D_CACHE
134 | LM32_FEATURE_CYCLE_COUNT
),
138 void cpu_lm32_list(FILE *f
, fprintf_function cpu_fprintf
)
142 cpu_fprintf(f
, "Available CPUs:\n");
143 for (i
= 0; i
< ARRAY_SIZE(lm32_defs
); i
++) {
144 cpu_fprintf(f
, " %s\n", lm32_defs
[i
].name
);
148 static const LM32Def
*cpu_lm32_find_by_name(const char *name
)
152 for (i
= 0; i
< ARRAY_SIZE(lm32_defs
); i
++) {
153 if (strcasecmp(name
, lm32_defs
[i
].name
) == 0) {
154 return &lm32_defs
[i
];
161 static uint32_t cfg_by_def(const LM32Def
*def
)
165 if (def
->features
& LM32_FEATURE_MULTIPLY
) {
169 if (def
->features
& LM32_FEATURE_DIVIDE
) {
173 if (def
->features
& LM32_FEATURE_SHIFT
) {
177 if (def
->features
& LM32_FEATURE_SIGN_EXTEND
) {
181 if (def
->features
& LM32_FEATURE_I_CACHE
) {
185 if (def
->features
& LM32_FEATURE_D_CACHE
) {
189 if (def
->features
& LM32_FEATURE_CYCLE_COUNT
) {
193 cfg
|= (def
->num_interrupts
<< CFG_INT_SHIFT
);
194 cfg
|= (def
->num_breakpoints
<< CFG_BP_SHIFT
);
195 cfg
|= (def
->num_watchpoints
<< CFG_WP_SHIFT
);
196 cfg
|= (def
->revision
<< CFG_REV_SHIFT
);
201 CPUState
*cpu_lm32_init(const char *cpu_model
)
205 static int tcg_initialized
;
207 def
= cpu_lm32_find_by_name(cpu_model
);
212 env
= qemu_mallocz(sizeof(CPUState
));
214 env
->features
= def
->features
;
215 env
->num_bps
= def
->num_breakpoints
;
216 env
->num_wps
= def
->num_watchpoints
;
217 env
->cfg
= cfg_by_def(def
);
223 if (!tcg_initialized
) {
225 lm32_translate_init();
231 /* Some soc ignores the MSB on the address bus. Thus creating a shadow memory
232 * area. As a general rule, 0x00000000-0x7fffffff is cached, whereas
233 * 0x80000000-0xffffffff is not cached and used to access IO devices. */
234 void cpu_lm32_set_phys_msb_ignore(CPUState
*env
, int value
)
237 env
->flags
|= LM32_FLAG_IGNORE_MSB
;
239 env
->flags
&= ~LM32_FLAG_IGNORE_MSB
;
243 void cpu_reset(CPUState
*env
)
245 if (qemu_loglevel_mask(CPU_LOG_RESET
)) {
246 qemu_log("CPU Reset (CPU %d)\n", env
->cpu_index
);
247 log_cpu_state(env
, 0);
252 /* reset cpu state */
253 memset(env
, 0, offsetof(CPULM32State
, breakpoints
));