hw/misc/aspeed_sdmc.c

   1 /*
   2  * ASPEED SDRAM Memory Controller
   3  *
   4  * Copyright (C) 2016 IBM Corp.
   5  *
   6  * This code is licensed under the GPL version 2 or later.  See
   7  * the COPYING file in the top-level directory.
   8  */
   9
  10 #include "qemu/osdep.h"
  11 #include "qemu/log.h"
  12 #include "qemu/module.h"
  13 #include "qemu/error-report.h"
  14 #include "hw/misc/aspeed_sdmc.h"
  15 #include "hw/misc/aspeed_scu.h"
  16 #include "hw/qdev-properties.h"
  17 #include "migration/vmstate.h"
  18 #include "qapi/error.h"
  19 #include "trace.h"
  20
  21 /* Protection Key Register */
  22 #define R_PROT            (0x00 / 4)
  23 #define   PROT_KEY_UNLOCK     0xFC600309
  24
  25 /* Configuration Register */
  26 #define R_CONF            (0x04 / 4)
  27
  28 /* Control/Status Register #1 (ast2500) */
  29 #define R_STATUS1         (0x60 / 4)
  30 #define   PHY_BUSY_STATE      BIT(0)
  31
  32 #define R_ECC_TEST_CTRL   (0x70 / 4)
  33 #define   ECC_TEST_FINISHED   BIT(12)
  34 #define   ECC_TEST_FAIL       BIT(13)
  35
  36 /*
  37  * Configuration register Ox4 (for Aspeed AST2400 SOC)
  38  *
  39  * These are for the record and future use. ASPEED_SDMC_DRAM_SIZE is
  40  * what we care about right now as it is checked by U-Boot to
  41  * determine the RAM size.
  42  */
  43
  44 #define ASPEED_SDMC_RESERVED            0xFFFFF800 /* 31:11 reserved */
  45 #define ASPEED_SDMC_AST2300_COMPAT      (1 << 10)
  46 #define ASPEED_SDMC_SCRAMBLE_PATTERN    (1 << 9)
  47 #define ASPEED_SDMC_DATA_SCRAMBLE       (1 << 8)
  48 #define ASPEED_SDMC_ECC_ENABLE          (1 << 7)
  49 #define ASPEED_SDMC_VGA_COMPAT          (1 << 6) /* readonly */
  50 #define ASPEED_SDMC_DRAM_BANK           (1 << 5)
  51 #define ASPEED_SDMC_DRAM_BURST          (1 << 4)
  52 #define ASPEED_SDMC_VGA_APERTURE(x)     ((x & 0x3) << 2) /* readonly */
  53 #define     ASPEED_SDMC_VGA_8MB             0x0
  54 #define     ASPEED_SDMC_VGA_16MB            0x1
  55 #define     ASPEED_SDMC_VGA_32MB            0x2
  56 #define     ASPEED_SDMC_VGA_64MB            0x3
  57 #define ASPEED_SDMC_DRAM_SIZE(x)        (x & 0x3)
  58 #define     ASPEED_SDMC_DRAM_64MB           0x0
  59 #define     ASPEED_SDMC_DRAM_128MB          0x1
  60 #define     ASPEED_SDMC_DRAM_256MB          0x2
  61 #define     ASPEED_SDMC_DRAM_512MB          0x3
  62
  63 #define ASPEED_SDMC_READONLY_MASK                       \
  64     (ASPEED_SDMC_RESERVED | ASPEED_SDMC_VGA_COMPAT |    \
  65      ASPEED_SDMC_VGA_APERTURE(ASPEED_SDMC_VGA_64MB))
  66 /*
  67  * Configuration register Ox4 (for Aspeed AST2500 SOC and higher)
  68  *
  69  * Incompatibilities are annotated in the list. ASPEED_SDMC_HW_VERSION
  70  * should be set to 1 for the AST2500 SOC.
  71  */
  72 #define ASPEED_SDMC_HW_VERSION(x)       ((x & 0xf) << 28) /* readonly */
  73 #define ASPEED_SDMC_SW_VERSION          ((x & 0xff) << 20)
  74 #define ASPEED_SDMC_CACHE_INITIAL_DONE  (1 << 19)  /* readonly */
  75 #define ASPEED_SDMC_AST2500_RESERVED    0x7C000 /* 18:14 reserved */
  76 #define ASPEED_SDMC_CACHE_DDR4_CONF     (1 << 13)
  77 #define ASPEED_SDMC_CACHE_INITIAL       (1 << 12)
  78 #define ASPEED_SDMC_CACHE_RANGE_CTRL    (1 << 11)
  79 #define ASPEED_SDMC_CACHE_ENABLE        (1 << 10) /* differs from AST2400 */
  80 #define ASPEED_SDMC_DRAM_TYPE           (1 << 4)  /* differs from AST2400 */
  81
  82 /* DRAM size definitions differs */
  83 #define     ASPEED_SDMC_AST2500_128MB       0x0
  84 #define     ASPEED_SDMC_AST2500_256MB       0x1
  85 #define     ASPEED_SDMC_AST2500_512MB       0x2
  86 #define     ASPEED_SDMC_AST2500_1024MB      0x3
  87
  88 #define ASPEED_SDMC_AST2500_READONLY_MASK                               \
  89     (ASPEED_SDMC_HW_VERSION(0xf) | ASPEED_SDMC_CACHE_INITIAL_DONE |     \
  90      ASPEED_SDMC_AST2500_RESERVED | ASPEED_SDMC_VGA_COMPAT |            \
  91      ASPEED_SDMC_VGA_APERTURE(ASPEED_SDMC_VGA_64MB))
  92
  93 static uint64_t aspeed_sdmc_read(void *opaque, hwaddr addr, unsigned size)
  94 {
  95     AspeedSDMCState *s = ASPEED_SDMC(opaque);
  96
  97     addr >>= 2;
  98
  99     if (addr >= ARRAY_SIZE(s->regs)) {
 100         qemu_log_mask(LOG_GUEST_ERROR,
 101                       "%s: Out-of-bounds read at offset 0x%" HWADDR_PRIx "\n",
 102                       __func__, addr);
 103         return 0;
 104     }
 105
 106     return s->regs[addr];
 107 }
 108
 109 static void aspeed_sdmc_write(void *opaque, hwaddr addr, uint64_t data,
 110                              unsigned int size)
 111 {
 112     AspeedSDMCState *s = ASPEED_SDMC(opaque);
 113     AspeedSDMCClass *asc = ASPEED_SDMC_GET_CLASS(s);
 114
 115     addr >>= 2;
 116
 117     if (addr >= ARRAY_SIZE(s->regs)) {
 118         qemu_log_mask(LOG_GUEST_ERROR,
 119                       "%s: Out-of-bounds write at offset 0x%" HWADDR_PRIx "\n",
 120                       __func__, addr);
 121         return;
 122     }
 123
 124     if (addr == R_PROT) {
 125         s->regs[addr] = (data == PROT_KEY_UNLOCK) ? 1 : 0;
 126         return;
 127     }
 128
 129     if (!s->regs[R_PROT]) {
 130         qemu_log_mask(LOG_GUEST_ERROR, "%s: SDMC is locked!\n", __func__);
 131         return;
 132     }
 133
 134     asc->write(s, addr, data);
 135 }
 136
 137 static const MemoryRegionOps aspeed_sdmc_ops = {
 138     .read = aspeed_sdmc_read,
 139     .write = aspeed_sdmc_write,
 140     .endianness = DEVICE_LITTLE_ENDIAN,
 141     .valid.min_access_size = 4,
 142     .valid.max_access_size = 4,
 143 };
 144
 145 static int ast2400_rambits(AspeedSDMCState *s)
 146 {
 147     switch (s->ram_size >> 20) {
 148     case 64:
 149         return ASPEED_SDMC_DRAM_64MB;
 150     case 128:
 151         return ASPEED_SDMC_DRAM_128MB;
 152     case 256:
 153         return ASPEED_SDMC_DRAM_256MB;
 154     case 512:
 155         return ASPEED_SDMC_DRAM_512MB;
 156     default:
 157         break;
 158     }
 159
 160     /* use a common default */
 161     warn_report("Invalid RAM size 0x%" PRIx64 ". Using default 256M",
 162                 s->ram_size);
 163     s->ram_size = 256 << 20;
 164     return ASPEED_SDMC_DRAM_256MB;
 165 }
 166
 167 static int ast2500_rambits(AspeedSDMCState *s)
 168 {
 169     switch (s->ram_size >> 20) {
 170     case 128:
 171         return ASPEED_SDMC_AST2500_128MB;
 172     case 256:
 173         return ASPEED_SDMC_AST2500_256MB;
 174     case 512:
 175         return ASPEED_SDMC_AST2500_512MB;
 176     case 1024:
 177         return ASPEED_SDMC_AST2500_1024MB;
 178     default:
 179         break;
 180     }
 181
 182     /* use a common default */
 183     warn_report("Invalid RAM size 0x%" PRIx64 ". Using default 512M",
 184                 s->ram_size);
 185     s->ram_size = 512 << 20;
 186     return ASPEED_SDMC_AST2500_512MB;
 187 }
 188
 189 static void aspeed_sdmc_reset(DeviceState *dev)
 190 {
 191     AspeedSDMCState *s = ASPEED_SDMC(dev);
 192     AspeedSDMCClass *asc = ASPEED_SDMC_GET_CLASS(s);
 193
 194     memset(s->regs, 0, sizeof(s->regs));
 195
 196     /* Set ram size bit and defaults values */
 197     s->regs[R_CONF] = asc->compute_conf(s, 0);
 198 }
 199
 200 static void aspeed_sdmc_realize(DeviceState *dev, Error **errp)
 201 {
 202     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
 203     AspeedSDMCState *s = ASPEED_SDMC(dev);
 204     AspeedSDMCClass *asc = ASPEED_SDMC_GET_CLASS(s);
 205
 206     s->max_ram_size = asc->max_ram_size;
 207
 208     memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_sdmc_ops, s,
 209                           TYPE_ASPEED_SDMC, 0x1000);
 210     sysbus_init_mmio(sbd, &s->iomem);
 211 }
 212
 213 static const VMStateDescription vmstate_aspeed_sdmc = {
 214     .name = "aspeed.sdmc",
 215     .version_id = 1,
 216     .minimum_version_id = 1,
 217     .fields = (VMStateField[]) {
 218         VMSTATE_UINT32_ARRAY(regs, AspeedSDMCState, ASPEED_SDMC_NR_REGS),
 219         VMSTATE_END_OF_LIST()
 220     }
 221 };
 222
 223 static Property aspeed_sdmc_properties[] = {
 224     DEFINE_PROP_UINT64("ram-size", AspeedSDMCState, ram_size, 0),
 225     DEFINE_PROP_UINT64("max-ram-size", AspeedSDMCState, max_ram_size, 0),
 226     DEFINE_PROP_END_OF_LIST(),
 227 };
 228
 229 static void aspeed_sdmc_class_init(ObjectClass *klass, void *data)
 230 {
 231     DeviceClass *dc = DEVICE_CLASS(klass);
 232     dc->realize = aspeed_sdmc_realize;
 233     dc->reset = aspeed_sdmc_reset;
 234     dc->desc = "ASPEED SDRAM Memory Controller";
 235     dc->vmsd = &vmstate_aspeed_sdmc;
 236     dc->props = aspeed_sdmc_properties;
 237 }
 238
 239 static const TypeInfo aspeed_sdmc_info = {
 240     .name = TYPE_ASPEED_SDMC,
 241     .parent = TYPE_SYS_BUS_DEVICE,
 242     .instance_size = sizeof(AspeedSDMCState),
 243     .class_init = aspeed_sdmc_class_init,
 244     .class_size = sizeof(AspeedSDMCClass),
 245     .abstract   = true,
 246 };
 247
 248 static uint32_t aspeed_2400_sdmc_compute_conf(AspeedSDMCState *s, uint32_t data)
 249 {
 250     uint32_t fixed_conf = ASPEED_SDMC_VGA_COMPAT |
 251         ASPEED_SDMC_DRAM_SIZE(ast2400_rambits(s));
 252
 253     /* Make sure readonly bits are kept */
 254     data &= ~ASPEED_SDMC_READONLY_MASK;
 255
 256     return data | fixed_conf;
 257 }
 258
 259 static void aspeed_2400_sdmc_write(AspeedSDMCState *s, uint32_t reg,
 260                                    uint32_t data)
 261 {
 262     switch (reg) {
 263     case R_CONF:
 264         data = aspeed_2400_sdmc_compute_conf(s, data);
 265         break;
 266     default:
 267         break;
 268     }
 269
 270     s->regs[reg] = data;
 271 }
 272
 273 static void aspeed_2400_sdmc_class_init(ObjectClass *klass, void *data)
 274 {
 275     DeviceClass *dc = DEVICE_CLASS(klass);
 276     AspeedSDMCClass *asc = ASPEED_SDMC_CLASS(klass);
 277
 278     dc->desc = "ASPEED 2400 SDRAM Memory Controller";
 279     asc->max_ram_size = 512 << 20;
 280     asc->compute_conf = aspeed_2400_sdmc_compute_conf;
 281     asc->write = aspeed_2400_sdmc_write;
 282 }
 283
 284 static const TypeInfo aspeed_2400_sdmc_info = {
 285     .name = TYPE_ASPEED_2400_SDMC,
 286     .parent = TYPE_ASPEED_SDMC,
 287     .class_init = aspeed_2400_sdmc_class_init,
 288 };
 289
 290 static uint32_t aspeed_2500_sdmc_compute_conf(AspeedSDMCState *s, uint32_t data)
 291 {
 292     uint32_t fixed_conf = ASPEED_SDMC_HW_VERSION(1) |
 293         ASPEED_SDMC_VGA_APERTURE(ASPEED_SDMC_VGA_64MB) |
 294         ASPEED_SDMC_CACHE_INITIAL_DONE |
 295         ASPEED_SDMC_DRAM_SIZE(ast2500_rambits(s));
 296
 297     /* Make sure readonly bits are kept */
 298     data &= ~ASPEED_SDMC_AST2500_READONLY_MASK;
 299
 300     return data | fixed_conf;
 301 }
 302
 303 static void aspeed_2500_sdmc_write(AspeedSDMCState *s, uint32_t reg,
 304                                    uint32_t data)
 305 {
 306     switch (reg) {
 307     case R_CONF:
 308         data = aspeed_2500_sdmc_compute_conf(s, data);
 309         break;
 310     case R_STATUS1:
 311         /* Will never return 'busy' */
 312         data &= ~PHY_BUSY_STATE;
 313         break;
 314     case R_ECC_TEST_CTRL:
 315         /* Always done, always happy */
 316         data |= ECC_TEST_FINISHED;
 317         data &= ~ECC_TEST_FAIL;
 318         break;
 319     default:
 320         break;
 321     }
 322
 323     s->regs[reg] = data;
 324 }
 325
 326 static void aspeed_2500_sdmc_class_init(ObjectClass *klass, void *data)
 327 {
 328     DeviceClass *dc = DEVICE_CLASS(klass);
 329     AspeedSDMCClass *asc = ASPEED_SDMC_CLASS(klass);
 330
 331     dc->desc = "ASPEED 2500 SDRAM Memory Controller";
 332     asc->max_ram_size = 1024 << 20;
 333     asc->compute_conf = aspeed_2500_sdmc_compute_conf;
 334     asc->write = aspeed_2500_sdmc_write;
 335 }
 336
 337 static const TypeInfo aspeed_2500_sdmc_info = {
 338     .name = TYPE_ASPEED_2500_SDMC,
 339     .parent = TYPE_ASPEED_SDMC,
 340     .class_init = aspeed_2500_sdmc_class_init,
 341 };
 342
 343 static void aspeed_sdmc_register_types(void)
 344 {
 345     type_register_static(&aspeed_sdmc_info);
 346     type_register_static(&aspeed_2400_sdmc_info);
 347     type_register_static(&aspeed_2500_sdmc_info);
 348 }
 349
 350 type_init(aspeed_sdmc_register_types);