target-mips/gdbstub.c

   1 /*
   2  * MIPS gdb server stub
   3  *
   4  * Copyright (c) 2003-2005 Fabrice Bellard
   5  * Copyright (c) 2013 SUSE LINUX Products GmbH
   6  *
   7  * This library is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU Lesser General Public
   9  * License as published by the Free Software Foundation; either
  10  * version 2 of the License, or (at your option) any later version.
  11  *
  12  * This library is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * Lesser General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU Lesser General Public
  18  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  19  */
  20 #include "config.h"
  21 #include "qemu-common.h"
  22 #include "exec/gdbstub.h"
  23
  24 int mips_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n)
  25 {
  26     MIPSCPU *cpu = MIPS_CPU(cs);
  27     CPUMIPSState *env = &cpu->env;
  28
  29     if (n < 32) {
  30         return gdb_get_regl(mem_buf, env->active_tc.gpr[n]);
  31     }
  32     if (env->CP0_Config1 & (1 << CP0C1_FP)) {
  33         if (n >= 38 && n < 70) {
  34             if (env->CP0_Status & (1 << CP0St_FR)) {
  35                 return gdb_get_regl(mem_buf,
  36                     env->active_fpu.fpr[n - 38].d);
  37             } else {
  38                 return gdb_get_regl(mem_buf,
  39                     env->active_fpu.fpr[n - 38].w[FP_ENDIAN_IDX]);
  40             }
  41         }
  42         switch (n) {
  43         case 70:
  44             return gdb_get_regl(mem_buf, (int32_t)env->active_fpu.fcr31);
  45         case 71:
  46             return gdb_get_regl(mem_buf, (int32_t)env->active_fpu.fcr0);
  47         }
  48     }
  49     switch (n) {
  50     case 32:
  51         return gdb_get_regl(mem_buf, (int32_t)env->CP0_Status);
  52     case 33:
  53         return gdb_get_regl(mem_buf, env->active_tc.LO[0]);
  54     case 34:
  55         return gdb_get_regl(mem_buf, env->active_tc.HI[0]);
  56     case 35:
  57         return gdb_get_regl(mem_buf, env->CP0_BadVAddr);
  58     case 36:
  59         return gdb_get_regl(mem_buf, (int32_t)env->CP0_Cause);
  60     case 37:
  61         return gdb_get_regl(mem_buf, env->active_tc.PC |
  62                                      !!(env->hflags & MIPS_HFLAG_M16));
  63     case 72:
  64         return gdb_get_regl(mem_buf, 0); /* fp */
  65     case 89:
  66         return gdb_get_regl(mem_buf, (int32_t)env->CP0_PRid);
  67     }
  68     if (n >= 73 && n <= 88) {
  69         /* 16 embedded regs.  */
  70         return gdb_get_regl(mem_buf, 0);
  71     }
  72
  73     return 0;
  74 }
  75
  76 #define RESTORE_ROUNDING_MODE \
  77     set_float_rounding_mode(ieee_rm[env->active_fpu.fcr31 & 3], \
  78                             &env->active_fpu.fp_status)
  79
  80 int mips_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
  81 {
  82     MIPSCPU *cpu = MIPS_CPU(cs);
  83     CPUMIPSState *env = &cpu->env;
  84     target_ulong tmp;
  85
  86     tmp = ldtul_p(mem_buf);
  87
  88     if (n < 32) {
  89         env->active_tc.gpr[n] = tmp;
  90         return sizeof(target_ulong);
  91     }
  92     if (env->CP0_Config1 & (1 << CP0C1_FP)
  93             && n >= 38 && n < 73) {
  94         if (n < 70) {
  95             if (env->CP0_Status & (1 << CP0St_FR)) {
  96                 env->active_fpu.fpr[n - 38].d = tmp;
  97             } else {
  98                 env->active_fpu.fpr[n - 38].w[FP_ENDIAN_IDX] = tmp;
  99             }
 100         }
 101         switch (n) {
 102         case 70:
 103             env->active_fpu.fcr31 = tmp & 0xFF83FFFF;
 104             /* set rounding mode */
 105             RESTORE_ROUNDING_MODE;
 106             break;
 107         case 71:
 108             env->active_fpu.fcr0 = tmp;
 109             break;
 110         }
 111         return sizeof(target_ulong);
 112     }
 113     switch (n) {
 114     case 32:
 115         env->CP0_Status = tmp;
 116         break;
 117     case 33:
 118         env->active_tc.LO[0] = tmp;
 119         break;
 120     case 34:
 121         env->active_tc.HI[0] = tmp;
 122         break;
 123     case 35:
 124         env->CP0_BadVAddr = tmp;
 125         break;
 126     case 36:
 127         env->CP0_Cause = tmp;
 128         break;
 129     case 37:
 130         env->active_tc.PC = tmp & ~(target_ulong)1;
 131         if (tmp & 1) {
 132             env->hflags |= MIPS_HFLAG_M16;
 133         } else {
 134             env->hflags &= ~(MIPS_HFLAG_M16);
 135         }
 136         break;
 137     case 72: /* fp, ignored */
 138         break;
 139     default:
 140         if (n > 89) {
 141             return 0;
 142         }
 143         /* Other registers are readonly.  Ignore writes.  */
 144         break;
 145     }
 146
 147     return sizeof(target_ulong);
 148 }