4 * Copyright (c) 2012 SUSE LINUX Products GmbH
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see
18 * <http://www.gnu.org/licenses/gpl-2.0.html>
22 #include "qemu-common.h"
23 #if !defined(CONFIG_USER_ONLY)
24 #include "hw/loader.h"
26 #include "sysemu/sysemu.h"
28 static void cp_reg_reset(gpointer key
, gpointer value
, gpointer opaque
)
30 /* Reset a single ARMCPRegInfo register */
31 ARMCPRegInfo
*ri
= value
;
34 if (ri
->type
& ARM_CP_SPECIAL
) {
39 ri
->resetfn(&cpu
->env
, ri
);
43 /* A zero offset is never possible as it would be regs[0]
44 * so we use it to indicate that reset is being handled elsewhere.
45 * This is basically only used for fields in non-core coprocessors
46 * (like the pxa2xx ones).
48 if (!ri
->fieldoffset
) {
52 if (ri
->type
& ARM_CP_64BIT
) {
53 CPREG_FIELD64(&cpu
->env
, ri
) = ri
->resetvalue
;
55 CPREG_FIELD32(&cpu
->env
, ri
) = ri
->resetvalue
;
59 /* CPUClass::reset() */
60 static void arm_cpu_reset(CPUState
*s
)
62 ARMCPU
*cpu
= ARM_CPU(s
);
63 ARMCPUClass
*acc
= ARM_CPU_GET_CLASS(cpu
);
64 CPUARMState
*env
= &cpu
->env
;
66 if (qemu_loglevel_mask(CPU_LOG_RESET
)) {
67 qemu_log("CPU Reset (CPU %d)\n", s
->cpu_index
);
68 log_cpu_state(env
, 0);
73 memset(env
, 0, offsetof(CPUARMState
, breakpoints
));
74 g_hash_table_foreach(cpu
->cp_regs
, cp_reg_reset
, cpu
);
75 env
->vfp
.xregs
[ARM_VFP_FPSID
] = cpu
->reset_fpsid
;
76 env
->vfp
.xregs
[ARM_VFP_MVFR0
] = cpu
->mvfr0
;
77 env
->vfp
.xregs
[ARM_VFP_MVFR1
] = cpu
->mvfr1
;
79 if (arm_feature(env
, ARM_FEATURE_IWMMXT
)) {
80 env
->iwmmxt
.cregs
[ARM_IWMMXT_wCID
] = 0x69051000 | 'Q';
83 #if defined(CONFIG_USER_ONLY)
84 env
->uncached_cpsr
= ARM_CPU_MODE_USR
;
85 /* For user mode we must enable access to coprocessors */
86 env
->vfp
.xregs
[ARM_VFP_FPEXC
] = 1 << 30;
87 if (arm_feature(env
, ARM_FEATURE_IWMMXT
)) {
88 env
->cp15
.c15_cpar
= 3;
89 } else if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
90 env
->cp15
.c15_cpar
= 1;
93 /* SVC mode with interrupts disabled. */
94 env
->uncached_cpsr
= ARM_CPU_MODE_SVC
| CPSR_A
| CPSR_F
| CPSR_I
;
95 /* On ARMv7-M the CPSR_I is the value of the PRIMASK register, and is
96 clear at reset. Initial SP and PC are loaded from ROM. */
100 env
->uncached_cpsr
&= ~CPSR_I
;
103 /* We should really use ldl_phys here, in case the guest
104 modified flash and reset itself. However images
105 loaded via -kernel have not been copied yet, so load the
106 values directly from there. */
107 env
->regs
[13] = ldl_p(rom
);
110 env
->regs
[15] = pc
& ~1;
113 env
->vfp
.xregs
[ARM_VFP_FPEXC
] = 0;
115 set_flush_to_zero(1, &env
->vfp
.standard_fp_status
);
116 set_flush_inputs_to_zero(1, &env
->vfp
.standard_fp_status
);
117 set_default_nan_mode(1, &env
->vfp
.standard_fp_status
);
118 set_float_detect_tininess(float_tininess_before_rounding
,
119 &env
->vfp
.fp_status
);
120 set_float_detect_tininess(float_tininess_before_rounding
,
121 &env
->vfp
.standard_fp_status
);
123 /* Reset is a state change for some CPUARMState fields which we
124 * bake assumptions about into translated code, so we need to
130 static inline void set_feature(CPUARMState
*env
, int feature
)
132 env
->features
|= 1ULL << feature
;
135 static void arm_cpu_initfn(Object
*obj
)
137 ARMCPU
*cpu
= ARM_CPU(obj
);
139 cpu_exec_init(&cpu
->env
);
140 cpu
->cp_regs
= g_hash_table_new_full(g_int_hash
, g_int_equal
,
144 static void arm_cpu_finalizefn(Object
*obj
)
146 ARMCPU
*cpu
= ARM_CPU(obj
);
147 g_hash_table_destroy(cpu
->cp_regs
);
150 void arm_cpu_realize(ARMCPU
*cpu
)
152 /* This function is called by cpu_arm_init() because it
153 * needs to do common actions based on feature bits, etc
154 * that have been set by the subclass init functions.
155 * When we have QOM realize support it should become
156 * a true realize function instead.
158 CPUARMState
*env
= &cpu
->env
;
159 /* Some features automatically imply others: */
160 if (arm_feature(env
, ARM_FEATURE_V7
)) {
161 set_feature(env
, ARM_FEATURE_VAPA
);
162 set_feature(env
, ARM_FEATURE_THUMB2
);
163 set_feature(env
, ARM_FEATURE_MPIDR
);
164 if (!arm_feature(env
, ARM_FEATURE_M
)) {
165 set_feature(env
, ARM_FEATURE_V6K
);
167 set_feature(env
, ARM_FEATURE_V6
);
170 if (arm_feature(env
, ARM_FEATURE_V6K
)) {
171 set_feature(env
, ARM_FEATURE_V6
);
172 set_feature(env
, ARM_FEATURE_MVFR
);
174 if (arm_feature(env
, ARM_FEATURE_V6
)) {
175 set_feature(env
, ARM_FEATURE_V5
);
176 if (!arm_feature(env
, ARM_FEATURE_M
)) {
177 set_feature(env
, ARM_FEATURE_AUXCR
);
180 if (arm_feature(env
, ARM_FEATURE_V5
)) {
181 set_feature(env
, ARM_FEATURE_V4T
);
183 if (arm_feature(env
, ARM_FEATURE_M
)) {
184 set_feature(env
, ARM_FEATURE_THUMB_DIV
);
186 if (arm_feature(env
, ARM_FEATURE_ARM_DIV
)) {
187 set_feature(env
, ARM_FEATURE_THUMB_DIV
);
189 if (arm_feature(env
, ARM_FEATURE_VFP4
)) {
190 set_feature(env
, ARM_FEATURE_VFP3
);
192 if (arm_feature(env
, ARM_FEATURE_VFP3
)) {
193 set_feature(env
, ARM_FEATURE_VFP
);
195 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
196 set_feature(env
, ARM_FEATURE_PXN
);
199 register_cp_regs_for_features(cpu
);
204 static ObjectClass
*arm_cpu_class_by_name(const char *cpu_model
)
212 oc
= object_class_by_name(cpu_model
);
213 if (!oc
|| !object_class_dynamic_cast(oc
, TYPE_ARM_CPU
) ||
214 object_class_is_abstract(oc
)) {
220 static void arm926_initfn(Object
*obj
)
222 ARMCPU
*cpu
= ARM_CPU(obj
);
223 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
224 set_feature(&cpu
->env
, ARM_FEATURE_VFP
);
225 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
226 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_TEST_CLEAN
);
227 cpu
->midr
= 0x41069265;
228 cpu
->reset_fpsid
= 0x41011090;
229 cpu
->ctr
= 0x1dd20d2;
230 cpu
->reset_sctlr
= 0x00090078;
233 static void arm946_initfn(Object
*obj
)
235 ARMCPU
*cpu
= ARM_CPU(obj
);
236 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
237 set_feature(&cpu
->env
, ARM_FEATURE_MPU
);
238 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
239 cpu
->midr
= 0x41059461;
240 cpu
->ctr
= 0x0f004006;
241 cpu
->reset_sctlr
= 0x00000078;
244 static void arm1026_initfn(Object
*obj
)
246 ARMCPU
*cpu
= ARM_CPU(obj
);
247 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
248 set_feature(&cpu
->env
, ARM_FEATURE_VFP
);
249 set_feature(&cpu
->env
, ARM_FEATURE_AUXCR
);
250 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
251 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_TEST_CLEAN
);
252 cpu
->midr
= 0x4106a262;
253 cpu
->reset_fpsid
= 0x410110a0;
254 cpu
->ctr
= 0x1dd20d2;
255 cpu
->reset_sctlr
= 0x00090078;
256 cpu
->reset_auxcr
= 1;
258 /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */
259 ARMCPRegInfo ifar
= {
260 .name
= "IFAR", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 1,
262 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_insn
),
265 define_one_arm_cp_reg(cpu
, &ifar
);
269 static void arm1136_r2_initfn(Object
*obj
)
271 ARMCPU
*cpu
= ARM_CPU(obj
);
272 /* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an
273 * older core than plain "arm1136". In particular this does not
274 * have the v6K features.
275 * These ID register values are correct for 1136 but may be wrong
276 * for 1136_r2 (in particular r0p2 does not actually implement most
277 * of the ID registers).
279 set_feature(&cpu
->env
, ARM_FEATURE_V6
);
280 set_feature(&cpu
->env
, ARM_FEATURE_VFP
);
281 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
282 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_DIRTY_REG
);
283 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_BLOCK_OPS
);
284 cpu
->midr
= 0x4107b362;
285 cpu
->reset_fpsid
= 0x410120b4;
286 cpu
->mvfr0
= 0x11111111;
287 cpu
->mvfr1
= 0x00000000;
288 cpu
->ctr
= 0x1dd20d2;
289 cpu
->reset_sctlr
= 0x00050078;
290 cpu
->id_pfr0
= 0x111;
294 cpu
->id_mmfr0
= 0x01130003;
295 cpu
->id_mmfr1
= 0x10030302;
296 cpu
->id_mmfr2
= 0x01222110;
297 cpu
->id_isar0
= 0x00140011;
298 cpu
->id_isar1
= 0x12002111;
299 cpu
->id_isar2
= 0x11231111;
300 cpu
->id_isar3
= 0x01102131;
301 cpu
->id_isar4
= 0x141;
302 cpu
->reset_auxcr
= 7;
305 static void arm1136_initfn(Object
*obj
)
307 ARMCPU
*cpu
= ARM_CPU(obj
);
308 set_feature(&cpu
->env
, ARM_FEATURE_V6K
);
309 set_feature(&cpu
->env
, ARM_FEATURE_V6
);
310 set_feature(&cpu
->env
, ARM_FEATURE_VFP
);
311 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
312 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_DIRTY_REG
);
313 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_BLOCK_OPS
);
314 cpu
->midr
= 0x4117b363;
315 cpu
->reset_fpsid
= 0x410120b4;
316 cpu
->mvfr0
= 0x11111111;
317 cpu
->mvfr1
= 0x00000000;
318 cpu
->ctr
= 0x1dd20d2;
319 cpu
->reset_sctlr
= 0x00050078;
320 cpu
->id_pfr0
= 0x111;
324 cpu
->id_mmfr0
= 0x01130003;
325 cpu
->id_mmfr1
= 0x10030302;
326 cpu
->id_mmfr2
= 0x01222110;
327 cpu
->id_isar0
= 0x00140011;
328 cpu
->id_isar1
= 0x12002111;
329 cpu
->id_isar2
= 0x11231111;
330 cpu
->id_isar3
= 0x01102131;
331 cpu
->id_isar4
= 0x141;
332 cpu
->reset_auxcr
= 7;
335 static void arm1176_initfn(Object
*obj
)
337 ARMCPU
*cpu
= ARM_CPU(obj
);
338 set_feature(&cpu
->env
, ARM_FEATURE_V6K
);
339 set_feature(&cpu
->env
, ARM_FEATURE_VFP
);
340 set_feature(&cpu
->env
, ARM_FEATURE_VAPA
);
341 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
342 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_DIRTY_REG
);
343 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_BLOCK_OPS
);
344 cpu
->midr
= 0x410fb767;
345 cpu
->reset_fpsid
= 0x410120b5;
346 cpu
->mvfr0
= 0x11111111;
347 cpu
->mvfr1
= 0x00000000;
348 cpu
->ctr
= 0x1dd20d2;
349 cpu
->reset_sctlr
= 0x00050078;
350 cpu
->id_pfr0
= 0x111;
354 cpu
->id_mmfr0
= 0x01130003;
355 cpu
->id_mmfr1
= 0x10030302;
356 cpu
->id_mmfr2
= 0x01222100;
357 cpu
->id_isar0
= 0x0140011;
358 cpu
->id_isar1
= 0x12002111;
359 cpu
->id_isar2
= 0x11231121;
360 cpu
->id_isar3
= 0x01102131;
361 cpu
->id_isar4
= 0x01141;
362 cpu
->reset_auxcr
= 7;
365 static void arm11mpcore_initfn(Object
*obj
)
367 ARMCPU
*cpu
= ARM_CPU(obj
);
368 set_feature(&cpu
->env
, ARM_FEATURE_V6K
);
369 set_feature(&cpu
->env
, ARM_FEATURE_VFP
);
370 set_feature(&cpu
->env
, ARM_FEATURE_VAPA
);
371 set_feature(&cpu
->env
, ARM_FEATURE_MPIDR
);
372 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
373 cpu
->midr
= 0x410fb022;
374 cpu
->reset_fpsid
= 0x410120b4;
375 cpu
->mvfr0
= 0x11111111;
376 cpu
->mvfr1
= 0x00000000;
377 cpu
->ctr
= 0x1d192992; /* 32K icache 32K dcache */
378 cpu
->id_pfr0
= 0x111;
382 cpu
->id_mmfr0
= 0x01100103;
383 cpu
->id_mmfr1
= 0x10020302;
384 cpu
->id_mmfr2
= 0x01222000;
385 cpu
->id_isar0
= 0x00100011;
386 cpu
->id_isar1
= 0x12002111;
387 cpu
->id_isar2
= 0x11221011;
388 cpu
->id_isar3
= 0x01102131;
389 cpu
->id_isar4
= 0x141;
390 cpu
->reset_auxcr
= 1;
393 static void cortex_m3_initfn(Object
*obj
)
395 ARMCPU
*cpu
= ARM_CPU(obj
);
396 set_feature(&cpu
->env
, ARM_FEATURE_V7
);
397 set_feature(&cpu
->env
, ARM_FEATURE_M
);
398 cpu
->midr
= 0x410fc231;
401 static const ARMCPRegInfo cortexa8_cp_reginfo
[] = {
402 { .name
= "L2LOCKDOWN", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 1, .opc2
= 0,
403 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
404 { .name
= "L2AUXCR", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 1, .opc2
= 2,
405 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
409 static void cortex_a8_initfn(Object
*obj
)
411 ARMCPU
*cpu
= ARM_CPU(obj
);
412 set_feature(&cpu
->env
, ARM_FEATURE_V7
);
413 set_feature(&cpu
->env
, ARM_FEATURE_VFP3
);
414 set_feature(&cpu
->env
, ARM_FEATURE_NEON
);
415 set_feature(&cpu
->env
, ARM_FEATURE_THUMB2EE
);
416 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
417 cpu
->midr
= 0x410fc080;
418 cpu
->reset_fpsid
= 0x410330c0;
419 cpu
->mvfr0
= 0x11110222;
420 cpu
->mvfr1
= 0x00011100;
421 cpu
->ctr
= 0x82048004;
422 cpu
->reset_sctlr
= 0x00c50078;
423 cpu
->id_pfr0
= 0x1031;
425 cpu
->id_dfr0
= 0x400;
427 cpu
->id_mmfr0
= 0x31100003;
428 cpu
->id_mmfr1
= 0x20000000;
429 cpu
->id_mmfr2
= 0x01202000;
430 cpu
->id_mmfr3
= 0x11;
431 cpu
->id_isar0
= 0x00101111;
432 cpu
->id_isar1
= 0x12112111;
433 cpu
->id_isar2
= 0x21232031;
434 cpu
->id_isar3
= 0x11112131;
435 cpu
->id_isar4
= 0x00111142;
436 cpu
->clidr
= (1 << 27) | (2 << 24) | 3;
437 cpu
->ccsidr
[0] = 0xe007e01a; /* 16k L1 dcache. */
438 cpu
->ccsidr
[1] = 0x2007e01a; /* 16k L1 icache. */
439 cpu
->ccsidr
[2] = 0xf0000000; /* No L2 icache. */
440 cpu
->reset_auxcr
= 2;
441 define_arm_cp_regs(cpu
, cortexa8_cp_reginfo
);
444 static const ARMCPRegInfo cortexa9_cp_reginfo
[] = {
445 /* power_control should be set to maximum latency. Again,
446 * default to 0 and set by private hook
448 { .name
= "A9_PWRCTL", .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 0, .opc2
= 0,
449 .access
= PL1_RW
, .resetvalue
= 0,
450 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_power_control
) },
451 { .name
= "A9_DIAG", .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 0, .opc2
= 1,
452 .access
= PL1_RW
, .resetvalue
= 0,
453 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_diagnostic
) },
454 { .name
= "A9_PWRDIAG", .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 0, .opc2
= 2,
455 .access
= PL1_RW
, .resetvalue
= 0,
456 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_power_diagnostic
) },
457 { .name
= "NEONBUSY", .cp
= 15, .crn
= 15, .crm
= 1, .opc1
= 0, .opc2
= 0,
458 .access
= PL1_RW
, .resetvalue
= 0, .type
= ARM_CP_CONST
},
459 /* TLB lockdown control */
460 { .name
= "TLB_LOCKR", .cp
= 15, .crn
= 15, .crm
= 4, .opc1
= 5, .opc2
= 2,
461 .access
= PL1_W
, .resetvalue
= 0, .type
= ARM_CP_NOP
},
462 { .name
= "TLB_LOCKW", .cp
= 15, .crn
= 15, .crm
= 4, .opc1
= 5, .opc2
= 4,
463 .access
= PL1_W
, .resetvalue
= 0, .type
= ARM_CP_NOP
},
464 { .name
= "TLB_VA", .cp
= 15, .crn
= 15, .crm
= 5, .opc1
= 5, .opc2
= 2,
465 .access
= PL1_RW
, .resetvalue
= 0, .type
= ARM_CP_CONST
},
466 { .name
= "TLB_PA", .cp
= 15, .crn
= 15, .crm
= 6, .opc1
= 5, .opc2
= 2,
467 .access
= PL1_RW
, .resetvalue
= 0, .type
= ARM_CP_CONST
},
468 { .name
= "TLB_ATTR", .cp
= 15, .crn
= 15, .crm
= 7, .opc1
= 5, .opc2
= 2,
469 .access
= PL1_RW
, .resetvalue
= 0, .type
= ARM_CP_CONST
},
473 static void cortex_a9_initfn(Object
*obj
)
475 ARMCPU
*cpu
= ARM_CPU(obj
);
476 set_feature(&cpu
->env
, ARM_FEATURE_V7
);
477 set_feature(&cpu
->env
, ARM_FEATURE_VFP3
);
478 set_feature(&cpu
->env
, ARM_FEATURE_VFP_FP16
);
479 set_feature(&cpu
->env
, ARM_FEATURE_NEON
);
480 set_feature(&cpu
->env
, ARM_FEATURE_THUMB2EE
);
481 /* Note that A9 supports the MP extensions even for
482 * A9UP and single-core A9MP (which are both different
483 * and valid configurations; we don't model A9UP).
485 set_feature(&cpu
->env
, ARM_FEATURE_V7MP
);
486 cpu
->midr
= 0x410fc090;
487 cpu
->reset_fpsid
= 0x41033090;
488 cpu
->mvfr0
= 0x11110222;
489 cpu
->mvfr1
= 0x01111111;
490 cpu
->ctr
= 0x80038003;
491 cpu
->reset_sctlr
= 0x00c50078;
492 cpu
->id_pfr0
= 0x1031;
494 cpu
->id_dfr0
= 0x000;
496 cpu
->id_mmfr0
= 0x00100103;
497 cpu
->id_mmfr1
= 0x20000000;
498 cpu
->id_mmfr2
= 0x01230000;
499 cpu
->id_mmfr3
= 0x00002111;
500 cpu
->id_isar0
= 0x00101111;
501 cpu
->id_isar1
= 0x13112111;
502 cpu
->id_isar2
= 0x21232041;
503 cpu
->id_isar3
= 0x11112131;
504 cpu
->id_isar4
= 0x00111142;
505 cpu
->clidr
= (1 << 27) | (1 << 24) | 3;
506 cpu
->ccsidr
[0] = 0xe00fe015; /* 16k L1 dcache. */
507 cpu
->ccsidr
[1] = 0x200fe015; /* 16k L1 icache. */
509 ARMCPRegInfo cbar
= {
510 .name
= "CBAR", .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 4,
511 .opc2
= 0, .access
= PL1_R
|PL3_W
, .resetvalue
= cpu
->reset_cbar
,
512 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_config_base_address
)
514 define_one_arm_cp_reg(cpu
, &cbar
);
515 define_arm_cp_regs(cpu
, cortexa9_cp_reginfo
);
519 #ifndef CONFIG_USER_ONLY
520 static int a15_l2ctlr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
523 /* Linux wants the number of processors from here.
524 * Might as well set the interrupt-controller bit too.
526 *value
= ((smp_cpus
- 1) << 24) | (1 << 23);
531 static const ARMCPRegInfo cortexa15_cp_reginfo
[] = {
532 #ifndef CONFIG_USER_ONLY
533 { .name
= "L2CTLR", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 1, .opc2
= 2,
534 .access
= PL1_RW
, .resetvalue
= 0, .readfn
= a15_l2ctlr_read
,
535 .writefn
= arm_cp_write_ignore
, },
537 { .name
= "L2ECTLR", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 1, .opc2
= 3,
538 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
542 static void cortex_a15_initfn(Object
*obj
)
544 ARMCPU
*cpu
= ARM_CPU(obj
);
545 set_feature(&cpu
->env
, ARM_FEATURE_V7
);
546 set_feature(&cpu
->env
, ARM_FEATURE_VFP4
);
547 set_feature(&cpu
->env
, ARM_FEATURE_VFP_FP16
);
548 set_feature(&cpu
->env
, ARM_FEATURE_NEON
);
549 set_feature(&cpu
->env
, ARM_FEATURE_THUMB2EE
);
550 set_feature(&cpu
->env
, ARM_FEATURE_ARM_DIV
);
551 set_feature(&cpu
->env
, ARM_FEATURE_V7MP
);
552 set_feature(&cpu
->env
, ARM_FEATURE_GENERIC_TIMER
);
553 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
554 set_feature(&cpu
->env
, ARM_FEATURE_LPAE
);
555 cpu
->midr
= 0x412fc0f1;
556 cpu
->reset_fpsid
= 0x410430f0;
557 cpu
->mvfr0
= 0x10110222;
558 cpu
->mvfr1
= 0x11111111;
559 cpu
->ctr
= 0x8444c004;
560 cpu
->reset_sctlr
= 0x00c50078;
561 cpu
->id_pfr0
= 0x00001131;
562 cpu
->id_pfr1
= 0x00011011;
563 cpu
->id_dfr0
= 0x02010555;
564 cpu
->id_afr0
= 0x00000000;
565 cpu
->id_mmfr0
= 0x10201105;
566 cpu
->id_mmfr1
= 0x20000000;
567 cpu
->id_mmfr2
= 0x01240000;
568 cpu
->id_mmfr3
= 0x02102211;
569 cpu
->id_isar0
= 0x02101110;
570 cpu
->id_isar1
= 0x13112111;
571 cpu
->id_isar2
= 0x21232041;
572 cpu
->id_isar3
= 0x11112131;
573 cpu
->id_isar4
= 0x10011142;
574 cpu
->clidr
= 0x0a200023;
575 cpu
->ccsidr
[0] = 0x701fe00a; /* 32K L1 dcache */
576 cpu
->ccsidr
[1] = 0x201fe00a; /* 32K L1 icache */
577 cpu
->ccsidr
[2] = 0x711fe07a; /* 4096K L2 unified cache */
578 define_arm_cp_regs(cpu
, cortexa15_cp_reginfo
);
581 static void ti925t_initfn(Object
*obj
)
583 ARMCPU
*cpu
= ARM_CPU(obj
);
584 set_feature(&cpu
->env
, ARM_FEATURE_V4T
);
585 set_feature(&cpu
->env
, ARM_FEATURE_OMAPCP
);
586 cpu
->midr
= ARM_CPUID_TI925T
;
587 cpu
->ctr
= 0x5109149;
588 cpu
->reset_sctlr
= 0x00000070;
591 static void sa1100_initfn(Object
*obj
)
593 ARMCPU
*cpu
= ARM_CPU(obj
);
594 set_feature(&cpu
->env
, ARM_FEATURE_STRONGARM
);
595 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
596 cpu
->midr
= 0x4401A11B;
597 cpu
->reset_sctlr
= 0x00000070;
600 static void sa1110_initfn(Object
*obj
)
602 ARMCPU
*cpu
= ARM_CPU(obj
);
603 set_feature(&cpu
->env
, ARM_FEATURE_STRONGARM
);
604 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
605 cpu
->midr
= 0x6901B119;
606 cpu
->reset_sctlr
= 0x00000070;
609 static void pxa250_initfn(Object
*obj
)
611 ARMCPU
*cpu
= ARM_CPU(obj
);
612 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
613 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
614 cpu
->midr
= 0x69052100;
615 cpu
->ctr
= 0xd172172;
616 cpu
->reset_sctlr
= 0x00000078;
619 static void pxa255_initfn(Object
*obj
)
621 ARMCPU
*cpu
= ARM_CPU(obj
);
622 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
623 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
624 cpu
->midr
= 0x69052d00;
625 cpu
->ctr
= 0xd172172;
626 cpu
->reset_sctlr
= 0x00000078;
629 static void pxa260_initfn(Object
*obj
)
631 ARMCPU
*cpu
= ARM_CPU(obj
);
632 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
633 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
634 cpu
->midr
= 0x69052903;
635 cpu
->ctr
= 0xd172172;
636 cpu
->reset_sctlr
= 0x00000078;
639 static void pxa261_initfn(Object
*obj
)
641 ARMCPU
*cpu
= ARM_CPU(obj
);
642 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
643 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
644 cpu
->midr
= 0x69052d05;
645 cpu
->ctr
= 0xd172172;
646 cpu
->reset_sctlr
= 0x00000078;
649 static void pxa262_initfn(Object
*obj
)
651 ARMCPU
*cpu
= ARM_CPU(obj
);
652 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
653 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
654 cpu
->midr
= 0x69052d06;
655 cpu
->ctr
= 0xd172172;
656 cpu
->reset_sctlr
= 0x00000078;
659 static void pxa270a0_initfn(Object
*obj
)
661 ARMCPU
*cpu
= ARM_CPU(obj
);
662 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
663 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
664 set_feature(&cpu
->env
, ARM_FEATURE_IWMMXT
);
665 cpu
->midr
= 0x69054110;
666 cpu
->ctr
= 0xd172172;
667 cpu
->reset_sctlr
= 0x00000078;
670 static void pxa270a1_initfn(Object
*obj
)
672 ARMCPU
*cpu
= ARM_CPU(obj
);
673 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
674 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
675 set_feature(&cpu
->env
, ARM_FEATURE_IWMMXT
);
676 cpu
->midr
= 0x69054111;
677 cpu
->ctr
= 0xd172172;
678 cpu
->reset_sctlr
= 0x00000078;
681 static void pxa270b0_initfn(Object
*obj
)
683 ARMCPU
*cpu
= ARM_CPU(obj
);
684 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
685 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
686 set_feature(&cpu
->env
, ARM_FEATURE_IWMMXT
);
687 cpu
->midr
= 0x69054112;
688 cpu
->ctr
= 0xd172172;
689 cpu
->reset_sctlr
= 0x00000078;
692 static void pxa270b1_initfn(Object
*obj
)
694 ARMCPU
*cpu
= ARM_CPU(obj
);
695 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
696 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
697 set_feature(&cpu
->env
, ARM_FEATURE_IWMMXT
);
698 cpu
->midr
= 0x69054113;
699 cpu
->ctr
= 0xd172172;
700 cpu
->reset_sctlr
= 0x00000078;
703 static void pxa270c0_initfn(Object
*obj
)
705 ARMCPU
*cpu
= ARM_CPU(obj
);
706 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
707 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
708 set_feature(&cpu
->env
, ARM_FEATURE_IWMMXT
);
709 cpu
->midr
= 0x69054114;
710 cpu
->ctr
= 0xd172172;
711 cpu
->reset_sctlr
= 0x00000078;
714 static void pxa270c5_initfn(Object
*obj
)
716 ARMCPU
*cpu
= ARM_CPU(obj
);
717 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
718 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
719 set_feature(&cpu
->env
, ARM_FEATURE_IWMMXT
);
720 cpu
->midr
= 0x69054117;
721 cpu
->ctr
= 0xd172172;
722 cpu
->reset_sctlr
= 0x00000078;
725 static void arm_any_initfn(Object
*obj
)
727 ARMCPU
*cpu
= ARM_CPU(obj
);
728 set_feature(&cpu
->env
, ARM_FEATURE_V7
);
729 set_feature(&cpu
->env
, ARM_FEATURE_VFP4
);
730 set_feature(&cpu
->env
, ARM_FEATURE_VFP_FP16
);
731 set_feature(&cpu
->env
, ARM_FEATURE_NEON
);
732 set_feature(&cpu
->env
, ARM_FEATURE_THUMB2EE
);
733 set_feature(&cpu
->env
, ARM_FEATURE_ARM_DIV
);
734 set_feature(&cpu
->env
, ARM_FEATURE_V7MP
);
735 cpu
->midr
= 0xffffffff;
738 typedef struct ARMCPUInfo
{
740 void (*initfn
)(Object
*obj
);
743 static const ARMCPUInfo arm_cpus
[] = {
744 { .name
= "arm926", .initfn
= arm926_initfn
},
745 { .name
= "arm946", .initfn
= arm946_initfn
},
746 { .name
= "arm1026", .initfn
= arm1026_initfn
},
747 /* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an
748 * older core than plain "arm1136". In particular this does not
749 * have the v6K features.
751 { .name
= "arm1136-r2", .initfn
= arm1136_r2_initfn
},
752 { .name
= "arm1136", .initfn
= arm1136_initfn
},
753 { .name
= "arm1176", .initfn
= arm1176_initfn
},
754 { .name
= "arm11mpcore", .initfn
= arm11mpcore_initfn
},
755 { .name
= "cortex-m3", .initfn
= cortex_m3_initfn
},
756 { .name
= "cortex-a8", .initfn
= cortex_a8_initfn
},
757 { .name
= "cortex-a9", .initfn
= cortex_a9_initfn
},
758 { .name
= "cortex-a15", .initfn
= cortex_a15_initfn
},
759 { .name
= "ti925t", .initfn
= ti925t_initfn
},
760 { .name
= "sa1100", .initfn
= sa1100_initfn
},
761 { .name
= "sa1110", .initfn
= sa1110_initfn
},
762 { .name
= "pxa250", .initfn
= pxa250_initfn
},
763 { .name
= "pxa255", .initfn
= pxa255_initfn
},
764 { .name
= "pxa260", .initfn
= pxa260_initfn
},
765 { .name
= "pxa261", .initfn
= pxa261_initfn
},
766 { .name
= "pxa262", .initfn
= pxa262_initfn
},
767 /* "pxa270" is an alias for "pxa270-a0" */
768 { .name
= "pxa270", .initfn
= pxa270a0_initfn
},
769 { .name
= "pxa270-a0", .initfn
= pxa270a0_initfn
},
770 { .name
= "pxa270-a1", .initfn
= pxa270a1_initfn
},
771 { .name
= "pxa270-b0", .initfn
= pxa270b0_initfn
},
772 { .name
= "pxa270-b1", .initfn
= pxa270b1_initfn
},
773 { .name
= "pxa270-c0", .initfn
= pxa270c0_initfn
},
774 { .name
= "pxa270-c5", .initfn
= pxa270c5_initfn
},
775 { .name
= "any", .initfn
= arm_any_initfn
},
778 static void arm_cpu_class_init(ObjectClass
*oc
, void *data
)
780 ARMCPUClass
*acc
= ARM_CPU_CLASS(oc
);
781 CPUClass
*cc
= CPU_CLASS(acc
);
783 acc
->parent_reset
= cc
->reset
;
784 cc
->reset
= arm_cpu_reset
;
786 cc
->class_by_name
= arm_cpu_class_by_name
;
789 static void cpu_register(const ARMCPUInfo
*info
)
791 TypeInfo type_info
= {
793 .parent
= TYPE_ARM_CPU
,
794 .instance_size
= sizeof(ARMCPU
),
795 .instance_init
= info
->initfn
,
796 .class_size
= sizeof(ARMCPUClass
),
799 type_register(&type_info
);
802 static const TypeInfo arm_cpu_type_info
= {
803 .name
= TYPE_ARM_CPU
,
805 .instance_size
= sizeof(ARMCPU
),
806 .instance_init
= arm_cpu_initfn
,
807 .instance_finalize
= arm_cpu_finalizefn
,
809 .class_size
= sizeof(ARMCPUClass
),
810 .class_init
= arm_cpu_class_init
,
813 static void arm_cpu_register_types(void)
817 type_register_static(&arm_cpu_type_info
);
818 for (i
= 0; i
< ARRAY_SIZE(arm_cpus
); i
++) {
819 cpu_register(&arm_cpus
[i
]);
823 type_init(arm_cpu_register_types
)