hw/pci-host/q35.c

   1 /*
   2  * QEMU MCH/ICH9 PCI Bridge Emulation
   3  *
   4  * Copyright (c) 2006 Fabrice Bellard
   5  * Copyright (c) 2009, 2010, 2011
   6  *               Isaku Yamahata <yamahata at valinux co jp>
   7  *               VA Linux Systems Japan K.K.
   8  * Copyright (C) 2012 Jason Baron <jbaron@redhat.com>
   9  *
  10  * This is based on piix.c, but heavily modified.
  11  *
  12  * Permission is hereby granted, free of charge, to any person obtaining a copy
  13  * of this software and associated documentation files (the "Software"), to deal
  14  * in the Software without restriction, including without limitation the rights
  15  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  16  * copies of the Software, and to permit persons to whom the Software is
  17  * furnished to do so, subject to the following conditions:
  18  *
  19  * The above copyright notice and this permission notice shall be included in
  20  * all copies or substantial portions of the Software.
  21  *
  22  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  23  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  24  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  25  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  26  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  27  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  28  * THE SOFTWARE.
  29  */
  30 #include "qemu/osdep.h"
  31 #include "hw/hw.h"
  32 #include "hw/pci-host/q35.h"
  33 #include "qapi/error.h"
  34 #include "qapi/visitor.h"
  35
  36 /****************************************************************************
  37  * Q35 host
  38  */
  39
  40 static void q35_host_realize(DeviceState *dev, Error **errp)
  41 {
  42     PCIHostState *pci = PCI_HOST_BRIDGE(dev);
  43     Q35PCIHost *s = Q35_HOST_DEVICE(dev);
  44     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
  45
  46     sysbus_add_io(sbd, MCH_HOST_BRIDGE_CONFIG_ADDR, &pci->conf_mem);
  47     sysbus_init_ioports(sbd, MCH_HOST_BRIDGE_CONFIG_ADDR, 4);
  48
  49     sysbus_add_io(sbd, MCH_HOST_BRIDGE_CONFIG_DATA, &pci->data_mem);
  50     sysbus_init_ioports(sbd, MCH_HOST_BRIDGE_CONFIG_DATA, 4);
  51
  52     pci->bus = pci_bus_new(DEVICE(s), "pcie.0",
  53                            s->mch.pci_address_space, s->mch.address_space_io,
  54                            0, TYPE_PCIE_BUS);
  55     qdev_set_parent_bus(DEVICE(&s->mch), BUS(pci->bus));
  56     qdev_init_nofail(DEVICE(&s->mch));
  57 }
  58
  59 static const char *q35_host_root_bus_path(PCIHostState *host_bridge,
  60                                           PCIBus *rootbus)
  61 {
  62     Q35PCIHost *s = Q35_HOST_DEVICE(host_bridge);
  63
  64      /* For backwards compat with old device paths */
  65     if (s->mch.short_root_bus) {
  66         return "0000";
  67     }
  68     return "0000:00";
  69 }
  70
  71 static void q35_host_get_pci_hole_start(Object *obj, Visitor *v,
  72                                         const char *name, void *opaque,
  73                                         Error **errp)
  74 {
  75     Q35PCIHost *s = Q35_HOST_DEVICE(obj);
  76     uint32_t value = s->mch.pci_info.w32.begin;
  77
  78     visit_type_uint32(v, name, &value, errp);
  79 }
  80
  81 static void q35_host_get_pci_hole_end(Object *obj, Visitor *v,
  82                                       const char *name, void *opaque,
  83                                       Error **errp)
  84 {
  85     Q35PCIHost *s = Q35_HOST_DEVICE(obj);
  86     uint32_t value = s->mch.pci_info.w32.end;
  87
  88     visit_type_uint32(v, name, &value, errp);
  89 }
  90
  91 static void q35_host_get_pci_hole64_start(Object *obj, Visitor *v,
  92                                           const char *name, void *opaque,
  93                                           Error **errp)
  94 {
  95     PCIHostState *h = PCI_HOST_BRIDGE(obj);
  96     Range w64;
  97
  98     pci_bus_get_w64_range(h->bus, &w64);
  99
 100     visit_type_uint64(v, name, &w64.begin, errp);
 101 }
 102
 103 static void q35_host_get_pci_hole64_end(Object *obj, Visitor *v,
 104                                         const char *name, void *opaque,
 105                                         Error **errp)
 106 {
 107     PCIHostState *h = PCI_HOST_BRIDGE(obj);
 108     Range w64;
 109
 110     pci_bus_get_w64_range(h->bus, &w64);
 111
 112     visit_type_uint64(v, name, &w64.end, errp);
 113 }
 114
 115 static void q35_host_get_mmcfg_size(Object *obj, Visitor *v, const char *name,
 116                                     void *opaque, Error **errp)
 117 {
 118     PCIExpressHost *e = PCIE_HOST_BRIDGE(obj);
 119     uint32_t value = e->size;
 120
 121     visit_type_uint32(v, name, &value, errp);
 122 }
 123
 124 static Property mch_props[] = {
 125     DEFINE_PROP_UINT64(PCIE_HOST_MCFG_BASE, Q35PCIHost, parent_obj.base_addr,
 126                         MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT),
 127     DEFINE_PROP_SIZE(PCI_HOST_PROP_PCI_HOLE64_SIZE, Q35PCIHost,
 128                      mch.pci_hole64_size, DEFAULT_PCI_HOLE64_SIZE),
 129     DEFINE_PROP_UINT32("short_root_bus", Q35PCIHost, mch.short_root_bus, 0),
 130     DEFINE_PROP_END_OF_LIST(),
 131 };
 132
 133 static void q35_host_class_init(ObjectClass *klass, void *data)
 134 {
 135     DeviceClass *dc = DEVICE_CLASS(klass);
 136     PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass);
 137
 138     hc->root_bus_path = q35_host_root_bus_path;
 139     dc->realize = q35_host_realize;
 140     dc->props = mch_props;
 141     set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
 142     dc->fw_name = "pci";
 143 }
 144
 145 static void q35_host_initfn(Object *obj)
 146 {
 147     Q35PCIHost *s = Q35_HOST_DEVICE(obj);
 148     PCIHostState *phb = PCI_HOST_BRIDGE(obj);
 149
 150     memory_region_init_io(&phb->conf_mem, obj, &pci_host_conf_le_ops, phb,
 151                           "pci-conf-idx", 4);
 152     memory_region_init_io(&phb->data_mem, obj, &pci_host_data_le_ops, phb,
 153                           "pci-conf-data", 4);
 154
 155     object_initialize(&s->mch, sizeof(s->mch), TYPE_MCH_PCI_DEVICE);
 156     object_property_add_child(OBJECT(s), "mch", OBJECT(&s->mch), NULL);
 157     qdev_prop_set_uint32(DEVICE(&s->mch), "addr", PCI_DEVFN(0, 0));
 158     qdev_prop_set_bit(DEVICE(&s->mch), "multifunction", false);
 159
 160     object_property_add(obj, PCI_HOST_PROP_PCI_HOLE_START, "int",
 161                         q35_host_get_pci_hole_start,
 162                         NULL, NULL, NULL, NULL);
 163
 164     object_property_add(obj, PCI_HOST_PROP_PCI_HOLE_END, "int",
 165                         q35_host_get_pci_hole_end,
 166                         NULL, NULL, NULL, NULL);
 167
 168     object_property_add(obj, PCI_HOST_PROP_PCI_HOLE64_START, "int",
 169                         q35_host_get_pci_hole64_start,
 170                         NULL, NULL, NULL, NULL);
 171
 172     object_property_add(obj, PCI_HOST_PROP_PCI_HOLE64_END, "int",
 173                         q35_host_get_pci_hole64_end,
 174                         NULL, NULL, NULL, NULL);
 175
 176     object_property_add(obj, PCIE_HOST_MCFG_SIZE, "int",
 177                         q35_host_get_mmcfg_size,
 178                         NULL, NULL, NULL, NULL);
 179
 180     /* Leave enough space for the biggest MCFG BAR */
 181     /* TODO: this matches current bios behaviour, but
 182      * it's not a power of two, which means an MTRR
 183      * can't cover it exactly.
 184      */
 185     s->mch.pci_info.w32.begin = MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT +
 186         MCH_HOST_BRIDGE_PCIEXBAR_MAX;
 187     s->mch.pci_info.w32.end = IO_APIC_DEFAULT_ADDRESS;
 188 }
 189
 190 static const TypeInfo q35_host_info = {
 191     .name       = TYPE_Q35_HOST_DEVICE,
 192     .parent     = TYPE_PCIE_HOST_BRIDGE,
 193     .instance_size = sizeof(Q35PCIHost),
 194     .instance_init = q35_host_initfn,
 195     .class_init = q35_host_class_init,
 196 };
 197
 198 /****************************************************************************
 199  * MCH D0:F0
 200  */
 201
 202 static uint64_t tseg_blackhole_read(void *ptr, hwaddr reg, unsigned size)
 203 {
 204     return 0xffffffff;
 205 }
 206
 207 static void tseg_blackhole_write(void *opaque, hwaddr addr, uint64_t val,
 208                                  unsigned width)
 209 {
 210     /* nothing */
 211 }
 212
 213 static const MemoryRegionOps tseg_blackhole_ops = {
 214     .read = tseg_blackhole_read,
 215     .write = tseg_blackhole_write,
 216     .endianness = DEVICE_NATIVE_ENDIAN,
 217     .valid.min_access_size = 1,
 218     .valid.max_access_size = 4,
 219     .impl.min_access_size = 4,
 220     .impl.max_access_size = 4,
 221     .endianness = DEVICE_LITTLE_ENDIAN,
 222 };
 223
 224 /* PCIe MMCFG */
 225 static void mch_update_pciexbar(MCHPCIState *mch)
 226 {
 227     PCIDevice *pci_dev = PCI_DEVICE(mch);
 228     BusState *bus = qdev_get_parent_bus(DEVICE(mch));
 229     PCIExpressHost *pehb = PCIE_HOST_BRIDGE(bus->parent);
 230
 231     uint64_t pciexbar;
 232     int enable;
 233     uint64_t addr;
 234     uint64_t addr_mask;
 235     uint32_t length;
 236
 237     pciexbar = pci_get_quad(pci_dev->config + MCH_HOST_BRIDGE_PCIEXBAR);
 238     enable = pciexbar & MCH_HOST_BRIDGE_PCIEXBAREN;
 239     addr_mask = MCH_HOST_BRIDGE_PCIEXBAR_ADMSK;
 240     switch (pciexbar & MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_MASK) {
 241     case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_256M:
 242         length = 256 * 1024 * 1024;
 243         break;
 244     case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_128M:
 245         length = 128 * 1024 * 1024;
 246         addr_mask |= MCH_HOST_BRIDGE_PCIEXBAR_128ADMSK |
 247             MCH_HOST_BRIDGE_PCIEXBAR_64ADMSK;
 248         break;
 249     case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_64M:
 250         length = 64 * 1024 * 1024;
 251         addr_mask |= MCH_HOST_BRIDGE_PCIEXBAR_64ADMSK;
 252         break;
 253     case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_RVD:
 254     default:
 255         enable = 0;
 256         length = 0;
 257         abort();
 258         break;
 259     }
 260     addr = pciexbar & addr_mask;
 261     pcie_host_mmcfg_update(pehb, enable, addr, length);
 262     /* Leave enough space for the MCFG BAR */
 263     /*
 264      * TODO: this matches current bios behaviour, but it's not a power of two,
 265      * which means an MTRR can't cover it exactly.
 266      */
 267     if (enable) {
 268         mch->pci_info.w32.begin = addr + length;
 269     } else {
 270         mch->pci_info.w32.begin = MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT;
 271     }
 272 }
 273
 274 /* PAM */
 275 static void mch_update_pam(MCHPCIState *mch)
 276 {
 277     PCIDevice *pd = PCI_DEVICE(mch);
 278     int i;
 279
 280     memory_region_transaction_begin();
 281     for (i = 0; i < 13; i++) {
 282         pam_update(&mch->pam_regions[i], i,
 283                    pd->config[MCH_HOST_BRIDGE_PAM0 + ((i + 1) / 2)]);
 284     }
 285     memory_region_transaction_commit();
 286 }
 287
 288 /* SMRAM */
 289 static void mch_update_smram(MCHPCIState *mch)
 290 {
 291     PCIDevice *pd = PCI_DEVICE(mch);
 292     bool h_smrame = (pd->config[MCH_HOST_BRIDGE_ESMRAMC] & MCH_HOST_BRIDGE_ESMRAMC_H_SMRAME);
 293     uint32_t tseg_size;
 294
 295     /* implement SMRAM.D_LCK */
 296     if (pd->config[MCH_HOST_BRIDGE_SMRAM] & MCH_HOST_BRIDGE_SMRAM_D_LCK) {
 297         pd->config[MCH_HOST_BRIDGE_SMRAM] &= ~MCH_HOST_BRIDGE_SMRAM_D_OPEN;
 298         pd->wmask[MCH_HOST_BRIDGE_SMRAM] = MCH_HOST_BRIDGE_SMRAM_WMASK_LCK;
 299         pd->wmask[MCH_HOST_BRIDGE_ESMRAMC] = MCH_HOST_BRIDGE_ESMRAMC_WMASK_LCK;
 300     }
 301
 302     memory_region_transaction_begin();
 303
 304     if (pd->config[MCH_HOST_BRIDGE_SMRAM] & SMRAM_D_OPEN) {
 305         /* Hide (!) low SMRAM if H_SMRAME = 1 */
 306         memory_region_set_enabled(&mch->smram_region, h_smrame);
 307         /* Show high SMRAM if H_SMRAME = 1 */
 308         memory_region_set_enabled(&mch->open_high_smram, h_smrame);
 309     } else {
 310         /* Hide high SMRAM and low SMRAM */
 311         memory_region_set_enabled(&mch->smram_region, true);
 312         memory_region_set_enabled(&mch->open_high_smram, false);
 313     }
 314
 315     if (pd->config[MCH_HOST_BRIDGE_SMRAM] & SMRAM_G_SMRAME) {
 316         memory_region_set_enabled(&mch->low_smram, !h_smrame);
 317         memory_region_set_enabled(&mch->high_smram, h_smrame);
 318     } else {
 319         memory_region_set_enabled(&mch->low_smram, false);
 320         memory_region_set_enabled(&mch->high_smram, false);
 321     }
 322
 323     if (pd->config[MCH_HOST_BRIDGE_ESMRAMC] & MCH_HOST_BRIDGE_ESMRAMC_T_EN) {
 324         switch (pd->config[MCH_HOST_BRIDGE_ESMRAMC] &
 325                 MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_MASK) {
 326         case MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_1MB:
 327             tseg_size = 1024 * 1024;
 328             break;
 329         case MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_2MB:
 330             tseg_size = 1024 * 1024 * 2;
 331             break;
 332         case MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_8MB:
 333             tseg_size = 1024 * 1024 * 8;
 334             break;
 335         default:
 336             tseg_size = 0;
 337             break;
 338         }
 339     } else {
 340         tseg_size = 0;
 341     }
 342     memory_region_del_subregion(mch->system_memory, &mch->tseg_blackhole);
 343     memory_region_set_enabled(&mch->tseg_blackhole, tseg_size);
 344     memory_region_set_size(&mch->tseg_blackhole, tseg_size);
 345     memory_region_add_subregion_overlap(mch->system_memory,
 346                                         mch->below_4g_mem_size - tseg_size,
 347                                         &mch->tseg_blackhole, 1);
 348
 349     memory_region_set_enabled(&mch->tseg_window, tseg_size);
 350     memory_region_set_size(&mch->tseg_window, tseg_size);
 351     memory_region_set_address(&mch->tseg_window,
 352                               mch->below_4g_mem_size - tseg_size);
 353     memory_region_set_alias_offset(&mch->tseg_window,
 354                                    mch->below_4g_mem_size - tseg_size);
 355
 356     memory_region_transaction_commit();
 357 }
 358
 359 static void mch_write_config(PCIDevice *d,
 360                               uint32_t address, uint32_t val, int len)
 361 {
 362     MCHPCIState *mch = MCH_PCI_DEVICE(d);
 363
 364     pci_default_write_config(d, address, val, len);
 365
 366     if (ranges_overlap(address, len, MCH_HOST_BRIDGE_PAM0,
 367                        MCH_HOST_BRIDGE_PAM_SIZE)) {
 368         mch_update_pam(mch);
 369     }
 370
 371     if (ranges_overlap(address, len, MCH_HOST_BRIDGE_PCIEXBAR,
 372                        MCH_HOST_BRIDGE_PCIEXBAR_SIZE)) {
 373         mch_update_pciexbar(mch);
 374     }
 375
 376     if (ranges_overlap(address, len, MCH_HOST_BRIDGE_SMRAM,
 377                        MCH_HOST_BRIDGE_SMRAM_SIZE)) {
 378         mch_update_smram(mch);
 379     }
 380 }
 381
 382 static void mch_update(MCHPCIState *mch)
 383 {
 384     mch_update_pciexbar(mch);
 385     mch_update_pam(mch);
 386     mch_update_smram(mch);
 387 }
 388
 389 static int mch_post_load(void *opaque, int version_id)
 390 {
 391     MCHPCIState *mch = opaque;
 392     mch_update(mch);
 393     return 0;
 394 }
 395
 396 static const VMStateDescription vmstate_mch = {
 397     .name = "mch",
 398     .version_id = 1,
 399     .minimum_version_id = 1,
 400     .post_load = mch_post_load,
 401     .fields = (VMStateField[]) {
 402         VMSTATE_PCI_DEVICE(parent_obj, MCHPCIState),
 403         /* Used to be smm_enabled, which was basically always zero because
 404          * SeaBIOS hardly uses SMM.  SMRAM is now handled by CPU code.
 405          */
 406         VMSTATE_UNUSED(1),
 407         VMSTATE_END_OF_LIST()
 408     }
 409 };
 410
 411 static void mch_reset(DeviceState *qdev)
 412 {
 413     PCIDevice *d = PCI_DEVICE(qdev);
 414     MCHPCIState *mch = MCH_PCI_DEVICE(d);
 415
 416     pci_set_quad(d->config + MCH_HOST_BRIDGE_PCIEXBAR,
 417                  MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT);
 418
 419     d->config[MCH_HOST_BRIDGE_SMRAM] = MCH_HOST_BRIDGE_SMRAM_DEFAULT;
 420     d->config[MCH_HOST_BRIDGE_ESMRAMC] = MCH_HOST_BRIDGE_ESMRAMC_DEFAULT;
 421     d->wmask[MCH_HOST_BRIDGE_SMRAM] = MCH_HOST_BRIDGE_SMRAM_WMASK;
 422     d->wmask[MCH_HOST_BRIDGE_ESMRAMC] = MCH_HOST_BRIDGE_ESMRAMC_WMASK;
 423
 424     mch_update(mch);
 425 }
 426
 427 static AddressSpace *q35_host_dma_iommu(PCIBus *bus, void *opaque, int devfn)
 428 {
 429     IntelIOMMUState *s = opaque;
 430     VTDAddressSpace *vtd_as;
 431
 432     assert(0 <= devfn && devfn <= VTD_PCI_DEVFN_MAX);
 433
 434     vtd_as = vtd_find_add_as(s, bus, devfn);
 435     return &vtd_as->as;
 436 }
 437
 438 static void mch_init_dmar(MCHPCIState *mch)
 439 {
 440     PCIBus *pci_bus = PCI_BUS(qdev_get_parent_bus(DEVICE(mch)));
 441
 442     mch->iommu = INTEL_IOMMU_DEVICE(qdev_create(NULL, TYPE_INTEL_IOMMU_DEVICE));
 443     object_property_add_child(OBJECT(mch), "intel-iommu",
 444                               OBJECT(mch->iommu), NULL);
 445     qdev_init_nofail(DEVICE(mch->iommu));
 446     sysbus_mmio_map(SYS_BUS_DEVICE(mch->iommu), 0, Q35_HOST_BRIDGE_IOMMU_ADDR);
 447
 448     pci_setup_iommu(pci_bus, q35_host_dma_iommu, mch->iommu);
 449 }
 450
 451 static void mch_realize(PCIDevice *d, Error **errp)
 452 {
 453     int i;
 454     MCHPCIState *mch = MCH_PCI_DEVICE(d);
 455
 456     /* setup pci memory mapping */
 457     pc_pci_as_mapping_init(OBJECT(mch), mch->system_memory,
 458                            mch->pci_address_space);
 459
 460     /* if *disabled* show SMRAM to all CPUs */
 461     memory_region_init_alias(&mch->smram_region, OBJECT(mch), "smram-region",
 462                              mch->pci_address_space, 0xa0000, 0x20000);
 463     memory_region_add_subregion_overlap(mch->system_memory, 0xa0000,
 464                                         &mch->smram_region, 1);
 465     memory_region_set_enabled(&mch->smram_region, true);
 466
 467     memory_region_init_alias(&mch->open_high_smram, OBJECT(mch), "smram-open-high",
 468                              mch->ram_memory, 0xa0000, 0x20000);
 469     memory_region_add_subregion_overlap(mch->system_memory, 0xfeda0000,
 470                                         &mch->open_high_smram, 1);
 471     memory_region_set_enabled(&mch->open_high_smram, false);
 472
 473     /* smram, as seen by SMM CPUs */
 474     memory_region_init(&mch->smram, OBJECT(mch), "smram", 1ull << 32);
 475     memory_region_set_enabled(&mch->smram, true);
 476     memory_region_init_alias(&mch->low_smram, OBJECT(mch), "smram-low",
 477                              mch->ram_memory, 0xa0000, 0x20000);
 478     memory_region_set_enabled(&mch->low_smram, true);
 479     memory_region_add_subregion(&mch->smram, 0xa0000, &mch->low_smram);
 480     memory_region_init_alias(&mch->high_smram, OBJECT(mch), "smram-high",
 481                              mch->ram_memory, 0xa0000, 0x20000);
 482     memory_region_set_enabled(&mch->high_smram, true);
 483     memory_region_add_subregion(&mch->smram, 0xfeda0000, &mch->high_smram);
 484
 485     memory_region_init_io(&mch->tseg_blackhole, OBJECT(mch),
 486                           &tseg_blackhole_ops, NULL,
 487                           "tseg-blackhole", 0);
 488     memory_region_set_enabled(&mch->tseg_blackhole, false);
 489     memory_region_add_subregion_overlap(mch->system_memory,
 490                                         mch->below_4g_mem_size,
 491                                         &mch->tseg_blackhole, 1);
 492
 493     memory_region_init_alias(&mch->tseg_window, OBJECT(mch), "tseg-window",
 494                              mch->ram_memory, mch->below_4g_mem_size, 0);
 495     memory_region_set_enabled(&mch->tseg_window, false);
 496     memory_region_add_subregion(&mch->smram, mch->below_4g_mem_size,
 497                                 &mch->tseg_window);
 498     object_property_add_const_link(qdev_get_machine(), "smram",
 499                                    OBJECT(&mch->smram), &error_abort);
 500
 501     init_pam(DEVICE(mch), mch->ram_memory, mch->system_memory,
 502              mch->pci_address_space, &mch->pam_regions[0],
 503              PAM_BIOS_BASE, PAM_BIOS_SIZE);
 504     for (i = 0; i < 12; ++i) {
 505         init_pam(DEVICE(mch), mch->ram_memory, mch->system_memory,
 506                  mch->pci_address_space, &mch->pam_regions[i+1],
 507                  PAM_EXPAN_BASE + i * PAM_EXPAN_SIZE, PAM_EXPAN_SIZE);
 508     }
 509     /* Intel IOMMU (VT-d) */
 510     if (object_property_get_bool(qdev_get_machine(), "iommu", NULL)) {
 511         mch_init_dmar(mch);
 512     }
 513 }
 514
 515 uint64_t mch_mcfg_base(void)
 516 {
 517     bool ambiguous;
 518     Object *o = object_resolve_path_type("", TYPE_MCH_PCI_DEVICE, &ambiguous);
 519     if (!o) {
 520         return 0;
 521     }
 522     return MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT;
 523 }
 524
 525 static void mch_class_init(ObjectClass *klass, void *data)
 526 {
 527     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 528     DeviceClass *dc = DEVICE_CLASS(klass);
 529
 530     k->realize = mch_realize;
 531     k->config_write = mch_write_config;
 532     dc->reset = mch_reset;
 533     set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
 534     dc->desc = "Host bridge";
 535     dc->vmsd = &vmstate_mch;
 536     k->vendor_id = PCI_VENDOR_ID_INTEL;
 537     k->device_id = PCI_DEVICE_ID_INTEL_Q35_MCH;
 538     k->revision = MCH_HOST_BRIDGE_REVISION_DEFAULT;
 539     k->class_id = PCI_CLASS_BRIDGE_HOST;
 540     /*
 541      * PCI-facing part of the host bridge, not usable without the
 542      * host-facing part, which can't be device_add'ed, yet.
 543      */
 544     dc->cannot_instantiate_with_device_add_yet = true;
 545 }
 546
 547 static const TypeInfo mch_info = {
 548     .name = TYPE_MCH_PCI_DEVICE,
 549     .parent = TYPE_PCI_DEVICE,
 550     .instance_size = sizeof(MCHPCIState),
 551     .class_init = mch_class_init,
 552 };
 553
 554 static void q35_register(void)
 555 {
 556     type_register_static(&mch_info);
 557     type_register_static(&q35_host_info);
 558 }
 559
 560 type_init(q35_register);