ppc/pnv: Add a OCC model for POWER10
[qemu.git] / include / hw / ppc / pnv.h
blob21e69b0fc18769202a507df82635fe60cb177aed
1 /*
2 * QEMU PowerPC PowerNV various definitions
4 * Copyright (c) 2014-2016 BenH, IBM Corporation.
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 #ifndef PPC_PNV_H
21 #define PPC_PNV_H
23 #include "hw/boards.h"
24 #include "hw/sysbus.h"
25 #include "hw/ipmi/ipmi.h"
26 #include "hw/ppc/pnv_lpc.h"
27 #include "hw/ppc/pnv_pnor.h"
28 #include "hw/ppc/pnv_psi.h"
29 #include "hw/ppc/pnv_occ.h"
30 #include "hw/ppc/pnv_homer.h"
31 #include "hw/ppc/pnv_xive.h"
32 #include "hw/ppc/pnv_core.h"
33 #include "hw/pci-host/pnv_phb3.h"
34 #include "hw/pci-host/pnv_phb4.h"
35 #include "qom/object.h"
37 #define TYPE_PNV_CHIP "pnv-chip"
38 OBJECT_DECLARE_TYPE(PnvChip, PnvChipClass,
39 PNV_CHIP)
41 struct PnvChip {
42 /*< private >*/
43 SysBusDevice parent_obj;
45 /*< public >*/
46 uint32_t chip_id;
47 uint64_t ram_start;
48 uint64_t ram_size;
50 uint32_t nr_cores;
51 uint32_t nr_threads;
52 uint64_t cores_mask;
53 PnvCore **cores;
55 uint32_t num_pecs;
57 MemoryRegion xscom_mmio;
58 MemoryRegion xscom;
59 AddressSpace xscom_as;
61 MemoryRegion *fw_mr;
62 gchar *dt_isa_nodename;
65 #define TYPE_PNV8_CHIP "pnv8-chip"
66 typedef struct Pnv8Chip Pnv8Chip;
67 DECLARE_INSTANCE_CHECKER(Pnv8Chip, PNV8_CHIP,
68 TYPE_PNV8_CHIP)
70 struct Pnv8Chip {
71 /*< private >*/
72 PnvChip parent_obj;
74 /*< public >*/
75 MemoryRegion icp_mmio;
77 PnvLpcController lpc;
78 Pnv8Psi psi;
79 PnvOCC occ;
80 PnvHomer homer;
82 #define PNV8_CHIP_PHB3_MAX 4
83 PnvPHB3 phbs[PNV8_CHIP_PHB3_MAX];
84 uint32_t num_phbs;
86 XICSFabric *xics;
89 #define TYPE_PNV9_CHIP "pnv9-chip"
90 typedef struct Pnv9Chip Pnv9Chip;
91 DECLARE_INSTANCE_CHECKER(Pnv9Chip, PNV9_CHIP,
92 TYPE_PNV9_CHIP)
94 struct Pnv9Chip {
95 /*< private >*/
96 PnvChip parent_obj;
98 /*< public >*/
99 PnvXive xive;
100 Pnv9Psi psi;
101 PnvLpcController lpc;
102 PnvOCC occ;
103 PnvHomer homer;
105 uint32_t nr_quads;
106 PnvQuad *quads;
108 #define PNV9_CHIP_MAX_PEC 3
109 PnvPhb4PecState pecs[PNV9_CHIP_MAX_PEC];
113 * A SMT8 fused core is a pair of SMT4 cores.
115 #define PNV9_PIR2FUSEDCORE(pir) (((pir) >> 3) & 0xf)
116 #define PNV9_PIR2CHIP(pir) (((pir) >> 8) & 0x7f)
118 #define TYPE_PNV10_CHIP "pnv10-chip"
119 typedef struct Pnv10Chip Pnv10Chip;
120 DECLARE_INSTANCE_CHECKER(Pnv10Chip, PNV10_CHIP,
121 TYPE_PNV10_CHIP)
123 struct Pnv10Chip {
124 /*< private >*/
125 PnvChip parent_obj;
127 /*< public >*/
128 PnvXive2 xive;
129 Pnv9Psi psi;
130 PnvLpcController lpc;
131 PnvOCC occ;
134 #define PNV10_PIR2FUSEDCORE(pir) (((pir) >> 3) & 0xf)
135 #define PNV10_PIR2CHIP(pir) (((pir) >> 8) & 0x7f)
137 struct PnvChipClass {
138 /*< private >*/
139 SysBusDeviceClass parent_class;
141 /*< public >*/
142 uint64_t chip_cfam_id;
143 uint64_t cores_mask;
144 uint32_t num_pecs;
145 uint32_t num_phbs;
147 DeviceRealize parent_realize;
149 uint32_t (*core_pir)(PnvChip *chip, uint32_t core_id);
150 void (*intc_create)(PnvChip *chip, PowerPCCPU *cpu, Error **errp);
151 void (*intc_reset)(PnvChip *chip, PowerPCCPU *cpu);
152 void (*intc_destroy)(PnvChip *chip, PowerPCCPU *cpu);
153 void (*intc_print_info)(PnvChip *chip, PowerPCCPU *cpu, Monitor *mon);
154 ISABus *(*isa_create)(PnvChip *chip, Error **errp);
155 void (*dt_populate)(PnvChip *chip, void *fdt);
156 void (*pic_print_info)(PnvChip *chip, Monitor *mon);
157 uint64_t (*xscom_core_base)(PnvChip *chip, uint32_t core_id);
158 uint32_t (*xscom_pcba)(PnvChip *chip, uint64_t addr);
161 #define PNV_CHIP_TYPE_SUFFIX "-" TYPE_PNV_CHIP
162 #define PNV_CHIP_TYPE_NAME(cpu_model) cpu_model PNV_CHIP_TYPE_SUFFIX
164 #define TYPE_PNV_CHIP_POWER8E PNV_CHIP_TYPE_NAME("power8e_v2.1")
165 DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER8E,
166 TYPE_PNV_CHIP_POWER8E)
168 #define TYPE_PNV_CHIP_POWER8 PNV_CHIP_TYPE_NAME("power8_v2.0")
169 DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER8,
170 TYPE_PNV_CHIP_POWER8)
172 #define TYPE_PNV_CHIP_POWER8NVL PNV_CHIP_TYPE_NAME("power8nvl_v1.0")
173 DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER8NVL,
174 TYPE_PNV_CHIP_POWER8NVL)
176 #define TYPE_PNV_CHIP_POWER9 PNV_CHIP_TYPE_NAME("power9_v2.0")
177 DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER9,
178 TYPE_PNV_CHIP_POWER9)
180 #define TYPE_PNV_CHIP_POWER10 PNV_CHIP_TYPE_NAME("power10_v2.0")
181 DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER10,
182 TYPE_PNV_CHIP_POWER10)
184 PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir);
185 void pnv_phb_attach_root_port(PCIHostState *pci, const char *name);
186 void pnv_chip_parent_fixup(PnvChip *chip, Object *obj, int index);
188 #define TYPE_PNV_MACHINE MACHINE_TYPE_NAME("powernv")
189 typedef struct PnvMachineClass PnvMachineClass;
190 typedef struct PnvMachineState PnvMachineState;
191 DECLARE_OBJ_CHECKERS(PnvMachineState, PnvMachineClass,
192 PNV_MACHINE, TYPE_PNV_MACHINE)
195 struct PnvMachineClass {
196 /*< private >*/
197 MachineClass parent_class;
199 /*< public >*/
200 const char *compat;
201 int compat_size;
203 void (*dt_power_mgt)(PnvMachineState *pnv, void *fdt);
206 struct PnvMachineState {
207 /*< private >*/
208 MachineState parent_obj;
210 uint32_t initrd_base;
211 long initrd_size;
213 uint32_t num_chips;
214 PnvChip **chips;
216 ISABus *isa_bus;
217 uint32_t cpld_irqstate;
219 IPMIBmc *bmc;
220 Notifier powerdown_notifier;
222 PnvPnor *pnor;
224 hwaddr fw_load_addr;
227 PnvChip *pnv_get_chip(PnvMachineState *pnv, uint32_t chip_id);
229 #define PNV_FDT_ADDR 0x01000000
230 #define PNV_TIMEBASE_FREQ 512000000ULL
233 * BMC helpers
235 void pnv_dt_bmc_sensors(IPMIBmc *bmc, void *fdt);
236 void pnv_bmc_powerdown(IPMIBmc *bmc);
237 IPMIBmc *pnv_bmc_create(PnvPnor *pnor);
238 IPMIBmc *pnv_bmc_find(Error **errp);
239 void pnv_bmc_set_pnor(IPMIBmc *bmc, PnvPnor *pnor);
242 * POWER8 MMIO base addresses
244 #define PNV_XSCOM_SIZE 0x800000000ull
245 #define PNV_XSCOM_BASE(chip) \
246 (0x0003fc0000000000ull + ((uint64_t)(chip)->chip_id) * PNV_XSCOM_SIZE)
248 #define PNV_OCC_COMMON_AREA_SIZE 0x0000000000800000ull
249 #define PNV_OCC_COMMON_AREA_BASE 0x7fff800000ull
250 #define PNV_OCC_SENSOR_BASE(chip) (PNV_OCC_COMMON_AREA_BASE + \
251 PNV_OCC_SENSOR_DATA_BLOCK_BASE((chip)->chip_id))
253 #define PNV_HOMER_SIZE 0x0000000000400000ull
254 #define PNV_HOMER_BASE(chip) \
255 (0x7ffd800000ull + ((uint64_t)(chip)->chip_id) * PNV_HOMER_SIZE)
259 * XSCOM 0x20109CA defines the ICP BAR:
261 * 0:29 : bits 14 to 43 of address to define 1 MB region.
262 * 30 : 1 to enable ICP to receive loads/stores against its BAR region
263 * 31:63 : Constant 0
265 * Usually defined as :
267 * 0xffffe00200000000 -> 0x0003ffff80000000
268 * 0xffffe00600000000 -> 0x0003ffff80100000
269 * 0xffffe02200000000 -> 0x0003ffff80800000
270 * 0xffffe02600000000 -> 0x0003ffff80900000
272 #define PNV_ICP_SIZE 0x0000000000100000ull
273 #define PNV_ICP_BASE(chip) \
274 (0x0003ffff80000000ull + (uint64_t) (chip)->chip_id * PNV_ICP_SIZE)
277 #define PNV_PSIHB_SIZE 0x0000000000100000ull
278 #define PNV_PSIHB_BASE(chip) \
279 (0x0003fffe80000000ull + (uint64_t)(chip)->chip_id * PNV_PSIHB_SIZE)
281 #define PNV_PSIHB_FSP_SIZE 0x0000000100000000ull
282 #define PNV_PSIHB_FSP_BASE(chip) \
283 (0x0003ffe000000000ull + (uint64_t)(chip)->chip_id * \
284 PNV_PSIHB_FSP_SIZE)
287 * POWER9 MMIO base addresses
289 #define PNV9_CHIP_BASE(chip, base) \
290 ((base) + ((uint64_t) (chip)->chip_id << 42))
292 #define PNV9_XIVE_VC_SIZE 0x0000008000000000ull
293 #define PNV9_XIVE_VC_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006010000000000ull)
295 #define PNV9_XIVE_PC_SIZE 0x0000001000000000ull
296 #define PNV9_XIVE_PC_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006018000000000ull)
298 #define PNV9_LPCM_SIZE 0x0000000100000000ull
299 #define PNV9_LPCM_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006030000000000ull)
301 #define PNV9_PSIHB_SIZE 0x0000000000100000ull
302 #define PNV9_PSIHB_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006030203000000ull)
304 #define PNV9_XIVE_IC_SIZE 0x0000000000080000ull
305 #define PNV9_XIVE_IC_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006030203100000ull)
307 #define PNV9_XIVE_TM_SIZE 0x0000000000040000ull
308 #define PNV9_XIVE_TM_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006030203180000ull)
310 #define PNV9_PSIHB_ESB_SIZE 0x0000000000010000ull
311 #define PNV9_PSIHB_ESB_BASE(chip) PNV9_CHIP_BASE(chip, 0x00060302031c0000ull)
313 #define PNV9_XSCOM_SIZE 0x0000000400000000ull
314 #define PNV9_XSCOM_BASE(chip) PNV9_CHIP_BASE(chip, 0x00603fc00000000ull)
316 #define PNV9_OCC_COMMON_AREA_SIZE 0x0000000000800000ull
317 #define PNV9_OCC_COMMON_AREA_BASE 0x203fff800000ull
318 #define PNV9_OCC_SENSOR_BASE(chip) (PNV9_OCC_COMMON_AREA_BASE + \
319 PNV_OCC_SENSOR_DATA_BLOCK_BASE((chip)->chip_id))
321 #define PNV9_HOMER_SIZE 0x0000000000400000ull
322 #define PNV9_HOMER_BASE(chip) \
323 (0x203ffd800000ull + ((uint64_t)(chip)->chip_id) * PNV9_HOMER_SIZE)
326 * POWER10 MMIO base addresses - 16TB stride per chip
328 #define PNV10_CHIP_BASE(chip, base) \
329 ((base) + ((uint64_t) (chip)->chip_id << 44))
331 #define PNV10_XSCOM_SIZE 0x0000000400000000ull
332 #define PNV10_XSCOM_BASE(chip) PNV10_CHIP_BASE(chip, 0x00603fc00000000ull)
334 #define PNV10_LPCM_SIZE 0x0000000100000000ull
335 #define PNV10_LPCM_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006030000000000ull)
337 #define PNV10_XIVE2_IC_SIZE 0x0000000002000000ull
338 #define PNV10_XIVE2_IC_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006030200000000ull)
340 #define PNV10_PSIHB_ESB_SIZE 0x0000000000100000ull
341 #define PNV10_PSIHB_ESB_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006030202000000ull)
343 #define PNV10_PSIHB_SIZE 0x0000000000100000ull
344 #define PNV10_PSIHB_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006030203000000ull)
346 #define PNV10_XIVE2_TM_SIZE 0x0000000000040000ull
347 #define PNV10_XIVE2_TM_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006030203180000ull)
349 #define PNV10_XIVE2_NVC_SIZE 0x0000000008000000ull
350 #define PNV10_XIVE2_NVC_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006030208000000ull)
352 #define PNV10_XIVE2_NVPG_SIZE 0x0000010000000000ull
353 #define PNV10_XIVE2_NVPG_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006040000000000ull)
355 #define PNV10_XIVE2_ESB_SIZE 0x0000010000000000ull
356 #define PNV10_XIVE2_ESB_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006050000000000ull)
358 #define PNV10_XIVE2_END_SIZE 0x0000020000000000ull
359 #define PNV10_XIVE2_END_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006060000000000ull)
361 #endif /* PPC_PNV_H */