hw/pl110.c

   1 /*
   2  * Arm PrimeCell PL110 Color LCD Controller
   3  *
   4  * Copyright (c) 2005-2006 CodeSourcery.
   5  * Written by Paul Brook
   6  *
   7  * This code is licenced under the GNU LGPL
   8  */
   9
  10 #include "hw.h"
  11 #include "primecell.h"
  12 #include "console.h"
  13
  14 #define PL110_CR_EN   0x001
  15 #define PL110_CR_BGR  0x100
  16 #define PL110_CR_BEBO 0x200
  17 #define PL110_CR_BEPO 0x400
  18 #define PL110_CR_PWR  0x800
  19
  20 enum pl110_bppmode
  21 {
  22     BPP_1,
  23     BPP_2,
  24     BPP_4,
  25     BPP_8,
  26     BPP_16,
  27     BPP_32
  28 };
  29
  30 typedef struct {
  31     DisplayState *ds;
  32
  33     /* The Versatile/PB uses a slightly modified PL110 controller.  */
  34     int versatile;
  35     uint32_t timing[4];
  36     uint32_t cr;
  37     uint32_t upbase;
  38     uint32_t lpbase;
  39     uint32_t int_status;
  40     uint32_t int_mask;
  41     int cols;
  42     int rows;
  43     enum pl110_bppmode bpp;
  44     int invalidate;
  45     uint32_t pallette[256];
  46     uint32_t raw_pallette[128];
  47     qemu_irq irq;
  48 } pl110_state;
  49
  50 static const unsigned char pl110_id[] =
  51 { 0x10, 0x11, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 };
  52
  53 /* The Arm documentation (DDI0224C) says the CLDC on the Versatile board
  54    has a different ID.  However Linux only looks for the normal ID.  */
  55 #if 0
  56 static const unsigned char pl110_versatile_id[] =
  57 { 0x93, 0x10, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 };
  58 #else
  59 #define pl110_versatile_id pl110_id
  60 #endif
  61
  62 static inline uint32_t rgb_to_pixel8(unsigned int r, unsigned int g, unsigned b)
  63 {
  64     return ((r >> 5) << 5) | ((g >> 5) << 2) | (b >> 6);
  65 }
  66
  67 static inline uint32_t rgb_to_pixel15(unsigned int r, unsigned int g, unsigned b)
  68 {
  69     return ((r >> 3) << 10) | ((g >> 3) << 5) | (b >> 3);
  70 }
  71
  72 static inline uint32_t rgb_to_pixel16(unsigned int r, unsigned int g, unsigned b)
  73 {
  74     return ((r >> 3) << 11) | ((g >> 2) << 5) | (b >> 3);
  75 }
  76
  77 static inline uint32_t rgb_to_pixel24(unsigned int r, unsigned int g, unsigned b)
  78 {
  79     return (r << 16) | (g << 8) | b;
  80 }
  81
  82 static inline uint32_t rgb_to_pixel32(unsigned int r, unsigned int g, unsigned b)
  83 {
  84     return (r << 16) | (g << 8) | b;
  85 }
  86
  87 typedef void (*drawfn)(uint32_t *, uint8_t *, const uint8_t *, int);
  88
  89 #define BITS 8
  90 #include "pl110_template.h"
  91 #define BITS 15
  92 #include "pl110_template.h"
  93 #define BITS 16
  94 #include "pl110_template.h"
  95 #define BITS 24
  96 #include "pl110_template.h"
  97 #define BITS 32
  98 #include "pl110_template.h"
  99
 100 static int pl110_enabled(pl110_state *s)
 101 {
 102   return (s->cr & PL110_CR_EN) && (s->cr & PL110_CR_PWR);
 103 }
 104
 105 static void pl110_update_display(void *opaque)
 106 {
 107     pl110_state *s = (pl110_state *)opaque;
 108     drawfn* fntable;
 109     drawfn fn;
 110     uint32_t *pallette;
 111     uint32_t addr;
 112     uint32_t base;
 113     int dest_width;
 114     int src_width;
 115     uint8_t *dest;
 116     uint8_t *src;
 117     int first, last = 0;
 118     int dirty, new_dirty;
 119     int i;
 120     int bpp_offset;
 121
 122     if (!pl110_enabled(s))
 123         return;
 124
 125     switch (ds_get_bits_per_pixel(s->ds)) {
 126     case 0:
 127         return;
 128     case 8:
 129         fntable = pl110_draw_fn_8;
 130         dest_width = 1;
 131         break;
 132     case 15:
 133         fntable = pl110_draw_fn_15;
 134         dest_width = 2;
 135         break;
 136     case 16:
 137         fntable = pl110_draw_fn_16;
 138         dest_width = 2;
 139         break;
 140     case 24:
 141         fntable = pl110_draw_fn_24;
 142         dest_width = 3;
 143         break;
 144     case 32:
 145         fntable = pl110_draw_fn_32;
 146         dest_width = 4;
 147         break;
 148     default:
 149         fprintf(stderr, "pl110: Bad color depth\n");
 150         exit(1);
 151     }
 152     if (s->cr & PL110_CR_BGR)
 153         bpp_offset = 0;
 154     else
 155         bpp_offset = 18;
 156
 157     if (s->cr & PL110_CR_BEBO)
 158         fn = fntable[s->bpp + 6 + bpp_offset];
 159     else if (s->cr & PL110_CR_BEPO)
 160         fn = fntable[s->bpp + 12 + bpp_offset];
 161     else
 162         fn = fntable[s->bpp + bpp_offset];
 163
 164     src_width = s->cols;
 165     switch (s->bpp) {
 166     case BPP_1:
 167         src_width >>= 3;
 168         break;
 169     case BPP_2:
 170         src_width >>= 2;
 171         break;
 172     case BPP_4:
 173         src_width >>= 1;
 174         break;
 175     case BPP_8:
 176         break;
 177     case BPP_16:
 178         src_width <<= 1;
 179         break;
 180     case BPP_32:
 181         src_width <<= 2;
 182         break;
 183     }
 184     dest_width *= s->cols;
 185     pallette = s->pallette;
 186     base = s->upbase;
 187     /* HACK: Arm aliases physical memory at 0x80000000.  */
 188     if (base > 0x80000000)
 189         base -= 0x80000000;
 190     src = phys_ram_base + base;
 191     dest = ds_get_data(s->ds);
 192     first = -1;
 193     addr = base;
 194
 195     dirty = cpu_physical_memory_get_dirty(addr, VGA_DIRTY_FLAG);
 196     new_dirty = dirty;
 197     for (i = 0; i < s->rows; i++) {
 198         if ((addr & ~TARGET_PAGE_MASK) + src_width >= TARGET_PAGE_SIZE) {
 199             uint32_t tmp;
 200             new_dirty = 0;
 201             for (tmp = 0; tmp < src_width; tmp += TARGET_PAGE_SIZE) {
 202                 new_dirty |= cpu_physical_memory_get_dirty(addr + tmp,
 203                                                            VGA_DIRTY_FLAG);
 204             }
 205         }
 206
 207         if (dirty || new_dirty || s->invalidate) {
 208             fn(pallette, dest, src, s->cols);
 209             if (first == -1)
 210                 first = i;
 211             last = i;
 212         }
 213         dirty = new_dirty;
 214         addr += src_width;
 215         dest += dest_width;
 216         src += src_width;
 217     }
 218     if (first < 0)
 219       return;
 220
 221     s->invalidate = 0;
 222     cpu_physical_memory_reset_dirty(base + first * src_width,
 223                                     base + (last + 1) * src_width,
 224                                     VGA_DIRTY_FLAG);
 225     dpy_update(s->ds, 0, first, s->cols, last - first + 1);
 226 }
 227
 228 static void pl110_invalidate_display(void * opaque)
 229 {
 230     pl110_state *s = (pl110_state *)opaque;
 231     s->invalidate = 1;
 232 }
 233
 234 static void pl110_update_pallette(pl110_state *s, int n)
 235 {
 236     int i;
 237     uint32_t raw;
 238     unsigned int r, g, b;
 239
 240     raw = s->raw_pallette[n];
 241     n <<= 1;
 242     for (i = 0; i < 2; i++) {
 243         r = (raw & 0x1f) << 3;
 244         raw >>= 5;
 245         g = (raw & 0x1f) << 3;
 246         raw >>= 5;
 247         b = (raw & 0x1f) << 3;
 248         /* The I bit is ignored.  */
 249         raw >>= 6;
 250         switch (ds_get_bits_per_pixel(s->ds)) {
 251         case 8:
 252             s->pallette[n] = rgb_to_pixel8(r, g, b);
 253             break;
 254         case 15:
 255             s->pallette[n] = rgb_to_pixel15(r, g, b);
 256             break;
 257         case 16:
 258             s->pallette[n] = rgb_to_pixel16(r, g, b);
 259             break;
 260         case 24:
 261         case 32:
 262             s->pallette[n] = rgb_to_pixel32(r, g, b);
 263             break;
 264         }
 265         n++;
 266     }
 267 }
 268
 269 static void pl110_resize(pl110_state *s, int width, int height)
 270 {
 271     if (width != s->cols || height != s->rows) {
 272         if (pl110_enabled(s)) {
 273             qemu_console_resize(s->ds, width, height);
 274         }
 275     }
 276     s->cols = width;
 277     s->rows = height;
 278 }
 279
 280 /* Update interrupts.  */
 281 static void pl110_update(pl110_state *s)
 282 {
 283   /* TODO: Implement interrupts.  */
 284 }
 285
 286 static uint32_t pl110_read(void *opaque, target_phys_addr_t offset)
 287 {
 288     pl110_state *s = (pl110_state *)opaque;
 289
 290     if (offset >= 0xfe0 && offset < 0x1000) {
 291         if (s->versatile)
 292             return pl110_versatile_id[(offset - 0xfe0) >> 2];
 293         else
 294             return pl110_id[(offset - 0xfe0) >> 2];
 295     }
 296     if (offset >= 0x200 && offset < 0x400) {
 297         return s->raw_pallette[(offset - 0x200) >> 2];
 298     }
 299     switch (offset >> 2) {
 300     case 0: /* LCDTiming0 */
 301         return s->timing[0];
 302     case 1: /* LCDTiming1 */
 303         return s->timing[1];
 304     case 2: /* LCDTiming2 */
 305         return s->timing[2];
 306     case 3: /* LCDTiming3 */
 307         return s->timing[3];
 308     case 4: /* LCDUPBASE */
 309         return s->upbase;
 310     case 5: /* LCDLPBASE */
 311         return s->lpbase;
 312     case 6: /* LCDIMSC */
 313         if (s->versatile)
 314           return s->cr;
 315         return s->int_mask;
 316     case 7: /* LCDControl */
 317         if (s->versatile)
 318           return s->int_mask;
 319         return s->cr;
 320     case 8: /* LCDRIS */
 321         return s->int_status;
 322     case 9: /* LCDMIS */
 323         return s->int_status & s->int_mask;
 324     case 11: /* LCDUPCURR */
 325         /* TODO: Implement vertical refresh.  */
 326         return s->upbase;
 327     case 12: /* LCDLPCURR */
 328         return s->lpbase;
 329     default:
 330         cpu_abort (cpu_single_env, "pl110_read: Bad offset %x\n", (int)offset);
 331         return 0;
 332     }
 333 }
 334
 335 static void pl110_write(void *opaque, target_phys_addr_t offset,
 336                         uint32_t val)
 337 {
 338     pl110_state *s = (pl110_state *)opaque;
 339     int n;
 340
 341     /* For simplicity invalidate the display whenever a control register
 342        is writen to.  */
 343     s->invalidate = 1;
 344     if (offset >= 0x200 && offset < 0x400) {
 345         /* Pallette.  */
 346         n = (offset - 0x200) >> 2;
 347         s->raw_pallette[(offset - 0x200) >> 2] = val;
 348         pl110_update_pallette(s, n);
 349         return;
 350     }
 351     switch (offset >> 2) {
 352     case 0: /* LCDTiming0 */
 353         s->timing[0] = val;
 354         n = ((val & 0xfc) + 4) * 4;
 355         pl110_resize(s, n, s->rows);
 356         break;
 357     case 1: /* LCDTiming1 */
 358         s->timing[1] = val;
 359         n = (val & 0x3ff) + 1;
 360         pl110_resize(s, s->cols, n);
 361         break;
 362     case 2: /* LCDTiming2 */
 363         s->timing[2] = val;
 364         break;
 365     case 3: /* LCDTiming3 */
 366         s->timing[3] = val;
 367         break;
 368     case 4: /* LCDUPBASE */
 369         s->upbase = val;
 370         break;
 371     case 5: /* LCDLPBASE */
 372         s->lpbase = val;
 373         break;
 374     case 6: /* LCDIMSC */
 375         if (s->versatile)
 376             goto control;
 377     imsc:
 378         s->int_mask = val;
 379         pl110_update(s);
 380         break;
 381     case 7: /* LCDControl */
 382         if (s->versatile)
 383             goto imsc;
 384     control:
 385         s->cr = val;
 386         s->bpp = (val >> 1) & 7;
 387         if (pl110_enabled(s)) {
 388             qemu_console_resize(s->ds, s->cols, s->rows);
 389         }
 390         break;
 391     case 10: /* LCDICR */
 392         s->int_status &= ~val;
 393         pl110_update(s);
 394         break;
 395     default:
 396         cpu_abort (cpu_single_env, "pl110_write: Bad offset %x\n", (int)offset);
 397     }
 398 }
 399
 400 static CPUReadMemoryFunc *pl110_readfn[] = {
 401    pl110_read,
 402    pl110_read,
 403    pl110_read
 404 };
 405
 406 static CPUWriteMemoryFunc *pl110_writefn[] = {
 407    pl110_write,
 408    pl110_write,
 409    pl110_write
 410 };
 411
 412 void *pl110_init(uint32_t base, qemu_irq irq, int versatile)
 413 {
 414     pl110_state *s;
 415     int iomemtype;
 416
 417     s = (pl110_state *)qemu_mallocz(sizeof(pl110_state));
 418     iomemtype = cpu_register_io_memory(0, pl110_readfn,
 419                                        pl110_writefn, s);
 420     cpu_register_physical_memory(base, 0x00001000, iomemtype);
 421     s->versatile = versatile;
 422     s->irq = irq;
 423     s->ds = graphic_console_init(pl110_update_display,
 424                                  pl110_invalidate_display,
 425                                  NULL, NULL, s);
 426     /* ??? Save/restore.  */
 427     return s;
 428 }