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seabios: update to latest git
[qemu.git] / hw / pxa2xx.c
blob9b95e2c8e20ad46d41f2aa1d25e2cf7037ee780d
1 /*
2 * Intel XScale PXA255/270 processor support.
3 *
4 * Copyright (c) 2006 Openedhand Ltd.
5 * Written by Andrzej Zaborowski <balrog@zabor.org>
6 *
7 * This code is licenced under the GPL.
8 */
9
10 #include "sysbus.h"
11 #include "pxa.h"
12 #include "sysemu.h"
13 #include "pc.h"
14 #include "i2c.h"
15 #include "ssi.h"
16 #include "qemu-char.h"
17 #include "blockdev.h"
18
19 static struct {
20 target_phys_addr_t io_base;
21 int irqn;
22 } pxa255_serial[] = {
23 { 0x40100000, PXA2XX_PIC_FFUART },
24 { 0x40200000, PXA2XX_PIC_BTUART },
25 { 0x40700000, PXA2XX_PIC_STUART },
26 { 0x41600000, PXA25X_PIC_HWUART },
27 { 0, 0 }
28 }, pxa270_serial[] = {
29 { 0x40100000, PXA2XX_PIC_FFUART },
30 { 0x40200000, PXA2XX_PIC_BTUART },
31 { 0x40700000, PXA2XX_PIC_STUART },
32 { 0, 0 }
33 };
34
35 typedef struct PXASSPDef {
36 target_phys_addr_t io_base;
37 int irqn;
38 } PXASSPDef;
39
40 #if 0
41 static PXASSPDef pxa250_ssp[] = {
42 { 0x41000000, PXA2XX_PIC_SSP },
43 { 0, 0 }
44 };
45 #endif
46
47 static PXASSPDef pxa255_ssp[] = {
48 { 0x41000000, PXA2XX_PIC_SSP },
49 { 0x41400000, PXA25X_PIC_NSSP },
50 { 0, 0 }
51 };
52
53 #if 0
54 static PXASSPDef pxa26x_ssp[] = {
55 { 0x41000000, PXA2XX_PIC_SSP },
56 { 0x41400000, PXA25X_PIC_NSSP },
57 { 0x41500000, PXA26X_PIC_ASSP },
58 { 0, 0 }
59 };
60 #endif
61
62 static PXASSPDef pxa27x_ssp[] = {
63 { 0x41000000, PXA2XX_PIC_SSP },
64 { 0x41700000, PXA27X_PIC_SSP2 },
65 { 0x41900000, PXA2XX_PIC_SSP3 },
66 { 0, 0 }
67 };
68
69 #define PMCR 0x00 /* Power Manager Control register */
70 #define PSSR 0x04 /* Power Manager Sleep Status register */
71 #define PSPR 0x08 /* Power Manager Scratch-Pad register */
72 #define PWER 0x0c /* Power Manager Wake-Up Enable register */
73 #define PRER 0x10 /* Power Manager Rising-Edge Detect Enable register */
74 #define PFER 0x14 /* Power Manager Falling-Edge Detect Enable register */
75 #define PEDR 0x18 /* Power Manager Edge-Detect Status register */
76 #define PCFR 0x1c /* Power Manager General Configuration register */
77 #define PGSR0 0x20 /* Power Manager GPIO Sleep-State register 0 */
78 #define PGSR1 0x24 /* Power Manager GPIO Sleep-State register 1 */
79 #define PGSR2 0x28 /* Power Manager GPIO Sleep-State register 2 */
80 #define PGSR3 0x2c /* Power Manager GPIO Sleep-State register 3 */
81 #define RCSR 0x30 /* Reset Controller Status register */
82 #define PSLR 0x34 /* Power Manager Sleep Configuration register */
83 #define PTSR 0x38 /* Power Manager Standby Configuration register */
84 #define PVCR 0x40 /* Power Manager Voltage Change Control register */
85 #define PUCR 0x4c /* Power Manager USIM Card Control/Status register */
86 #define PKWR 0x50 /* Power Manager Keyboard Wake-Up Enable register */
87 #define PKSR 0x54 /* Power Manager Keyboard Level-Detect Status */
88 #define PCMD0 0x80 /* Power Manager I2C Command register File 0 */
89 #define PCMD31 0xfc /* Power Manager I2C Command register File 31 */
90
91 static uint32_t pxa2xx_pm_read(void *opaque, target_phys_addr_t addr)
92 {
93 PXA2xxState *s = (PXA2xxState *) opaque;
94
95 switch (addr) {
96 case PMCR ... PCMD31:
97 if (addr & 3)
98 goto fail;
99
100 return s->pm_regs[addr >> 2];
101 default:
102 fail:
103 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
104 break;
105 }
106 return 0;
107 }
108
109 static void pxa2xx_pm_write(void *opaque, target_phys_addr_t addr,
110 uint32_t value)
111 {
112 PXA2xxState *s = (PXA2xxState *) opaque;
113
114 switch (addr) {
115 case PMCR:
116 s->pm_regs[addr >> 2] &= 0x15 & ~(value & 0x2a);
117 s->pm_regs[addr >> 2] |= value & 0x15;
118 break;
119
120 case PSSR: /* Read-clean registers */
121 case RCSR:
122 case PKSR:
123 s->pm_regs[addr >> 2] &= ~value;
124 break;
125
126 default: /* Read-write registers */
127 if (!(addr & 3)) {
128 s->pm_regs[addr >> 2] = value;
129 break;
130 }
131
132 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
133 break;
134 }
135 }
136
137 static CPUReadMemoryFunc * const pxa2xx_pm_readfn[] = {
138 pxa2xx_pm_read,
139 pxa2xx_pm_read,
140 pxa2xx_pm_read,
141 };
142
143 static CPUWriteMemoryFunc * const pxa2xx_pm_writefn[] = {
144 pxa2xx_pm_write,
145 pxa2xx_pm_write,
146 pxa2xx_pm_write,
147 };
148
149 static void pxa2xx_pm_save(QEMUFile *f, void *opaque)
150 {
151 PXA2xxState *s = (PXA2xxState *) opaque;
152 int i;
153
154 for (i = 0; i < 0x40; i ++)
155 qemu_put_be32s(f, &s->pm_regs[i]);
156 }
157
158 static int pxa2xx_pm_load(QEMUFile *f, void *opaque, int version_id)
159 {
160 PXA2xxState *s = (PXA2xxState *) opaque;
161 int i;
162
163 for (i = 0; i < 0x40; i ++)
164 qemu_get_be32s(f, &s->pm_regs[i]);
165
166 return 0;
167 }
168
169 #define CCCR 0x00 /* Core Clock Configuration register */
170 #define CKEN 0x04 /* Clock Enable register */
171 #define OSCC 0x08 /* Oscillator Configuration register */
172 #define CCSR 0x0c /* Core Clock Status register */
173
174 static uint32_t pxa2xx_cm_read(void *opaque, target_phys_addr_t addr)
175 {
176 PXA2xxState *s = (PXA2xxState *) opaque;
177
178 switch (addr) {
179 case CCCR:
180 case CKEN:
181 case OSCC:
182 return s->cm_regs[addr >> 2];
183
184 case CCSR:
185 return s->cm_regs[CCCR >> 2] | (3 << 28);
186
187 default:
188 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
189 break;
190 }
191 return 0;
192 }
193
194 static void pxa2xx_cm_write(void *opaque, target_phys_addr_t addr,
195 uint32_t value)
196 {
197 PXA2xxState *s = (PXA2xxState *) opaque;
198
199 switch (addr) {
200 case CCCR:
201 case CKEN:
202 s->cm_regs[addr >> 2] = value;
203 break;
204
205 case OSCC:
206 s->cm_regs[addr >> 2] &= ~0x6c;
207 s->cm_regs[addr >> 2] |= value & 0x6e;
208 if ((value >> 1) & 1) /* OON */
209 s->cm_regs[addr >> 2] |= 1 << 0; /* Oscillator is now stable */
210 break;
211
212 default:
213 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
214 break;
215 }
216 }
217
218 static CPUReadMemoryFunc * const pxa2xx_cm_readfn[] = {
219 pxa2xx_cm_read,
220 pxa2xx_cm_read,
221 pxa2xx_cm_read,
222 };
223
224 static CPUWriteMemoryFunc * const pxa2xx_cm_writefn[] = {
225 pxa2xx_cm_write,
226 pxa2xx_cm_write,
227 pxa2xx_cm_write,
228 };
229
230 static void pxa2xx_cm_save(QEMUFile *f, void *opaque)
231 {
232 PXA2xxState *s = (PXA2xxState *) opaque;
233 int i;
234
235 for (i = 0; i < 4; i ++)
236 qemu_put_be32s(f, &s->cm_regs[i]);
237 qemu_put_be32s(f, &s->clkcfg);
238 qemu_put_be32s(f, &s->pmnc);
239 }
240
241 static int pxa2xx_cm_load(QEMUFile *f, void *opaque, int version_id)
242 {
243 PXA2xxState *s = (PXA2xxState *) opaque;
244 int i;
245
246 for (i = 0; i < 4; i ++)
247 qemu_get_be32s(f, &s->cm_regs[i]);
248 qemu_get_be32s(f, &s->clkcfg);
249 qemu_get_be32s(f, &s->pmnc);
250
251 return 0;
252 }
253
254 static uint32_t pxa2xx_clkpwr_read(void *opaque, int op2, int reg, int crm)
255 {
256 PXA2xxState *s = (PXA2xxState *) opaque;
257
258 switch (reg) {
259 case 6: /* Clock Configuration register */
260 return s->clkcfg;
261
262 case 7: /* Power Mode register */
263 return 0;
264
265 default:
266 printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);
267 break;
268 }
269 return 0;
270 }
271
272 static void pxa2xx_clkpwr_write(void *opaque, int op2, int reg, int crm,
273 uint32_t value)
274 {
275 PXA2xxState *s = (PXA2xxState *) opaque;
276 static const char *pwrmode[8] = {
277 "Normal", "Idle", "Deep-idle", "Standby",
278 "Sleep", "reserved (!)", "reserved (!)", "Deep-sleep",
279 };
280
281 switch (reg) {
282 case 6: /* Clock Configuration register */
283 s->clkcfg = value & 0xf;
284 if (value & 2)
285 printf("%s: CPU frequency change attempt\n", __FUNCTION__);
286 break;
287
288 case 7: /* Power Mode register */
289 if (value & 8)
290 printf("%s: CPU voltage change attempt\n", __FUNCTION__);
291 switch (value & 7) {
292 case 0:
293 /* Do nothing */
294 break;
295
296 case 1:
297 /* Idle */
298 if (!(s->cm_regs[CCCR >> 2] & (1 << 31))) { /* CPDIS */
299 cpu_interrupt(s->env, CPU_INTERRUPT_HALT);
300 break;
301 }
302 /* Fall through. */
303
304 case 2:
305 /* Deep-Idle */
306 cpu_interrupt(s->env, CPU_INTERRUPT_HALT);
307 s->pm_regs[RCSR >> 2] |= 0x8; /* Set GPR */
308 goto message;
309
310 case 3:
311 s->env->uncached_cpsr =
312 ARM_CPU_MODE_SVC | CPSR_A | CPSR_F | CPSR_I;
313 s->env->cp15.c1_sys = 0;
314 s->env->cp15.c1_coproc = 0;
315 s->env->cp15.c2_base0 = 0;
316 s->env->cp15.c3 = 0;
317 s->pm_regs[PSSR >> 2] |= 0x8; /* Set STS */
318 s->pm_regs[RCSR >> 2] |= 0x8; /* Set GPR */
319
320 /*
321 * The scratch-pad register is almost universally used
322 * for storing the return address on suspend. For the
323 * lack of a resuming bootloader, perform a jump
324 * directly to that address.
325 */
326 memset(s->env->regs, 0, 4 * 15);
327 s->env->regs[15] = s->pm_regs[PSPR >> 2];
328
329 #if 0
330 buffer = 0xe59ff000; /* ldr pc, [pc, #0] */
331 cpu_physical_memory_write(0, &buffer, 4);
332 buffer = s->pm_regs[PSPR >> 2];
333 cpu_physical_memory_write(8, &buffer, 4);
334 #endif
335
336 /* Suspend */
337 cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HALT);
338
339 goto message;
340
341 default:
342 message:
343 printf("%s: machine entered %s mode\n", __FUNCTION__,
344 pwrmode[value & 7]);
345 }
346 break;
347
348 default:
349 printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);
350 break;
351 }
352 }
353
354 /* Performace Monitoring Registers */
355 #define CPPMNC 0 /* Performance Monitor Control register */
356 #define CPCCNT 1 /* Clock Counter register */
357 #define CPINTEN 4 /* Interrupt Enable register */
358 #define CPFLAG 5 /* Overflow Flag register */
359 #define CPEVTSEL 8 /* Event Selection register */
360
361 #define CPPMN0 0 /* Performance Count register 0 */
362 #define CPPMN1 1 /* Performance Count register 1 */
363 #define CPPMN2 2 /* Performance Count register 2 */
364 #define CPPMN3 3 /* Performance Count register 3 */
365
366 static uint32_t pxa2xx_perf_read(void *opaque, int op2, int reg, int crm)
367 {
368 PXA2xxState *s = (PXA2xxState *) opaque;
369
370 switch (reg) {
371 case CPPMNC:
372 return s->pmnc;
373 case CPCCNT:
374 if (s->pmnc & 1)
375 return qemu_get_clock_ns(vm_clock);
376 else
377 return 0;
378 case CPINTEN:
379 case CPFLAG:
380 case CPEVTSEL:
381 return 0;
382
383 default:
384 printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);
385 break;
386 }
387 return 0;
388 }
389
390 static void pxa2xx_perf_write(void *opaque, int op2, int reg, int crm,
391 uint32_t value)
392 {
393 PXA2xxState *s = (PXA2xxState *) opaque;
394
395 switch (reg) {
396 case CPPMNC:
397 s->pmnc = value;
398 break;
399
400 case CPCCNT:
401 case CPINTEN:
402 case CPFLAG:
403 case CPEVTSEL:
404 break;
405
406 default:
407 printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);
408 break;
409 }
410 }
411
412 static uint32_t pxa2xx_cp14_read(void *opaque, int op2, int reg, int crm)
413 {
414 switch (crm) {
415 case 0:
416 return pxa2xx_clkpwr_read(opaque, op2, reg, crm);
417 case 1:
418 return pxa2xx_perf_read(opaque, op2, reg, crm);
419 case 2:
420 switch (reg) {
421 case CPPMN0:
422 case CPPMN1:
423 case CPPMN2:
424 case CPPMN3:
425 return 0;
426 }
427 /* Fall through */
428 default:
429 printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);
430 break;
431 }
432 return 0;
433 }
434
435 static void pxa2xx_cp14_write(void *opaque, int op2, int reg, int crm,
436 uint32_t value)
437 {
438 switch (crm) {
439 case 0:
440 pxa2xx_clkpwr_write(opaque, op2, reg, crm, value);
441 break;
442 case 1:
443 pxa2xx_perf_write(opaque, op2, reg, crm, value);
444 break;
445 case 2:
446 switch (reg) {
447 case CPPMN0:
448 case CPPMN1:
449 case CPPMN2:
450 case CPPMN3:
451 return;
452 }
453 /* Fall through */
454 default:
455 printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);
456 break;
457 }
458 }
459
460 #define MDCNFG 0x00 /* SDRAM Configuration register */
461 #define MDREFR 0x04 /* SDRAM Refresh Control register */
462 #define MSC0 0x08 /* Static Memory Control register 0 */
463 #define MSC1 0x0c /* Static Memory Control register 1 */
464 #define MSC2 0x10 /* Static Memory Control register 2 */
465 #define MECR 0x14 /* Expansion Memory Bus Config register */
466 #define SXCNFG 0x1c /* Synchronous Static Memory Config register */
467 #define MCMEM0 0x28 /* PC Card Memory Socket 0 Timing register */
468 #define MCMEM1 0x2c /* PC Card Memory Socket 1 Timing register */
469 #define MCATT0 0x30 /* PC Card Attribute Socket 0 register */
470 #define MCATT1 0x34 /* PC Card Attribute Socket 1 register */
471 #define MCIO0 0x38 /* PC Card I/O Socket 0 Timing register */
472 #define MCIO1 0x3c /* PC Card I/O Socket 1 Timing register */
473 #define MDMRS 0x40 /* SDRAM Mode Register Set Config register */
474 #define BOOT_DEF 0x44 /* Boot-time Default Configuration register */
475 #define ARB_CNTL 0x48 /* Arbiter Control register */
476 #define BSCNTR0 0x4c /* Memory Buffer Strength Control register 0 */
477 #define BSCNTR1 0x50 /* Memory Buffer Strength Control register 1 */
478 #define LCDBSCNTR 0x54 /* LCD Buffer Strength Control register */
479 #define MDMRSLP 0x58 /* Low Power SDRAM Mode Set Config register */
480 #define BSCNTR2 0x5c /* Memory Buffer Strength Control register 2 */
481 #define BSCNTR3 0x60 /* Memory Buffer Strength Control register 3 */
482 #define SA1110 0x64 /* SA-1110 Memory Compatibility register */
483
484 static uint32_t pxa2xx_mm_read(void *opaque, target_phys_addr_t addr)
485 {
486 PXA2xxState *s = (PXA2xxState *) opaque;
487
488 switch (addr) {
489 case MDCNFG ... SA1110:
490 if ((addr & 3) == 0)
491 return s->mm_regs[addr >> 2];
492
493 default:
494 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
495 break;
496 }
497 return 0;
498 }
499
500 static void pxa2xx_mm_write(void *opaque, target_phys_addr_t addr,
501 uint32_t value)
502 {
503 PXA2xxState *s = (PXA2xxState *) opaque;
504
505 switch (addr) {
506 case MDCNFG ... SA1110:
507 if ((addr & 3) == 0) {
508 s->mm_regs[addr >> 2] = value;
509 break;
510 }
511
512 default:
513 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
514 break;
515 }
516 }
517
518 static CPUReadMemoryFunc * const pxa2xx_mm_readfn[] = {
519 pxa2xx_mm_read,
520 pxa2xx_mm_read,
521 pxa2xx_mm_read,
522 };
523
524 static CPUWriteMemoryFunc * const pxa2xx_mm_writefn[] = {
525 pxa2xx_mm_write,
526 pxa2xx_mm_write,
527 pxa2xx_mm_write,
528 };
529
530 static void pxa2xx_mm_save(QEMUFile *f, void *opaque)
531 {
532 PXA2xxState *s = (PXA2xxState *) opaque;
533 int i;
534
535 for (i = 0; i < 0x1a; i ++)
536 qemu_put_be32s(f, &s->mm_regs[i]);
537 }
538
539 static int pxa2xx_mm_load(QEMUFile *f, void *opaque, int version_id)
540 {
541 PXA2xxState *s = (PXA2xxState *) opaque;
542 int i;
543
544 for (i = 0; i < 0x1a; i ++)
545 qemu_get_be32s(f, &s->mm_regs[i]);
546
547 return 0;
548 }
549
550 /* Synchronous Serial Ports */
551 typedef struct {
552 SysBusDevice busdev;
553 qemu_irq irq;
554 int enable;
555 SSIBus *bus;
556
557 uint32_t sscr[2];
558 uint32_t sspsp;
559 uint32_t ssto;
560 uint32_t ssitr;
561 uint32_t sssr;
562 uint8_t sstsa;
563 uint8_t ssrsa;
564 uint8_t ssacd;
565
566 uint32_t rx_fifo[16];
567 int rx_level;
568 int rx_start;
569 } PXA2xxSSPState;
570
571 #define SSCR0 0x00 /* SSP Control register 0 */
572 #define SSCR1 0x04 /* SSP Control register 1 */
573 #define SSSR 0x08 /* SSP Status register */
574 #define SSITR 0x0c /* SSP Interrupt Test register */
575 #define SSDR 0x10 /* SSP Data register */
576 #define SSTO 0x28 /* SSP Time-Out register */
577 #define SSPSP 0x2c /* SSP Programmable Serial Protocol register */
578 #define SSTSA 0x30 /* SSP TX Time Slot Active register */
579 #define SSRSA 0x34 /* SSP RX Time Slot Active register */
580 #define SSTSS 0x38 /* SSP Time Slot Status register */
581 #define SSACD 0x3c /* SSP Audio Clock Divider register */
582
583 /* Bitfields for above registers */
584 #define SSCR0_SPI(x) (((x) & 0x30) == 0x00)
585 #define SSCR0_SSP(x) (((x) & 0x30) == 0x10)
586 #define SSCR0_UWIRE(x) (((x) & 0x30) == 0x20)
587 #define SSCR0_PSP(x) (((x) & 0x30) == 0x30)
588 #define SSCR0_SSE (1 << 7)
589 #define SSCR0_RIM (1 << 22)
590 #define SSCR0_TIM (1 << 23)
591 #define SSCR0_MOD (1 << 31)
592 #define SSCR0_DSS(x) (((((x) >> 16) & 0x10) | ((x) & 0xf)) + 1)
593 #define SSCR1_RIE (1 << 0)
594 #define SSCR1_TIE (1 << 1)
595 #define SSCR1_LBM (1 << 2)
596 #define SSCR1_MWDS (1 << 5)
597 #define SSCR1_TFT(x) ((((x) >> 6) & 0xf) + 1)
598 #define SSCR1_RFT(x) ((((x) >> 10) & 0xf) + 1)
599 #define SSCR1_EFWR (1 << 14)
600 #define SSCR1_PINTE (1 << 18)
601 #define SSCR1_TINTE (1 << 19)
602 #define SSCR1_RSRE (1 << 20)
603 #define SSCR1_TSRE (1 << 21)
604 #define SSCR1_EBCEI (1 << 29)
605 #define SSITR_INT (7 << 5)
606 #define SSSR_TNF (1 << 2)
607 #define SSSR_RNE (1 << 3)
608 #define SSSR_TFS (1 << 5)
609 #define SSSR_RFS (1 << 6)
610 #define SSSR_ROR (1 << 7)
611 #define SSSR_PINT (1 << 18)
612 #define SSSR_TINT (1 << 19)
613 #define SSSR_EOC (1 << 20)
614 #define SSSR_TUR (1 << 21)
615 #define SSSR_BCE (1 << 23)
616 #define SSSR_RW 0x00bc0080
617
618 static void pxa2xx_ssp_int_update(PXA2xxSSPState *s)
619 {
620 int level = 0;
621
622 level |= s->ssitr & SSITR_INT;
623 level |= (s->sssr & SSSR_BCE) && (s->sscr[1] & SSCR1_EBCEI);
624 level |= (s->sssr & SSSR_TUR) && !(s->sscr[0] & SSCR0_TIM);
625 level |= (s->sssr & SSSR_EOC) && (s->sssr & (SSSR_TINT | SSSR_PINT));
626 level |= (s->sssr & SSSR_TINT) && (s->sscr[1] & SSCR1_TINTE);
627 level |= (s->sssr & SSSR_PINT) && (s->sscr[1] & SSCR1_PINTE);
628 level |= (s->sssr & SSSR_ROR) && !(s->sscr[0] & SSCR0_RIM);
629 level |= (s->sssr & SSSR_RFS) && (s->sscr[1] & SSCR1_RIE);
630 level |= (s->sssr & SSSR_TFS) && (s->sscr[1] & SSCR1_TIE);
631 qemu_set_irq(s->irq, !!level);
632 }
633
634 static void pxa2xx_ssp_fifo_update(PXA2xxSSPState *s)
635 {
636 s->sssr &= ~(0xf << 12); /* Clear RFL */
637 s->sssr &= ~(0xf << 8); /* Clear TFL */
638 s->sssr &= ~SSSR_TFS;
639 s->sssr &= ~SSSR_TNF;
640 if (s->enable) {
641 s->sssr |= ((s->rx_level - 1) & 0xf) << 12;
642 if (s->rx_level >= SSCR1_RFT(s->sscr[1]))
643 s->sssr |= SSSR_RFS;
644 else
645 s->sssr &= ~SSSR_RFS;
646 if (s->rx_level)
647 s->sssr |= SSSR_RNE;
648 else
649 s->sssr &= ~SSSR_RNE;
650 /* TX FIFO is never filled, so it is always in underrun
651 condition if SSP is enabled */
652 s->sssr |= SSSR_TFS;
653 s->sssr |= SSSR_TNF;
654 }
655
656 pxa2xx_ssp_int_update(s);
657 }
658
659 static uint32_t pxa2xx_ssp_read(void *opaque, target_phys_addr_t addr)
660 {
661 PXA2xxSSPState *s = (PXA2xxSSPState *) opaque;
662 uint32_t retval;
663
664 switch (addr) {
665 case SSCR0:
666 return s->sscr[0];
667 case SSCR1:
668 return s->sscr[1];
669 case SSPSP:
670 return s->sspsp;
671 case SSTO:
672 return s->ssto;
673 case SSITR:
674 return s->ssitr;
675 case SSSR:
676 return s->sssr | s->ssitr;
677 case SSDR:
678 if (!s->enable)
679 return 0xffffffff;
680 if (s->rx_level < 1) {
681 printf("%s: SSP Rx Underrun\n", __FUNCTION__);
682 return 0xffffffff;
683 }
684 s->rx_level --;
685 retval = s->rx_fifo[s->rx_start ++];
686 s->rx_start &= 0xf;
687 pxa2xx_ssp_fifo_update(s);
688 return retval;
689 case SSTSA:
690 return s->sstsa;
691 case SSRSA:
692 return s->ssrsa;
693 case SSTSS:
694 return 0;
695 case SSACD:
696 return s->ssacd;
697 default:
698 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
699 break;
700 }
701 return 0;
702 }
703
704 static void pxa2xx_ssp_write(void *opaque, target_phys_addr_t addr,
705 uint32_t value)
706 {
707 PXA2xxSSPState *s = (PXA2xxSSPState *) opaque;
708
709 switch (addr) {
710 case SSCR0:
711 s->sscr[0] = value & 0xc7ffffff;
712 s->enable = value & SSCR0_SSE;
713 if (value & SSCR0_MOD)
714 printf("%s: Attempt to use network mode\n", __FUNCTION__);
715 if (s->enable && SSCR0_DSS(value) < 4)
716 printf("%s: Wrong data size: %i bits\n", __FUNCTION__,
717 SSCR0_DSS(value));
718 if (!(value & SSCR0_SSE)) {
719 s->sssr = 0;
720 s->ssitr = 0;
721 s->rx_level = 0;
722 }
723 pxa2xx_ssp_fifo_update(s);
724 break;
725
726 case SSCR1:
727 s->sscr[1] = value;
728 if (value & (SSCR1_LBM | SSCR1_EFWR))
729 printf("%s: Attempt to use SSP test mode\n", __FUNCTION__);
730 pxa2xx_ssp_fifo_update(s);
731 break;
732
733 case SSPSP:
734 s->sspsp = value;
735 break;
736
737 case SSTO:
738 s->ssto = value;
739 break;
740
741 case SSITR:
742 s->ssitr = value & SSITR_INT;
743 pxa2xx_ssp_int_update(s);
744 break;
745
746 case SSSR:
747 s->sssr &= ~(value & SSSR_RW);
748 pxa2xx_ssp_int_update(s);
749 break;
750
751 case SSDR:
752 if (SSCR0_UWIRE(s->sscr[0])) {
753 if (s->sscr[1] & SSCR1_MWDS)
754 value &= 0xffff;
755 else
756 value &= 0xff;
757 } else
758 /* Note how 32bits overflow does no harm here */
759 value &= (1 << SSCR0_DSS(s->sscr[0])) - 1;
760
761 /* Data goes from here to the Tx FIFO and is shifted out from
762 * there directly to the slave, no need to buffer it.
763 */
764 if (s->enable) {
765 uint32_t readval;
766 readval = ssi_transfer(s->bus, value);
767 if (s->rx_level < 0x10) {
768 s->rx_fifo[(s->rx_start + s->rx_level ++) & 0xf] = readval;
769 } else {
770 s->sssr |= SSSR_ROR;
771 }
772 }
773 pxa2xx_ssp_fifo_update(s);
774 break;
775
776 case SSTSA:
777 s->sstsa = value;
778 break;
779
780 case SSRSA:
781 s->ssrsa = value;
782 break;
783
784 case SSACD:
785 s->ssacd = value;
786 break;
787
788 default:
789 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
790 break;
791 }
792 }
793
794 static CPUReadMemoryFunc * const pxa2xx_ssp_readfn[] = {
795 pxa2xx_ssp_read,
796 pxa2xx_ssp_read,
797 pxa2xx_ssp_read,
798 };
799
800 static CPUWriteMemoryFunc * const pxa2xx_ssp_writefn[] = {
801 pxa2xx_ssp_write,
802 pxa2xx_ssp_write,
803 pxa2xx_ssp_write,
804 };
805
806 static void pxa2xx_ssp_save(QEMUFile *f, void *opaque)
807 {
808 PXA2xxSSPState *s = (PXA2xxSSPState *) opaque;
809 int i;
810
811 qemu_put_be32(f, s->enable);
812
813 qemu_put_be32s(f, &s->sscr[0]);
814 qemu_put_be32s(f, &s->sscr[1]);
815 qemu_put_be32s(f, &s->sspsp);
816 qemu_put_be32s(f, &s->ssto);
817 qemu_put_be32s(f, &s->ssitr);
818 qemu_put_be32s(f, &s->sssr);
819 qemu_put_8s(f, &s->sstsa);
820 qemu_put_8s(f, &s->ssrsa);
821 qemu_put_8s(f, &s->ssacd);
822
823 qemu_put_byte(f, s->rx_level);
824 for (i = 0; i < s->rx_level; i ++)
825 qemu_put_byte(f, s->rx_fifo[(s->rx_start + i) & 0xf]);
826 }
827
828 static int pxa2xx_ssp_load(QEMUFile *f, void *opaque, int version_id)
829 {
830 PXA2xxSSPState *s = (PXA2xxSSPState *) opaque;
831 int i;
832
833 s->enable = qemu_get_be32(f);
834
835 qemu_get_be32s(f, &s->sscr[0]);
836 qemu_get_be32s(f, &s->sscr[1]);
837 qemu_get_be32s(f, &s->sspsp);
838 qemu_get_be32s(f, &s->ssto);
839 qemu_get_be32s(f, &s->ssitr);
840 qemu_get_be32s(f, &s->sssr);
841 qemu_get_8s(f, &s->sstsa);
842 qemu_get_8s(f, &s->ssrsa);
843 qemu_get_8s(f, &s->ssacd);
844
845 s->rx_level = qemu_get_byte(f);
846 s->rx_start = 0;
847 for (i = 0; i < s->rx_level; i ++)
848 s->rx_fifo[i] = qemu_get_byte(f);
849
850 return 0;
851 }
852
853 static int pxa2xx_ssp_init(SysBusDevice *dev)
854 {
855 int iomemtype;
856 PXA2xxSSPState *s = FROM_SYSBUS(PXA2xxSSPState, dev);
857
858 sysbus_init_irq(dev, &s->irq);
859
860 iomemtype = cpu_register_io_memory(pxa2xx_ssp_readfn,
861 pxa2xx_ssp_writefn, s,
862 DEVICE_NATIVE_ENDIAN);
863 sysbus_init_mmio(dev, 0x1000, iomemtype);
864 register_savevm(&dev->qdev, "pxa2xx_ssp", -1, 0,
865 pxa2xx_ssp_save, pxa2xx_ssp_load, s);
866
867 s->bus = ssi_create_bus(&dev->qdev, "ssi");
868 return 0;
869 }
870
871 /* Real-Time Clock */
872 #define RCNR 0x00 /* RTC Counter register */
873 #define RTAR 0x04 /* RTC Alarm register */
874 #define RTSR 0x08 /* RTC Status register */
875 #define RTTR 0x0c /* RTC Timer Trim register */
876 #define RDCR 0x10 /* RTC Day Counter register */
877 #define RYCR 0x14 /* RTC Year Counter register */
878 #define RDAR1 0x18 /* RTC Wristwatch Day Alarm register 1 */
879 #define RYAR1 0x1c /* RTC Wristwatch Year Alarm register 1 */
880 #define RDAR2 0x20 /* RTC Wristwatch Day Alarm register 2 */
881 #define RYAR2 0x24 /* RTC Wristwatch Year Alarm register 2 */
882 #define SWCR 0x28 /* RTC Stopwatch Counter register */
883 #define SWAR1 0x2c /* RTC Stopwatch Alarm register 1 */
884 #define SWAR2 0x30 /* RTC Stopwatch Alarm register 2 */
885 #define RTCPICR 0x34 /* RTC Periodic Interrupt Counter register */
886 #define PIAR 0x38 /* RTC Periodic Interrupt Alarm register */
887
888 typedef struct {
889 SysBusDevice busdev;
890 uint32_t rttr;
891 uint32_t rtsr;
892 uint32_t rtar;
893 uint32_t rdar1;
894 uint32_t rdar2;
895 uint32_t ryar1;
896 uint32_t ryar2;
897 uint32_t swar1;
898 uint32_t swar2;
899 uint32_t piar;
900 uint32_t last_rcnr;
901 uint32_t last_rdcr;
902 uint32_t last_rycr;
903 uint32_t last_swcr;
904 uint32_t last_rtcpicr;
905 int64_t last_hz;
906 int64_t last_sw;
907 int64_t last_pi;
908 QEMUTimer *rtc_hz;
909 QEMUTimer *rtc_rdal1;
910 QEMUTimer *rtc_rdal2;
911 QEMUTimer *rtc_swal1;
912 QEMUTimer *rtc_swal2;
913 QEMUTimer *rtc_pi;
914 qemu_irq rtc_irq;
915 } PXA2xxRTCState;
916
917 static inline void pxa2xx_rtc_int_update(PXA2xxRTCState *s)
918 {
919 qemu_set_irq(s->rtc_irq, !!(s->rtsr & 0x2553));
920 }
921
922 static void pxa2xx_rtc_hzupdate(PXA2xxRTCState *s)
923 {
924 int64_t rt = qemu_get_clock_ms(rt_clock);
925 s->last_rcnr += ((rt - s->last_hz) << 15) /
926 (1000 * ((s->rttr & 0xffff) + 1));
927 s->last_rdcr += ((rt - s->last_hz) << 15) /
928 (1000 * ((s->rttr & 0xffff) + 1));
929 s->last_hz = rt;
930 }
931
932 static void pxa2xx_rtc_swupdate(PXA2xxRTCState *s)
933 {
934 int64_t rt = qemu_get_clock_ms(rt_clock);
935 if (s->rtsr & (1 << 12))
936 s->last_swcr += (rt - s->last_sw) / 10;
937 s->last_sw = rt;
938 }
939
940 static void pxa2xx_rtc_piupdate(PXA2xxRTCState *s)
941 {
942 int64_t rt = qemu_get_clock_ms(rt_clock);
943 if (s->rtsr & (1 << 15))
944 s->last_swcr += rt - s->last_pi;
945 s->last_pi = rt;
946 }
947
948 static inline void pxa2xx_rtc_alarm_update(PXA2xxRTCState *s,
949 uint32_t rtsr)
950 {
951 if ((rtsr & (1 << 2)) && !(rtsr & (1 << 0)))
952 qemu_mod_timer(s->rtc_hz, s->last_hz +
953 (((s->rtar - s->last_rcnr) * 1000 *
954 ((s->rttr & 0xffff) + 1)) >> 15));
955 else
956 qemu_del_timer(s->rtc_hz);
957
958 if ((rtsr & (1 << 5)) && !(rtsr & (1 << 4)))
959 qemu_mod_timer(s->rtc_rdal1, s->last_hz +
960 (((s->rdar1 - s->last_rdcr) * 1000 *
961 ((s->rttr & 0xffff) + 1)) >> 15)); /* TODO: fixup */
962 else
963 qemu_del_timer(s->rtc_rdal1);
964
965 if ((rtsr & (1 << 7)) && !(rtsr & (1 << 6)))
966 qemu_mod_timer(s->rtc_rdal2, s->last_hz +
967 (((s->rdar2 - s->last_rdcr) * 1000 *
968 ((s->rttr & 0xffff) + 1)) >> 15)); /* TODO: fixup */
969 else
970 qemu_del_timer(s->rtc_rdal2);
971
972 if ((rtsr & 0x1200) == 0x1200 && !(rtsr & (1 << 8)))
973 qemu_mod_timer(s->rtc_swal1, s->last_sw +
974 (s->swar1 - s->last_swcr) * 10); /* TODO: fixup */
975 else
976 qemu_del_timer(s->rtc_swal1);
977
978 if ((rtsr & 0x1800) == 0x1800 && !(rtsr & (1 << 10)))
979 qemu_mod_timer(s->rtc_swal2, s->last_sw +
980 (s->swar2 - s->last_swcr) * 10); /* TODO: fixup */
981 else
982 qemu_del_timer(s->rtc_swal2);
983
984 if ((rtsr & 0xc000) == 0xc000 && !(rtsr & (1 << 13)))
985 qemu_mod_timer(s->rtc_pi, s->last_pi +
986 (s->piar & 0xffff) - s->last_rtcpicr);
987 else
988 qemu_del_timer(s->rtc_pi);
989 }
990
991 static inline void pxa2xx_rtc_hz_tick(void *opaque)
992 {
993 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
994 s->rtsr |= (1 << 0);
995 pxa2xx_rtc_alarm_update(s, s->rtsr);
996 pxa2xx_rtc_int_update(s);
997 }
998
999 static inline void pxa2xx_rtc_rdal1_tick(void *opaque)
1000 {
1001 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
1002 s->rtsr |= (1 << 4);
1003 pxa2xx_rtc_alarm_update(s, s->rtsr);
1004 pxa2xx_rtc_int_update(s);
1005 }
1006
1007 static inline void pxa2xx_rtc_rdal2_tick(void *opaque)
1008 {
1009 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
1010 s->rtsr |= (1 << 6);
1011 pxa2xx_rtc_alarm_update(s, s->rtsr);
1012 pxa2xx_rtc_int_update(s);
1013 }
1014
1015 static inline void pxa2xx_rtc_swal1_tick(void *opaque)
1016 {
1017 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
1018 s->rtsr |= (1 << 8);
1019 pxa2xx_rtc_alarm_update(s, s->rtsr);
1020 pxa2xx_rtc_int_update(s);
1021 }
1022
1023 static inline void pxa2xx_rtc_swal2_tick(void *opaque)
1024 {
1025 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
1026 s->rtsr |= (1 << 10);
1027 pxa2xx_rtc_alarm_update(s, s->rtsr);
1028 pxa2xx_rtc_int_update(s);
1029 }
1030
1031 static inline void pxa2xx_rtc_pi_tick(void *opaque)
1032 {
1033 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
1034 s->rtsr |= (1 << 13);
1035 pxa2xx_rtc_piupdate(s);
1036 s->last_rtcpicr = 0;
1037 pxa2xx_rtc_alarm_update(s, s->rtsr);
1038 pxa2xx_rtc_int_update(s);
1039 }
1040
1041 static uint32_t pxa2xx_rtc_read(void *opaque, target_phys_addr_t addr)
1042 {
1043 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
1044
1045 switch (addr) {
1046 case RTTR:
1047 return s->rttr;
1048 case RTSR:
1049 return s->rtsr;
1050 case RTAR:
1051 return s->rtar;
1052 case RDAR1:
1053 return s->rdar1;
1054 case RDAR2:
1055 return s->rdar2;
1056 case RYAR1:
1057 return s->ryar1;
1058 case RYAR2:
1059 return s->ryar2;
1060 case SWAR1:
1061 return s->swar1;
1062 case SWAR2:
1063 return s->swar2;
1064 case PIAR:
1065 return s->piar;
1066 case RCNR:
1067 return s->last_rcnr + ((qemu_get_clock_ms(rt_clock) - s->last_hz) << 15) /
1068 (1000 * ((s->rttr & 0xffff) + 1));
1069 case RDCR:
1070 return s->last_rdcr + ((qemu_get_clock_ms(rt_clock) - s->last_hz) << 15) /
1071 (1000 * ((s->rttr & 0xffff) + 1));
1072 case RYCR:
1073 return s->last_rycr;
1074 case SWCR:
1075 if (s->rtsr & (1 << 12))
1076 return s->last_swcr + (qemu_get_clock_ms(rt_clock) - s->last_sw) / 10;
1077 else
1078 return s->last_swcr;
1079 default:
1080 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1081 break;
1082 }
1083 return 0;
1084 }
1085
1086 static void pxa2xx_rtc_write(void *opaque, target_phys_addr_t addr,
1087 uint32_t value)
1088 {
1089 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
1090
1091 switch (addr) {
1092 case RTTR:
1093 if (!(s->rttr & (1 << 31))) {
1094 pxa2xx_rtc_hzupdate(s);
1095 s->rttr = value;
1096 pxa2xx_rtc_alarm_update(s, s->rtsr);
1097 }
1098 break;
1099
1100 case RTSR:
1101 if ((s->rtsr ^ value) & (1 << 15))
1102 pxa2xx_rtc_piupdate(s);
1103
1104 if ((s->rtsr ^ value) & (1 << 12))
1105 pxa2xx_rtc_swupdate(s);
1106
1107 if (((s->rtsr ^ value) & 0x4aac) | (value & ~0xdaac))
1108 pxa2xx_rtc_alarm_update(s, value);
1109
1110 s->rtsr = (value & 0xdaac) | (s->rtsr & ~(value & ~0xdaac));
1111 pxa2xx_rtc_int_update(s);
1112 break;
1113
1114 case RTAR:
1115 s->rtar = value;
1116 pxa2xx_rtc_alarm_update(s, s->rtsr);
1117 break;
1118
1119 case RDAR1:
1120 s->rdar1 = value;
1121 pxa2xx_rtc_alarm_update(s, s->rtsr);
1122 break;
1123
1124 case RDAR2:
1125 s->rdar2 = value;
1126 pxa2xx_rtc_alarm_update(s, s->rtsr);
1127 break;
1128
1129 case RYAR1:
1130 s->ryar1 = value;
1131 pxa2xx_rtc_alarm_update(s, s->rtsr);
1132 break;
1133
1134 case RYAR2:
1135 s->ryar2 = value;
1136 pxa2xx_rtc_alarm_update(s, s->rtsr);
1137 break;
1138
1139 case SWAR1:
1140 pxa2xx_rtc_swupdate(s);
1141 s->swar1 = value;
1142 s->last_swcr = 0;
1143 pxa2xx_rtc_alarm_update(s, s->rtsr);
1144 break;
1145
1146 case SWAR2:
1147 s->swar2 = value;
1148 pxa2xx_rtc_alarm_update(s, s->rtsr);
1149 break;
1150
1151 case PIAR:
1152 s->piar = value;
1153 pxa2xx_rtc_alarm_update(s, s->rtsr);
1154 break;
1155
1156 case RCNR:
1157 pxa2xx_rtc_hzupdate(s);
1158 s->last_rcnr = value;
1159 pxa2xx_rtc_alarm_update(s, s->rtsr);
1160 break;
1161
1162 case RDCR:
1163 pxa2xx_rtc_hzupdate(s);
1164 s->last_rdcr = value;
1165 pxa2xx_rtc_alarm_update(s, s->rtsr);
1166 break;
1167
1168 case RYCR:
1169 s->last_rycr = value;
1170 break;
1171
1172 case SWCR:
1173 pxa2xx_rtc_swupdate(s);
1174 s->last_swcr = value;
1175 pxa2xx_rtc_alarm_update(s, s->rtsr);
1176 break;
1177
1178 case RTCPICR:
1179 pxa2xx_rtc_piupdate(s);
1180 s->last_rtcpicr = value & 0xffff;
1181 pxa2xx_rtc_alarm_update(s, s->rtsr);
1182 break;
1183
1184 default:
1185 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1186 }
1187 }
1188
1189 static CPUReadMemoryFunc * const pxa2xx_rtc_readfn[] = {
1190 pxa2xx_rtc_read,
1191 pxa2xx_rtc_read,
1192 pxa2xx_rtc_read,
1193 };
1194
1195 static CPUWriteMemoryFunc * const pxa2xx_rtc_writefn[] = {
1196 pxa2xx_rtc_write,
1197 pxa2xx_rtc_write,
1198 pxa2xx_rtc_write,
1199 };
1200
1201 static int pxa2xx_rtc_init(SysBusDevice *dev)
1202 {
1203 PXA2xxRTCState *s = FROM_SYSBUS(PXA2xxRTCState, dev);
1204 struct tm tm;
1205 int wom;
1206 int iomemtype;
1207
1208 s->rttr = 0x7fff;
1209 s->rtsr = 0;
1210
1211 qemu_get_timedate(&tm, 0);
1212 wom = ((tm.tm_mday - 1) / 7) + 1;
1213
1214 s->last_rcnr = (uint32_t) mktimegm(&tm);
1215 s->last_rdcr = (wom << 20) | ((tm.tm_wday + 1) << 17) |
1216 (tm.tm_hour << 12) | (tm.tm_min << 6) | tm.tm_sec;
1217 s->last_rycr = ((tm.tm_year + 1900) << 9) |
1218 ((tm.tm_mon + 1) << 5) | tm.tm_mday;
1219 s->last_swcr = (tm.tm_hour << 19) |
1220 (tm.tm_min << 13) | (tm.tm_sec << 7);
1221 s->last_rtcpicr = 0;
1222 s->last_hz = s->last_sw = s->last_pi = qemu_get_clock_ms(rt_clock);
1223
1224 s->rtc_hz = qemu_new_timer_ms(rt_clock, pxa2xx_rtc_hz_tick, s);
1225 s->rtc_rdal1 = qemu_new_timer_ms(rt_clock, pxa2xx_rtc_rdal1_tick, s);
1226 s->rtc_rdal2 = qemu_new_timer_ms(rt_clock, pxa2xx_rtc_rdal2_tick, s);
1227 s->rtc_swal1 = qemu_new_timer_ms(rt_clock, pxa2xx_rtc_swal1_tick, s);
1228 s->rtc_swal2 = qemu_new_timer_ms(rt_clock, pxa2xx_rtc_swal2_tick, s);
1229 s->rtc_pi = qemu_new_timer_ms(rt_clock, pxa2xx_rtc_pi_tick, s);
1230
1231 sysbus_init_irq(dev, &s->rtc_irq);
1232
1233 iomemtype = cpu_register_io_memory(pxa2xx_rtc_readfn,
1234 pxa2xx_rtc_writefn, s, DEVICE_NATIVE_ENDIAN);
1235 sysbus_init_mmio(dev, 0x10000, iomemtype);
1236
1237 return 0;
1238 }
1239
1240 static void pxa2xx_rtc_pre_save(void *opaque)
1241 {
1242 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
1243
1244 pxa2xx_rtc_hzupdate(s);
1245 pxa2xx_rtc_piupdate(s);
1246 pxa2xx_rtc_swupdate(s);
1247 }
1248
1249 static int pxa2xx_rtc_post_load(void *opaque, int version_id)
1250 {
1251 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
1252
1253 pxa2xx_rtc_alarm_update(s, s->rtsr);
1254
1255 return 0;
1256 }
1257
1258 static const VMStateDescription vmstate_pxa2xx_rtc_regs = {
1259 .name = "pxa2xx_rtc",
1260 .version_id = 0,
1261 .minimum_version_id = 0,
1262 .minimum_version_id_old = 0,
1263 .pre_save = pxa2xx_rtc_pre_save,
1264 .post_load = pxa2xx_rtc_post_load,
1265 .fields = (VMStateField[]) {
1266 VMSTATE_UINT32(rttr, PXA2xxRTCState),
1267 VMSTATE_UINT32(rtsr, PXA2xxRTCState),
1268 VMSTATE_UINT32(rtar, PXA2xxRTCState),
1269 VMSTATE_UINT32(rdar1, PXA2xxRTCState),
1270 VMSTATE_UINT32(rdar2, PXA2xxRTCState),
1271 VMSTATE_UINT32(ryar1, PXA2xxRTCState),
1272 VMSTATE_UINT32(ryar2, PXA2xxRTCState),
1273 VMSTATE_UINT32(swar1, PXA2xxRTCState),
1274 VMSTATE_UINT32(swar2, PXA2xxRTCState),
1275 VMSTATE_UINT32(piar, PXA2xxRTCState),
1276 VMSTATE_UINT32(last_rcnr, PXA2xxRTCState),
1277 VMSTATE_UINT32(last_rdcr, PXA2xxRTCState),
1278 VMSTATE_UINT32(last_rycr, PXA2xxRTCState),
1279 VMSTATE_UINT32(last_swcr, PXA2xxRTCState),
1280 VMSTATE_UINT32(last_rtcpicr, PXA2xxRTCState),
1281 VMSTATE_INT64(last_hz, PXA2xxRTCState),
1282 VMSTATE_INT64(last_sw, PXA2xxRTCState),
1283 VMSTATE_INT64(last_pi, PXA2xxRTCState),
1284 VMSTATE_END_OF_LIST(),
1285 },
1286 };
1287
1288 static SysBusDeviceInfo pxa2xx_rtc_sysbus_info = {
1289 .init = pxa2xx_rtc_init,
1290 .qdev.name = "pxa2xx_rtc",
1291 .qdev.desc = "PXA2xx RTC Controller",
1292 .qdev.size = sizeof(PXA2xxRTCState),
1293 .qdev.vmsd = &vmstate_pxa2xx_rtc_regs,
1294 };
1295
1296 /* I2C Interface */
1297 typedef struct {
1298 i2c_slave i2c;
1299 PXA2xxI2CState *host;
1300 } PXA2xxI2CSlaveState;
1301
1302 struct PXA2xxI2CState {
1303 SysBusDevice busdev;
1304 PXA2xxI2CSlaveState *slave;
1305 i2c_bus *bus;
1306 qemu_irq irq;
1307 uint32_t offset;
1308 uint32_t region_size;
1309
1310 uint16_t control;
1311 uint16_t status;
1312 uint8_t ibmr;
1313 uint8_t data;
1314 };
1315
1316 #define IBMR 0x80 /* I2C Bus Monitor register */
1317 #define IDBR 0x88 /* I2C Data Buffer register */
1318 #define ICR 0x90 /* I2C Control register */
1319 #define ISR 0x98 /* I2C Status register */
1320 #define ISAR 0xa0 /* I2C Slave Address register */
1321
1322 static void pxa2xx_i2c_update(PXA2xxI2CState *s)
1323 {
1324 uint16_t level = 0;
1325 level |= s->status & s->control & (1 << 10); /* BED */
1326 level |= (s->status & (1 << 7)) && (s->control & (1 << 9)); /* IRF */
1327 level |= (s->status & (1 << 6)) && (s->control & (1 << 8)); /* ITE */
1328 level |= s->status & (1 << 9); /* SAD */
1329 qemu_set_irq(s->irq, !!level);
1330 }
1331
1332 /* These are only stubs now. */
1333 static void pxa2xx_i2c_event(i2c_slave *i2c, enum i2c_event event)
1334 {
1335 PXA2xxI2CSlaveState *slave = FROM_I2C_SLAVE(PXA2xxI2CSlaveState, i2c);
1336 PXA2xxI2CState *s = slave->host;
1337
1338 switch (event) {
1339 case I2C_START_SEND:
1340 s->status |= (1 << 9); /* set SAD */
1341 s->status &= ~(1 << 0); /* clear RWM */
1342 break;
1343 case I2C_START_RECV:
1344 s->status |= (1 << 9); /* set SAD */
1345 s->status |= 1 << 0; /* set RWM */
1346 break;
1347 case I2C_FINISH:
1348 s->status |= (1 << 4); /* set SSD */
1349 break;
1350 case I2C_NACK:
1351 s->status |= 1 << 1; /* set ACKNAK */
1352 break;
1353 }
1354 pxa2xx_i2c_update(s);
1355 }
1356
1357 static int pxa2xx_i2c_rx(i2c_slave *i2c)
1358 {
1359 PXA2xxI2CSlaveState *slave = FROM_I2C_SLAVE(PXA2xxI2CSlaveState, i2c);
1360 PXA2xxI2CState *s = slave->host;
1361 if ((s->control & (1 << 14)) || !(s->control & (1 << 6)))
1362 return 0;
1363
1364 if (s->status & (1 << 0)) { /* RWM */
1365 s->status |= 1 << 6; /* set ITE */
1366 }
1367 pxa2xx_i2c_update(s);
1368
1369 return s->data;
1370 }
1371
1372 static int pxa2xx_i2c_tx(i2c_slave *i2c, uint8_t data)
1373 {
1374 PXA2xxI2CSlaveState *slave = FROM_I2C_SLAVE(PXA2xxI2CSlaveState, i2c);
1375 PXA2xxI2CState *s = slave->host;
1376 if ((s->control & (1 << 14)) || !(s->control & (1 << 6)))
1377 return 1;
1378
1379 if (!(s->status & (1 << 0))) { /* RWM */
1380 s->status |= 1 << 7; /* set IRF */
1381 s->data = data;
1382 }
1383 pxa2xx_i2c_update(s);
1384
1385 return 1;
1386 }
1387
1388 static uint32_t pxa2xx_i2c_read(void *opaque, target_phys_addr_t addr)
1389 {
1390 PXA2xxI2CState *s = (PXA2xxI2CState *) opaque;
1391
1392 addr -= s->offset;
1393 switch (addr) {
1394 case ICR:
1395 return s->control;
1396 case ISR:
1397 return s->status | (i2c_bus_busy(s->bus) << 2);
1398 case ISAR:
1399 return s->slave->i2c.address;
1400 case IDBR:
1401 return s->data;
1402 case IBMR:
1403 if (s->status & (1 << 2))
1404 s->ibmr ^= 3; /* Fake SCL and SDA pin changes */
1405 else
1406 s->ibmr = 0;
1407 return s->ibmr;
1408 default:
1409 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1410 break;
1411 }
1412 return 0;
1413 }
1414
1415 static void pxa2xx_i2c_write(void *opaque, target_phys_addr_t addr,
1416 uint32_t value)
1417 {
1418 PXA2xxI2CState *s = (PXA2xxI2CState *) opaque;
1419 int ack;
1420
1421 addr -= s->offset;
1422 switch (addr) {
1423 case ICR:
1424 s->control = value & 0xfff7;
1425 if ((value & (1 << 3)) && (value & (1 << 6))) { /* TB and IUE */
1426 /* TODO: slave mode */
1427 if (value & (1 << 0)) { /* START condition */
1428 if (s->data & 1)
1429 s->status |= 1 << 0; /* set RWM */
1430 else
1431 s->status &= ~(1 << 0); /* clear RWM */
1432 ack = !i2c_start_transfer(s->bus, s->data >> 1, s->data & 1);
1433 } else {
1434 if (s->status & (1 << 0)) { /* RWM */
1435 s->data = i2c_recv(s->bus);
1436 if (value & (1 << 2)) /* ACKNAK */
1437 i2c_nack(s->bus);
1438 ack = 1;
1439 } else
1440 ack = !i2c_send(s->bus, s->data);
1441 }
1442
1443 if (value & (1 << 1)) /* STOP condition */
1444 i2c_end_transfer(s->bus);
1445
1446 if (ack) {
1447 if (value & (1 << 0)) /* START condition */
1448 s->status |= 1 << 6; /* set ITE */
1449 else
1450 if (s->status & (1 << 0)) /* RWM */
1451 s->status |= 1 << 7; /* set IRF */
1452 else
1453 s->status |= 1 << 6; /* set ITE */
1454 s->status &= ~(1 << 1); /* clear ACKNAK */
1455 } else {
1456 s->status |= 1 << 6; /* set ITE */
1457 s->status |= 1 << 10; /* set BED */
1458 s->status |= 1 << 1; /* set ACKNAK */
1459 }
1460 }
1461 if (!(value & (1 << 3)) && (value & (1 << 6))) /* !TB and IUE */
1462 if (value & (1 << 4)) /* MA */
1463 i2c_end_transfer(s->bus);
1464 pxa2xx_i2c_update(s);
1465 break;
1466
1467 case ISR:
1468 s->status &= ~(value & 0x07f0);
1469 pxa2xx_i2c_update(s);
1470 break;
1471
1472 case ISAR:
1473 i2c_set_slave_address(&s->slave->i2c, value & 0x7f);
1474 break;
1475
1476 case IDBR:
1477 s->data = value & 0xff;
1478 break;
1479
1480 default:
1481 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1482 }
1483 }
1484
1485 static CPUReadMemoryFunc * const pxa2xx_i2c_readfn[] = {
1486 pxa2xx_i2c_read,
1487 pxa2xx_i2c_read,
1488 pxa2xx_i2c_read,
1489 };
1490
1491 static CPUWriteMemoryFunc * const pxa2xx_i2c_writefn[] = {
1492 pxa2xx_i2c_write,
1493 pxa2xx_i2c_write,
1494 pxa2xx_i2c_write,
1495 };
1496
1497 static const VMStateDescription vmstate_pxa2xx_i2c_slave = {
1498 .name = "pxa2xx_i2c_slave",
1499 .version_id = 1,
1500 .minimum_version_id = 1,
1501 .minimum_version_id_old = 1,
1502 .fields = (VMStateField []) {
1503 VMSTATE_I2C_SLAVE(i2c, PXA2xxI2CSlaveState),
1504 VMSTATE_END_OF_LIST()
1505 }
1506 };
1507
1508 static const VMStateDescription vmstate_pxa2xx_i2c = {
1509 .name = "pxa2xx_i2c",
1510 .version_id = 1,
1511 .minimum_version_id = 1,
1512 .minimum_version_id_old = 1,
1513 .fields = (VMStateField []) {
1514 VMSTATE_UINT16(control, PXA2xxI2CState),
1515 VMSTATE_UINT16(status, PXA2xxI2CState),
1516 VMSTATE_UINT8(ibmr, PXA2xxI2CState),
1517 VMSTATE_UINT8(data, PXA2xxI2CState),
1518 VMSTATE_STRUCT_POINTER(slave, PXA2xxI2CState,
1519 vmstate_pxa2xx_i2c_slave, PXA2xxI2CSlaveState *),
1520 VMSTATE_END_OF_LIST()
1521 }
1522 };
1523
1524 static int pxa2xx_i2c_slave_init(i2c_slave *i2c)
1525 {
1526 /* Nothing to do. */
1527 return 0;
1528 }
1529
1530 static I2CSlaveInfo pxa2xx_i2c_slave_info = {
1531 .qdev.name = "pxa2xx-i2c-slave",
1532 .qdev.size = sizeof(PXA2xxI2CSlaveState),
1533 .init = pxa2xx_i2c_slave_init,
1534 .event = pxa2xx_i2c_event,
1535 .recv = pxa2xx_i2c_rx,
1536 .send = pxa2xx_i2c_tx
1537 };
1538
1539 PXA2xxI2CState *pxa2xx_i2c_init(target_phys_addr_t base,
1540 qemu_irq irq, uint32_t region_size)
1541 {
1542 DeviceState *dev;
1543 SysBusDevice *i2c_dev;
1544 PXA2xxI2CState *s;
1545
1546 i2c_dev = sysbus_from_qdev(qdev_create(NULL, "pxa2xx_i2c"));
1547 qdev_prop_set_uint32(&i2c_dev->qdev, "size", region_size + 1);
1548 qdev_prop_set_uint32(&i2c_dev->qdev, "offset",
1549 base - (base & (~region_size) & TARGET_PAGE_MASK));
1550
1551 qdev_init_nofail(&i2c_dev->qdev);
1552
1553 sysbus_mmio_map(i2c_dev, 0, base & ~region_size);
1554 sysbus_connect_irq(i2c_dev, 0, irq);
1555
1556 s = FROM_SYSBUS(PXA2xxI2CState, i2c_dev);
1557 /* FIXME: Should the slave device really be on a separate bus? */
1558 dev = i2c_create_slave(i2c_init_bus(NULL, "dummy"), "pxa2xx-i2c-slave", 0);
1559 s->slave = FROM_I2C_SLAVE(PXA2xxI2CSlaveState, I2C_SLAVE_FROM_QDEV(dev));
1560 s->slave->host = s;
1561
1562 return s;
1563 }
1564
1565 static int pxa2xx_i2c_initfn(SysBusDevice *dev)
1566 {
1567 PXA2xxI2CState *s = FROM_SYSBUS(PXA2xxI2CState, dev);
1568 int iomemtype;
1569
1570 s->bus = i2c_init_bus(&dev->qdev, "i2c");
1571
1572 iomemtype = cpu_register_io_memory(pxa2xx_i2c_readfn,
1573 pxa2xx_i2c_writefn, s, DEVICE_NATIVE_ENDIAN);
1574 sysbus_init_mmio(dev, s->region_size, iomemtype);
1575 sysbus_init_irq(dev, &s->irq);
1576
1577 return 0;
1578 }
1579
1580 i2c_bus *pxa2xx_i2c_bus(PXA2xxI2CState *s)
1581 {
1582 return s->bus;
1583 }
1584
1585 static SysBusDeviceInfo pxa2xx_i2c_info = {
1586 .init = pxa2xx_i2c_initfn,
1587 .qdev.name = "pxa2xx_i2c",
1588 .qdev.desc = "PXA2xx I2C Bus Controller",
1589 .qdev.size = sizeof(PXA2xxI2CState),
1590 .qdev.vmsd = &vmstate_pxa2xx_i2c,
1591 .qdev.props = (Property[]) {
1592 DEFINE_PROP_UINT32("size", PXA2xxI2CState, region_size, 0x10000),
1593 DEFINE_PROP_UINT32("offset", PXA2xxI2CState, offset, 0),
1594 DEFINE_PROP_END_OF_LIST(),
1595 },
1596 };
1597
1598 /* PXA Inter-IC Sound Controller */
1599 static void pxa2xx_i2s_reset(PXA2xxI2SState *i2s)
1600 {
1601 i2s->rx_len = 0;
1602 i2s->tx_len = 0;
1603 i2s->fifo_len = 0;
1604 i2s->clk = 0x1a;
1605 i2s->control[0] = 0x00;
1606 i2s->control[1] = 0x00;
1607 i2s->status = 0x00;
1608 i2s->mask = 0x00;
1609 }
1610
1611 #define SACR_TFTH(val) ((val >> 8) & 0xf)
1612 #define SACR_RFTH(val) ((val >> 12) & 0xf)
1613 #define SACR_DREC(val) (val & (1 << 3))
1614 #define SACR_DPRL(val) (val & (1 << 4))
1615
1616 static inline void pxa2xx_i2s_update(PXA2xxI2SState *i2s)
1617 {
1618 int rfs, tfs;
1619 rfs = SACR_RFTH(i2s->control[0]) < i2s->rx_len &&
1620 !SACR_DREC(i2s->control[1]);
1621 tfs = (i2s->tx_len || i2s->fifo_len < SACR_TFTH(i2s->control[0])) &&
1622 i2s->enable && !SACR_DPRL(i2s->control[1]);
1623
1624 qemu_set_irq(i2s->rx_dma, rfs);
1625 qemu_set_irq(i2s->tx_dma, tfs);
1626
1627 i2s->status &= 0xe0;
1628 if (i2s->fifo_len < 16 || !i2s->enable)
1629 i2s->status |= 1 << 0; /* TNF */
1630 if (i2s->rx_len)
1631 i2s->status |= 1 << 1; /* RNE */
1632 if (i2s->enable)
1633 i2s->status |= 1 << 2; /* BSY */
1634 if (tfs)
1635 i2s->status |= 1 << 3; /* TFS */
1636 if (rfs)
1637 i2s->status |= 1 << 4; /* RFS */
1638 if (!(i2s->tx_len && i2s->enable))
1639 i2s->status |= i2s->fifo_len << 8; /* TFL */
1640 i2s->status |= MAX(i2s->rx_len, 0xf) << 12; /* RFL */
1641
1642 qemu_set_irq(i2s->irq, i2s->status & i2s->mask);
1643 }
1644
1645 #define SACR0 0x00 /* Serial Audio Global Control register */
1646 #define SACR1 0x04 /* Serial Audio I2S/MSB-Justified Control register */
1647 #define SASR0 0x0c /* Serial Audio Interface and FIFO Status register */
1648 #define SAIMR 0x14 /* Serial Audio Interrupt Mask register */
1649 #define SAICR 0x18 /* Serial Audio Interrupt Clear register */
1650 #define SADIV 0x60 /* Serial Audio Clock Divider register */
1651 #define SADR 0x80 /* Serial Audio Data register */
1652
1653 static uint32_t pxa2xx_i2s_read(void *opaque, target_phys_addr_t addr)
1654 {
1655 PXA2xxI2SState *s = (PXA2xxI2SState *) opaque;
1656
1657 switch (addr) {
1658 case SACR0:
1659 return s->control[0];
1660 case SACR1:
1661 return s->control[1];
1662 case SASR0:
1663 return s->status;
1664 case SAIMR:
1665 return s->mask;
1666 case SAICR:
1667 return 0;
1668 case SADIV:
1669 return s->clk;
1670 case SADR:
1671 if (s->rx_len > 0) {
1672 s->rx_len --;
1673 pxa2xx_i2s_update(s);
1674 return s->codec_in(s->opaque);
1675 }
1676 return 0;
1677 default:
1678 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1679 break;
1680 }
1681 return 0;
1682 }
1683
1684 static void pxa2xx_i2s_write(void *opaque, target_phys_addr_t addr,
1685 uint32_t value)
1686 {
1687 PXA2xxI2SState *s = (PXA2xxI2SState *) opaque;
1688 uint32_t *sample;
1689
1690 switch (addr) {
1691 case SACR0:
1692 if (value & (1 << 3)) /* RST */
1693 pxa2xx_i2s_reset(s);
1694 s->control[0] = value & 0xff3d;
1695 if (!s->enable && (value & 1) && s->tx_len) { /* ENB */
1696 for (sample = s->fifo; s->fifo_len > 0; s->fifo_len --, sample ++)
1697 s->codec_out(s->opaque, *sample);
1698 s->status &= ~(1 << 7); /* I2SOFF */
1699 }
1700 if (value & (1 << 4)) /* EFWR */
1701 printf("%s: Attempt to use special function\n", __FUNCTION__);
1702 s->enable = (value & 9) == 1; /* ENB && !RST*/
1703 pxa2xx_i2s_update(s);
1704 break;
1705 case SACR1:
1706 s->control[1] = value & 0x0039;
1707 if (value & (1 << 5)) /* ENLBF */
1708 printf("%s: Attempt to use loopback function\n", __FUNCTION__);
1709 if (value & (1 << 4)) /* DPRL */
1710 s->fifo_len = 0;
1711 pxa2xx_i2s_update(s);
1712 break;
1713 case SAIMR:
1714 s->mask = value & 0x0078;
1715 pxa2xx_i2s_update(s);
1716 break;
1717 case SAICR:
1718 s->status &= ~(value & (3 << 5));
1719 pxa2xx_i2s_update(s);
1720 break;
1721 case SADIV:
1722 s->clk = value & 0x007f;
1723 break;
1724 case SADR:
1725 if (s->tx_len && s->enable) {
1726 s->tx_len --;
1727 pxa2xx_i2s_update(s);
1728 s->codec_out(s->opaque, value);
1729 } else if (s->fifo_len < 16) {
1730 s->fifo[s->fifo_len ++] = value;
1731 pxa2xx_i2s_update(s);
1732 }
1733 break;
1734 default:
1735 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1736 }
1737 }
1738
1739 static CPUReadMemoryFunc * const pxa2xx_i2s_readfn[] = {
1740 pxa2xx_i2s_read,
1741 pxa2xx_i2s_read,
1742 pxa2xx_i2s_read,
1743 };
1744
1745 static CPUWriteMemoryFunc * const pxa2xx_i2s_writefn[] = {
1746 pxa2xx_i2s_write,
1747 pxa2xx_i2s_write,
1748 pxa2xx_i2s_write,
1749 };
1750
1751 static void pxa2xx_i2s_save(QEMUFile *f, void *opaque)
1752 {
1753 PXA2xxI2SState *s = (PXA2xxI2SState *) opaque;
1754
1755 qemu_put_be32s(f, &s->control[0]);
1756 qemu_put_be32s(f, &s->control[1]);
1757 qemu_put_be32s(f, &s->status);
1758 qemu_put_be32s(f, &s->mask);
1759 qemu_put_be32s(f, &s->clk);
1760
1761 qemu_put_be32(f, s->enable);
1762 qemu_put_be32(f, s->rx_len);
1763 qemu_put_be32(f, s->tx_len);
1764 qemu_put_be32(f, s->fifo_len);
1765 }
1766
1767 static int pxa2xx_i2s_load(QEMUFile *f, void *opaque, int version_id)
1768 {
1769 PXA2xxI2SState *s = (PXA2xxI2SState *) opaque;
1770
1771 qemu_get_be32s(f, &s->control[0]);
1772 qemu_get_be32s(f, &s->control[1]);
1773 qemu_get_be32s(f, &s->status);
1774 qemu_get_be32s(f, &s->mask);
1775 qemu_get_be32s(f, &s->clk);
1776
1777 s->enable = qemu_get_be32(f);
1778 s->rx_len = qemu_get_be32(f);
1779 s->tx_len = qemu_get_be32(f);
1780 s->fifo_len = qemu_get_be32(f);
1781
1782 return 0;
1783 }
1784
1785 static void pxa2xx_i2s_data_req(void *opaque, int tx, int rx)
1786 {
1787 PXA2xxI2SState *s = (PXA2xxI2SState *) opaque;
1788 uint32_t *sample;
1789
1790 /* Signal FIFO errors */
1791 if (s->enable && s->tx_len)
1792 s->status |= 1 << 5; /* TUR */
1793 if (s->enable && s->rx_len)
1794 s->status |= 1 << 6; /* ROR */
1795
1796 /* Should be tx - MIN(tx, s->fifo_len) but we don't really need to
1797 * handle the cases where it makes a difference. */
1798 s->tx_len = tx - s->fifo_len;
1799 s->rx_len = rx;
1800 /* Note that is s->codec_out wasn't set, we wouldn't get called. */
1801 if (s->enable)
1802 for (sample = s->fifo; s->fifo_len; s->fifo_len --, sample ++)
1803 s->codec_out(s->opaque, *sample);
1804 pxa2xx_i2s_update(s);
1805 }
1806
1807 static PXA2xxI2SState *pxa2xx_i2s_init(target_phys_addr_t base,
1808 qemu_irq irq, qemu_irq rx_dma, qemu_irq tx_dma)
1809 {
1810 int iomemtype;
1811 PXA2xxI2SState *s = (PXA2xxI2SState *)
1812 qemu_mallocz(sizeof(PXA2xxI2SState));
1813
1814 s->irq = irq;
1815 s->rx_dma = rx_dma;
1816 s->tx_dma = tx_dma;
1817 s->data_req = pxa2xx_i2s_data_req;
1818
1819 pxa2xx_i2s_reset(s);
1820
1821 iomemtype = cpu_register_io_memory(pxa2xx_i2s_readfn,
1822 pxa2xx_i2s_writefn, s, DEVICE_NATIVE_ENDIAN);
1823 cpu_register_physical_memory(base, 0x100000, iomemtype);
1824
1825 register_savevm(NULL, "pxa2xx_i2s", base, 0,
1826 pxa2xx_i2s_save, pxa2xx_i2s_load, s);
1827
1828 return s;
1829 }
1830
1831 /* PXA Fast Infra-red Communications Port */
1832 struct PXA2xxFIrState {
1833 qemu_irq irq;
1834 qemu_irq rx_dma;
1835 qemu_irq tx_dma;
1836 int enable;
1837 CharDriverState *chr;
1838
1839 uint8_t control[3];
1840 uint8_t status[2];
1841
1842 int rx_len;
1843 int rx_start;
1844 uint8_t rx_fifo[64];
1845 };
1846
1847 static void pxa2xx_fir_reset(PXA2xxFIrState *s)
1848 {
1849 s->control[0] = 0x00;
1850 s->control[1] = 0x00;
1851 s->control[2] = 0x00;
1852 s->status[0] = 0x00;
1853 s->status[1] = 0x00;
1854 s->enable = 0;
1855 }
1856
1857 static inline void pxa2xx_fir_update(PXA2xxFIrState *s)
1858 {
1859 static const int tresh[4] = { 8, 16, 32, 0 };
1860 int intr = 0;
1861 if ((s->control[0] & (1 << 4)) && /* RXE */
1862 s->rx_len >= tresh[s->control[2] & 3]) /* TRIG */
1863 s->status[0] |= 1 << 4; /* RFS */
1864 else
1865 s->status[0] &= ~(1 << 4); /* RFS */
1866 if (s->control[0] & (1 << 3)) /* TXE */
1867 s->status[0] |= 1 << 3; /* TFS */
1868 else
1869 s->status[0] &= ~(1 << 3); /* TFS */
1870 if (s->rx_len)
1871 s->status[1] |= 1 << 2; /* RNE */
1872 else
1873 s->status[1] &= ~(1 << 2); /* RNE */
1874 if (s->control[0] & (1 << 4)) /* RXE */
1875 s->status[1] |= 1 << 0; /* RSY */
1876 else
1877 s->status[1] &= ~(1 << 0); /* RSY */
1878
1879 intr |= (s->control[0] & (1 << 5)) && /* RIE */
1880 (s->status[0] & (1 << 4)); /* RFS */
1881 intr |= (s->control[0] & (1 << 6)) && /* TIE */
1882 (s->status[0] & (1 << 3)); /* TFS */
1883 intr |= (s->control[2] & (1 << 4)) && /* TRAIL */
1884 (s->status[0] & (1 << 6)); /* EOC */
1885 intr |= (s->control[0] & (1 << 2)) && /* TUS */
1886 (s->status[0] & (1 << 1)); /* TUR */
1887 intr |= s->status[0] & 0x25; /* FRE, RAB, EIF */
1888
1889 qemu_set_irq(s->rx_dma, (s->status[0] >> 4) & 1);
1890 qemu_set_irq(s->tx_dma, (s->status[0] >> 3) & 1);
1891
1892 qemu_set_irq(s->irq, intr && s->enable);
1893 }
1894
1895 #define ICCR0 0x00 /* FICP Control register 0 */
1896 #define ICCR1 0x04 /* FICP Control register 1 */
1897 #define ICCR2 0x08 /* FICP Control register 2 */
1898 #define ICDR 0x0c /* FICP Data register */
1899 #define ICSR0 0x14 /* FICP Status register 0 */
1900 #define ICSR1 0x18 /* FICP Status register 1 */
1901 #define ICFOR 0x1c /* FICP FIFO Occupancy Status register */
1902
1903 static uint32_t pxa2xx_fir_read(void *opaque, target_phys_addr_t addr)
1904 {
1905 PXA2xxFIrState *s = (PXA2xxFIrState *) opaque;
1906 uint8_t ret;
1907
1908 switch (addr) {
1909 case ICCR0:
1910 return s->control[0];
1911 case ICCR1:
1912 return s->control[1];
1913 case ICCR2:
1914 return s->control[2];
1915 case ICDR:
1916 s->status[0] &= ~0x01;
1917 s->status[1] &= ~0x72;
1918 if (s->rx_len) {
1919 s->rx_len --;
1920 ret = s->rx_fifo[s->rx_start ++];
1921 s->rx_start &= 63;
1922 pxa2xx_fir_update(s);
1923 return ret;
1924 }
1925 printf("%s: Rx FIFO underrun.\n", __FUNCTION__);
1926 break;
1927 case ICSR0:
1928 return s->status[0];
1929 case ICSR1:
1930 return s->status[1] | (1 << 3); /* TNF */
1931 case ICFOR:
1932 return s->rx_len;
1933 default:
1934 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1935 break;
1936 }
1937 return 0;
1938 }
1939
1940 static void pxa2xx_fir_write(void *opaque, target_phys_addr_t addr,
1941 uint32_t value)
1942 {
1943 PXA2xxFIrState *s = (PXA2xxFIrState *) opaque;
1944 uint8_t ch;
1945
1946 switch (addr) {
1947 case ICCR0:
1948 s->control[0] = value;
1949 if (!(value & (1 << 4))) /* RXE */
1950 s->rx_len = s->rx_start = 0;
1951 if (!(value & (1 << 3))) { /* TXE */
1952 /* Nop */
1953 }
1954 s->enable = value & 1; /* ITR */
1955 if (!s->enable)
1956 s->status[0] = 0;
1957 pxa2xx_fir_update(s);
1958 break;
1959 case ICCR1:
1960 s->control[1] = value;
1961 break;
1962 case ICCR2:
1963 s->control[2] = value & 0x3f;
1964 pxa2xx_fir_update(s);
1965 break;
1966 case ICDR:
1967 if (s->control[2] & (1 << 2)) /* TXP */
1968 ch = value;
1969 else
1970 ch = ~value;
1971 if (s->chr && s->enable && (s->control[0] & (1 << 3))) /* TXE */
1972 qemu_chr_write(s->chr, &ch, 1);
1973 break;
1974 case ICSR0:
1975 s->status[0] &= ~(value & 0x66);
1976 pxa2xx_fir_update(s);
1977 break;
1978 case ICFOR:
1979 break;
1980 default:
1981 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1982 }
1983 }
1984
1985 static CPUReadMemoryFunc * const pxa2xx_fir_readfn[] = {
1986 pxa2xx_fir_read,
1987 pxa2xx_fir_read,
1988 pxa2xx_fir_read,
1989 };
1990
1991 static CPUWriteMemoryFunc * const pxa2xx_fir_writefn[] = {
1992 pxa2xx_fir_write,
1993 pxa2xx_fir_write,
1994 pxa2xx_fir_write,
1995 };
1996
1997 static int pxa2xx_fir_is_empty(void *opaque)
1998 {
1999 PXA2xxFIrState *s = (PXA2xxFIrState *) opaque;
2000 return (s->rx_len < 64);
2001 }
2002
2003 static void pxa2xx_fir_rx(void *opaque, const uint8_t *buf, int size)
2004 {
2005 PXA2xxFIrState *s = (PXA2xxFIrState *) opaque;
2006 if (!(s->control[0] & (1 << 4))) /* RXE */
2007 return;
2008
2009 while (size --) {
2010 s->status[1] |= 1 << 4; /* EOF */
2011 if (s->rx_len >= 64) {
2012 s->status[1] |= 1 << 6; /* ROR */
2013 break;
2014 }
2015
2016 if (s->control[2] & (1 << 3)) /* RXP */
2017 s->rx_fifo[(s->rx_start + s->rx_len ++) & 63] = *(buf ++);
2018 else
2019 s->rx_fifo[(s->rx_start + s->rx_len ++) & 63] = ~*(buf ++);
2020 }
2021
2022 pxa2xx_fir_update(s);
2023 }
2024
2025 static void pxa2xx_fir_event(void *opaque, int event)
2026 {
2027 }
2028
2029 static void pxa2xx_fir_save(QEMUFile *f, void *opaque)
2030 {
2031 PXA2xxFIrState *s = (PXA2xxFIrState *) opaque;
2032 int i;
2033
2034 qemu_put_be32(f, s->enable);
2035
2036 qemu_put_8s(f, &s->control[0]);
2037 qemu_put_8s(f, &s->control[1]);
2038 qemu_put_8s(f, &s->control[2]);
2039 qemu_put_8s(f, &s->status[0]);
2040 qemu_put_8s(f, &s->status[1]);
2041
2042 qemu_put_byte(f, s->rx_len);
2043 for (i = 0; i < s->rx_len; i ++)
2044 qemu_put_byte(f, s->rx_fifo[(s->rx_start + i) & 63]);
2045 }
2046
2047 static int pxa2xx_fir_load(QEMUFile *f, void *opaque, int version_id)
2048 {
2049 PXA2xxFIrState *s = (PXA2xxFIrState *) opaque;
2050 int i;
2051
2052 s->enable = qemu_get_be32(f);
2053
2054 qemu_get_8s(f, &s->control[0]);
2055 qemu_get_8s(f, &s->control[1]);
2056 qemu_get_8s(f, &s->control[2]);
2057 qemu_get_8s(f, &s->status[0]);
2058 qemu_get_8s(f, &s->status[1]);
2059
2060 s->rx_len = qemu_get_byte(f);
2061 s->rx_start = 0;
2062 for (i = 0; i < s->rx_len; i ++)
2063 s->rx_fifo[i] = qemu_get_byte(f);
2064
2065 return 0;
2066 }
2067
2068 static PXA2xxFIrState *pxa2xx_fir_init(target_phys_addr_t base,
2069 qemu_irq irq, qemu_irq rx_dma, qemu_irq tx_dma,
2070 CharDriverState *chr)
2071 {
2072 int iomemtype;
2073 PXA2xxFIrState *s = (PXA2xxFIrState *)
2074 qemu_mallocz(sizeof(PXA2xxFIrState));
2075
2076 s->irq = irq;
2077 s->rx_dma = rx_dma;
2078 s->tx_dma = tx_dma;
2079 s->chr = chr;
2080
2081 pxa2xx_fir_reset(s);
2082
2083 iomemtype = cpu_register_io_memory(pxa2xx_fir_readfn,
2084 pxa2xx_fir_writefn, s, DEVICE_NATIVE_ENDIAN);
2085 cpu_register_physical_memory(base, 0x1000, iomemtype);
2086
2087 if (chr)
2088 qemu_chr_add_handlers(chr, pxa2xx_fir_is_empty,
2089 pxa2xx_fir_rx, pxa2xx_fir_event, s);
2090
2091 register_savevm(NULL, "pxa2xx_fir", 0, 0, pxa2xx_fir_save,
2092 pxa2xx_fir_load, s);
2093
2094 return s;
2095 }
2096
2097 static void pxa2xx_reset(void *opaque, int line, int level)
2098 {
2099 PXA2xxState *s = (PXA2xxState *) opaque;
2100
2101 if (level && (s->pm_regs[PCFR >> 2] & 0x10)) { /* GPR_EN */
2102 cpu_reset(s->env);
2103 /* TODO: reset peripherals */
2104 }
2105 }
2106
2107 /* Initialise a PXA270 integrated chip (ARM based core). */
2108 PXA2xxState *pxa270_init(unsigned int sdram_size, const char *revision)
2109 {
2110 PXA2xxState *s;
2111 int iomemtype, i;
2112 DriveInfo *dinfo;
2113 s = (PXA2xxState *) qemu_mallocz(sizeof(PXA2xxState));
2114
2115 if (revision && strncmp(revision, "pxa27", 5)) {
2116 fprintf(stderr, "Machine requires a PXA27x processor.\n");
2117 exit(1);
2118 }
2119 if (!revision)
2120 revision = "pxa270";
2121
2122 s->env = cpu_init(revision);
2123 if (!s->env) {
2124 fprintf(stderr, "Unable to find CPU definition\n");
2125 exit(1);
2126 }
2127 s->reset = qemu_allocate_irqs(pxa2xx_reset, s, 1)[0];
2128
2129 /* SDRAM & Internal Memory Storage */
2130 cpu_register_physical_memory(PXA2XX_SDRAM_BASE,
2131 sdram_size, qemu_ram_alloc(NULL, "pxa270.sdram",
2132 sdram_size) | IO_MEM_RAM);
2133 cpu_register_physical_memory(PXA2XX_INTERNAL_BASE,
2134 0x40000, qemu_ram_alloc(NULL, "pxa270.internal",
2135 0x40000) | IO_MEM_RAM);
2136
2137 s->pic = pxa2xx_pic_init(0x40d00000, s->env);
2138
2139 s->dma = pxa27x_dma_init(0x40000000,
2140 qdev_get_gpio_in(s->pic, PXA2XX_PIC_DMA));
2141
2142 sysbus_create_varargs("pxa27x-timer", 0x40a00000,
2143 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 0),
2144 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 1),
2145 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 2),
2146 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 3),
2147 qdev_get_gpio_in(s->pic, PXA27X_PIC_OST_4_11),
2148 NULL);
2149
2150 s->gpio = pxa2xx_gpio_init(0x40e00000, s->env, s->pic, 121);
2151
2152 dinfo = drive_get(IF_SD, 0, 0);
2153 if (!dinfo) {
2154 fprintf(stderr, "qemu: missing SecureDigital device\n");
2155 exit(1);
2156 }
2157 s->mmc = pxa2xx_mmci_init(0x41100000, dinfo->bdrv,
2158 qdev_get_gpio_in(s->pic, PXA2XX_PIC_MMC),
2159 qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_MMCI),
2160 qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_MMCI));
2161
2162 for (i = 0; pxa270_serial[i].io_base; i ++)
2163 if (serial_hds[i])
2164 #ifdef TARGET_WORDS_BIGENDIAN
2165 serial_mm_init(pxa270_serial[i].io_base, 2,
2166 qdev_get_gpio_in(s->pic, pxa270_serial[i].irqn),
2167 14857000 / 16, serial_hds[i], 1, 1);
2168 #else
2169 serial_mm_init(pxa270_serial[i].io_base, 2,
2170 qdev_get_gpio_in(s->pic, pxa270_serial[i].irqn),
2171 14857000 / 16, serial_hds[i], 1, 0);
2172 #endif
2173 else
2174 break;
2175 if (serial_hds[i])
2176 s->fir = pxa2xx_fir_init(0x40800000,
2177 qdev_get_gpio_in(s->pic, PXA2XX_PIC_ICP),
2178 qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_ICP),
2179 qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_ICP),
2180 serial_hds[i]);
2181
2182 s->lcd = pxa2xx_lcdc_init(0x44000000,
2183 qdev_get_gpio_in(s->pic, PXA2XX_PIC_LCD));
2184
2185 s->cm_base = 0x41300000;
2186 s->cm_regs[CCCR >> 2] = 0x02000210; /* 416.0 MHz */
2187 s->clkcfg = 0x00000009; /* Turbo mode active */
2188 iomemtype = cpu_register_io_memory(pxa2xx_cm_readfn,
2189 pxa2xx_cm_writefn, s, DEVICE_NATIVE_ENDIAN);
2190 cpu_register_physical_memory(s->cm_base, 0x1000, iomemtype);
2191 register_savevm(NULL, "pxa2xx_cm", 0, 0, pxa2xx_cm_save, pxa2xx_cm_load, s);
2192
2193 cpu_arm_set_cp_io(s->env, 14, pxa2xx_cp14_read, pxa2xx_cp14_write, s);
2194
2195 s->mm_base = 0x48000000;
2196 s->mm_regs[MDMRS >> 2] = 0x00020002;
2197 s->mm_regs[MDREFR >> 2] = 0x03ca4000;
2198 s->mm_regs[MECR >> 2] = 0x00000001; /* Two PC Card sockets */
2199 iomemtype = cpu_register_io_memory(pxa2xx_mm_readfn,
2200 pxa2xx_mm_writefn, s, DEVICE_NATIVE_ENDIAN);
2201 cpu_register_physical_memory(s->mm_base, 0x1000, iomemtype);
2202 register_savevm(NULL, "pxa2xx_mm", 0, 0, pxa2xx_mm_save, pxa2xx_mm_load, s);
2203
2204 s->pm_base = 0x40f00000;
2205 iomemtype = cpu_register_io_memory(pxa2xx_pm_readfn,
2206 pxa2xx_pm_writefn, s, DEVICE_NATIVE_ENDIAN);
2207 cpu_register_physical_memory(s->pm_base, 0x100, iomemtype);
2208 register_savevm(NULL, "pxa2xx_pm", 0, 0, pxa2xx_pm_save, pxa2xx_pm_load, s);
2209
2210 for (i = 0; pxa27x_ssp[i].io_base; i ++);
2211 s->ssp = (SSIBus **)qemu_mallocz(sizeof(SSIBus *) * i);
2212 for (i = 0; pxa27x_ssp[i].io_base; i ++) {
2213 DeviceState *dev;
2214 dev = sysbus_create_simple("pxa2xx-ssp", pxa27x_ssp[i].io_base,
2215 qdev_get_gpio_in(s->pic, pxa27x_ssp[i].irqn));
2216 s->ssp[i] = (SSIBus *)qdev_get_child_bus(dev, "ssi");
2217 }
2218
2219 if (usb_enabled) {
2220 sysbus_create_simple("sysbus-ohci", 0x4c000000,
2221 qdev_get_gpio_in(s->pic, PXA2XX_PIC_USBH1));
2222 }
2223
2224 s->pcmcia[0] = pxa2xx_pcmcia_init(0x20000000);
2225 s->pcmcia[1] = pxa2xx_pcmcia_init(0x30000000);
2226
2227 sysbus_create_simple("pxa2xx_rtc", 0x40900000,
2228 qdev_get_gpio_in(s->pic, PXA2XX_PIC_RTCALARM));
2229
2230 s->i2c[0] = pxa2xx_i2c_init(0x40301600,
2231 qdev_get_gpio_in(s->pic, PXA2XX_PIC_I2C), 0xffff);
2232 s->i2c[1] = pxa2xx_i2c_init(0x40f00100,
2233 qdev_get_gpio_in(s->pic, PXA2XX_PIC_PWRI2C), 0xff);
2234
2235 s->i2s = pxa2xx_i2s_init(0x40400000,
2236 qdev_get_gpio_in(s->pic, PXA2XX_PIC_I2S),
2237 qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_I2S),
2238 qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_I2S));
2239
2240 s->kp = pxa27x_keypad_init(0x41500000,
2241 qdev_get_gpio_in(s->pic, PXA2XX_PIC_KEYPAD));
2242
2243 /* GPIO1 resets the processor */
2244 /* The handler can be overridden by board-specific code */
2245 qdev_connect_gpio_out(s->gpio, 1, s->reset);
2246 return s;
2247 }
2248
2249 /* Initialise a PXA255 integrated chip (ARM based core). */
2250 PXA2xxState *pxa255_init(unsigned int sdram_size)
2251 {
2252 PXA2xxState *s;
2253 int iomemtype, i;
2254 DriveInfo *dinfo;
2255
2256 s = (PXA2xxState *) qemu_mallocz(sizeof(PXA2xxState));
2257
2258 s->env = cpu_init("pxa255");
2259 if (!s->env) {
2260 fprintf(stderr, "Unable to find CPU definition\n");
2261 exit(1);
2262 }
2263 s->reset = qemu_allocate_irqs(pxa2xx_reset, s, 1)[0];
2264
2265 /* SDRAM & Internal Memory Storage */
2266 cpu_register_physical_memory(PXA2XX_SDRAM_BASE, sdram_size,
2267 qemu_ram_alloc(NULL, "pxa255.sdram",
2268 sdram_size) | IO_MEM_RAM);
2269 cpu_register_physical_memory(PXA2XX_INTERNAL_BASE, PXA2XX_INTERNAL_SIZE,
2270 qemu_ram_alloc(NULL, "pxa255.internal",
2271 PXA2XX_INTERNAL_SIZE) | IO_MEM_RAM);
2272
2273 s->pic = pxa2xx_pic_init(0x40d00000, s->env);
2274
2275 s->dma = pxa255_dma_init(0x40000000,
2276 qdev_get_gpio_in(s->pic, PXA2XX_PIC_DMA));
2277
2278 sysbus_create_varargs("pxa25x-timer", 0x40a00000,
2279 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 0),
2280 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 1),
2281 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 2),
2282 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 3),
2283 NULL);
2284
2285 s->gpio = pxa2xx_gpio_init(0x40e00000, s->env, s->pic, 85);
2286
2287 dinfo = drive_get(IF_SD, 0, 0);
2288 if (!dinfo) {
2289 fprintf(stderr, "qemu: missing SecureDigital device\n");
2290 exit(1);
2291 }
2292 s->mmc = pxa2xx_mmci_init(0x41100000, dinfo->bdrv,
2293 qdev_get_gpio_in(s->pic, PXA2XX_PIC_MMC),
2294 qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_MMCI),
2295 qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_MMCI));
2296
2297 for (i = 0; pxa255_serial[i].io_base; i ++)
2298 if (serial_hds[i]) {
2299 #ifdef TARGET_WORDS_BIGENDIAN
2300 serial_mm_init(pxa255_serial[i].io_base, 2,
2301 qdev_get_gpio_in(s->pic, pxa255_serial[i].irqn),
2302 14745600 / 16, serial_hds[i], 1, 1);
2303 #else
2304 serial_mm_init(pxa255_serial[i].io_base, 2,
2305 qdev_get_gpio_in(s->pic, pxa255_serial[i].irqn),
2306 14745600 / 16, serial_hds[i], 1, 0);
2307 #endif
2308 } else {
2309 break;
2310 }
2311 if (serial_hds[i])
2312 s->fir = pxa2xx_fir_init(0x40800000,
2313 qdev_get_gpio_in(s->pic, PXA2XX_PIC_ICP),
2314 qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_ICP),
2315 qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_ICP),
2316 serial_hds[i]);
2317
2318 s->lcd = pxa2xx_lcdc_init(0x44000000,
2319 qdev_get_gpio_in(s->pic, PXA2XX_PIC_LCD));
2320
2321 s->cm_base = 0x41300000;
2322 s->cm_regs[CCCR >> 2] = 0x02000210; /* 416.0 MHz */
2323 s->clkcfg = 0x00000009; /* Turbo mode active */
2324 iomemtype = cpu_register_io_memory(pxa2xx_cm_readfn,
2325 pxa2xx_cm_writefn, s, DEVICE_NATIVE_ENDIAN);
2326 cpu_register_physical_memory(s->cm_base, 0x1000, iomemtype);
2327 register_savevm(NULL, "pxa2xx_cm", 0, 0, pxa2xx_cm_save, pxa2xx_cm_load, s);
2328
2329 cpu_arm_set_cp_io(s->env, 14, pxa2xx_cp14_read, pxa2xx_cp14_write, s);
2330
2331 s->mm_base = 0x48000000;
2332 s->mm_regs[MDMRS >> 2] = 0x00020002;
2333 s->mm_regs[MDREFR >> 2] = 0x03ca4000;
2334 s->mm_regs[MECR >> 2] = 0x00000001; /* Two PC Card sockets */
2335 iomemtype = cpu_register_io_memory(pxa2xx_mm_readfn,
2336 pxa2xx_mm_writefn, s, DEVICE_NATIVE_ENDIAN);
2337 cpu_register_physical_memory(s->mm_base, 0x1000, iomemtype);
2338 register_savevm(NULL, "pxa2xx_mm", 0, 0, pxa2xx_mm_save, pxa2xx_mm_load, s);
2339
2340 s->pm_base = 0x40f00000;
2341 iomemtype = cpu_register_io_memory(pxa2xx_pm_readfn,
2342 pxa2xx_pm_writefn, s, DEVICE_NATIVE_ENDIAN);
2343 cpu_register_physical_memory(s->pm_base, 0x100, iomemtype);
2344 register_savevm(NULL, "pxa2xx_pm", 0, 0, pxa2xx_pm_save, pxa2xx_pm_load, s);
2345
2346 for (i = 0; pxa255_ssp[i].io_base; i ++);
2347 s->ssp = (SSIBus **)qemu_mallocz(sizeof(SSIBus *) * i);
2348 for (i = 0; pxa255_ssp[i].io_base; i ++) {
2349 DeviceState *dev;
2350 dev = sysbus_create_simple("pxa2xx-ssp", pxa255_ssp[i].io_base,
2351 qdev_get_gpio_in(s->pic, pxa255_ssp[i].irqn));
2352 s->ssp[i] = (SSIBus *)qdev_get_child_bus(dev, "ssi");
2353 }
2354
2355 if (usb_enabled) {
2356 sysbus_create_simple("sysbus-ohci", 0x4c000000,
2357 qdev_get_gpio_in(s->pic, PXA2XX_PIC_USBH1));
2358 }
2359
2360 s->pcmcia[0] = pxa2xx_pcmcia_init(0x20000000);
2361 s->pcmcia[1] = pxa2xx_pcmcia_init(0x30000000);
2362
2363 sysbus_create_simple("pxa2xx_rtc", 0x40900000,
2364 qdev_get_gpio_in(s->pic, PXA2XX_PIC_RTCALARM));
2365
2366 s->i2c[0] = pxa2xx_i2c_init(0x40301600,
2367 qdev_get_gpio_in(s->pic, PXA2XX_PIC_I2C), 0xffff);
2368 s->i2c[1] = pxa2xx_i2c_init(0x40f00100,
2369 qdev_get_gpio_in(s->pic, PXA2XX_PIC_PWRI2C), 0xff);
2370
2371 s->i2s = pxa2xx_i2s_init(0x40400000,
2372 qdev_get_gpio_in(s->pic, PXA2XX_PIC_I2S),
2373 qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_I2S),
2374 qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_I2S));
2375
2376 /* GPIO1 resets the processor */
2377 /* The handler can be overridden by board-specific code */
2378 qdev_connect_gpio_out(s->gpio, 1, s->reset);
2379 return s;
2380 }
2381
2382 static void pxa2xx_register_devices(void)
2383 {
2384 i2c_register_slave(&pxa2xx_i2c_slave_info);
2385 sysbus_register_dev("pxa2xx-ssp", sizeof(PXA2xxSSPState), pxa2xx_ssp_init);
2386 sysbus_register_withprop(&pxa2xx_i2c_info);
2387 sysbus_register_withprop(&pxa2xx_rtc_sysbus_info);
2388 }
2389
2390 device_init(pxa2xx_register_devices)
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