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cirrus_vga: rename cirrus_hook_read_sr() cirrus_vga_read_sr()
[qemu.git] / hw / nseries.c
blobe9b68a7f105774e89c770ed499cb7b4d3037ebcd
1 /*
2 * Nokia N-series internet tablets.
3 *
4 * Copyright (C) 2007 Nokia Corporation
5 * Written by Andrzej Zaborowski <andrew@openedhand.com>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 or
10 * (at your option) version 3 of the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "qemu-common.h"
22 #include "sysemu.h"
23 #include "omap.h"
24 #include "arm-misc.h"
25 #include "irq.h"
26 #include "console.h"
27 #include "boards.h"
28 #include "i2c.h"
29 #include "devices.h"
30 #include "flash.h"
31 #include "hw.h"
32 #include "bt.h"
33
34 /* Nokia N8x0 support */
35 struct n800_s {
36 struct omap_mpu_state_s *cpu;
37
38 struct rfbi_chip_s blizzard;
39 struct {
40 void *opaque;
41 uint32_t (*txrx)(void *opaque, uint32_t value, int len);
42 uWireSlave *chip;
43 } ts;
44 i2c_bus *i2c;
45
46 int keymap[0x80];
47 i2c_slave *kbd;
48
49 TUSBState *usb;
50 void *retu;
51 void *tahvo;
52 void *nand;
53 };
54
55 /* GPIO pins */
56 #define N8X0_TUSB_ENABLE_GPIO 0
57 #define N800_MMC2_WP_GPIO 8
58 #define N800_UNKNOWN_GPIO0 9 /* out */
59 #define N810_MMC2_VIOSD_GPIO 9
60 #define N810_HEADSET_AMP_GPIO 10
61 #define N800_CAM_TURN_GPIO 12
62 #define N810_GPS_RESET_GPIO 12
63 #define N800_BLIZZARD_POWERDOWN_GPIO 15
64 #define N800_MMC1_WP_GPIO 23
65 #define N810_MMC2_VSD_GPIO 23
66 #define N8X0_ONENAND_GPIO 26
67 #define N810_BLIZZARD_RESET_GPIO 30
68 #define N800_UNKNOWN_GPIO2 53 /* out */
69 #define N8X0_TUSB_INT_GPIO 58
70 #define N8X0_BT_WKUP_GPIO 61
71 #define N8X0_STI_GPIO 62
72 #define N8X0_CBUS_SEL_GPIO 64
73 #define N8X0_CBUS_DAT_GPIO 65
74 #define N8X0_CBUS_CLK_GPIO 66
75 #define N8X0_WLAN_IRQ_GPIO 87
76 #define N8X0_BT_RESET_GPIO 92
77 #define N8X0_TEA5761_CS_GPIO 93
78 #define N800_UNKNOWN_GPIO 94
79 #define N810_TSC_RESET_GPIO 94
80 #define N800_CAM_ACT_GPIO 95
81 #define N810_GPS_WAKEUP_GPIO 95
82 #define N8X0_MMC_CS_GPIO 96
83 #define N8X0_WLAN_PWR_GPIO 97
84 #define N8X0_BT_HOST_WKUP_GPIO 98
85 #define N810_SPEAKER_AMP_GPIO 101
86 #define N810_KB_LOCK_GPIO 102
87 #define N800_TSC_TS_GPIO 103
88 #define N810_TSC_TS_GPIO 106
89 #define N8X0_HEADPHONE_GPIO 107
90 #define N8X0_RETU_GPIO 108
91 #define N800_TSC_KP_IRQ_GPIO 109
92 #define N810_KEYBOARD_GPIO 109
93 #define N800_BAT_COVER_GPIO 110
94 #define N810_SLIDE_GPIO 110
95 #define N8X0_TAHVO_GPIO 111
96 #define N800_UNKNOWN_GPIO4 112 /* out */
97 #define N810_SLEEPX_LED_GPIO 112
98 #define N800_TSC_RESET_GPIO 118 /* ? */
99 #define N810_AIC33_RESET_GPIO 118
100 #define N800_TSC_UNKNOWN_GPIO 119 /* out */
101 #define N8X0_TMP105_GPIO 125
102
103 /* Config */
104 #define BT_UART 0
105 #define XLDR_LL_UART 1
106
107 /* Addresses on the I2C bus 0 */
108 #define N810_TLV320AIC33_ADDR 0x18 /* Audio CODEC */
109 #define N8X0_TCM825x_ADDR 0x29 /* Camera */
110 #define N810_LP5521_ADDR 0x32 /* LEDs */
111 #define N810_TSL2563_ADDR 0x3d /* Light sensor */
112 #define N810_LM8323_ADDR 0x45 /* Keyboard */
113 /* Addresses on the I2C bus 1 */
114 #define N8X0_TMP105_ADDR 0x48 /* Temperature sensor */
115 #define N8X0_MENELAUS_ADDR 0x72 /* Power management */
116
117 /* Chipselects on GPMC NOR interface */
118 #define N8X0_ONENAND_CS 0
119 #define N8X0_USB_ASYNC_CS 1
120 #define N8X0_USB_SYNC_CS 4
121
122 #define N8X0_BD_ADDR 0x00, 0x1a, 0x89, 0x9e, 0x3e, 0x81
123
124 static void n800_mmc_cs_cb(void *opaque, int line, int level)
125 {
126 /* TODO: this seems to actually be connected to the menelaus, to
127 * which also both MMC slots connect. */
128 omap_mmc_enable((struct omap_mmc_s *) opaque, !level);
129
130 printf("%s: MMC slot %i active\n", __FUNCTION__, level + 1);
131 }
132
133 static void n8x0_gpio_setup(struct n800_s *s)
134 {
135 qemu_irq *mmc_cs = qemu_allocate_irqs(n800_mmc_cs_cb, s->cpu->mmc, 1);
136 omap2_gpio_out_set(s->cpu->gpif, N8X0_MMC_CS_GPIO, mmc_cs[0]);
137
138 qemu_irq_lower(omap2_gpio_in_get(s->cpu->gpif, N800_BAT_COVER_GPIO)[0]);
139 }
140
141 #define MAEMO_CAL_HEADER(...) \
142 'C', 'o', 'n', 'F', 0x02, 0x00, 0x04, 0x00, \
143 __VA_ARGS__, \
144 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
145
146 static const uint8_t n8x0_cal_wlan_mac[] = {
147 MAEMO_CAL_HEADER('w', 'l', 'a', 'n', '-', 'm', 'a', 'c')
148 0x1c, 0x00, 0x00, 0x00, 0x47, 0xd6, 0x69, 0xb3,
149 0x30, 0x08, 0xa0, 0x83, 0x00, 0x00, 0x00, 0x00,
150 0x00, 0x00, 0x00, 0x00, 0x1a, 0x00, 0x00, 0x00,
151 0x89, 0x00, 0x00, 0x00, 0x9e, 0x00, 0x00, 0x00,
152 0x5d, 0x00, 0x00, 0x00, 0xc1, 0x00, 0x00, 0x00,
153 };
154
155 static const uint8_t n8x0_cal_bt_id[] = {
156 MAEMO_CAL_HEADER('b', 't', '-', 'i', 'd', 0, 0, 0)
157 0x0a, 0x00, 0x00, 0x00, 0xa3, 0x4b, 0xf6, 0x96,
158 0xa8, 0xeb, 0xb2, 0x41, 0x00, 0x00, 0x00, 0x00,
159 N8X0_BD_ADDR,
160 };
161
162 static void n8x0_nand_setup(struct n800_s *s)
163 {
164 char *otp_region;
165
166 /* Either ec40xx or ec48xx are OK for the ID */
167 omap_gpmc_attach(s->cpu->gpmc, N8X0_ONENAND_CS, 0, onenand_base_update,
168 onenand_base_unmap,
169 (s->nand = onenand_init(0xec4800, 1,
170 omap2_gpio_in_get(s->cpu->gpif,
171 N8X0_ONENAND_GPIO)[0])));
172 otp_region = onenand_raw_otp(s->nand);
173
174 memcpy(otp_region + 0x000, n8x0_cal_wlan_mac, sizeof(n8x0_cal_wlan_mac));
175 memcpy(otp_region + 0x800, n8x0_cal_bt_id, sizeof(n8x0_cal_bt_id));
176 /* XXX: in theory should also update the OOB for both pages */
177 }
178
179 static void n8x0_i2c_setup(struct n800_s *s)
180 {
181 DeviceState *dev;
182 qemu_irq tmp_irq = omap2_gpio_in_get(s->cpu->gpif, N8X0_TMP105_GPIO)[0];
183
184 /* Attach the CPU on one end of our I2C bus. */
185 s->i2c = omap_i2c_bus(s->cpu->i2c[0]);
186
187 /* Attach a menelaus PM chip */
188 dev = i2c_create_slave(s->i2c, "twl92230", N8X0_MENELAUS_ADDR);
189 qdev_connect_gpio_out(dev, 3, s->cpu->irq[0][OMAP_INT_24XX_SYS_NIRQ]);
190
191 /* Attach a TMP105 PM chip (A0 wired to ground) */
192 dev = i2c_create_slave(s->i2c, "tmp105", N8X0_TMP105_ADDR);
193 qdev_connect_gpio_out(dev, 0, tmp_irq);
194 }
195
196 /* Touchscreen and keypad controller */
197 static MouseTransformInfo n800_pointercal = {
198 .x = 800,
199 .y = 480,
200 .a = { 14560, -68, -3455208, -39, -9621, 35152972, 65536 },
201 };
202
203 static MouseTransformInfo n810_pointercal = {
204 .x = 800,
205 .y = 480,
206 .a = { 15041, 148, -4731056, 171, -10238, 35933380, 65536 },
207 };
208
209 #define RETU_KEYCODE 61 /* F3 */
210
211 static void n800_key_event(void *opaque, int keycode)
212 {
213 struct n800_s *s = (struct n800_s *) opaque;
214 int code = s->keymap[keycode & 0x7f];
215
216 if (code == -1) {
217 if ((keycode & 0x7f) == RETU_KEYCODE)
218 retu_key_event(s->retu, !(keycode & 0x80));
219 return;
220 }
221
222 tsc210x_key_event(s->ts.chip, code, !(keycode & 0x80));
223 }
224
225 static const int n800_keys[16] = {
226 -1,
227 72, /* Up */
228 63, /* Home (F5) */
229 -1,
230 75, /* Left */
231 28, /* Enter */
232 77, /* Right */
233 -1,
234 1, /* Cycle (ESC) */
235 80, /* Down */
236 62, /* Menu (F4) */
237 -1,
238 66, /* Zoom- (F8) */
239 64, /* FullScreen (F6) */
240 65, /* Zoom+ (F7) */
241 -1,
242 };
243
244 static void n800_tsc_kbd_setup(struct n800_s *s)
245 {
246 int i;
247
248 /* XXX: are the three pins inverted inside the chip between the
249 * tsc and the cpu (N4111)? */
250 qemu_irq penirq = 0; /* NC */
251 qemu_irq kbirq = omap2_gpio_in_get(s->cpu->gpif, N800_TSC_KP_IRQ_GPIO)[0];
252 qemu_irq dav = omap2_gpio_in_get(s->cpu->gpif, N800_TSC_TS_GPIO)[0];
253
254 s->ts.chip = tsc2301_init(penirq, kbirq, dav);
255 s->ts.opaque = s->ts.chip->opaque;
256 s->ts.txrx = tsc210x_txrx;
257
258 for (i = 0; i < 0x80; i ++)
259 s->keymap[i] = -1;
260 for (i = 0; i < 0x10; i ++)
261 if (n800_keys[i] >= 0)
262 s->keymap[n800_keys[i]] = i;
263
264 qemu_add_kbd_event_handler(n800_key_event, s);
265
266 tsc210x_set_transform(s->ts.chip, &n800_pointercal);
267 }
268
269 static void n810_tsc_setup(struct n800_s *s)
270 {
271 qemu_irq pintdav = omap2_gpio_in_get(s->cpu->gpif, N810_TSC_TS_GPIO)[0];
272
273 s->ts.opaque = tsc2005_init(pintdav);
274 s->ts.txrx = tsc2005_txrx;
275
276 tsc2005_set_transform(s->ts.opaque, &n810_pointercal);
277 }
278
279 /* N810 Keyboard controller */
280 static void n810_key_event(void *opaque, int keycode)
281 {
282 struct n800_s *s = (struct n800_s *) opaque;
283 int code = s->keymap[keycode & 0x7f];
284
285 if (code == -1) {
286 if ((keycode & 0x7f) == RETU_KEYCODE)
287 retu_key_event(s->retu, !(keycode & 0x80));
288 return;
289 }
290
291 lm832x_key_event(s->kbd, code, !(keycode & 0x80));
292 }
293
294 #define M 0
295
296 static int n810_keys[0x80] = {
297 [0x01] = 16, /* Q */
298 [0x02] = 37, /* K */
299 [0x03] = 24, /* O */
300 [0x04] = 25, /* P */
301 [0x05] = 14, /* Backspace */
302 [0x06] = 30, /* A */
303 [0x07] = 31, /* S */
304 [0x08] = 32, /* D */
305 [0x09] = 33, /* F */
306 [0x0a] = 34, /* G */
307 [0x0b] = 35, /* H */
308 [0x0c] = 36, /* J */
309
310 [0x11] = 17, /* W */
311 [0x12] = 62, /* Menu (F4) */
312 [0x13] = 38, /* L */
313 [0x14] = 40, /* ' (Apostrophe) */
314 [0x16] = 44, /* Z */
315 [0x17] = 45, /* X */
316 [0x18] = 46, /* C */
317 [0x19] = 47, /* V */
318 [0x1a] = 48, /* B */
319 [0x1b] = 49, /* N */
320 [0x1c] = 42, /* Shift (Left shift) */
321 [0x1f] = 65, /* Zoom+ (F7) */
322
323 [0x21] = 18, /* E */
324 [0x22] = 39, /* ; (Semicolon) */
325 [0x23] = 12, /* - (Minus) */
326 [0x24] = 13, /* = (Equal) */
327 [0x2b] = 56, /* Fn (Left Alt) */
328 [0x2c] = 50, /* M */
329 [0x2f] = 66, /* Zoom- (F8) */
330
331 [0x31] = 19, /* R */
332 [0x32] = 29 | M, /* Right Ctrl */
333 [0x34] = 57, /* Space */
334 [0x35] = 51, /* , (Comma) */
335 [0x37] = 72 | M, /* Up */
336 [0x3c] = 82 | M, /* Compose (Insert) */
337 [0x3f] = 64, /* FullScreen (F6) */
338
339 [0x41] = 20, /* T */
340 [0x44] = 52, /* . (Dot) */
341 [0x46] = 77 | M, /* Right */
342 [0x4f] = 63, /* Home (F5) */
343 [0x51] = 21, /* Y */
344 [0x53] = 80 | M, /* Down */
345 [0x55] = 28, /* Enter */
346 [0x5f] = 1, /* Cycle (ESC) */
347
348 [0x61] = 22, /* U */
349 [0x64] = 75 | M, /* Left */
350
351 [0x71] = 23, /* I */
352 #if 0
353 [0x75] = 28 | M, /* KP Enter (KP Enter) */
354 #else
355 [0x75] = 15, /* KP Enter (Tab) */
356 #endif
357 };
358
359 #undef M
360
361 static void n810_kbd_setup(struct n800_s *s)
362 {
363 qemu_irq kbd_irq = omap2_gpio_in_get(s->cpu->gpif, N810_KEYBOARD_GPIO)[0];
364 DeviceState *dev;
365 int i;
366
367 for (i = 0; i < 0x80; i ++)
368 s->keymap[i] = -1;
369 for (i = 0; i < 0x80; i ++)
370 if (n810_keys[i] > 0)
371 s->keymap[n810_keys[i]] = i;
372
373 qemu_add_kbd_event_handler(n810_key_event, s);
374
375 /* Attach the LM8322 keyboard to the I2C bus,
376 * should happen in n8x0_i2c_setup and s->kbd be initialised here. */
377 dev = i2c_create_slave(s->i2c, "lm8323", N810_LM8323_ADDR);
378 qdev_connect_gpio_out(dev, 0, kbd_irq);
379 }
380
381 /* LCD MIPI DBI-C controller (URAL) */
382 struct mipid_s {
383 int resp[4];
384 int param[4];
385 int p;
386 int pm;
387 int cmd;
388
389 int sleep;
390 int booster;
391 int te;
392 int selfcheck;
393 int partial;
394 int normal;
395 int vscr;
396 int invert;
397 int onoff;
398 int gamma;
399 uint32_t id;
400 };
401
402 static void mipid_reset(struct mipid_s *s)
403 {
404 if (!s->sleep)
405 fprintf(stderr, "%s: Display off\n", __FUNCTION__);
406
407 s->pm = 0;
408 s->cmd = 0;
409
410 s->sleep = 1;
411 s->booster = 0;
412 s->selfcheck =
413 (1 << 7) | /* Register loading OK. */
414 (1 << 5) | /* The chip is attached. */
415 (1 << 4); /* Display glass still in one piece. */
416 s->te = 0;
417 s->partial = 0;
418 s->normal = 1;
419 s->vscr = 0;
420 s->invert = 0;
421 s->onoff = 1;
422 s->gamma = 0;
423 }
424
425 static uint32_t mipid_txrx(void *opaque, uint32_t cmd, int len)
426 {
427 struct mipid_s *s = (struct mipid_s *) opaque;
428 uint8_t ret;
429
430 if (len > 9)
431 hw_error("%s: FIXME: bad SPI word width %i\n", __FUNCTION__, len);
432
433 if (s->p >= ARRAY_SIZE(s->resp))
434 ret = 0;
435 else
436 ret = s->resp[s->p ++];
437 if (s->pm --> 0)
438 s->param[s->pm] = cmd;
439 else
440 s->cmd = cmd;
441
442 switch (s->cmd) {
443 case 0x00: /* NOP */
444 break;
445
446 case 0x01: /* SWRESET */
447 mipid_reset(s);
448 break;
449
450 case 0x02: /* BSTROFF */
451 s->booster = 0;
452 break;
453 case 0x03: /* BSTRON */
454 s->booster = 1;
455 break;
456
457 case 0x04: /* RDDID */
458 s->p = 0;
459 s->resp[0] = (s->id >> 16) & 0xff;
460 s->resp[1] = (s->id >> 8) & 0xff;
461 s->resp[2] = (s->id >> 0) & 0xff;
462 break;
463
464 case 0x06: /* RD_RED */
465 case 0x07: /* RD_GREEN */
466 /* XXX the bootloader sometimes issues RD_BLUE meaning RDDID so
467 * for the bootloader one needs to change this. */
468 case 0x08: /* RD_BLUE */
469 s->p = 0;
470 /* TODO: return first pixel components */
471 s->resp[0] = 0x01;
472 break;
473
474 case 0x09: /* RDDST */
475 s->p = 0;
476 s->resp[0] = s->booster << 7;
477 s->resp[1] = (5 << 4) | (s->partial << 2) |
478 (s->sleep << 1) | s->normal;
479 s->resp[2] = (s->vscr << 7) | (s->invert << 5) |
480 (s->onoff << 2) | (s->te << 1) | (s->gamma >> 2);
481 s->resp[3] = s->gamma << 6;
482 break;
483
484 case 0x0a: /* RDDPM */
485 s->p = 0;
486 s->resp[0] = (s->onoff << 2) | (s->normal << 3) | (s->sleep << 4) |
487 (s->partial << 5) | (s->sleep << 6) | (s->booster << 7);
488 break;
489 case 0x0b: /* RDDMADCTR */
490 s->p = 0;
491 s->resp[0] = 0;
492 break;
493 case 0x0c: /* RDDCOLMOD */
494 s->p = 0;
495 s->resp[0] = 5; /* 65K colours */
496 break;
497 case 0x0d: /* RDDIM */
498 s->p = 0;
499 s->resp[0] = (s->invert << 5) | (s->vscr << 7) | s->gamma;
500 break;
501 case 0x0e: /* RDDSM */
502 s->p = 0;
503 s->resp[0] = s->te << 7;
504 break;
505 case 0x0f: /* RDDSDR */
506 s->p = 0;
507 s->resp[0] = s->selfcheck;
508 break;
509
510 case 0x10: /* SLPIN */
511 s->sleep = 1;
512 break;
513 case 0x11: /* SLPOUT */
514 s->sleep = 0;
515 s->selfcheck ^= 1 << 6; /* POFF self-diagnosis Ok */
516 break;
517
518 case 0x12: /* PTLON */
519 s->partial = 1;
520 s->normal = 0;
521 s->vscr = 0;
522 break;
523 case 0x13: /* NORON */
524 s->partial = 0;
525 s->normal = 1;
526 s->vscr = 0;
527 break;
528
529 case 0x20: /* INVOFF */
530 s->invert = 0;
531 break;
532 case 0x21: /* INVON */
533 s->invert = 1;
534 break;
535
536 case 0x22: /* APOFF */
537 case 0x23: /* APON */
538 goto bad_cmd;
539
540 case 0x25: /* WRCNTR */
541 if (s->pm < 0)
542 s->pm = 1;
543 goto bad_cmd;
544
545 case 0x26: /* GAMSET */
546 if (!s->pm)
547 s->gamma = ffs(s->param[0] & 0xf) - 1;
548 else if (s->pm < 0)
549 s->pm = 1;
550 break;
551
552 case 0x28: /* DISPOFF */
553 s->onoff = 0;
554 fprintf(stderr, "%s: Display off\n", __FUNCTION__);
555 break;
556 case 0x29: /* DISPON */
557 s->onoff = 1;
558 fprintf(stderr, "%s: Display on\n", __FUNCTION__);
559 break;
560
561 case 0x2a: /* CASET */
562 case 0x2b: /* RASET */
563 case 0x2c: /* RAMWR */
564 case 0x2d: /* RGBSET */
565 case 0x2e: /* RAMRD */
566 case 0x30: /* PTLAR */
567 case 0x33: /* SCRLAR */
568 goto bad_cmd;
569
570 case 0x34: /* TEOFF */
571 s->te = 0;
572 break;
573 case 0x35: /* TEON */
574 if (!s->pm)
575 s->te = 1;
576 else if (s->pm < 0)
577 s->pm = 1;
578 break;
579
580 case 0x36: /* MADCTR */
581 goto bad_cmd;
582
583 case 0x37: /* VSCSAD */
584 s->partial = 0;
585 s->normal = 0;
586 s->vscr = 1;
587 break;
588
589 case 0x38: /* IDMOFF */
590 case 0x39: /* IDMON */
591 case 0x3a: /* COLMOD */
592 goto bad_cmd;
593
594 case 0xb0: /* CLKINT / DISCTL */
595 case 0xb1: /* CLKEXT */
596 if (s->pm < 0)
597 s->pm = 2;
598 break;
599
600 case 0xb4: /* FRMSEL */
601 break;
602
603 case 0xb5: /* FRM8SEL */
604 case 0xb6: /* TMPRNG / INIESC */
605 case 0xb7: /* TMPHIS / NOP2 */
606 case 0xb8: /* TMPREAD / MADCTL */
607 case 0xba: /* DISTCTR */
608 case 0xbb: /* EPVOL */
609 goto bad_cmd;
610
611 case 0xbd: /* Unknown */
612 s->p = 0;
613 s->resp[0] = 0;
614 s->resp[1] = 1;
615 break;
616
617 case 0xc2: /* IFMOD */
618 if (s->pm < 0)
619 s->pm = 2;
620 break;
621
622 case 0xc6: /* PWRCTL */
623 case 0xc7: /* PPWRCTL */
624 case 0xd0: /* EPWROUT */
625 case 0xd1: /* EPWRIN */
626 case 0xd4: /* RDEV */
627 case 0xd5: /* RDRR */
628 goto bad_cmd;
629
630 case 0xda: /* RDID1 */
631 s->p = 0;
632 s->resp[0] = (s->id >> 16) & 0xff;
633 break;
634 case 0xdb: /* RDID2 */
635 s->p = 0;
636 s->resp[0] = (s->id >> 8) & 0xff;
637 break;
638 case 0xdc: /* RDID3 */
639 s->p = 0;
640 s->resp[0] = (s->id >> 0) & 0xff;
641 break;
642
643 default:
644 bad_cmd:
645 fprintf(stderr, "%s: unknown command %02x\n", __FUNCTION__, s->cmd);
646 break;
647 }
648
649 return ret;
650 }
651
652 static void *mipid_init(void)
653 {
654 struct mipid_s *s = (struct mipid_s *) qemu_mallocz(sizeof(*s));
655
656 s->id = 0x838f03;
657 mipid_reset(s);
658
659 return s;
660 }
661
662 static void n8x0_spi_setup(struct n800_s *s)
663 {
664 void *tsc = s->ts.opaque;
665 void *mipid = mipid_init();
666
667 omap_mcspi_attach(s->cpu->mcspi[0], s->ts.txrx, tsc, 0);
668 omap_mcspi_attach(s->cpu->mcspi[0], mipid_txrx, mipid, 1);
669 }
670
671 /* This task is normally performed by the bootloader. If we're loading
672 * a kernel directly, we need to enable the Blizzard ourselves. */
673 static void n800_dss_init(struct rfbi_chip_s *chip)
674 {
675 uint8_t *fb_blank;
676
677 chip->write(chip->opaque, 0, 0x2a); /* LCD Width register */
678 chip->write(chip->opaque, 1, 0x64);
679 chip->write(chip->opaque, 0, 0x2c); /* LCD HNDP register */
680 chip->write(chip->opaque, 1, 0x1e);
681 chip->write(chip->opaque, 0, 0x2e); /* LCD Height 0 register */
682 chip->write(chip->opaque, 1, 0xe0);
683 chip->write(chip->opaque, 0, 0x30); /* LCD Height 1 register */
684 chip->write(chip->opaque, 1, 0x01);
685 chip->write(chip->opaque, 0, 0x32); /* LCD VNDP register */
686 chip->write(chip->opaque, 1, 0x06);
687 chip->write(chip->opaque, 0, 0x68); /* Display Mode register */
688 chip->write(chip->opaque, 1, 1); /* Enable bit */
689
690 chip->write(chip->opaque, 0, 0x6c);
691 chip->write(chip->opaque, 1, 0x00); /* Input X Start Position */
692 chip->write(chip->opaque, 1, 0x00); /* Input X Start Position */
693 chip->write(chip->opaque, 1, 0x00); /* Input Y Start Position */
694 chip->write(chip->opaque, 1, 0x00); /* Input Y Start Position */
695 chip->write(chip->opaque, 1, 0x1f); /* Input X End Position */
696 chip->write(chip->opaque, 1, 0x03); /* Input X End Position */
697 chip->write(chip->opaque, 1, 0xdf); /* Input Y End Position */
698 chip->write(chip->opaque, 1, 0x01); /* Input Y End Position */
699 chip->write(chip->opaque, 1, 0x00); /* Output X Start Position */
700 chip->write(chip->opaque, 1, 0x00); /* Output X Start Position */
701 chip->write(chip->opaque, 1, 0x00); /* Output Y Start Position */
702 chip->write(chip->opaque, 1, 0x00); /* Output Y Start Position */
703 chip->write(chip->opaque, 1, 0x1f); /* Output X End Position */
704 chip->write(chip->opaque, 1, 0x03); /* Output X End Position */
705 chip->write(chip->opaque, 1, 0xdf); /* Output Y End Position */
706 chip->write(chip->opaque, 1, 0x01); /* Output Y End Position */
707 chip->write(chip->opaque, 1, 0x01); /* Input Data Format */
708 chip->write(chip->opaque, 1, 0x01); /* Data Source Select */
709
710 fb_blank = memset(qemu_malloc(800 * 480 * 2), 0xff, 800 * 480 * 2);
711 /* Display Memory Data Port */
712 chip->block(chip->opaque, 1, fb_blank, 800 * 480 * 2, 800);
713 free(fb_blank);
714 }
715
716 static void n8x0_dss_setup(struct n800_s *s)
717 {
718 s->blizzard.opaque = s1d13745_init(0);
719 s->blizzard.block = s1d13745_write_block;
720 s->blizzard.write = s1d13745_write;
721 s->blizzard.read = s1d13745_read;
722
723 omap_rfbi_attach(s->cpu->dss, 0, &s->blizzard);
724 }
725
726 static void n8x0_cbus_setup(struct n800_s *s)
727 {
728 qemu_irq dat_out = omap2_gpio_in_get(s->cpu->gpif, N8X0_CBUS_DAT_GPIO)[0];
729 qemu_irq retu_irq = omap2_gpio_in_get(s->cpu->gpif, N8X0_RETU_GPIO)[0];
730 qemu_irq tahvo_irq = omap2_gpio_in_get(s->cpu->gpif, N8X0_TAHVO_GPIO)[0];
731
732 CBus *cbus = cbus_init(dat_out);
733
734 omap2_gpio_out_set(s->cpu->gpif, N8X0_CBUS_CLK_GPIO, cbus->clk);
735 omap2_gpio_out_set(s->cpu->gpif, N8X0_CBUS_DAT_GPIO, cbus->dat);
736 omap2_gpio_out_set(s->cpu->gpif, N8X0_CBUS_SEL_GPIO, cbus->sel);
737
738 cbus_attach(cbus, s->retu = retu_init(retu_irq, 1));
739 cbus_attach(cbus, s->tahvo = tahvo_init(tahvo_irq, 1));
740 }
741
742 static void n8x0_uart_setup(struct n800_s *s)
743 {
744 CharDriverState *radio = uart_hci_init(
745 omap2_gpio_in_get(s->cpu->gpif,
746 N8X0_BT_HOST_WKUP_GPIO)[0]);
747
748 omap2_gpio_out_set(s->cpu->gpif, N8X0_BT_RESET_GPIO,
749 csrhci_pins_get(radio)[csrhci_pin_reset]);
750 omap2_gpio_out_set(s->cpu->gpif, N8X0_BT_WKUP_GPIO,
751 csrhci_pins_get(radio)[csrhci_pin_wakeup]);
752
753 omap_uart_attach(s->cpu->uart[BT_UART], radio);
754 }
755
756 static void n8x0_usb_power_cb(void *opaque, int line, int level)
757 {
758 struct n800_s *s = opaque;
759
760 tusb6010_power(s->usb, level);
761 }
762
763 static void n8x0_usb_setup(struct n800_s *s)
764 {
765 qemu_irq tusb_irq = omap2_gpio_in_get(s->cpu->gpif, N8X0_TUSB_INT_GPIO)[0];
766 qemu_irq tusb_pwr = qemu_allocate_irqs(n8x0_usb_power_cb, s, 1)[0];
767 TUSBState *tusb = tusb6010_init(tusb_irq);
768
769 /* Using the NOR interface */
770 omap_gpmc_attach(s->cpu->gpmc, N8X0_USB_ASYNC_CS,
771 tusb6010_async_io(tusb), 0, 0, tusb);
772 omap_gpmc_attach(s->cpu->gpmc, N8X0_USB_SYNC_CS,
773 tusb6010_sync_io(tusb), 0, 0, tusb);
774
775 s->usb = tusb;
776 omap2_gpio_out_set(s->cpu->gpif, N8X0_TUSB_ENABLE_GPIO, tusb_pwr);
777 }
778
779 /* Setup done before the main bootloader starts by some early setup code
780 * - used when we want to run the main bootloader in emulation. This
781 * isn't documented. */
782 static uint32_t n800_pinout[104] = {
783 0x080f00d8, 0x00d40808, 0x03080808, 0x080800d0,
784 0x00dc0808, 0x0b0f0f00, 0x080800b4, 0x00c00808,
785 0x08080808, 0x180800c4, 0x00b80000, 0x08080808,
786 0x080800bc, 0x00cc0808, 0x08081818, 0x18180128,
787 0x01241800, 0x18181818, 0x000000f0, 0x01300000,
788 0x00001b0b, 0x1b0f0138, 0x00e0181b, 0x1b031b0b,
789 0x180f0078, 0x00740018, 0x0f0f0f1a, 0x00000080,
790 0x007c0000, 0x00000000, 0x00000088, 0x00840000,
791 0x00000000, 0x00000094, 0x00980300, 0x0f180003,
792 0x0000008c, 0x00900f0f, 0x0f0f1b00, 0x0f00009c,
793 0x01140000, 0x1b1b0f18, 0x0818013c, 0x01400008,
794 0x00001818, 0x000b0110, 0x010c1800, 0x0b030b0f,
795 0x181800f4, 0x00f81818, 0x00000018, 0x000000fc,
796 0x00401808, 0x00000000, 0x0f1b0030, 0x003c0008,
797 0x00000000, 0x00000038, 0x00340000, 0x00000000,
798 0x1a080070, 0x00641a1a, 0x08080808, 0x08080060,
799 0x005c0808, 0x08080808, 0x08080058, 0x00540808,
800 0x08080808, 0x0808006c, 0x00680808, 0x08080808,
801 0x000000a8, 0x00b00000, 0x08080808, 0x000000a0,
802 0x00a40000, 0x00000000, 0x08ff0050, 0x004c0808,
803 0xffffffff, 0xffff0048, 0x0044ffff, 0xffffffff,
804 0x000000ac, 0x01040800, 0x08080b0f, 0x18180100,
805 0x01081818, 0x0b0b1808, 0x1a0300e4, 0x012c0b1a,
806 0x02020018, 0x0b000134, 0x011c0800, 0x0b1b1b00,
807 0x0f0000c8, 0x00ec181b, 0x000f0f02, 0x00180118,
808 0x01200000, 0x0f0b1b1b, 0x0f0200e8, 0x0000020b,
809 };
810
811 static void n800_setup_nolo_tags(void *sram_base)
812 {
813 int i;
814 uint32_t *p = sram_base + 0x8000;
815 uint32_t *v = sram_base + 0xa000;
816
817 memset(p, 0, 0x3000);
818
819 strcpy((void *) (p + 0), "QEMU N800");
820
821 strcpy((void *) (p + 8), "F5");
822
823 stl_raw(p + 10, 0x04f70000);
824 strcpy((void *) (p + 9), "RX-34");
825
826 /* RAM size in MB? */
827 stl_raw(p + 12, 0x80);
828
829 /* Pointer to the list of tags */
830 stl_raw(p + 13, OMAP2_SRAM_BASE + 0x9000);
831
832 /* The NOLO tags start here */
833 p = sram_base + 0x9000;
834 #define ADD_TAG(tag, len) \
835 stw_raw((uint16_t *) p + 0, tag); \
836 stw_raw((uint16_t *) p + 1, len); p ++; \
837 stl_raw(p ++, OMAP2_SRAM_BASE | (((void *) v - sram_base) & 0xffff));
838
839 /* OMAP STI console? Pin out settings? */
840 ADD_TAG(0x6e01, 414);
841 for (i = 0; i < ARRAY_SIZE(n800_pinout); i ++)
842 stl_raw(v ++, n800_pinout[i]);
843
844 /* Kernel memsize? */
845 ADD_TAG(0x6e05, 1);
846 stl_raw(v ++, 2);
847
848 /* NOLO serial console */
849 ADD_TAG(0x6e02, 4);
850 stl_raw(v ++, XLDR_LL_UART); /* UART number (1 - 3) */
851
852 #if 0
853 /* CBUS settings (Retu/AVilma) */
854 ADD_TAG(0x6e03, 6);
855 stw_raw((uint16_t *) v + 0, 65); /* CBUS GPIO0 */
856 stw_raw((uint16_t *) v + 1, 66); /* CBUS GPIO1 */
857 stw_raw((uint16_t *) v + 2, 64); /* CBUS GPIO2 */
858 v += 2;
859 #endif
860
861 /* Nokia ASIC BB5 (Retu/Tahvo) */
862 ADD_TAG(0x6e0a, 4);
863 stw_raw((uint16_t *) v + 0, 111); /* "Retu" interrupt GPIO */
864 stw_raw((uint16_t *) v + 1, 108); /* "Tahvo" interrupt GPIO */
865 v ++;
866
867 /* LCD console? */
868 ADD_TAG(0x6e04, 4);
869 stw_raw((uint16_t *) v + 0, 30); /* ??? */
870 stw_raw((uint16_t *) v + 1, 24); /* ??? */
871 v ++;
872
873 #if 0
874 /* LCD settings */
875 ADD_TAG(0x6e06, 2);
876 stw_raw((uint16_t *) (v ++), 15); /* ??? */
877 #endif
878
879 /* I^2C (Menelaus) */
880 ADD_TAG(0x6e07, 4);
881 stl_raw(v ++, 0x00720000); /* ??? */
882
883 /* Unknown */
884 ADD_TAG(0x6e0b, 6);
885 stw_raw((uint16_t *) v + 0, 94); /* ??? */
886 stw_raw((uint16_t *) v + 1, 23); /* ??? */
887 stw_raw((uint16_t *) v + 2, 0); /* ??? */
888 v += 2;
889
890 /* OMAP gpio switch info */
891 ADD_TAG(0x6e0c, 80);
892 strcpy((void *) v, "bat_cover"); v += 3;
893 stw_raw((uint16_t *) v + 0, 110); /* GPIO num ??? */
894 stw_raw((uint16_t *) v + 1, 1); /* GPIO num ??? */
895 v += 2;
896 strcpy((void *) v, "cam_act"); v += 3;
897 stw_raw((uint16_t *) v + 0, 95); /* GPIO num ??? */
898 stw_raw((uint16_t *) v + 1, 32); /* GPIO num ??? */
899 v += 2;
900 strcpy((void *) v, "cam_turn"); v += 3;
901 stw_raw((uint16_t *) v + 0, 12); /* GPIO num ??? */
902 stw_raw((uint16_t *) v + 1, 33); /* GPIO num ??? */
903 v += 2;
904 strcpy((void *) v, "headphone"); v += 3;
905 stw_raw((uint16_t *) v + 0, 107); /* GPIO num ??? */
906 stw_raw((uint16_t *) v + 1, 17); /* GPIO num ??? */
907 v += 2;
908
909 /* Bluetooth */
910 ADD_TAG(0x6e0e, 12);
911 stl_raw(v ++, 0x5c623d01); /* ??? */
912 stl_raw(v ++, 0x00000201); /* ??? */
913 stl_raw(v ++, 0x00000000); /* ??? */
914
915 /* CX3110x WLAN settings */
916 ADD_TAG(0x6e0f, 8);
917 stl_raw(v ++, 0x00610025); /* ??? */
918 stl_raw(v ++, 0xffff0057); /* ??? */
919
920 /* MMC host settings */
921 ADD_TAG(0x6e10, 12);
922 stl_raw(v ++, 0xffff000f); /* ??? */
923 stl_raw(v ++, 0xffffffff); /* ??? */
924 stl_raw(v ++, 0x00000060); /* ??? */
925
926 /* OneNAND chip select */
927 ADD_TAG(0x6e11, 10);
928 stl_raw(v ++, 0x00000401); /* ??? */
929 stl_raw(v ++, 0x0002003a); /* ??? */
930 stl_raw(v ++, 0x00000002); /* ??? */
931
932 /* TEA5761 sensor settings */
933 ADD_TAG(0x6e12, 2);
934 stl_raw(v ++, 93); /* GPIO num ??? */
935
936 #if 0
937 /* Unknown tag */
938 ADD_TAG(6e09, 0);
939
940 /* Kernel UART / console */
941 ADD_TAG(6e12, 0);
942 #endif
943
944 /* End of the list */
945 stl_raw(p ++, 0x00000000);
946 stl_raw(p ++, 0x00000000);
947 }
948
949 /* This task is normally performed by the bootloader. If we're loading
950 * a kernel directly, we need to set up GPMC mappings ourselves. */
951 static void n800_gpmc_init(struct n800_s *s)
952 {
953 uint32_t config7 =
954 (0xf << 8) | /* MASKADDRESS */
955 (1 << 6) | /* CSVALID */
956 (4 << 0); /* BASEADDRESS */
957
958 cpu_physical_memory_write(0x6800a078, /* GPMC_CONFIG7_0 */
959 (void *) &config7, sizeof(config7));
960 }
961
962 /* Setup sequence done by the bootloader */
963 static void n8x0_boot_init(void *opaque)
964 {
965 struct n800_s *s = (struct n800_s *) opaque;
966 uint32_t buf;
967
968 /* PRCM setup */
969 #define omap_writel(addr, val) \
970 buf = (val); \
971 cpu_physical_memory_write(addr, (void *) &buf, sizeof(buf))
972
973 omap_writel(0x48008060, 0x41); /* PRCM_CLKSRC_CTRL */
974 omap_writel(0x48008070, 1); /* PRCM_CLKOUT_CTRL */
975 omap_writel(0x48008078, 0); /* PRCM_CLKEMUL_CTRL */
976 omap_writel(0x48008090, 0); /* PRCM_VOLTSETUP */
977 omap_writel(0x48008094, 0); /* PRCM_CLKSSETUP */
978 omap_writel(0x48008098, 0); /* PRCM_POLCTRL */
979 omap_writel(0x48008140, 2); /* CM_CLKSEL_MPU */
980 omap_writel(0x48008148, 0); /* CM_CLKSTCTRL_MPU */
981 omap_writel(0x48008158, 1); /* RM_RSTST_MPU */
982 omap_writel(0x480081c8, 0x15); /* PM_WKDEP_MPU */
983 omap_writel(0x480081d4, 0x1d4); /* PM_EVGENCTRL_MPU */
984 omap_writel(0x480081d8, 0); /* PM_EVEGENONTIM_MPU */
985 omap_writel(0x480081dc, 0); /* PM_EVEGENOFFTIM_MPU */
986 omap_writel(0x480081e0, 0xc); /* PM_PWSTCTRL_MPU */
987 omap_writel(0x48008200, 0x047e7ff7); /* CM_FCLKEN1_CORE */
988 omap_writel(0x48008204, 0x00000004); /* CM_FCLKEN2_CORE */
989 omap_writel(0x48008210, 0x047e7ff1); /* CM_ICLKEN1_CORE */
990 omap_writel(0x48008214, 0x00000004); /* CM_ICLKEN2_CORE */
991 omap_writel(0x4800821c, 0x00000000); /* CM_ICLKEN4_CORE */
992 omap_writel(0x48008230, 0); /* CM_AUTOIDLE1_CORE */
993 omap_writel(0x48008234, 0); /* CM_AUTOIDLE2_CORE */
994 omap_writel(0x48008238, 7); /* CM_AUTOIDLE3_CORE */
995 omap_writel(0x4800823c, 0); /* CM_AUTOIDLE4_CORE */
996 omap_writel(0x48008240, 0x04360626); /* CM_CLKSEL1_CORE */
997 omap_writel(0x48008244, 0x00000014); /* CM_CLKSEL2_CORE */
998 omap_writel(0x48008248, 0); /* CM_CLKSTCTRL_CORE */
999 omap_writel(0x48008300, 0x00000000); /* CM_FCLKEN_GFX */
1000 omap_writel(0x48008310, 0x00000000); /* CM_ICLKEN_GFX */
1001 omap_writel(0x48008340, 0x00000001); /* CM_CLKSEL_GFX */
1002 omap_writel(0x48008400, 0x00000004); /* CM_FCLKEN_WKUP */
1003 omap_writel(0x48008410, 0x00000004); /* CM_ICLKEN_WKUP */
1004 omap_writel(0x48008440, 0x00000000); /* CM_CLKSEL_WKUP */
1005 omap_writel(0x48008500, 0x000000cf); /* CM_CLKEN_PLL */
1006 omap_writel(0x48008530, 0x0000000c); /* CM_AUTOIDLE_PLL */
1007 omap_writel(0x48008540, /* CM_CLKSEL1_PLL */
1008 (0x78 << 12) | (6 << 8));
1009 omap_writel(0x48008544, 2); /* CM_CLKSEL2_PLL */
1010
1011 /* GPMC setup */
1012 n800_gpmc_init(s);
1013
1014 /* Video setup */
1015 n800_dss_init(&s->blizzard);
1016
1017 /* CPU setup */
1018 s->cpu->env->regs[15] = s->cpu->env->boot_info->loader_start;
1019 s->cpu->env->GE = 0x5;
1020
1021 /* If the machine has a slided keyboard, open it */
1022 if (s->kbd)
1023 qemu_irq_raise(omap2_gpio_in_get(s->cpu->gpif, N810_SLIDE_GPIO)[0]);
1024 }
1025
1026 #define OMAP_TAG_NOKIA_BT 0x4e01
1027 #define OMAP_TAG_WLAN_CX3110X 0x4e02
1028 #define OMAP_TAG_CBUS 0x4e03
1029 #define OMAP_TAG_EM_ASIC_BB5 0x4e04
1030
1031 static struct omap_gpiosw_info_s {
1032 const char *name;
1033 int line;
1034 int type;
1035 } n800_gpiosw_info[] = {
1036 {
1037 "bat_cover", N800_BAT_COVER_GPIO,
1038 OMAP_GPIOSW_TYPE_COVER | OMAP_GPIOSW_INVERTED,
1039 }, {
1040 "cam_act", N800_CAM_ACT_GPIO,
1041 OMAP_GPIOSW_TYPE_ACTIVITY,
1042 }, {
1043 "cam_turn", N800_CAM_TURN_GPIO,
1044 OMAP_GPIOSW_TYPE_ACTIVITY | OMAP_GPIOSW_INVERTED,
1045 }, {
1046 "headphone", N8X0_HEADPHONE_GPIO,
1047 OMAP_GPIOSW_TYPE_CONNECTION | OMAP_GPIOSW_INVERTED,
1048 },
1049 { 0 }
1050 }, n810_gpiosw_info[] = {
1051 {
1052 "gps_reset", N810_GPS_RESET_GPIO,
1053 OMAP_GPIOSW_TYPE_ACTIVITY | OMAP_GPIOSW_OUTPUT,
1054 }, {
1055 "gps_wakeup", N810_GPS_WAKEUP_GPIO,
1056 OMAP_GPIOSW_TYPE_ACTIVITY | OMAP_GPIOSW_OUTPUT,
1057 }, {
1058 "headphone", N8X0_HEADPHONE_GPIO,
1059 OMAP_GPIOSW_TYPE_CONNECTION | OMAP_GPIOSW_INVERTED,
1060 }, {
1061 "kb_lock", N810_KB_LOCK_GPIO,
1062 OMAP_GPIOSW_TYPE_COVER | OMAP_GPIOSW_INVERTED,
1063 }, {
1064 "sleepx_led", N810_SLEEPX_LED_GPIO,
1065 OMAP_GPIOSW_TYPE_ACTIVITY | OMAP_GPIOSW_INVERTED | OMAP_GPIOSW_OUTPUT,
1066 }, {
1067 "slide", N810_SLIDE_GPIO,
1068 OMAP_GPIOSW_TYPE_COVER | OMAP_GPIOSW_INVERTED,
1069 },
1070 { 0 }
1071 };
1072
1073 static struct omap_partition_info_s {
1074 uint32_t offset;
1075 uint32_t size;
1076 int mask;
1077 const char *name;
1078 } n800_part_info[] = {
1079 { 0x00000000, 0x00020000, 0x3, "bootloader" },
1080 { 0x00020000, 0x00060000, 0x0, "config" },
1081 { 0x00080000, 0x00200000, 0x0, "kernel" },
1082 { 0x00280000, 0x00200000, 0x3, "initfs" },
1083 { 0x00480000, 0x0fb80000, 0x3, "rootfs" },
1084
1085 { 0, 0, 0, 0 }
1086 }, n810_part_info[] = {
1087 { 0x00000000, 0x00020000, 0x3, "bootloader" },
1088 { 0x00020000, 0x00060000, 0x0, "config" },
1089 { 0x00080000, 0x00220000, 0x0, "kernel" },
1090 { 0x002a0000, 0x00400000, 0x0, "initfs" },
1091 { 0x006a0000, 0x0f960000, 0x0, "rootfs" },
1092
1093 { 0, 0, 0, 0 }
1094 };
1095
1096 static bdaddr_t n8x0_bd_addr = {{ N8X0_BD_ADDR }};
1097
1098 static int n8x0_atag_setup(void *p, int model)
1099 {
1100 uint8_t *b;
1101 uint16_t *w;
1102 uint32_t *l;
1103 struct omap_gpiosw_info_s *gpiosw;
1104 struct omap_partition_info_s *partition;
1105 const char *tag;
1106
1107 w = p;
1108
1109 stw_raw(w ++, OMAP_TAG_UART); /* u16 tag */
1110 stw_raw(w ++, 4); /* u16 len */
1111 stw_raw(w ++, (1 << 2) | (1 << 1) | (1 << 0)); /* uint enabled_uarts */
1112 w ++;
1113
1114 #if 0
1115 stw_raw(w ++, OMAP_TAG_SERIAL_CONSOLE); /* u16 tag */
1116 stw_raw(w ++, 4); /* u16 len */
1117 stw_raw(w ++, XLDR_LL_UART + 1); /* u8 console_uart */
1118 stw_raw(w ++, 115200); /* u32 console_speed */
1119 #endif
1120
1121 stw_raw(w ++, OMAP_TAG_LCD); /* u16 tag */
1122 stw_raw(w ++, 36); /* u16 len */
1123 strcpy((void *) w, "QEMU LCD panel"); /* char panel_name[16] */
1124 w += 8;
1125 strcpy((void *) w, "blizzard"); /* char ctrl_name[16] */
1126 w += 8;
1127 stw_raw(w ++, N810_BLIZZARD_RESET_GPIO); /* TODO: n800 s16 nreset_gpio */
1128 stw_raw(w ++, 24); /* u8 data_lines */
1129
1130 stw_raw(w ++, OMAP_TAG_CBUS); /* u16 tag */
1131 stw_raw(w ++, 8); /* u16 len */
1132 stw_raw(w ++, N8X0_CBUS_CLK_GPIO); /* s16 clk_gpio */
1133 stw_raw(w ++, N8X0_CBUS_DAT_GPIO); /* s16 dat_gpio */
1134 stw_raw(w ++, N8X0_CBUS_SEL_GPIO); /* s16 sel_gpio */
1135 w ++;
1136
1137 stw_raw(w ++, OMAP_TAG_EM_ASIC_BB5); /* u16 tag */
1138 stw_raw(w ++, 4); /* u16 len */
1139 stw_raw(w ++, N8X0_RETU_GPIO); /* s16 retu_irq_gpio */
1140 stw_raw(w ++, N8X0_TAHVO_GPIO); /* s16 tahvo_irq_gpio */
1141
1142 gpiosw = (model == 810) ? n810_gpiosw_info : n800_gpiosw_info;
1143 for (; gpiosw->name; gpiosw ++) {
1144 stw_raw(w ++, OMAP_TAG_GPIO_SWITCH); /* u16 tag */
1145 stw_raw(w ++, 20); /* u16 len */
1146 strcpy((void *) w, gpiosw->name); /* char name[12] */
1147 w += 6;
1148 stw_raw(w ++, gpiosw->line); /* u16 gpio */
1149 stw_raw(w ++, gpiosw->type);
1150 stw_raw(w ++, 0);
1151 stw_raw(w ++, 0);
1152 }
1153
1154 stw_raw(w ++, OMAP_TAG_NOKIA_BT); /* u16 tag */
1155 stw_raw(w ++, 12); /* u16 len */
1156 b = (void *) w;
1157 stb_raw(b ++, 0x01); /* u8 chip_type (CSR) */
1158 stb_raw(b ++, N8X0_BT_WKUP_GPIO); /* u8 bt_wakeup_gpio */
1159 stb_raw(b ++, N8X0_BT_HOST_WKUP_GPIO); /* u8 host_wakeup_gpio */
1160 stb_raw(b ++, N8X0_BT_RESET_GPIO); /* u8 reset_gpio */
1161 stb_raw(b ++, BT_UART + 1); /* u8 bt_uart */
1162 memcpy(b, &n8x0_bd_addr, 6); /* u8 bd_addr[6] */
1163 b += 6;
1164 stb_raw(b ++, 0x02); /* u8 bt_sysclk (38.4) */
1165 w = (void *) b;
1166
1167 stw_raw(w ++, OMAP_TAG_WLAN_CX3110X); /* u16 tag */
1168 stw_raw(w ++, 8); /* u16 len */
1169 stw_raw(w ++, 0x25); /* u8 chip_type */
1170 stw_raw(w ++, N8X0_WLAN_PWR_GPIO); /* s16 power_gpio */
1171 stw_raw(w ++, N8X0_WLAN_IRQ_GPIO); /* s16 irq_gpio */
1172 stw_raw(w ++, -1); /* s16 spi_cs_gpio */
1173
1174 stw_raw(w ++, OMAP_TAG_MMC); /* u16 tag */
1175 stw_raw(w ++, 16); /* u16 len */
1176 if (model == 810) {
1177 stw_raw(w ++, 0x23f); /* unsigned flags */
1178 stw_raw(w ++, -1); /* s16 power_pin */
1179 stw_raw(w ++, -1); /* s16 switch_pin */
1180 stw_raw(w ++, -1); /* s16 wp_pin */
1181 stw_raw(w ++, 0x240); /* unsigned flags */
1182 stw_raw(w ++, 0xc000); /* s16 power_pin */
1183 stw_raw(w ++, 0x0248); /* s16 switch_pin */
1184 stw_raw(w ++, 0xc000); /* s16 wp_pin */
1185 } else {
1186 stw_raw(w ++, 0xf); /* unsigned flags */
1187 stw_raw(w ++, -1); /* s16 power_pin */
1188 stw_raw(w ++, -1); /* s16 switch_pin */
1189 stw_raw(w ++, -1); /* s16 wp_pin */
1190 stw_raw(w ++, 0); /* unsigned flags */
1191 stw_raw(w ++, 0); /* s16 power_pin */
1192 stw_raw(w ++, 0); /* s16 switch_pin */
1193 stw_raw(w ++, 0); /* s16 wp_pin */
1194 }
1195
1196 stw_raw(w ++, OMAP_TAG_TEA5761); /* u16 tag */
1197 stw_raw(w ++, 4); /* u16 len */
1198 stw_raw(w ++, N8X0_TEA5761_CS_GPIO); /* u16 enable_gpio */
1199 w ++;
1200
1201 partition = (model == 810) ? n810_part_info : n800_part_info;
1202 for (; partition->name; partition ++) {
1203 stw_raw(w ++, OMAP_TAG_PARTITION); /* u16 tag */
1204 stw_raw(w ++, 28); /* u16 len */
1205 strcpy((void *) w, partition->name); /* char name[16] */
1206 l = (void *) (w + 8);
1207 stl_raw(l ++, partition->size); /* unsigned int size */
1208 stl_raw(l ++, partition->offset); /* unsigned int offset */
1209 stl_raw(l ++, partition->mask); /* unsigned int mask_flags */
1210 w = (void *) l;
1211 }
1212
1213 stw_raw(w ++, OMAP_TAG_BOOT_REASON); /* u16 tag */
1214 stw_raw(w ++, 12); /* u16 len */
1215 #if 0
1216 strcpy((void *) w, "por"); /* char reason_str[12] */
1217 strcpy((void *) w, "charger"); /* char reason_str[12] */
1218 strcpy((void *) w, "32wd_to"); /* char reason_str[12] */
1219 strcpy((void *) w, "sw_rst"); /* char reason_str[12] */
1220 strcpy((void *) w, "mbus"); /* char reason_str[12] */
1221 strcpy((void *) w, "unknown"); /* char reason_str[12] */
1222 strcpy((void *) w, "swdg_to"); /* char reason_str[12] */
1223 strcpy((void *) w, "sec_vio"); /* char reason_str[12] */
1224 strcpy((void *) w, "pwr_key"); /* char reason_str[12] */
1225 strcpy((void *) w, "rtc_alarm"); /* char reason_str[12] */
1226 #else
1227 strcpy((void *) w, "pwr_key"); /* char reason_str[12] */
1228 #endif
1229 w += 6;
1230
1231 tag = (model == 810) ? "RX-44" : "RX-34";
1232 stw_raw(w ++, OMAP_TAG_VERSION_STR); /* u16 tag */
1233 stw_raw(w ++, 24); /* u16 len */
1234 strcpy((void *) w, "product"); /* char component[12] */
1235 w += 6;
1236 strcpy((void *) w, tag); /* char version[12] */
1237 w += 6;
1238
1239 stw_raw(w ++, OMAP_TAG_VERSION_STR); /* u16 tag */
1240 stw_raw(w ++, 24); /* u16 len */
1241 strcpy((void *) w, "hw-build"); /* char component[12] */
1242 w += 6;
1243 strcpy((void *) w, "QEMU " QEMU_VERSION); /* char version[12] */
1244 w += 6;
1245
1246 tag = (model == 810) ? "1.1.10-qemu" : "1.1.6-qemu";
1247 stw_raw(w ++, OMAP_TAG_VERSION_STR); /* u16 tag */
1248 stw_raw(w ++, 24); /* u16 len */
1249 strcpy((void *) w, "nolo"); /* char component[12] */
1250 w += 6;
1251 strcpy((void *) w, tag); /* char version[12] */
1252 w += 6;
1253
1254 return (void *) w - p;
1255 }
1256
1257 static int n800_atag_setup(struct arm_boot_info *info, void *p)
1258 {
1259 return n8x0_atag_setup(p, 800);
1260 }
1261
1262 static int n810_atag_setup(struct arm_boot_info *info, void *p)
1263 {
1264 return n8x0_atag_setup(p, 810);
1265 }
1266
1267 static void n8x0_init(ram_addr_t ram_size, const char *boot_device,
1268 const char *kernel_filename,
1269 const char *kernel_cmdline, const char *initrd_filename,
1270 const char *cpu_model, struct arm_boot_info *binfo, int model)
1271 {
1272 struct n800_s *s = (struct n800_s *) qemu_mallocz(sizeof(*s));
1273 int sdram_size = binfo->ram_size;
1274 DisplayState *ds;
1275
1276 s->cpu = omap2420_mpu_init(sdram_size, cpu_model);
1277
1278 /* Setup peripherals
1279 *
1280 * Believed external peripherals layout in the N810:
1281 * (spi bus 1)
1282 * tsc2005
1283 * lcd_mipid
1284 * (spi bus 2)
1285 * Conexant cx3110x (WLAN)
1286 * optional: pc2400m (WiMAX)
1287 * (i2c bus 0)
1288 * TLV320AIC33 (audio codec)
1289 * TCM825x (camera by Toshiba)
1290 * lp5521 (clever LEDs)
1291 * tsl2563 (light sensor, hwmon, model 7, rev. 0)
1292 * lm8323 (keypad, manf 00, rev 04)
1293 * (i2c bus 1)
1294 * tmp105 (temperature sensor, hwmon)
1295 * menelaus (pm)
1296 * (somewhere on i2c - maybe N800-only)
1297 * tea5761 (FM tuner)
1298 * (serial 0)
1299 * GPS
1300 * (some serial port)
1301 * csr41814 (Bluetooth)
1302 */
1303 n8x0_gpio_setup(s);
1304 n8x0_nand_setup(s);
1305 n8x0_i2c_setup(s);
1306 if (model == 800)
1307 n800_tsc_kbd_setup(s);
1308 else if (model == 810) {
1309 n810_tsc_setup(s);
1310 n810_kbd_setup(s);
1311 }
1312 n8x0_spi_setup(s);
1313 n8x0_dss_setup(s);
1314 n8x0_cbus_setup(s);
1315 n8x0_uart_setup(s);
1316 if (usb_enabled)
1317 n8x0_usb_setup(s);
1318
1319 /* Setup initial (reset) machine state */
1320
1321 /* Start at the OneNAND bootloader. */
1322 s->cpu->env->regs[15] = 0;
1323
1324 if (kernel_filename) {
1325 /* Or at the linux loader. */
1326 binfo->kernel_filename = kernel_filename;
1327 binfo->kernel_cmdline = kernel_cmdline;
1328 binfo->initrd_filename = initrd_filename;
1329 arm_load_kernel(s->cpu->env, binfo);
1330
1331 qemu_register_reset(n8x0_boot_init, s);
1332 n8x0_boot_init(s);
1333 }
1334
1335 if (option_rom[0] && (boot_device[0] == 'n' || !kernel_filename)) {
1336 int rom_size;
1337 uint8_t nolo_tags[0x10000];
1338 /* No, wait, better start at the ROM. */
1339 s->cpu->env->regs[15] = OMAP2_Q2_BASE + 0x400000;
1340
1341 /* This is intended for loading the `secondary.bin' program from
1342 * Nokia images (the NOLO bootloader). The entry point seems
1343 * to be at OMAP2_Q2_BASE + 0x400000.
1344 *
1345 * The `2nd.bin' files contain some kind of earlier boot code and
1346 * for them the entry point needs to be set to OMAP2_SRAM_BASE.
1347 *
1348 * The code above is for loading the `zImage' file from Nokia
1349 * images. */
1350 rom_size = load_image_targphys(option_rom[0],
1351 OMAP2_Q2_BASE + 0x400000,
1352 sdram_size - 0x400000);
1353 printf("%i bytes of image loaded\n", rom_size);
1354
1355 n800_setup_nolo_tags(nolo_tags);
1356 cpu_physical_memory_write(OMAP2_SRAM_BASE, nolo_tags, 0x10000);
1357 }
1358 /* FIXME: We shouldn't really be doing this here. The LCD controller
1359 will set the size once configured, so this just sets an initial
1360 size until the guest activates the display. */
1361 ds = get_displaystate();
1362 ds->surface = qemu_resize_displaysurface(ds, 800, 480);
1363 dpy_resize(ds);
1364 }
1365
1366 static struct arm_boot_info n800_binfo = {
1367 .loader_start = OMAP2_Q2_BASE,
1368 /* Actually two chips of 0x4000000 bytes each */
1369 .ram_size = 0x08000000,
1370 .board_id = 0x4f7,
1371 .atag_board = n800_atag_setup,
1372 };
1373
1374 static struct arm_boot_info n810_binfo = {
1375 .loader_start = OMAP2_Q2_BASE,
1376 /* Actually two chips of 0x4000000 bytes each */
1377 .ram_size = 0x08000000,
1378 /* 0x60c and 0x6bf (WiMAX Edition) have been assigned but are not
1379 * used by some older versions of the bootloader and 5555 is used
1380 * instead (including versions that shipped with many devices). */
1381 .board_id = 0x60c,
1382 .atag_board = n810_atag_setup,
1383 };
1384
1385 static void n800_init(ram_addr_t ram_size,
1386 const char *boot_device,
1387 const char *kernel_filename, const char *kernel_cmdline,
1388 const char *initrd_filename, const char *cpu_model)
1389 {
1390 return n8x0_init(ram_size, boot_device,
1391 kernel_filename, kernel_cmdline, initrd_filename,
1392 cpu_model, &n800_binfo, 800);
1393 }
1394
1395 static void n810_init(ram_addr_t ram_size,
1396 const char *boot_device,
1397 const char *kernel_filename, const char *kernel_cmdline,
1398 const char *initrd_filename, const char *cpu_model)
1399 {
1400 return n8x0_init(ram_size, boot_device,
1401 kernel_filename, kernel_cmdline, initrd_filename,
1402 cpu_model, &n810_binfo, 810);
1403 }
1404
1405 static QEMUMachine n800_machine = {
1406 .name = "n800",
1407 .desc = "Nokia N800 tablet aka. RX-34 (OMAP2420)",
1408 .init = n800_init,
1409 };
1410
1411 static QEMUMachine n810_machine = {
1412 .name = "n810",
1413 .desc = "Nokia N810 tablet aka. RX-44 (OMAP2420)",
1414 .init = n810_init,
1415 };
1416
1417 static void nseries_machine_init(void)
1418 {
1419 qemu_register_machine(&n800_machine);
1420 qemu_register_machine(&n810_machine);
1421 }
1422
1423 machine_init(nseries_machine_init);
QEmu