1 #ifndef __libqos_ahci_h
2 #define __libqos_ahci_h
5 * AHCI qtest library functions and definitions
7 * Copyright (c) 2014 John Snow <jsnow@redhat.com>
9 * Permission is hereby granted, free of charge, to any person obtaining a copy
10 * of this software and associated documentation files (the "Software"), to deal
11 * in the Software without restriction, including without limitation the rights
12 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
13 * copies of the Software, and to permit persons to whom the Software is
14 * furnished to do so, subject to the following conditions:
16 * The above copyright notice and this permission notice shall be included in
17 * all copies or substantial portions of the Software.
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
24 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
31 #include "libqos/libqos.h"
32 #include "libqos/pci.h"
33 #include "libqos/malloc-pc.h"
35 /*** Supplementary PCI Config Space IDs & Masks ***/
36 #define PCI_DEVICE_ID_INTEL_Q35_AHCI (0x2922)
37 #define PCI_MSI_FLAGS_RESERVED (0xFF00)
38 #define PCI_PM_CTRL_RESERVED (0xFC)
39 #define PCI_BCC(REG32) ((REG32) >> 24)
40 #define PCI_PI(REG32) (((REG32) >> 8) & 0xFF)
41 #define PCI_SCC(REG32) (((REG32) >> 16) & 0xFF)
43 /*** Recognized AHCI Device Types ***/
44 #define AHCI_INTEL_ICH9 (PCI_DEVICE_ID_INTEL_Q35_AHCI << 16 | \
47 /*** AHCI/HBA Register Offsets and Bitmasks ***/
49 #define AHCI_CAP_NP (0x1F)
50 #define AHCI_CAP_SXS (0x20)
51 #define AHCI_CAP_EMS (0x40)
52 #define AHCI_CAP_CCCS (0x80)
53 #define AHCI_CAP_NCS (0x1F00)
54 #define AHCI_CAP_PSC (0x2000)
55 #define AHCI_CAP_SSC (0x4000)
56 #define AHCI_CAP_PMD (0x8000)
57 #define AHCI_CAP_FBSS (0x10000)
58 #define AHCI_CAP_SPM (0x20000)
59 #define AHCI_CAP_SAM (0x40000)
60 #define AHCI_CAP_RESERVED (0x80000)
61 #define AHCI_CAP_ISS (0xF00000)
62 #define AHCI_CAP_SCLO (0x1000000)
63 #define AHCI_CAP_SAL (0x2000000)
64 #define AHCI_CAP_SALP (0x4000000)
65 #define AHCI_CAP_SSS (0x8000000)
66 #define AHCI_CAP_SMPS (0x10000000)
67 #define AHCI_CAP_SSNTF (0x20000000)
68 #define AHCI_CAP_SNCQ (0x40000000)
69 #define AHCI_CAP_S64A (0x80000000)
72 #define AHCI_GHC_HR (0x01)
73 #define AHCI_GHC_IE (0x02)
74 #define AHCI_GHC_MRSM (0x04)
75 #define AHCI_GHC_RESERVED (0x7FFFFFF8)
76 #define AHCI_GHC_AE (0x80000000)
82 #define AHCI_CCCCTL (5)
83 #define AHCI_CCCCTL_EN (0x01)
84 #define AHCI_CCCCTL_RESERVED (0x06)
85 #define AHCI_CCCCTL_CC (0xFF00)
86 #define AHCI_CCCCTL_TV (0xFFFF0000)
88 #define AHCI_CCCPORTS (6)
89 #define AHCI_EMLOC (7)
91 #define AHCI_EMCTL (8)
92 #define AHCI_EMCTL_STSMR (0x01)
93 #define AHCI_EMCTL_CTLTM (0x100)
94 #define AHCI_EMCTL_CTLRST (0x200)
95 #define AHCI_EMCTL_RESERVED (0xF0F0FCFE)
98 #define AHCI_CAP2_BOH (0x01)
99 #define AHCI_CAP2_NVMP (0x02)
100 #define AHCI_CAP2_APST (0x04)
101 #define AHCI_CAP2_RESERVED (0xFFFFFFF8)
103 #define AHCI_BOHC (10)
104 #define AHCI_RESERVED (11)
105 #define AHCI_NVMHCI (24)
106 #define AHCI_VENDOR (40)
107 #define AHCI_PORTS (64)
109 /*** Port Memory Offsets & Bitmasks ***/
110 #define AHCI_PX_CLB (0)
111 #define AHCI_PX_CLB_RESERVED (0x1FF)
113 #define AHCI_PX_CLBU (1)
115 #define AHCI_PX_FB (2)
116 #define AHCI_PX_FB_RESERVED (0xFF)
118 #define AHCI_PX_FBU (3)
120 #define AHCI_PX_IS (4)
121 #define AHCI_PX_IS_DHRS (0x1)
122 #define AHCI_PX_IS_PSS (0x2)
123 #define AHCI_PX_IS_DSS (0x4)
124 #define AHCI_PX_IS_SDBS (0x8)
125 #define AHCI_PX_IS_UFS (0x10)
126 #define AHCI_PX_IS_DPS (0x20)
127 #define AHCI_PX_IS_PCS (0x40)
128 #define AHCI_PX_IS_DMPS (0x80)
129 #define AHCI_PX_IS_RESERVED (0x23FFF00)
130 #define AHCI_PX_IS_PRCS (0x400000)
131 #define AHCI_PX_IS_IPMS (0x800000)
132 #define AHCI_PX_IS_OFS (0x1000000)
133 #define AHCI_PX_IS_INFS (0x4000000)
134 #define AHCI_PX_IS_IFS (0x8000000)
135 #define AHCI_PX_IS_HBDS (0x10000000)
136 #define AHCI_PX_IS_HBFS (0x20000000)
137 #define AHCI_PX_IS_TFES (0x40000000)
138 #define AHCI_PX_IS_CPDS (0x80000000)
140 #define AHCI_PX_IE (5)
141 #define AHCI_PX_IE_DHRE (0x1)
142 #define AHCI_PX_IE_PSE (0x2)
143 #define AHCI_PX_IE_DSE (0x4)
144 #define AHCI_PX_IE_SDBE (0x8)
145 #define AHCI_PX_IE_UFE (0x10)
146 #define AHCI_PX_IE_DPE (0x20)
147 #define AHCI_PX_IE_PCE (0x40)
148 #define AHCI_PX_IE_DMPE (0x80)
149 #define AHCI_PX_IE_RESERVED (0x23FFF00)
150 #define AHCI_PX_IE_PRCE (0x400000)
151 #define AHCI_PX_IE_IPME (0x800000)
152 #define AHCI_PX_IE_OFE (0x1000000)
153 #define AHCI_PX_IE_INFE (0x4000000)
154 #define AHCI_PX_IE_IFE (0x8000000)
155 #define AHCI_PX_IE_HBDE (0x10000000)
156 #define AHCI_PX_IE_HBFE (0x20000000)
157 #define AHCI_PX_IE_TFEE (0x40000000)
158 #define AHCI_PX_IE_CPDE (0x80000000)
160 #define AHCI_PX_CMD (6)
161 #define AHCI_PX_CMD_ST (0x1)
162 #define AHCI_PX_CMD_SUD (0x2)
163 #define AHCI_PX_CMD_POD (0x4)
164 #define AHCI_PX_CMD_CLO (0x8)
165 #define AHCI_PX_CMD_FRE (0x10)
166 #define AHCI_PX_CMD_RESERVED (0xE0)
167 #define AHCI_PX_CMD_CCS (0x1F00)
168 #define AHCI_PX_CMD_MPSS (0x2000)
169 #define AHCI_PX_CMD_FR (0x4000)
170 #define AHCI_PX_CMD_CR (0x8000)
171 #define AHCI_PX_CMD_CPS (0x10000)
172 #define AHCI_PX_CMD_PMA (0x20000)
173 #define AHCI_PX_CMD_HPCP (0x40000)
174 #define AHCI_PX_CMD_MPSP (0x80000)
175 #define AHCI_PX_CMD_CPD (0x100000)
176 #define AHCI_PX_CMD_ESP (0x200000)
177 #define AHCI_PX_CMD_FBSCP (0x400000)
178 #define AHCI_PX_CMD_APSTE (0x800000)
179 #define AHCI_PX_CMD_ATAPI (0x1000000)
180 #define AHCI_PX_CMD_DLAE (0x2000000)
181 #define AHCI_PX_CMD_ALPE (0x4000000)
182 #define AHCI_PX_CMD_ASP (0x8000000)
183 #define AHCI_PX_CMD_ICC (0xF0000000)
185 #define AHCI_PX_RES1 (7)
187 #define AHCI_PX_TFD (8)
188 #define AHCI_PX_TFD_STS (0xFF)
189 #define AHCI_PX_TFD_STS_ERR (0x01)
190 #define AHCI_PX_TFD_STS_CS1 (0x06)
191 #define AHCI_PX_TFD_STS_DRQ (0x08)
192 #define AHCI_PX_TFD_STS_CS2 (0x70)
193 #define AHCI_PX_TFD_STS_BSY (0x80)
194 #define AHCI_PX_TFD_ERR (0xFF00)
195 #define AHCI_PX_TFD_RESERVED (0xFFFF0000)
197 #define AHCI_PX_SIG (9)
198 #define AHCI_PX_SIG_SECTOR_COUNT (0xFF)
199 #define AHCI_PX_SIG_LBA_LOW (0xFF00)
200 #define AHCI_PX_SIG_LBA_MID (0xFF0000)
201 #define AHCI_PX_SIG_LBA_HIGH (0xFF000000)
203 #define AHCI_PX_SSTS (10)
204 #define AHCI_PX_SSTS_DET (0x0F)
205 #define AHCI_PX_SSTS_SPD (0xF0)
206 #define AHCI_PX_SSTS_IPM (0xF00)
207 #define AHCI_PX_SSTS_RESERVED (0xFFFFF000)
208 #define SSTS_DET_NO_DEVICE (0x00)
209 #define SSTS_DET_PRESENT (0x01)
210 #define SSTS_DET_ESTABLISHED (0x03)
211 #define SSTS_DET_OFFLINE (0x04)
213 #define AHCI_PX_SCTL (11)
215 #define AHCI_PX_SERR (12)
216 #define AHCI_PX_SERR_ERR (0xFFFF)
217 #define AHCI_PX_SERR_DIAG (0xFFFF0000)
218 #define AHCI_PX_SERR_DIAG_X (0x04000000)
220 #define AHCI_PX_SACT (13)
221 #define AHCI_PX_CI (14)
222 #define AHCI_PX_SNTF (15)
224 #define AHCI_PX_FBS (16)
225 #define AHCI_PX_FBS_EN (0x1)
226 #define AHCI_PX_FBS_DEC (0x2)
227 #define AHCI_PX_FBS_SDE (0x4)
228 #define AHCI_PX_FBS_DEV (0xF00)
229 #define AHCI_PX_FBS_ADO (0xF000)
230 #define AHCI_PX_FBS_DWE (0xF0000)
231 #define AHCI_PX_FBS_RESERVED (0xFFF000F8)
233 #define AHCI_PX_RES2 (17)
234 #define AHCI_PX_VS (28)
236 #define HBA_DATA_REGION_SIZE (256)
237 #define HBA_PORT_DATA_SIZE (128)
238 #define HBA_PORT_NUM_REG (HBA_PORT_DATA_SIZE/4)
240 #define AHCI_VERSION_0_95 (0x00000905)
241 #define AHCI_VERSION_1_0 (0x00010000)
242 #define AHCI_VERSION_1_1 (0x00010100)
243 #define AHCI_VERSION_1_2 (0x00010200)
244 #define AHCI_VERSION_1_3 (0x00010300)
248 typedef struct AHCIPortQState
{
253 uint8_t next
; /** Next Command Slot to Use **/
256 typedef struct AHCIQState
{
261 uint32_t fingerprint
;
264 AHCIPortQState port
[32];
268 * Generic FIS structure.
274 } __attribute__((__packed__
)) FIS
;
277 * Register device-to-host FIS structure.
279 typedef struct RegD2HFIS
{
302 } __attribute__((__packed__
)) RegD2HFIS
;
305 * Register host-to-device FIS structure.
307 typedef struct RegH2DFIS
{
322 uint8_t feature_high
;
329 } __attribute__((__packed__
)) RegH2DFIS
;
332 * Command List entry structure.
333 * The command list contains between 1-32 of these structures.
335 typedef struct AHCICommandHeader
{
336 uint16_t flags
; /* Cmd-Fis-Len, PMP#, and flags. */
337 uint16_t prdtl
; /* Phys Region Desc. Table Length */
338 uint32_t prdbc
; /* Phys Region Desc. Byte Count */
339 uint64_t ctba
; /* Command Table Descriptor Base Address */
341 } __attribute__((__packed__
)) AHCICommandHeader
;
344 * Physical Region Descriptor; pointed to by the Command List Header,
345 * struct ahci_command.
348 uint64_t dba
; /* Data Base Address */
349 uint32_t res
; /* Reserved */
350 uint32_t dbc
; /* Data Byte Count (0-indexed) & Interrupt Flag (bit 2^31) */
351 } __attribute__((__packed__
)) PRD
;
353 /*** Macro Utilities ***/
354 #define BITANY(data, mask) (((data) & (mask)) != 0)
355 #define BITSET(data, mask) (((data) & (mask)) == (mask))
356 #define BITCLR(data, mask) (((data) & (mask)) == 0)
357 #define ASSERT_BIT_SET(data, mask) g_assert_cmphex((data) & (mask), ==, (mask))
358 #define ASSERT_BIT_CLEAR(data, mask) g_assert_cmphex((data) & (mask), ==, 0)
360 /* For calculating how big the PRD table needs to be: */
361 #define CMD_TBL_SIZ(n) ((0x80 + ((n) * sizeof(PRD)) + 0x7F) & ~0x7F)
363 /* Helpers for reading/writing AHCI HBA register values */
365 static inline uint32_t ahci_mread(AHCIQState
*ahci
, size_t offset
)
367 return qpci_io_readl(ahci
->dev
, ahci
->hba_base
+ offset
);
370 static inline void ahci_mwrite(AHCIQState
*ahci
, size_t offset
, uint32_t value
)
372 qpci_io_writel(ahci
->dev
, ahci
->hba_base
+ offset
, value
);
375 static inline uint32_t ahci_rreg(AHCIQState
*ahci
, uint32_t reg_num
)
377 return ahci_mread(ahci
, 4 * reg_num
);
380 static inline void ahci_wreg(AHCIQState
*ahci
, uint32_t reg_num
, uint32_t value
)
382 ahci_mwrite(ahci
, 4 * reg_num
, value
);
385 static inline void ahci_set(AHCIQState
*ahci
, uint32_t reg_num
, uint32_t mask
)
387 ahci_wreg(ahci
, reg_num
, ahci_rreg(ahci
, reg_num
) | mask
);
390 static inline void ahci_clr(AHCIQState
*ahci
, uint32_t reg_num
, uint32_t mask
)
392 ahci_wreg(ahci
, reg_num
, ahci_rreg(ahci
, reg_num
) & ~mask
);
395 static inline size_t ahci_px_offset(uint8_t port
, uint32_t reg_num
)
397 return AHCI_PORTS
+ (HBA_PORT_NUM_REG
* port
) + reg_num
;
400 static inline uint32_t ahci_px_rreg(AHCIQState
*ahci
, uint8_t port
,
403 return ahci_rreg(ahci
, ahci_px_offset(port
, reg_num
));
406 static inline void ahci_px_wreg(AHCIQState
*ahci
, uint8_t port
,
407 uint32_t reg_num
, uint32_t value
)
409 ahci_wreg(ahci
, ahci_px_offset(port
, reg_num
), value
);
412 static inline void ahci_px_set(AHCIQState
*ahci
, uint8_t port
,
413 uint32_t reg_num
, uint32_t mask
)
415 ahci_px_wreg(ahci
, port
, reg_num
,
416 ahci_px_rreg(ahci
, port
, reg_num
) | mask
);
419 static inline void ahci_px_clr(AHCIQState
*ahci
, uint8_t port
,
420 uint32_t reg_num
, uint32_t mask
)
422 ahci_px_wreg(ahci
, port
, reg_num
,
423 ahci_px_rreg(ahci
, port
, reg_num
) & ~mask
);
427 uint64_t ahci_alloc(AHCIQState
*ahci
, size_t bytes
);
428 void ahci_free(AHCIQState
*ahci
, uint64_t addr
);
429 QPCIDevice
*get_ahci_device(uint32_t *fingerprint
);
430 void free_ahci_device(QPCIDevice
*dev
);
431 void ahci_pci_enable(AHCIQState
*ahci
);
432 void start_ahci_device(AHCIQState
*ahci
);
433 void ahci_hba_enable(AHCIQState
*ahci
);
434 unsigned ahci_port_select(AHCIQState
*ahci
);
435 void ahci_port_clear(AHCIQState
*ahci
, uint8_t port
);
436 void ahci_port_check_error(AHCIQState
*ahci
, uint8_t port
);
437 void ahci_port_check_interrupts(AHCIQState
*ahci
, uint8_t port
,
439 void ahci_port_check_nonbusy(AHCIQState
*ahci
, uint8_t port
, uint8_t slot
);
440 void ahci_get_command_header(AHCIQState
*ahci
, uint8_t port
,
441 uint8_t slot
, AHCICommandHeader
*cmd
);
442 void ahci_set_command_header(AHCIQState
*ahci
, uint8_t port
,
443 uint8_t slot
, AHCICommandHeader
*cmd
);
444 void ahci_destroy_command(AHCIQState
*ahci
, uint8_t port
, uint8_t slot
);
445 unsigned ahci_pick_cmd(AHCIQState
*ahci
, uint8_t port
);