hw/misc/mips_itu.c

   1 /*
   2  * Inter-Thread Communication Unit emulation.
   3  *
   4  * Copyright (c) 2016 Imagination Technologies
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "qemu/osdep.h"
  21 #include "qapi/error.h"
  22 #include "cpu.h"
  23 #include "qemu/log.h"
  24 #include "exec/exec-all.h"
  25 #include "hw/hw.h"
  26 #include "hw/sysbus.h"
  27 #include "sysemu/sysemu.h"
  28 #include "hw/misc/mips_itu.h"
  29
  30 #define ITC_TAG_ADDRSPACE_SZ (ITC_ADDRESSMAP_NUM * 8)
  31 /* Initialize as 4kB area to fit all 32 cells with default 128B grain.
  32    Storage may be resized by the software. */
  33 #define ITC_STORAGE_ADDRSPACE_SZ 0x1000
  34
  35 #define ITC_FIFO_NUM_MAX 16
  36 #define ITC_SEMAPH_NUM_MAX 16
  37 #define ITC_AM1_NUMENTRIES_OFS 20
  38
  39 #define ITC_CELL_PV_MAX_VAL 0xFFFF
  40
  41 #define ITC_CELL_TAG_FIFO_DEPTH 28
  42 #define ITC_CELL_TAG_FIFO_PTR 18
  43 #define ITC_CELL_TAG_FIFO 17
  44 #define ITC_CELL_TAG_T 16
  45 #define ITC_CELL_TAG_F 1
  46 #define ITC_CELL_TAG_E 0
  47
  48 #define ITC_AM0_BASE_ADDRESS_MASK 0xFFFFFC00ULL
  49 #define ITC_AM0_EN_MASK 0x1
  50
  51 #define ITC_AM1_ADDR_MASK_MASK 0x1FC00
  52 #define ITC_AM1_ENTRY_GRAIN_MASK 0x7
  53
  54 typedef enum ITCView {
  55     ITCVIEW_BYPASS  = 0,
  56     ITCVIEW_CONTROL = 1,
  57     ITCVIEW_EF_SYNC = 2,
  58     ITCVIEW_EF_TRY  = 3,
  59     ITCVIEW_PV_SYNC = 4,
  60     ITCVIEW_PV_TRY  = 5
  61 } ITCView;
  62
  63 MemoryRegion *mips_itu_get_tag_region(MIPSITUState *itu)
  64 {
  65     return &itu->tag_io;
  66 }
  67
  68 static uint64_t itc_tag_read(void *opaque, hwaddr addr, unsigned size)
  69 {
  70     MIPSITUState *tag = (MIPSITUState *)opaque;
  71     uint64_t index = addr >> 3;
  72
  73     if (index >= ITC_ADDRESSMAP_NUM) {
  74         qemu_log_mask(LOG_GUEST_ERROR, "Read 0x%" PRIx64 "\n", addr);
  75         return 0;
  76     }
  77
  78     return tag->ITCAddressMap[index];
  79 }
  80
  81 static void itc_reconfigure(MIPSITUState *tag)
  82 {
  83     uint64_t *am = &tag->ITCAddressMap[0];
  84     MemoryRegion *mr = &tag->storage_io;
  85     hwaddr address = am[0] & ITC_AM0_BASE_ADDRESS_MASK;
  86     uint64_t size = (1 << 10) + (am[1] & ITC_AM1_ADDR_MASK_MASK);
  87     bool is_enabled = (am[0] & ITC_AM0_EN_MASK) != 0;
  88
  89     memory_region_transaction_begin();
  90     if (!(size & (size - 1))) {
  91         memory_region_set_size(mr, size);
  92     }
  93     memory_region_set_address(mr, address);
  94     memory_region_set_enabled(mr, is_enabled);
  95     memory_region_transaction_commit();
  96 }
  97
  98 static void itc_tag_write(void *opaque, hwaddr addr,
  99                           uint64_t data, unsigned size)
 100 {
 101     MIPSITUState *tag = (MIPSITUState *)opaque;
 102     uint64_t *am = &tag->ITCAddressMap[0];
 103     uint64_t am_old, mask;
 104     uint64_t index = addr >> 3;
 105
 106     switch (index) {
 107     case 0:
 108         mask = ITC_AM0_BASE_ADDRESS_MASK | ITC_AM0_EN_MASK;
 109         break;
 110     case 1:
 111         mask = ITC_AM1_ADDR_MASK_MASK | ITC_AM1_ENTRY_GRAIN_MASK;
 112         break;
 113     default:
 114         qemu_log_mask(LOG_GUEST_ERROR, "Bad write 0x%" PRIx64 "\n", addr);
 115         return;
 116     }
 117
 118     am_old = am[index];
 119     am[index] = (data & mask) | (am_old & ~mask);
 120     if (am_old != am[index]) {
 121         itc_reconfigure(tag);
 122     }
 123 }
 124
 125 static const MemoryRegionOps itc_tag_ops = {
 126     .read = itc_tag_read,
 127     .write = itc_tag_write,
 128     .impl = {
 129         .max_access_size = 8,
 130     },
 131     .endianness = DEVICE_NATIVE_ENDIAN,
 132 };
 133
 134 static inline uint32_t get_num_cells(MIPSITUState *s)
 135 {
 136     return s->num_fifo + s->num_semaphores;
 137 }
 138
 139 static inline ITCView get_itc_view(hwaddr addr)
 140 {
 141     return (addr >> 3) & 0xf;
 142 }
 143
 144 static inline int get_cell_stride_shift(const MIPSITUState *s)
 145 {
 146     /* Minimum interval (for EntryGain = 0) is 128 B */
 147     return 7 + (s->ITCAddressMap[1] & ITC_AM1_ENTRY_GRAIN_MASK);
 148 }
 149
 150 static inline ITCStorageCell *get_cell(MIPSITUState *s,
 151                                        hwaddr addr)
 152 {
 153     uint32_t cell_idx = addr >> get_cell_stride_shift(s);
 154     uint32_t num_cells = get_num_cells(s);
 155
 156     if (cell_idx >= num_cells) {
 157         cell_idx = num_cells - 1;
 158     }
 159
 160     return &s->cell[cell_idx];
 161 }
 162
 163 static void wake_blocked_threads(ITCStorageCell *c)
 164 {
 165     CPUState *cs;
 166     CPU_FOREACH(cs) {
 167         if (cs->halted && (c->blocked_threads & (1ULL << cs->cpu_index))) {
 168             cpu_interrupt(cs, CPU_INTERRUPT_WAKE);
 169         }
 170     }
 171     c->blocked_threads = 0;
 172 }
 173
 174 static void QEMU_NORETURN block_thread_and_exit(ITCStorageCell *c)
 175 {
 176     c->blocked_threads |= 1ULL << current_cpu->cpu_index;
 177     cpu_restore_state(current_cpu, current_cpu->mem_io_pc);
 178     current_cpu->halted = 1;
 179     current_cpu->exception_index = EXCP_HLT;
 180     cpu_loop_exit(current_cpu);
 181 }
 182
 183 /* ITC Bypass View */
 184
 185 static inline uint64_t view_bypass_read(ITCStorageCell *c)
 186 {
 187     if (c->tag.FIFO) {
 188         return c->data[c->fifo_out];
 189     } else {
 190         return c->data[0];
 191     }
 192 }
 193
 194 static inline void view_bypass_write(ITCStorageCell *c, uint64_t val)
 195 {
 196     if (c->tag.FIFO && (c->tag.FIFOPtr > 0)) {
 197         int idx = (c->fifo_out + c->tag.FIFOPtr - 1) % ITC_CELL_DEPTH;
 198         c->data[idx] = val;
 199     }
 200
 201     /* ignore a write to the semaphore cell */
 202 }
 203
 204 /* ITC Control View */
 205
 206 static inline uint64_t view_control_read(ITCStorageCell *c)
 207 {
 208     return ((uint64_t)c->tag.FIFODepth << ITC_CELL_TAG_FIFO_DEPTH) |
 209            (c->tag.FIFOPtr << ITC_CELL_TAG_FIFO_PTR) |
 210            (c->tag.FIFO << ITC_CELL_TAG_FIFO) |
 211            (c->tag.T << ITC_CELL_TAG_T) |
 212            (c->tag.E << ITC_CELL_TAG_E) |
 213            (c->tag.F << ITC_CELL_TAG_F);
 214 }
 215
 216 static inline void view_control_write(ITCStorageCell *c, uint64_t val)
 217 {
 218     c->tag.T = (val >> ITC_CELL_TAG_T) & 1;
 219     c->tag.E = (val >> ITC_CELL_TAG_E) & 1;
 220     c->tag.F = (val >> ITC_CELL_TAG_F) & 1;
 221
 222     if (c->tag.E) {
 223         c->tag.FIFOPtr = 0;
 224     }
 225 }
 226
 227 /* ITC Empty/Full View */
 228
 229 static uint64_t view_ef_common_read(ITCStorageCell *c, bool blocking)
 230 {
 231     uint64_t ret = 0;
 232
 233     if (!c->tag.FIFO) {
 234         return 0;
 235     }
 236
 237     c->tag.F = 0;
 238
 239     if (blocking && c->tag.E) {
 240         block_thread_and_exit(c);
 241     }
 242
 243     if (c->blocked_threads) {
 244         wake_blocked_threads(c);
 245     }
 246
 247     if (c->tag.FIFOPtr > 0) {
 248         ret = c->data[c->fifo_out];
 249         c->fifo_out = (c->fifo_out + 1) % ITC_CELL_DEPTH;
 250         c->tag.FIFOPtr--;
 251     }
 252
 253     if (c->tag.FIFOPtr == 0) {
 254         c->tag.E = 1;
 255     }
 256
 257     return ret;
 258 }
 259
 260 static uint64_t view_ef_sync_read(ITCStorageCell *c)
 261 {
 262     return view_ef_common_read(c, true);
 263 }
 264
 265 static uint64_t view_ef_try_read(ITCStorageCell *c)
 266 {
 267     return view_ef_common_read(c, false);
 268 }
 269
 270 static inline void view_ef_common_write(ITCStorageCell *c, uint64_t val,
 271                                         bool blocking)
 272 {
 273     if (!c->tag.FIFO) {
 274         return;
 275     }
 276
 277     c->tag.E = 0;
 278
 279     if (blocking && c->tag.F) {
 280         block_thread_and_exit(c);
 281     }
 282
 283     if (c->blocked_threads) {
 284         wake_blocked_threads(c);
 285     }
 286
 287     if (c->tag.FIFOPtr < ITC_CELL_DEPTH) {
 288         int idx = (c->fifo_out + c->tag.FIFOPtr) % ITC_CELL_DEPTH;
 289         c->data[idx] = val;
 290         c->tag.FIFOPtr++;
 291     }
 292
 293     if (c->tag.FIFOPtr == ITC_CELL_DEPTH) {
 294         c->tag.F = 1;
 295     }
 296 }
 297
 298 static void view_ef_sync_write(ITCStorageCell *c, uint64_t val)
 299 {
 300     view_ef_common_write(c, val, true);
 301 }
 302
 303 static void view_ef_try_write(ITCStorageCell *c, uint64_t val)
 304 {
 305     view_ef_common_write(c, val, false);
 306 }
 307
 308 /* ITC P/V View */
 309
 310 static uint64_t view_pv_common_read(ITCStorageCell *c, bool blocking)
 311 {
 312     uint64_t ret = c->data[0];
 313
 314     if (c->tag.FIFO) {
 315         return 0;
 316     }
 317
 318     if (c->data[0] > 0) {
 319         c->data[0]--;
 320     } else if (blocking) {
 321         block_thread_and_exit(c);
 322     }
 323
 324     return ret;
 325 }
 326
 327 static uint64_t view_pv_sync_read(ITCStorageCell *c)
 328 {
 329     return view_pv_common_read(c, true);
 330 }
 331
 332 static uint64_t view_pv_try_read(ITCStorageCell *c)
 333 {
 334     return view_pv_common_read(c, false);
 335 }
 336
 337 static inline void view_pv_common_write(ITCStorageCell *c)
 338 {
 339     if (c->tag.FIFO) {
 340         return;
 341     }
 342
 343     if (c->data[0] < ITC_CELL_PV_MAX_VAL) {
 344         c->data[0]++;
 345     }
 346
 347     if (c->blocked_threads) {
 348         wake_blocked_threads(c);
 349     }
 350 }
 351
 352 static void view_pv_sync_write(ITCStorageCell *c)
 353 {
 354     view_pv_common_write(c);
 355 }
 356
 357 static void view_pv_try_write(ITCStorageCell *c)
 358 {
 359     view_pv_common_write(c);
 360 }
 361
 362 static uint64_t itc_storage_read(void *opaque, hwaddr addr, unsigned size)
 363 {
 364     MIPSITUState *s = (MIPSITUState *)opaque;
 365     ITCStorageCell *cell = get_cell(s, addr);
 366     ITCView view = get_itc_view(addr);
 367     uint64_t ret = -1;
 368
 369     switch (view) {
 370     case ITCVIEW_BYPASS:
 371         ret = view_bypass_read(cell);
 372         break;
 373     case ITCVIEW_CONTROL:
 374         ret = view_control_read(cell);
 375         break;
 376     case ITCVIEW_EF_SYNC:
 377         ret = view_ef_sync_read(cell);
 378         break;
 379     case ITCVIEW_EF_TRY:
 380         ret = view_ef_try_read(cell);
 381         break;
 382     case ITCVIEW_PV_SYNC:
 383         ret = view_pv_sync_read(cell);
 384         break;
 385     case ITCVIEW_PV_TRY:
 386         ret = view_pv_try_read(cell);
 387         break;
 388     default:
 389         qemu_log_mask(LOG_GUEST_ERROR,
 390                       "itc_storage_read: Bad ITC View %d\n", (int)view);
 391         break;
 392     }
 393
 394     return ret;
 395 }
 396
 397 static void itc_storage_write(void *opaque, hwaddr addr, uint64_t data,
 398                               unsigned size)
 399 {
 400     MIPSITUState *s = (MIPSITUState *)opaque;
 401     ITCStorageCell *cell = get_cell(s, addr);
 402     ITCView view = get_itc_view(addr);
 403
 404     switch (view) {
 405     case ITCVIEW_BYPASS:
 406         view_bypass_write(cell, data);
 407         break;
 408     case ITCVIEW_CONTROL:
 409         view_control_write(cell, data);
 410         break;
 411     case ITCVIEW_EF_SYNC:
 412         view_ef_sync_write(cell, data);
 413         break;
 414     case ITCVIEW_EF_TRY:
 415         view_ef_try_write(cell, data);
 416         break;
 417     case ITCVIEW_PV_SYNC:
 418         view_pv_sync_write(cell);
 419         break;
 420     case ITCVIEW_PV_TRY:
 421         view_pv_try_write(cell);
 422         break;
 423     default:
 424         qemu_log_mask(LOG_GUEST_ERROR,
 425                       "itc_storage_write: Bad ITC View %d\n", (int)view);
 426         break;
 427     }
 428
 429 }
 430
 431 static const MemoryRegionOps itc_storage_ops = {
 432     .read = itc_storage_read,
 433     .write = itc_storage_write,
 434     .endianness = DEVICE_NATIVE_ENDIAN,
 435 };
 436
 437 static void itc_reset_cells(MIPSITUState *s)
 438 {
 439     int i;
 440
 441     memset(s->cell, 0, get_num_cells(s) * sizeof(s->cell[0]));
 442
 443     for (i = 0; i < s->num_fifo; i++) {
 444         s->cell[i].tag.E = 1;
 445         s->cell[i].tag.FIFO = 1;
 446         s->cell[i].tag.FIFODepth = ITC_CELL_DEPTH_SHIFT;
 447     }
 448 }
 449
 450 static void mips_itu_init(Object *obj)
 451 {
 452     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
 453     MIPSITUState *s = MIPS_ITU(obj);
 454
 455     memory_region_init_io(&s->storage_io, OBJECT(s), &itc_storage_ops, s,
 456                           "mips-itc-storage", ITC_STORAGE_ADDRSPACE_SZ);
 457     sysbus_init_mmio(sbd, &s->storage_io);
 458
 459     memory_region_init_io(&s->tag_io, OBJECT(s), &itc_tag_ops, s,
 460                           "mips-itc-tag", ITC_TAG_ADDRSPACE_SZ);
 461 }
 462
 463 static void mips_itu_realize(DeviceState *dev, Error **errp)
 464 {
 465     MIPSITUState *s = MIPS_ITU(dev);
 466
 467     if (s->num_fifo > ITC_FIFO_NUM_MAX) {
 468         error_setg(errp, "Exceed maximum number of FIFO cells: %d",
 469                    s->num_fifo);
 470         return;
 471     }
 472     if (s->num_semaphores > ITC_SEMAPH_NUM_MAX) {
 473         error_setg(errp, "Exceed maximum number of Semaphore cells: %d",
 474                    s->num_semaphores);
 475         return;
 476     }
 477
 478     s->cell = g_new(ITCStorageCell, get_num_cells(s));
 479 }
 480
 481 static void mips_itu_reset(DeviceState *dev)
 482 {
 483     MIPSITUState *s = MIPS_ITU(dev);
 484
 485     s->ITCAddressMap[0] = 0;
 486     s->ITCAddressMap[1] =
 487         ((ITC_STORAGE_ADDRSPACE_SZ - 1) & ITC_AM1_ADDR_MASK_MASK) |
 488         (get_num_cells(s) << ITC_AM1_NUMENTRIES_OFS);
 489     itc_reconfigure(s);
 490
 491     itc_reset_cells(s);
 492 }
 493
 494 static Property mips_itu_properties[] = {
 495     DEFINE_PROP_INT32("num-fifo", MIPSITUState, num_fifo,
 496                       ITC_FIFO_NUM_MAX),
 497     DEFINE_PROP_INT32("num-semaphores", MIPSITUState, num_semaphores,
 498                       ITC_SEMAPH_NUM_MAX),
 499     DEFINE_PROP_END_OF_LIST(),
 500 };
 501
 502 static void mips_itu_class_init(ObjectClass *klass, void *data)
 503 {
 504     DeviceClass *dc = DEVICE_CLASS(klass);
 505
 506     dc->props = mips_itu_properties;
 507     dc->realize = mips_itu_realize;
 508     dc->reset = mips_itu_reset;
 509 }
 510
 511 static const TypeInfo mips_itu_info = {
 512     .name          = TYPE_MIPS_ITU,
 513     .parent        = TYPE_SYS_BUS_DEVICE,
 514     .instance_size = sizeof(MIPSITUState),
 515     .instance_init = mips_itu_init,
 516     .class_init    = mips_itu_class_init,
 517 };
 518
 519 static void mips_itu_register_types(void)
 520 {
 521     type_register_static(&mips_itu_info);
 522 }
 523
 524 type_init(mips_itu_register_types)