2 * QEMU 16550A UART emulation
4 * Copyright (c) 2003-2004 Fabrice Bellard
5 * Copyright (c) 2008 Citrix Systems, Inc.
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
26 #include "hw/char/serial.h"
27 #include "sysemu/char.h"
28 #include "qemu/timer.h"
29 #include "exec/address-spaces.h"
30 #include "qemu/error-report.h"
32 //#define DEBUG_SERIAL
34 #define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
36 #define UART_IER_MSI 0x08 /* Enable Modem status interrupt */
37 #define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */
38 #define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */
39 #define UART_IER_RDI 0x01 /* Enable receiver data interrupt */
41 #define UART_IIR_NO_INT 0x01 /* No interrupts pending */
42 #define UART_IIR_ID 0x06 /* Mask for the interrupt ID */
44 #define UART_IIR_MSI 0x00 /* Modem status interrupt */
45 #define UART_IIR_THRI 0x02 /* Transmitter holding register empty */
46 #define UART_IIR_RDI 0x04 /* Receiver data interrupt */
47 #define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */
48 #define UART_IIR_CTI 0x0C /* Character Timeout Indication */
50 #define UART_IIR_FENF 0x80 /* Fifo enabled, but not functionning */
51 #define UART_IIR_FE 0xC0 /* Fifo enabled */
54 * These are the definitions for the Modem Control Register
56 #define UART_MCR_LOOP 0x10 /* Enable loopback test mode */
57 #define UART_MCR_OUT2 0x08 /* Out2 complement */
58 #define UART_MCR_OUT1 0x04 /* Out1 complement */
59 #define UART_MCR_RTS 0x02 /* RTS complement */
60 #define UART_MCR_DTR 0x01 /* DTR complement */
63 * These are the definitions for the Modem Status Register
65 #define UART_MSR_DCD 0x80 /* Data Carrier Detect */
66 #define UART_MSR_RI 0x40 /* Ring Indicator */
67 #define UART_MSR_DSR 0x20 /* Data Set Ready */
68 #define UART_MSR_CTS 0x10 /* Clear to Send */
69 #define UART_MSR_DDCD 0x08 /* Delta DCD */
70 #define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */
71 #define UART_MSR_DDSR 0x02 /* Delta DSR */
72 #define UART_MSR_DCTS 0x01 /* Delta CTS */
73 #define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */
75 #define UART_LSR_TEMT 0x40 /* Transmitter empty */
76 #define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */
77 #define UART_LSR_BI 0x10 /* Break interrupt indicator */
78 #define UART_LSR_FE 0x08 /* Frame error indicator */
79 #define UART_LSR_PE 0x04 /* Parity error indicator */
80 #define UART_LSR_OE 0x02 /* Overrun error indicator */
81 #define UART_LSR_DR 0x01 /* Receiver data ready */
82 #define UART_LSR_INT_ANY 0x1E /* Any of the lsr-interrupt-triggering status bits */
84 /* Interrupt trigger levels. The byte-counts are for 16550A - in newer UARTs the byte-count for each ITL is higher. */
86 #define UART_FCR_ITL_1 0x00 /* 1 byte ITL */
87 #define UART_FCR_ITL_2 0x40 /* 4 bytes ITL */
88 #define UART_FCR_ITL_3 0x80 /* 8 bytes ITL */
89 #define UART_FCR_ITL_4 0xC0 /* 14 bytes ITL */
91 #define UART_FCR_DMS 0x08 /* DMA Mode Select */
92 #define UART_FCR_XFR 0x04 /* XMIT Fifo Reset */
93 #define UART_FCR_RFR 0x02 /* RCVR Fifo Reset */
94 #define UART_FCR_FE 0x01 /* FIFO Enable */
96 #define MAX_XMIT_RETRY 4
99 #define DPRINTF(fmt, ...) \
100 do { fprintf(stderr, "serial: " fmt , ## __VA_ARGS__); } while (0)
102 #define DPRINTF(fmt, ...) \
106 static void serial_receive1(void *opaque
, const uint8_t *buf
, int size
);
108 static inline void recv_fifo_put(SerialState
*s
, uint8_t chr
)
110 /* Receive overruns do not overwrite FIFO contents. */
111 if (!fifo8_is_full(&s
->recv_fifo
)) {
112 fifo8_push(&s
->recv_fifo
, chr
);
114 s
->lsr
|= UART_LSR_OE
;
118 static void serial_update_irq(SerialState
*s
)
120 uint8_t tmp_iir
= UART_IIR_NO_INT
;
122 if ((s
->ier
& UART_IER_RLSI
) && (s
->lsr
& UART_LSR_INT_ANY
)) {
123 tmp_iir
= UART_IIR_RLSI
;
124 } else if ((s
->ier
& UART_IER_RDI
) && s
->timeout_ipending
) {
125 /* Note that(s->ier & UART_IER_RDI) can mask this interrupt,
126 * this is not in the specification but is observed on existing
128 tmp_iir
= UART_IIR_CTI
;
129 } else if ((s
->ier
& UART_IER_RDI
) && (s
->lsr
& UART_LSR_DR
) &&
130 (!(s
->fcr
& UART_FCR_FE
) ||
131 s
->recv_fifo
.num
>= s
->recv_fifo_itl
)) {
132 tmp_iir
= UART_IIR_RDI
;
133 } else if ((s
->ier
& UART_IER_THRI
) && s
->thr_ipending
) {
134 tmp_iir
= UART_IIR_THRI
;
135 } else if ((s
->ier
& UART_IER_MSI
) && (s
->msr
& UART_MSR_ANY_DELTA
)) {
136 tmp_iir
= UART_IIR_MSI
;
139 s
->iir
= tmp_iir
| (s
->iir
& 0xF0);
141 if (tmp_iir
!= UART_IIR_NO_INT
) {
142 qemu_irq_raise(s
->irq
);
144 qemu_irq_lower(s
->irq
);
148 static void serial_update_parameters(SerialState
*s
)
150 int speed
, parity
, data_bits
, stop_bits
, frame_size
;
151 QEMUSerialSetParams ssp
;
173 data_bits
= (s
->lcr
& 0x03) + 5;
174 frame_size
+= data_bits
+ stop_bits
;
175 speed
= s
->baudbase
/ s
->divider
;
178 ssp
.data_bits
= data_bits
;
179 ssp
.stop_bits
= stop_bits
;
180 s
->char_transmit_time
= (get_ticks_per_sec() / speed
) * frame_size
;
181 qemu_chr_fe_ioctl(s
->chr
, CHR_IOCTL_SERIAL_SET_PARAMS
, &ssp
);
183 DPRINTF("speed=%d parity=%c data=%d stop=%d\n",
184 speed
, parity
, data_bits
, stop_bits
);
187 static void serial_update_msl(SerialState
*s
)
192 timer_del(s
->modem_status_poll
);
194 if (qemu_chr_fe_ioctl(s
->chr
,CHR_IOCTL_SERIAL_GET_TIOCM
, &flags
) == -ENOTSUP
) {
201 s
->msr
= (flags
& CHR_TIOCM_CTS
) ? s
->msr
| UART_MSR_CTS
: s
->msr
& ~UART_MSR_CTS
;
202 s
->msr
= (flags
& CHR_TIOCM_DSR
) ? s
->msr
| UART_MSR_DSR
: s
->msr
& ~UART_MSR_DSR
;
203 s
->msr
= (flags
& CHR_TIOCM_CAR
) ? s
->msr
| UART_MSR_DCD
: s
->msr
& ~UART_MSR_DCD
;
204 s
->msr
= (flags
& CHR_TIOCM_RI
) ? s
->msr
| UART_MSR_RI
: s
->msr
& ~UART_MSR_RI
;
206 if (s
->msr
!= omsr
) {
208 s
->msr
= s
->msr
| ((s
->msr
>> 4) ^ (omsr
>> 4));
209 /* UART_MSR_TERI only if change was from 1 -> 0 */
210 if ((s
->msr
& UART_MSR_TERI
) && !(omsr
& UART_MSR_RI
))
211 s
->msr
&= ~UART_MSR_TERI
;
212 serial_update_irq(s
);
215 /* The real 16550A apparently has a 250ns response latency to line status changes.
216 We'll be lazy and poll only every 10ms, and only poll it at all if MSI interrupts are turned on */
219 timer_mod(s
->modem_status_poll
, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) + get_ticks_per_sec() / 100);
222 static gboolean
serial_xmit(GIOChannel
*chan
, GIOCondition cond
, void *opaque
)
224 SerialState
*s
= opaque
;
227 assert(!(s
->lsr
& UART_LSR_TEMT
));
228 if (s
->tsr_retry
<= 0) {
229 assert(!(s
->lsr
& UART_LSR_THRE
));
231 if (s
->fcr
& UART_FCR_FE
) {
232 assert(!fifo8_is_empty(&s
->xmit_fifo
));
233 s
->tsr
= fifo8_pop(&s
->xmit_fifo
);
234 if (!s
->xmit_fifo
.num
) {
235 s
->lsr
|= UART_LSR_THRE
;
239 s
->lsr
|= UART_LSR_THRE
;
241 if ((s
->lsr
& UART_LSR_THRE
) && !s
->thr_ipending
) {
243 serial_update_irq(s
);
247 if (s
->mcr
& UART_MCR_LOOP
) {
248 /* in loopback mode, say that we just received a char */
249 serial_receive1(s
, &s
->tsr
, 1);
250 } else if (qemu_chr_fe_write(s
->chr
, &s
->tsr
, 1) != 1) {
251 if (s
->tsr_retry
>= 0 && s
->tsr_retry
< MAX_XMIT_RETRY
&&
252 qemu_chr_fe_add_watch(s
->chr
, G_IO_OUT
|G_IO_HUP
,
253 serial_xmit
, s
) > 0) {
262 /* Transmit another byte if it is already available. It is only
263 possible when FIFO is enabled and not empty. */
264 } while (!(s
->lsr
& UART_LSR_THRE
));
266 s
->last_xmit_ts
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
);
267 s
->lsr
|= UART_LSR_TEMT
;
274 is_load flag means, that value is set while loading VM state
275 and interrupt should not be invoked */
276 static void serial_write_fcr(SerialState
*s
, uint8_t val
)
278 /* Set fcr - val only has the bits that are supposed to "stick" */
281 if (val
& UART_FCR_FE
) {
282 s
->iir
|= UART_IIR_FE
;
283 /* Set recv_fifo trigger Level */
284 switch (val
& 0xC0) {
286 s
->recv_fifo_itl
= 1;
289 s
->recv_fifo_itl
= 4;
292 s
->recv_fifo_itl
= 8;
295 s
->recv_fifo_itl
= 14;
299 s
->iir
&= ~UART_IIR_FE
;
303 static void serial_ioport_write(void *opaque
, hwaddr addr
, uint64_t val
,
306 SerialState
*s
= opaque
;
309 DPRINTF("write addr=0x%" HWADDR_PRIx
" val=0x%" PRIx64
"\n", addr
, val
);
313 if (s
->lcr
& UART_LCR_DLAB
) {
314 s
->divider
= (s
->divider
& 0xff00) | val
;
315 serial_update_parameters(s
);
317 s
->thr
= (uint8_t) val
;
318 if(s
->fcr
& UART_FCR_FE
) {
319 /* xmit overruns overwrite data, so make space if needed */
320 if (fifo8_is_full(&s
->xmit_fifo
)) {
321 fifo8_pop(&s
->xmit_fifo
);
323 fifo8_push(&s
->xmit_fifo
, s
->thr
);
326 s
->lsr
&= ~UART_LSR_THRE
;
327 s
->lsr
&= ~UART_LSR_TEMT
;
328 serial_update_irq(s
);
329 if (s
->tsr_retry
<= 0) {
330 serial_xmit(NULL
, G_IO_OUT
, s
);
335 if (s
->lcr
& UART_LCR_DLAB
) {
336 s
->divider
= (s
->divider
& 0x00ff) | (val
<< 8);
337 serial_update_parameters(s
);
339 uint8_t changed
= (s
->ier
^ val
) & 0x0f;
341 /* If the backend device is a real serial port, turn polling of the modem
342 * status lines on physical port on or off depending on UART_IER_MSI state.
344 if ((changed
& UART_IER_MSI
) && s
->poll_msl
>= 0) {
345 if (s
->ier
& UART_IER_MSI
) {
347 serial_update_msl(s
);
349 timer_del(s
->modem_status_poll
);
354 /* Turning on the THRE interrupt on IER can trigger the interrupt
355 * if LSR.THRE=1, even if it had been masked before by reading IIR.
356 * This is not in the datasheet, but Windows relies on it. It is
357 * unclear if THRE has to be resampled every time THRI becomes
358 * 1, or only on the rising edge. Bochs does the latter, and Windows
359 * always toggles IER to all zeroes and back to all ones, so do the
362 * If IER.THRI is zero, thr_ipending is not used. Set it to zero
363 * so that the thr_ipending subsection is not migrated.
365 if (changed
& UART_IER_THRI
) {
366 if ((s
->ier
& UART_IER_THRI
) && (s
->lsr
& UART_LSR_THRE
)) {
374 serial_update_irq(s
);
379 /* Did the enable/disable flag change? If so, make sure FIFOs get flushed */
380 if ((val
^ s
->fcr
) & UART_FCR_FE
) {
381 val
|= UART_FCR_XFR
| UART_FCR_RFR
;
386 if (val
& UART_FCR_RFR
) {
387 s
->lsr
&= ~(UART_LSR_DR
| UART_LSR_BI
);
388 timer_del(s
->fifo_timeout_timer
);
389 s
->timeout_ipending
= 0;
390 fifo8_reset(&s
->recv_fifo
);
393 if (val
& UART_FCR_XFR
) {
394 s
->lsr
|= UART_LSR_THRE
;
396 fifo8_reset(&s
->xmit_fifo
);
399 serial_write_fcr(s
, val
& 0xC9);
400 serial_update_irq(s
);
406 serial_update_parameters(s
);
407 break_enable
= (val
>> 6) & 1;
408 if (break_enable
!= s
->last_break_enable
) {
409 s
->last_break_enable
= break_enable
;
410 qemu_chr_fe_ioctl(s
->chr
, CHR_IOCTL_SERIAL_SET_BREAK
,
418 int old_mcr
= s
->mcr
;
420 if (val
& UART_MCR_LOOP
)
423 if (s
->poll_msl
>= 0 && old_mcr
!= s
->mcr
) {
425 qemu_chr_fe_ioctl(s
->chr
,CHR_IOCTL_SERIAL_GET_TIOCM
, &flags
);
427 flags
&= ~(CHR_TIOCM_RTS
| CHR_TIOCM_DTR
);
429 if (val
& UART_MCR_RTS
)
430 flags
|= CHR_TIOCM_RTS
;
431 if (val
& UART_MCR_DTR
)
432 flags
|= CHR_TIOCM_DTR
;
434 qemu_chr_fe_ioctl(s
->chr
,CHR_IOCTL_SERIAL_SET_TIOCM
, &flags
);
435 /* Update the modem status after a one-character-send wait-time, since there may be a response
436 from the device/computer at the other end of the serial line */
437 timer_mod(s
->modem_status_poll
, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) + s
->char_transmit_time
);
451 static uint64_t serial_ioport_read(void *opaque
, hwaddr addr
, unsigned size
)
453 SerialState
*s
= opaque
;
460 if (s
->lcr
& UART_LCR_DLAB
) {
461 ret
= s
->divider
& 0xff;
463 if(s
->fcr
& UART_FCR_FE
) {
464 ret
= fifo8_is_empty(&s
->recv_fifo
) ?
465 0 : fifo8_pop(&s
->recv_fifo
);
466 if (s
->recv_fifo
.num
== 0) {
467 s
->lsr
&= ~(UART_LSR_DR
| UART_LSR_BI
);
469 timer_mod(s
->fifo_timeout_timer
, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) + s
->char_transmit_time
* 4);
471 s
->timeout_ipending
= 0;
474 s
->lsr
&= ~(UART_LSR_DR
| UART_LSR_BI
);
476 serial_update_irq(s
);
477 if (!(s
->mcr
& UART_MCR_LOOP
)) {
478 /* in loopback mode, don't receive any data */
479 qemu_chr_accept_input(s
->chr
);
484 if (s
->lcr
& UART_LCR_DLAB
) {
485 ret
= (s
->divider
>> 8) & 0xff;
492 if ((ret
& UART_IIR_ID
) == UART_IIR_THRI
) {
494 serial_update_irq(s
);
505 /* Clear break and overrun interrupts */
506 if (s
->lsr
& (UART_LSR_BI
|UART_LSR_OE
)) {
507 s
->lsr
&= ~(UART_LSR_BI
|UART_LSR_OE
);
508 serial_update_irq(s
);
512 if (s
->mcr
& UART_MCR_LOOP
) {
513 /* in loopback, the modem output pins are connected to the
515 ret
= (s
->mcr
& 0x0c) << 4;
516 ret
|= (s
->mcr
& 0x02) << 3;
517 ret
|= (s
->mcr
& 0x01) << 5;
519 if (s
->poll_msl
>= 0)
520 serial_update_msl(s
);
522 /* Clear delta bits & msr int after read, if they were set */
523 if (s
->msr
& UART_MSR_ANY_DELTA
) {
525 serial_update_irq(s
);
533 DPRINTF("read addr=0x%" HWADDR_PRIx
" val=0x%02x\n", addr
, ret
);
537 static int serial_can_receive(SerialState
*s
)
539 if(s
->fcr
& UART_FCR_FE
) {
540 if (s
->recv_fifo
.num
< UART_FIFO_LENGTH
) {
542 * Advertise (fifo.itl - fifo.count) bytes when count < ITL, and 1
543 * if above. If UART_FIFO_LENGTH - fifo.count is advertised the
544 * effect will be to almost always fill the fifo completely before
545 * the guest has a chance to respond, effectively overriding the ITL
546 * that the guest has set.
548 return (s
->recv_fifo
.num
<= s
->recv_fifo_itl
) ?
549 s
->recv_fifo_itl
- s
->recv_fifo
.num
: 1;
554 return !(s
->lsr
& UART_LSR_DR
);
558 static void serial_receive_break(SerialState
*s
)
561 /* When the LSR_DR is set a null byte is pushed into the fifo */
562 recv_fifo_put(s
, '\0');
563 s
->lsr
|= UART_LSR_BI
| UART_LSR_DR
;
564 serial_update_irq(s
);
567 /* There's data in recv_fifo and s->rbr has not been read for 4 char transmit times */
568 static void fifo_timeout_int (void *opaque
) {
569 SerialState
*s
= opaque
;
570 if (s
->recv_fifo
.num
) {
571 s
->timeout_ipending
= 1;
572 serial_update_irq(s
);
576 static int serial_can_receive1(void *opaque
)
578 SerialState
*s
= opaque
;
579 return serial_can_receive(s
);
582 static void serial_receive1(void *opaque
, const uint8_t *buf
, int size
)
584 SerialState
*s
= opaque
;
587 qemu_system_wakeup_request(QEMU_WAKEUP_REASON_OTHER
);
589 if(s
->fcr
& UART_FCR_FE
) {
591 for (i
= 0; i
< size
; i
++) {
592 recv_fifo_put(s
, buf
[i
]);
594 s
->lsr
|= UART_LSR_DR
;
595 /* call the timeout receive callback in 4 char transmit time */
596 timer_mod(s
->fifo_timeout_timer
, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) + s
->char_transmit_time
* 4);
598 if (s
->lsr
& UART_LSR_DR
)
599 s
->lsr
|= UART_LSR_OE
;
601 s
->lsr
|= UART_LSR_DR
;
603 serial_update_irq(s
);
606 static void serial_event(void *opaque
, int event
)
608 SerialState
*s
= opaque
;
609 DPRINTF("event %x\n", event
);
610 if (event
== CHR_EVENT_BREAK
)
611 serial_receive_break(s
);
614 static void serial_pre_save(void *opaque
)
616 SerialState
*s
= opaque
;
617 s
->fcr_vmstate
= s
->fcr
;
620 static int serial_pre_load(void *opaque
)
622 SerialState
*s
= opaque
;
623 s
->thr_ipending
= -1;
628 static int serial_post_load(void *opaque
, int version_id
)
630 SerialState
*s
= opaque
;
632 if (version_id
< 3) {
635 if (s
->thr_ipending
== -1) {
636 s
->thr_ipending
= ((s
->iir
& UART_IIR_ID
) == UART_IIR_THRI
);
638 s
->last_break_enable
= (s
->lcr
>> 6) & 1;
639 /* Initialize fcr via setter to perform essential side-effects */
640 serial_write_fcr(s
, s
->fcr_vmstate
);
641 serial_update_parameters(s
);
645 static bool serial_thr_ipending_needed(void *opaque
)
647 SerialState
*s
= opaque
;
649 if (s
->ier
& UART_IER_THRI
) {
650 bool expected_value
= ((s
->iir
& UART_IIR_ID
) == UART_IIR_THRI
);
651 return s
->thr_ipending
!= expected_value
;
653 /* LSR.THRE will be sampled again when the interrupt is
654 * enabled. thr_ipending is not used in this case, do
661 static const VMStateDescription vmstate_serial_thr_ipending
= {
662 .name
= "serial/thr_ipending",
664 .minimum_version_id
= 1,
665 .needed
= serial_thr_ipending_needed
,
666 .fields
= (VMStateField
[]) {
667 VMSTATE_INT32(thr_ipending
, SerialState
),
668 VMSTATE_END_OF_LIST()
672 static bool serial_tsr_needed(void *opaque
)
674 SerialState
*s
= (SerialState
*)opaque
;
675 return s
->tsr_retry
!= 0;
678 static const VMStateDescription vmstate_serial_tsr
= {
679 .name
= "serial/tsr",
681 .minimum_version_id
= 1,
682 .needed
= serial_tsr_needed
,
683 .fields
= (VMStateField
[]) {
684 VMSTATE_INT32(tsr_retry
, SerialState
),
685 VMSTATE_UINT8(thr
, SerialState
),
686 VMSTATE_UINT8(tsr
, SerialState
),
687 VMSTATE_END_OF_LIST()
691 static bool serial_recv_fifo_needed(void *opaque
)
693 SerialState
*s
= (SerialState
*)opaque
;
694 return !fifo8_is_empty(&s
->recv_fifo
);
698 static const VMStateDescription vmstate_serial_recv_fifo
= {
699 .name
= "serial/recv_fifo",
701 .minimum_version_id
= 1,
702 .needed
= serial_recv_fifo_needed
,
703 .fields
= (VMStateField
[]) {
704 VMSTATE_STRUCT(recv_fifo
, SerialState
, 1, vmstate_fifo8
, Fifo8
),
705 VMSTATE_END_OF_LIST()
709 static bool serial_xmit_fifo_needed(void *opaque
)
711 SerialState
*s
= (SerialState
*)opaque
;
712 return !fifo8_is_empty(&s
->xmit_fifo
);
715 static const VMStateDescription vmstate_serial_xmit_fifo
= {
716 .name
= "serial/xmit_fifo",
718 .minimum_version_id
= 1,
719 .needed
= serial_xmit_fifo_needed
,
720 .fields
= (VMStateField
[]) {
721 VMSTATE_STRUCT(xmit_fifo
, SerialState
, 1, vmstate_fifo8
, Fifo8
),
722 VMSTATE_END_OF_LIST()
726 static bool serial_fifo_timeout_timer_needed(void *opaque
)
728 SerialState
*s
= (SerialState
*)opaque
;
729 return timer_pending(s
->fifo_timeout_timer
);
732 static const VMStateDescription vmstate_serial_fifo_timeout_timer
= {
733 .name
= "serial/fifo_timeout_timer",
735 .minimum_version_id
= 1,
736 .needed
= serial_fifo_timeout_timer_needed
,
737 .fields
= (VMStateField
[]) {
738 VMSTATE_TIMER_PTR(fifo_timeout_timer
, SerialState
),
739 VMSTATE_END_OF_LIST()
743 static bool serial_timeout_ipending_needed(void *opaque
)
745 SerialState
*s
= (SerialState
*)opaque
;
746 return s
->timeout_ipending
!= 0;
749 static const VMStateDescription vmstate_serial_timeout_ipending
= {
750 .name
= "serial/timeout_ipending",
752 .minimum_version_id
= 1,
753 .needed
= serial_timeout_ipending_needed
,
754 .fields
= (VMStateField
[]) {
755 VMSTATE_INT32(timeout_ipending
, SerialState
),
756 VMSTATE_END_OF_LIST()
760 static bool serial_poll_needed(void *opaque
)
762 SerialState
*s
= (SerialState
*)opaque
;
763 return s
->poll_msl
>= 0;
766 static const VMStateDescription vmstate_serial_poll
= {
767 .name
= "serial/poll",
769 .needed
= serial_poll_needed
,
770 .minimum_version_id
= 1,
771 .fields
= (VMStateField
[]) {
772 VMSTATE_INT32(poll_msl
, SerialState
),
773 VMSTATE_TIMER_PTR(modem_status_poll
, SerialState
),
774 VMSTATE_END_OF_LIST()
778 const VMStateDescription vmstate_serial
= {
781 .minimum_version_id
= 2,
782 .pre_save
= serial_pre_save
,
783 .pre_load
= serial_pre_load
,
784 .post_load
= serial_post_load
,
785 .fields
= (VMStateField
[]) {
786 VMSTATE_UINT16_V(divider
, SerialState
, 2),
787 VMSTATE_UINT8(rbr
, SerialState
),
788 VMSTATE_UINT8(ier
, SerialState
),
789 VMSTATE_UINT8(iir
, SerialState
),
790 VMSTATE_UINT8(lcr
, SerialState
),
791 VMSTATE_UINT8(mcr
, SerialState
),
792 VMSTATE_UINT8(lsr
, SerialState
),
793 VMSTATE_UINT8(msr
, SerialState
),
794 VMSTATE_UINT8(scr
, SerialState
),
795 VMSTATE_UINT8_V(fcr_vmstate
, SerialState
, 3),
796 VMSTATE_END_OF_LIST()
798 .subsections
= (const VMStateDescription
*[]) {
799 &vmstate_serial_thr_ipending
,
801 &vmstate_serial_recv_fifo
,
802 &vmstate_serial_xmit_fifo
,
803 &vmstate_serial_fifo_timeout_timer
,
804 &vmstate_serial_timeout_ipending
,
805 &vmstate_serial_poll
,
810 static void serial_reset(void *opaque
)
812 SerialState
*s
= opaque
;
816 s
->iir
= UART_IIR_NO_INT
;
818 s
->lsr
= UART_LSR_TEMT
| UART_LSR_THRE
;
819 s
->msr
= UART_MSR_DCD
| UART_MSR_DSR
| UART_MSR_CTS
;
820 /* Default to 9600 baud, 1 start bit, 8 data bits, 1 stop bit, no parity. */
822 s
->mcr
= UART_MCR_OUT2
;
825 s
->char_transmit_time
= (get_ticks_per_sec() / 9600) * 10;
828 s
->timeout_ipending
= 0;
829 timer_del(s
->fifo_timeout_timer
);
830 timer_del(s
->modem_status_poll
);
832 fifo8_reset(&s
->recv_fifo
);
833 fifo8_reset(&s
->xmit_fifo
);
835 s
->last_xmit_ts
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
);
838 s
->last_break_enable
= 0;
839 qemu_irq_lower(s
->irq
);
841 serial_update_msl(s
);
842 s
->msr
&= ~UART_MSR_ANY_DELTA
;
845 void serial_realize_core(SerialState
*s
, Error
**errp
)
848 error_setg(errp
, "Can't create serial device, empty char device");
852 s
->modem_status_poll
= timer_new_ns(QEMU_CLOCK_VIRTUAL
, (QEMUTimerCB
*) serial_update_msl
, s
);
854 s
->fifo_timeout_timer
= timer_new_ns(QEMU_CLOCK_VIRTUAL
, (QEMUTimerCB
*) fifo_timeout_int
, s
);
855 qemu_register_reset(serial_reset
, s
);
857 qemu_chr_add_handlers(s
->chr
, serial_can_receive1
, serial_receive1
,
859 fifo8_create(&s
->recv_fifo
, UART_FIFO_LENGTH
);
860 fifo8_create(&s
->xmit_fifo
, UART_FIFO_LENGTH
);
864 void serial_exit_core(SerialState
*s
)
866 qemu_chr_add_handlers(s
->chr
, NULL
, NULL
, NULL
, NULL
);
867 qemu_unregister_reset(serial_reset
, s
);
870 /* Change the main reference oscillator frequency. */
871 void serial_set_frequency(SerialState
*s
, uint32_t frequency
)
873 s
->baudbase
= frequency
;
874 serial_update_parameters(s
);
877 const MemoryRegionOps serial_io_ops
= {
878 .read
= serial_ioport_read
,
879 .write
= serial_ioport_write
,
881 .min_access_size
= 1,
882 .max_access_size
= 1,
884 .endianness
= DEVICE_LITTLE_ENDIAN
,
887 SerialState
*serial_init(int base
, qemu_irq irq
, int baudbase
,
888 CharDriverState
*chr
, MemoryRegion
*system_io
)
893 s
= g_malloc0(sizeof(SerialState
));
896 s
->baudbase
= baudbase
;
898 serial_realize_core(s
, &err
);
900 error_report_err(err
);
904 vmstate_register(NULL
, base
, &vmstate_serial
, s
);
906 memory_region_init_io(&s
->io
, NULL
, &serial_io_ops
, s
, "serial", 8);
907 memory_region_add_subregion(system_io
, base
, &s
->io
);
912 /* Memory mapped interface */
913 static uint64_t serial_mm_read(void *opaque
, hwaddr addr
,
916 SerialState
*s
= opaque
;
917 return serial_ioport_read(s
, addr
>> s
->it_shift
, 1);
920 static void serial_mm_write(void *opaque
, hwaddr addr
,
921 uint64_t value
, unsigned size
)
923 SerialState
*s
= opaque
;
924 value
&= ~0u >> (32 - (size
* 8));
925 serial_ioport_write(s
, addr
>> s
->it_shift
, value
, 1);
928 static const MemoryRegionOps serial_mm_ops
[3] = {
929 [DEVICE_NATIVE_ENDIAN
] = {
930 .read
= serial_mm_read
,
931 .write
= serial_mm_write
,
932 .endianness
= DEVICE_NATIVE_ENDIAN
,
934 [DEVICE_LITTLE_ENDIAN
] = {
935 .read
= serial_mm_read
,
936 .write
= serial_mm_write
,
937 .endianness
= DEVICE_LITTLE_ENDIAN
,
939 [DEVICE_BIG_ENDIAN
] = {
940 .read
= serial_mm_read
,
941 .write
= serial_mm_write
,
942 .endianness
= DEVICE_BIG_ENDIAN
,
946 SerialState
*serial_mm_init(MemoryRegion
*address_space
,
947 hwaddr base
, int it_shift
,
948 qemu_irq irq
, int baudbase
,
949 CharDriverState
*chr
, enum device_endian end
)
954 s
= g_malloc0(sizeof(SerialState
));
956 s
->it_shift
= it_shift
;
958 s
->baudbase
= baudbase
;
961 serial_realize_core(s
, &err
);
963 error_report_err(err
);
966 vmstate_register(NULL
, base
, &vmstate_serial
, s
);
968 memory_region_init_io(&s
->io
, NULL
, &serial_mm_ops
[end
], s
,
969 "serial", 8 << it_shift
);
970 memory_region_add_subregion(address_space
, base
, &s
->io
);