2 * QEMU PowerPC 4xx embedded processors shared devices emulation
4 * Copyright (c) 2007 Jocelyn Mayer
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 #include "qemu/osdep.h"
26 #include "qemu/units.h"
27 #include "sysemu/reset.h"
30 #include "hw/ppc/ppc.h"
31 #include "hw/ppc/ppc4xx.h"
32 #include "hw/boards.h"
33 #include "hw/intc/ppc-uic.h"
34 #include "hw/qdev-properties.h"
36 #include "exec/address-spaces.h"
37 #include "qemu/error-report.h"
38 #include "qapi/error.h"
43 # define LOG_UIC(...) qemu_log_mask(CPU_LOG_INT, ## __VA_ARGS__)
45 # define LOG_UIC(...) do { } while (0)
48 static void ppc4xx_reset(void *opaque
)
50 PowerPCCPU
*cpu
= opaque
;
55 /*****************************************************************************/
56 /* Generic PowerPC 4xx processor instantiation */
57 PowerPCCPU
*ppc4xx_init(const char *cpu_type
,
58 clk_setup_t
*cpu_clk
, clk_setup_t
*tb_clk
,
65 cpu
= POWERPC_CPU(cpu_create(cpu_type
));
68 cpu_clk
->cb
= NULL
; /* We don't care about CPU clock frequency changes */
69 cpu_clk
->opaque
= env
;
70 /* Set time-base frequency to sysclk */
71 tb_clk
->cb
= ppc_40x_timers_init(env
, sysclk
, PPC_INTERRUPT_PIT
);
73 ppc_dcr_init(env
, NULL
, NULL
);
74 /* Register qemu callbacks */
75 qemu_register_reset(ppc4xx_reset
, cpu
);
80 /*****************************************************************************/
81 /* SDRAM controller */
82 typedef struct ppc4xx_sdram_t ppc4xx_sdram_t
;
83 struct ppc4xx_sdram_t
{
86 MemoryRegion containers
[4]; /* used for clipping */
87 MemoryRegion
*ram_memories
;
105 SDRAM0_CFGADDR
= 0x010,
106 SDRAM0_CFGDATA
= 0x011,
109 /* XXX: TOFIX: some patches have made this code become inconsistent:
110 * there are type inconsistencies, mixing hwaddr, target_ulong
113 static uint32_t sdram_bcr (hwaddr ram_base
,
141 printf("%s: invalid RAM size " TARGET_FMT_plx
"\n", __func__
,
145 bcr
|= ram_base
& 0xFF800000;
151 static inline hwaddr
sdram_base(uint32_t bcr
)
153 return bcr
& 0xFF800000;
156 static target_ulong
sdram_size (uint32_t bcr
)
161 sh
= (bcr
>> 17) & 0x7;
165 size
= (4 * MiB
) << sh
;
170 static void sdram_set_bcr(ppc4xx_sdram_t
*sdram
, int i
,
171 uint32_t bcr
, int enabled
)
173 if (sdram
->bcr
[i
] & 0x00000001) {
176 printf("%s: unmap RAM area " TARGET_FMT_plx
" " TARGET_FMT_lx
"\n",
177 __func__
, sdram_base(sdram
->bcr
[i
]), sdram_size(sdram
->bcr
[i
]));
179 memory_region_del_subregion(get_system_memory(),
180 &sdram
->containers
[i
]);
181 memory_region_del_subregion(&sdram
->containers
[i
],
182 &sdram
->ram_memories
[i
]);
183 object_unparent(OBJECT(&sdram
->containers
[i
]));
185 sdram
->bcr
[i
] = bcr
& 0xFFDEE001;
186 if (enabled
&& (bcr
& 0x00000001)) {
188 printf("%s: Map RAM area " TARGET_FMT_plx
" " TARGET_FMT_lx
"\n",
189 __func__
, sdram_base(bcr
), sdram_size(bcr
));
191 memory_region_init(&sdram
->containers
[i
], NULL
, "sdram-containers",
193 memory_region_add_subregion(&sdram
->containers
[i
], 0,
194 &sdram
->ram_memories
[i
]);
195 memory_region_add_subregion(get_system_memory(),
197 &sdram
->containers
[i
]);
201 static void sdram_map_bcr (ppc4xx_sdram_t
*sdram
)
205 for (i
= 0; i
< sdram
->nbanks
; i
++) {
206 if (sdram
->ram_sizes
[i
] != 0) {
207 sdram_set_bcr(sdram
, i
, sdram_bcr(sdram
->ram_bases
[i
],
208 sdram
->ram_sizes
[i
]), 1);
210 sdram_set_bcr(sdram
, i
, 0x00000000, 0);
215 static void sdram_unmap_bcr (ppc4xx_sdram_t
*sdram
)
219 for (i
= 0; i
< sdram
->nbanks
; i
++) {
221 printf("%s: Unmap RAM area " TARGET_FMT_plx
" " TARGET_FMT_lx
"\n",
222 __func__
, sdram_base(sdram
->bcr
[i
]), sdram_size(sdram
->bcr
[i
]));
224 memory_region_del_subregion(get_system_memory(),
225 &sdram
->ram_memories
[i
]);
229 static uint32_t dcr_read_sdram (void *opaque
, int dcrn
)
231 ppc4xx_sdram_t
*sdram
;
240 switch (sdram
->addr
) {
241 case 0x00: /* SDRAM_BESR0 */
244 case 0x08: /* SDRAM_BESR1 */
247 case 0x10: /* SDRAM_BEAR */
250 case 0x20: /* SDRAM_CFG */
253 case 0x24: /* SDRAM_STATUS */
256 case 0x30: /* SDRAM_RTR */
259 case 0x34: /* SDRAM_PMIT */
262 case 0x40: /* SDRAM_B0CR */
265 case 0x44: /* SDRAM_B1CR */
268 case 0x48: /* SDRAM_B2CR */
271 case 0x4C: /* SDRAM_B3CR */
274 case 0x80: /* SDRAM_TR */
277 case 0x94: /* SDRAM_ECCCFG */
280 case 0x98: /* SDRAM_ECCESR */
289 /* Avoid gcc warning */
297 static void dcr_write_sdram (void *opaque
, int dcrn
, uint32_t val
)
299 ppc4xx_sdram_t
*sdram
;
307 switch (sdram
->addr
) {
308 case 0x00: /* SDRAM_BESR0 */
309 sdram
->besr0
&= ~val
;
311 case 0x08: /* SDRAM_BESR1 */
312 sdram
->besr1
&= ~val
;
314 case 0x10: /* SDRAM_BEAR */
317 case 0x20: /* SDRAM_CFG */
319 if (!(sdram
->cfg
& 0x80000000) && (val
& 0x80000000)) {
321 printf("%s: enable SDRAM controller\n", __func__
);
323 /* validate all RAM mappings */
324 sdram_map_bcr(sdram
);
325 sdram
->status
&= ~0x80000000;
326 } else if ((sdram
->cfg
& 0x80000000) && !(val
& 0x80000000)) {
328 printf("%s: disable SDRAM controller\n", __func__
);
330 /* invalidate all RAM mappings */
331 sdram_unmap_bcr(sdram
);
332 sdram
->status
|= 0x80000000;
334 if (!(sdram
->cfg
& 0x40000000) && (val
& 0x40000000))
335 sdram
->status
|= 0x40000000;
336 else if ((sdram
->cfg
& 0x40000000) && !(val
& 0x40000000))
337 sdram
->status
&= ~0x40000000;
340 case 0x24: /* SDRAM_STATUS */
341 /* Read-only register */
343 case 0x30: /* SDRAM_RTR */
344 sdram
->rtr
= val
& 0x3FF80000;
346 case 0x34: /* SDRAM_PMIT */
347 sdram
->pmit
= (val
& 0xF8000000) | 0x07C00000;
349 case 0x40: /* SDRAM_B0CR */
350 sdram_set_bcr(sdram
, 0, val
, sdram
->cfg
& 0x80000000);
352 case 0x44: /* SDRAM_B1CR */
353 sdram_set_bcr(sdram
, 1, val
, sdram
->cfg
& 0x80000000);
355 case 0x48: /* SDRAM_B2CR */
356 sdram_set_bcr(sdram
, 2, val
, sdram
->cfg
& 0x80000000);
358 case 0x4C: /* SDRAM_B3CR */
359 sdram_set_bcr(sdram
, 3, val
, sdram
->cfg
& 0x80000000);
361 case 0x80: /* SDRAM_TR */
362 sdram
->tr
= val
& 0x018FC01F;
364 case 0x94: /* SDRAM_ECCCFG */
365 sdram
->ecccfg
= val
& 0x00F00000;
367 case 0x98: /* SDRAM_ECCESR */
369 if (sdram
->eccesr
== 0 && val
!= 0)
370 qemu_irq_raise(sdram
->irq
);
371 else if (sdram
->eccesr
!= 0 && val
== 0)
372 qemu_irq_lower(sdram
->irq
);
382 static void sdram_reset (void *opaque
)
384 ppc4xx_sdram_t
*sdram
;
387 sdram
->addr
= 0x00000000;
388 sdram
->bear
= 0x00000000;
389 sdram
->besr0
= 0x00000000; /* No error */
390 sdram
->besr1
= 0x00000000; /* No error */
391 sdram
->cfg
= 0x00000000;
392 sdram
->ecccfg
= 0x00000000; /* No ECC */
393 sdram
->eccesr
= 0x00000000; /* No error */
394 sdram
->pmit
= 0x07C00000;
395 sdram
->rtr
= 0x05F00000;
396 sdram
->tr
= 0x00854009;
397 /* We pre-initialize RAM banks */
398 sdram
->status
= 0x00000000;
399 sdram
->cfg
= 0x00800000;
402 void ppc4xx_sdram_init (CPUPPCState
*env
, qemu_irq irq
, int nbanks
,
403 MemoryRegion
*ram_memories
,
408 ppc4xx_sdram_t
*sdram
;
410 sdram
= g_malloc0(sizeof(ppc4xx_sdram_t
));
412 sdram
->nbanks
= nbanks
;
413 sdram
->ram_memories
= ram_memories
;
414 memset(sdram
->ram_bases
, 0, 4 * sizeof(hwaddr
));
415 memcpy(sdram
->ram_bases
, ram_bases
,
416 nbanks
* sizeof(hwaddr
));
417 memset(sdram
->ram_sizes
, 0, 4 * sizeof(hwaddr
));
418 memcpy(sdram
->ram_sizes
, ram_sizes
,
419 nbanks
* sizeof(hwaddr
));
420 qemu_register_reset(&sdram_reset
, sdram
);
421 ppc_dcr_register(env
, SDRAM0_CFGADDR
,
422 sdram
, &dcr_read_sdram
, &dcr_write_sdram
);
423 ppc_dcr_register(env
, SDRAM0_CFGDATA
,
424 sdram
, &dcr_read_sdram
, &dcr_write_sdram
);
426 sdram_map_bcr(sdram
);
430 * Split RAM between SDRAM banks.
432 * sdram_bank_sizes[] must be in descending order, that is sizes[i] > sizes[i+1]
433 * and must be 0-terminated.
435 * The 4xx SDRAM controller supports a small number of banks, and each bank
436 * must be one of a small set of sizes. The number of banks and the supported
437 * sizes varies by SoC.
439 void ppc4xx_sdram_banks(MemoryRegion
*ram
, int nr_banks
,
440 MemoryRegion ram_memories
[],
441 hwaddr ram_bases
[], hwaddr ram_sizes
[],
442 const ram_addr_t sdram_bank_sizes
[])
444 ram_addr_t size_left
= memory_region_size(ram
);
446 ram_addr_t bank_size
;
450 for (i
= 0; i
< nr_banks
; i
++) {
451 for (j
= 0; sdram_bank_sizes
[j
] != 0; j
++) {
452 bank_size
= sdram_bank_sizes
[j
];
453 if (bank_size
<= size_left
) {
457 ram_sizes
[i
] = bank_size
;
459 size_left
-= bank_size
;
460 snprintf(name
, sizeof(name
), "ppc4xx.sdram%d", i
);
461 memory_region_init_alias(&ram_memories
[i
], NULL
, name
, ram
,
462 ram_bases
[i
], ram_sizes
[i
]);
467 /* No need to use the remaining banks. */
473 ram_addr_t used_size
= memory_region_size(ram
) - size_left
;
474 GString
*s
= g_string_new(NULL
);
476 for (i
= 0; sdram_bank_sizes
[i
]; i
++) {
477 g_string_append_printf(s
, "%" PRIi64
"%s",
478 sdram_bank_sizes
[i
] / MiB
,
479 sdram_bank_sizes
[i
+ 1] ? ", " : "");
481 error_report("at most %d bank%s of %s MiB each supported",
482 nr_banks
, nr_banks
== 1 ? "" : "s", s
->str
);
483 error_printf("Possible valid RAM size: %" PRIi64
" MiB \n",
484 used_size
? used_size
/ MiB
: sdram_bank_sizes
[i
- 1] / MiB
);
486 g_string_free(s
, true);
491 /*****************************************************************************/
500 MAL0_TXEOBISR
= 0x186,
504 MAL0_RXEOBISR
= 0x192,
506 MAL0_TXCTP0R
= 0x1A0,
507 MAL0_RXCTP0R
= 0x1C0,
512 typedef struct ppc4xx_mal_t ppc4xx_mal_t
;
513 struct ppc4xx_mal_t
{
533 static void ppc4xx_mal_reset(void *opaque
)
538 mal
->cfg
= 0x0007C000;
539 mal
->esr
= 0x00000000;
540 mal
->ier
= 0x00000000;
541 mal
->rxcasr
= 0x00000000;
542 mal
->rxdeir
= 0x00000000;
543 mal
->rxeobisr
= 0x00000000;
544 mal
->txcasr
= 0x00000000;
545 mal
->txdeir
= 0x00000000;
546 mal
->txeobisr
= 0x00000000;
549 static uint32_t dcr_read_mal(void *opaque
, int dcrn
)
593 if (dcrn
>= MAL0_TXCTP0R
&& dcrn
< MAL0_TXCTP0R
+ mal
->txcnum
) {
594 ret
= mal
->txctpr
[dcrn
- MAL0_TXCTP0R
];
596 if (dcrn
>= MAL0_RXCTP0R
&& dcrn
< MAL0_RXCTP0R
+ mal
->rxcnum
) {
597 ret
= mal
->rxctpr
[dcrn
- MAL0_RXCTP0R
];
599 if (dcrn
>= MAL0_RCBS0
&& dcrn
< MAL0_RCBS0
+ mal
->rxcnum
) {
600 ret
= mal
->rcbs
[dcrn
- MAL0_RCBS0
];
606 static void dcr_write_mal(void *opaque
, int dcrn
, uint32_t val
)
613 if (val
& 0x80000000) {
614 ppc4xx_mal_reset(mal
);
616 mal
->cfg
= val
& 0x00FFC087;
623 mal
->ier
= val
& 0x0000001F;
626 mal
->txcasr
= val
& 0xF0000000;
629 mal
->txcarr
= val
& 0xF0000000;
633 mal
->txeobisr
&= ~val
;
640 mal
->rxcasr
= val
& 0xC0000000;
643 mal
->rxcarr
= val
& 0xC0000000;
647 mal
->rxeobisr
&= ~val
;
654 if (dcrn
>= MAL0_TXCTP0R
&& dcrn
< MAL0_TXCTP0R
+ mal
->txcnum
) {
655 mal
->txctpr
[dcrn
- MAL0_TXCTP0R
] = val
;
657 if (dcrn
>= MAL0_RXCTP0R
&& dcrn
< MAL0_RXCTP0R
+ mal
->rxcnum
) {
658 mal
->rxctpr
[dcrn
- MAL0_RXCTP0R
] = val
;
660 if (dcrn
>= MAL0_RCBS0
&& dcrn
< MAL0_RCBS0
+ mal
->rxcnum
) {
661 mal
->rcbs
[dcrn
- MAL0_RCBS0
] = val
& 0x000000FF;
665 void ppc4xx_mal_init(CPUPPCState
*env
, uint8_t txcnum
, uint8_t rxcnum
,
671 assert(txcnum
<= 32 && rxcnum
<= 32);
672 mal
= g_malloc0(sizeof(*mal
));
673 mal
->txcnum
= txcnum
;
674 mal
->rxcnum
= rxcnum
;
675 mal
->txctpr
= g_new0(uint32_t, txcnum
);
676 mal
->rxctpr
= g_new0(uint32_t, rxcnum
);
677 mal
->rcbs
= g_new0(uint32_t, rxcnum
);
678 for (i
= 0; i
< 4; i
++) {
679 mal
->irqs
[i
] = irqs
[i
];
681 qemu_register_reset(&ppc4xx_mal_reset
, mal
);
682 ppc_dcr_register(env
, MAL0_CFG
,
683 mal
, &dcr_read_mal
, &dcr_write_mal
);
684 ppc_dcr_register(env
, MAL0_ESR
,
685 mal
, &dcr_read_mal
, &dcr_write_mal
);
686 ppc_dcr_register(env
, MAL0_IER
,
687 mal
, &dcr_read_mal
, &dcr_write_mal
);
688 ppc_dcr_register(env
, MAL0_TXCASR
,
689 mal
, &dcr_read_mal
, &dcr_write_mal
);
690 ppc_dcr_register(env
, MAL0_TXCARR
,
691 mal
, &dcr_read_mal
, &dcr_write_mal
);
692 ppc_dcr_register(env
, MAL0_TXEOBISR
,
693 mal
, &dcr_read_mal
, &dcr_write_mal
);
694 ppc_dcr_register(env
, MAL0_TXDEIR
,
695 mal
, &dcr_read_mal
, &dcr_write_mal
);
696 ppc_dcr_register(env
, MAL0_RXCASR
,
697 mal
, &dcr_read_mal
, &dcr_write_mal
);
698 ppc_dcr_register(env
, MAL0_RXCARR
,
699 mal
, &dcr_read_mal
, &dcr_write_mal
);
700 ppc_dcr_register(env
, MAL0_RXEOBISR
,
701 mal
, &dcr_read_mal
, &dcr_write_mal
);
702 ppc_dcr_register(env
, MAL0_RXDEIR
,
703 mal
, &dcr_read_mal
, &dcr_write_mal
);
704 for (i
= 0; i
< txcnum
; i
++) {
705 ppc_dcr_register(env
, MAL0_TXCTP0R
+ i
,
706 mal
, &dcr_read_mal
, &dcr_write_mal
);
708 for (i
= 0; i
< rxcnum
; i
++) {
709 ppc_dcr_register(env
, MAL0_RXCTP0R
+ i
,
710 mal
, &dcr_read_mal
, &dcr_write_mal
);
712 for (i
= 0; i
< rxcnum
; i
++) {
713 ppc_dcr_register(env
, MAL0_RCBS0
+ i
,
714 mal
, &dcr_read_mal
, &dcr_write_mal
);