1 #include "qemu/osdep.h"
2 #include "target/arm/idau.h"
6 #include "exec/gdbstub.h"
7 #include "exec/helper-proto.h"
8 #include "qemu/host-utils.h"
9 #include "sysemu/arch_init.h"
10 #include "sysemu/sysemu.h"
11 #include "qemu/bitops.h"
12 #include "qemu/crc32c.h"
13 #include "exec/exec-all.h"
14 #include "exec/cpu_ldst.h"
16 #include <zlib.h> /* For crc32 */
17 #include "exec/semihost.h"
18 #include "sysemu/kvm.h"
19 #include "fpu/softfloat.h"
20 #include "qemu/range.h"
22 #define ARM_CPU_FREQ 1000000000 /* FIXME: 1 GHz, should be configurable */
24 #ifndef CONFIG_USER_ONLY
25 /* Cacheability and shareability attributes for a memory access */
26 typedef struct ARMCacheAttrs
{
27 unsigned int attrs
:8; /* as in the MAIR register encoding */
28 unsigned int shareability
:2; /* as in the SH field of the VMSAv8-64 PTEs */
31 static bool get_phys_addr(CPUARMState
*env
, target_ulong address
,
32 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
33 hwaddr
*phys_ptr
, MemTxAttrs
*attrs
, int *prot
,
34 target_ulong
*page_size
,
35 ARMMMUFaultInfo
*fi
, ARMCacheAttrs
*cacheattrs
);
37 static bool get_phys_addr_lpae(CPUARMState
*env
, target_ulong address
,
38 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
39 hwaddr
*phys_ptr
, MemTxAttrs
*txattrs
, int *prot
,
40 target_ulong
*page_size_ptr
,
41 ARMMMUFaultInfo
*fi
, ARMCacheAttrs
*cacheattrs
);
43 /* Security attributes for an address, as returned by v8m_security_lookup. */
44 typedef struct V8M_SAttributes
{
45 bool subpage
; /* true if these attrs don't cover the whole TARGET_PAGE */
54 static void v8m_security_lookup(CPUARMState
*env
, uint32_t address
,
55 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
56 V8M_SAttributes
*sattrs
);
59 static int vfp_gdb_get_reg(CPUARMState
*env
, uint8_t *buf
, int reg
)
63 /* VFP data registers are always little-endian. */
64 nregs
= arm_feature(env
, ARM_FEATURE_VFP3
) ? 32 : 16;
66 stq_le_p(buf
, *aa32_vfp_dreg(env
, reg
));
69 if (arm_feature(env
, ARM_FEATURE_NEON
)) {
70 /* Aliases for Q regs. */
73 uint64_t *q
= aa32_vfp_qreg(env
, reg
- 32);
75 stq_le_p(buf
+ 8, q
[1]);
79 switch (reg
- nregs
) {
80 case 0: stl_p(buf
, env
->vfp
.xregs
[ARM_VFP_FPSID
]); return 4;
81 case 1: stl_p(buf
, env
->vfp
.xregs
[ARM_VFP_FPSCR
]); return 4;
82 case 2: stl_p(buf
, env
->vfp
.xregs
[ARM_VFP_FPEXC
]); return 4;
87 static int vfp_gdb_set_reg(CPUARMState
*env
, uint8_t *buf
, int reg
)
91 nregs
= arm_feature(env
, ARM_FEATURE_VFP3
) ? 32 : 16;
93 *aa32_vfp_dreg(env
, reg
) = ldq_le_p(buf
);
96 if (arm_feature(env
, ARM_FEATURE_NEON
)) {
99 uint64_t *q
= aa32_vfp_qreg(env
, reg
- 32);
100 q
[0] = ldq_le_p(buf
);
101 q
[1] = ldq_le_p(buf
+ 8);
105 switch (reg
- nregs
) {
106 case 0: env
->vfp
.xregs
[ARM_VFP_FPSID
] = ldl_p(buf
); return 4;
107 case 1: env
->vfp
.xregs
[ARM_VFP_FPSCR
] = ldl_p(buf
); return 4;
108 case 2: env
->vfp
.xregs
[ARM_VFP_FPEXC
] = ldl_p(buf
) & (1 << 30); return 4;
113 static int aarch64_fpu_gdb_get_reg(CPUARMState
*env
, uint8_t *buf
, int reg
)
117 /* 128 bit FP register */
119 uint64_t *q
= aa64_vfp_qreg(env
, reg
);
121 stq_le_p(buf
+ 8, q
[1]);
126 stl_p(buf
, vfp_get_fpsr(env
));
130 stl_p(buf
, vfp_get_fpcr(env
));
137 static int aarch64_fpu_gdb_set_reg(CPUARMState
*env
, uint8_t *buf
, int reg
)
141 /* 128 bit FP register */
143 uint64_t *q
= aa64_vfp_qreg(env
, reg
);
144 q
[0] = ldq_le_p(buf
);
145 q
[1] = ldq_le_p(buf
+ 8);
150 vfp_set_fpsr(env
, ldl_p(buf
));
154 vfp_set_fpcr(env
, ldl_p(buf
));
161 static uint64_t raw_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
163 assert(ri
->fieldoffset
);
164 if (cpreg_field_is_64bit(ri
)) {
165 return CPREG_FIELD64(env
, ri
);
167 return CPREG_FIELD32(env
, ri
);
171 static void raw_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
174 assert(ri
->fieldoffset
);
175 if (cpreg_field_is_64bit(ri
)) {
176 CPREG_FIELD64(env
, ri
) = value
;
178 CPREG_FIELD32(env
, ri
) = value
;
182 static void *raw_ptr(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
184 return (char *)env
+ ri
->fieldoffset
;
187 uint64_t read_raw_cp_reg(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
189 /* Raw read of a coprocessor register (as needed for migration, etc). */
190 if (ri
->type
& ARM_CP_CONST
) {
191 return ri
->resetvalue
;
192 } else if (ri
->raw_readfn
) {
193 return ri
->raw_readfn(env
, ri
);
194 } else if (ri
->readfn
) {
195 return ri
->readfn(env
, ri
);
197 return raw_read(env
, ri
);
201 static void write_raw_cp_reg(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
204 /* Raw write of a coprocessor register (as needed for migration, etc).
205 * Note that constant registers are treated as write-ignored; the
206 * caller should check for success by whether a readback gives the
209 if (ri
->type
& ARM_CP_CONST
) {
211 } else if (ri
->raw_writefn
) {
212 ri
->raw_writefn(env
, ri
, v
);
213 } else if (ri
->writefn
) {
214 ri
->writefn(env
, ri
, v
);
216 raw_write(env
, ri
, v
);
220 static int arm_gdb_get_sysreg(CPUARMState
*env
, uint8_t *buf
, int reg
)
222 ARMCPU
*cpu
= arm_env_get_cpu(env
);
223 const ARMCPRegInfo
*ri
;
226 key
= cpu
->dyn_xml
.cpregs_keys
[reg
];
227 ri
= get_arm_cp_reginfo(cpu
->cp_regs
, key
);
229 if (cpreg_field_is_64bit(ri
)) {
230 return gdb_get_reg64(buf
, (uint64_t)read_raw_cp_reg(env
, ri
));
232 return gdb_get_reg32(buf
, (uint32_t)read_raw_cp_reg(env
, ri
));
238 static int arm_gdb_set_sysreg(CPUARMState
*env
, uint8_t *buf
, int reg
)
243 static bool raw_accessors_invalid(const ARMCPRegInfo
*ri
)
245 /* Return true if the regdef would cause an assertion if you called
246 * read_raw_cp_reg() or write_raw_cp_reg() on it (ie if it is a
247 * program bug for it not to have the NO_RAW flag).
248 * NB that returning false here doesn't necessarily mean that calling
249 * read/write_raw_cp_reg() is safe, because we can't distinguish "has
250 * read/write access functions which are safe for raw use" from "has
251 * read/write access functions which have side effects but has forgotten
252 * to provide raw access functions".
253 * The tests here line up with the conditions in read/write_raw_cp_reg()
254 * and assertions in raw_read()/raw_write().
256 if ((ri
->type
& ARM_CP_CONST
) ||
258 ((ri
->raw_writefn
|| ri
->writefn
) && (ri
->raw_readfn
|| ri
->readfn
))) {
264 bool write_cpustate_to_list(ARMCPU
*cpu
)
266 /* Write the coprocessor state from cpu->env to the (index,value) list. */
270 for (i
= 0; i
< cpu
->cpreg_array_len
; i
++) {
271 uint32_t regidx
= kvm_to_cpreg_id(cpu
->cpreg_indexes
[i
]);
272 const ARMCPRegInfo
*ri
;
274 ri
= get_arm_cp_reginfo(cpu
->cp_regs
, regidx
);
279 if (ri
->type
& ARM_CP_NO_RAW
) {
282 cpu
->cpreg_values
[i
] = read_raw_cp_reg(&cpu
->env
, ri
);
287 bool write_list_to_cpustate(ARMCPU
*cpu
)
292 for (i
= 0; i
< cpu
->cpreg_array_len
; i
++) {
293 uint32_t regidx
= kvm_to_cpreg_id(cpu
->cpreg_indexes
[i
]);
294 uint64_t v
= cpu
->cpreg_values
[i
];
295 const ARMCPRegInfo
*ri
;
297 ri
= get_arm_cp_reginfo(cpu
->cp_regs
, regidx
);
302 if (ri
->type
& ARM_CP_NO_RAW
) {
305 /* Write value and confirm it reads back as written
306 * (to catch read-only registers and partially read-only
307 * registers where the incoming migration value doesn't match)
309 write_raw_cp_reg(&cpu
->env
, ri
, v
);
310 if (read_raw_cp_reg(&cpu
->env
, ri
) != v
) {
317 static void add_cpreg_to_list(gpointer key
, gpointer opaque
)
319 ARMCPU
*cpu
= opaque
;
321 const ARMCPRegInfo
*ri
;
323 regidx
= *(uint32_t *)key
;
324 ri
= get_arm_cp_reginfo(cpu
->cp_regs
, regidx
);
326 if (!(ri
->type
& (ARM_CP_NO_RAW
|ARM_CP_ALIAS
))) {
327 cpu
->cpreg_indexes
[cpu
->cpreg_array_len
] = cpreg_to_kvm_id(regidx
);
328 /* The value array need not be initialized at this point */
329 cpu
->cpreg_array_len
++;
333 static void count_cpreg(gpointer key
, gpointer opaque
)
335 ARMCPU
*cpu
= opaque
;
337 const ARMCPRegInfo
*ri
;
339 regidx
= *(uint32_t *)key
;
340 ri
= get_arm_cp_reginfo(cpu
->cp_regs
, regidx
);
342 if (!(ri
->type
& (ARM_CP_NO_RAW
|ARM_CP_ALIAS
))) {
343 cpu
->cpreg_array_len
++;
347 static gint
cpreg_key_compare(gconstpointer a
, gconstpointer b
)
349 uint64_t aidx
= cpreg_to_kvm_id(*(uint32_t *)a
);
350 uint64_t bidx
= cpreg_to_kvm_id(*(uint32_t *)b
);
361 void init_cpreg_list(ARMCPU
*cpu
)
363 /* Initialise the cpreg_tuples[] array based on the cp_regs hash.
364 * Note that we require cpreg_tuples[] to be sorted by key ID.
369 keys
= g_hash_table_get_keys(cpu
->cp_regs
);
370 keys
= g_list_sort(keys
, cpreg_key_compare
);
372 cpu
->cpreg_array_len
= 0;
374 g_list_foreach(keys
, count_cpreg
, cpu
);
376 arraylen
= cpu
->cpreg_array_len
;
377 cpu
->cpreg_indexes
= g_new(uint64_t, arraylen
);
378 cpu
->cpreg_values
= g_new(uint64_t, arraylen
);
379 cpu
->cpreg_vmstate_indexes
= g_new(uint64_t, arraylen
);
380 cpu
->cpreg_vmstate_values
= g_new(uint64_t, arraylen
);
381 cpu
->cpreg_vmstate_array_len
= cpu
->cpreg_array_len
;
382 cpu
->cpreg_array_len
= 0;
384 g_list_foreach(keys
, add_cpreg_to_list
, cpu
);
386 assert(cpu
->cpreg_array_len
== arraylen
);
392 * Some registers are not accessible if EL3.NS=0 and EL3 is using AArch32 but
393 * they are accessible when EL3 is using AArch64 regardless of EL3.NS.
395 * access_el3_aa32ns: Used to check AArch32 register views.
396 * access_el3_aa32ns_aa64any: Used to check both AArch32/64 register views.
398 static CPAccessResult
access_el3_aa32ns(CPUARMState
*env
,
399 const ARMCPRegInfo
*ri
,
402 bool secure
= arm_is_secure_below_el3(env
);
404 assert(!arm_el_is_aa64(env
, 3));
406 return CP_ACCESS_TRAP_UNCATEGORIZED
;
411 static CPAccessResult
access_el3_aa32ns_aa64any(CPUARMState
*env
,
412 const ARMCPRegInfo
*ri
,
415 if (!arm_el_is_aa64(env
, 3)) {
416 return access_el3_aa32ns(env
, ri
, isread
);
421 /* Some secure-only AArch32 registers trap to EL3 if used from
422 * Secure EL1 (but are just ordinary UNDEF in other non-EL3 contexts).
423 * Note that an access from Secure EL1 can only happen if EL3 is AArch64.
424 * We assume that the .access field is set to PL1_RW.
426 static CPAccessResult
access_trap_aa32s_el1(CPUARMState
*env
,
427 const ARMCPRegInfo
*ri
,
430 if (arm_current_el(env
) == 3) {
433 if (arm_is_secure_below_el3(env
)) {
434 return CP_ACCESS_TRAP_EL3
;
436 /* This will be EL1 NS and EL2 NS, which just UNDEF */
437 return CP_ACCESS_TRAP_UNCATEGORIZED
;
440 /* Check for traps to "powerdown debug" registers, which are controlled
443 static CPAccessResult
access_tdosa(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
446 int el
= arm_current_el(env
);
447 bool mdcr_el2_tdosa
= (env
->cp15
.mdcr_el2
& MDCR_TDOSA
) ||
448 (env
->cp15
.mdcr_el2
& MDCR_TDE
) ||
449 (env
->cp15
.hcr_el2
& HCR_TGE
);
451 if (el
< 2 && mdcr_el2_tdosa
&& !arm_is_secure_below_el3(env
)) {
452 return CP_ACCESS_TRAP_EL2
;
454 if (el
< 3 && (env
->cp15
.mdcr_el3
& MDCR_TDOSA
)) {
455 return CP_ACCESS_TRAP_EL3
;
460 /* Check for traps to "debug ROM" registers, which are controlled
461 * by MDCR_EL2.TDRA for EL2 but by the more general MDCR_EL3.TDA for EL3.
463 static CPAccessResult
access_tdra(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
466 int el
= arm_current_el(env
);
467 bool mdcr_el2_tdra
= (env
->cp15
.mdcr_el2
& MDCR_TDRA
) ||
468 (env
->cp15
.mdcr_el2
& MDCR_TDE
) ||
469 (env
->cp15
.hcr_el2
& HCR_TGE
);
471 if (el
< 2 && mdcr_el2_tdra
&& !arm_is_secure_below_el3(env
)) {
472 return CP_ACCESS_TRAP_EL2
;
474 if (el
< 3 && (env
->cp15
.mdcr_el3
& MDCR_TDA
)) {
475 return CP_ACCESS_TRAP_EL3
;
480 /* Check for traps to general debug registers, which are controlled
481 * by MDCR_EL2.TDA for EL2 and MDCR_EL3.TDA for EL3.
483 static CPAccessResult
access_tda(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
486 int el
= arm_current_el(env
);
487 bool mdcr_el2_tda
= (env
->cp15
.mdcr_el2
& MDCR_TDA
) ||
488 (env
->cp15
.mdcr_el2
& MDCR_TDE
) ||
489 (env
->cp15
.hcr_el2
& HCR_TGE
);
491 if (el
< 2 && mdcr_el2_tda
&& !arm_is_secure_below_el3(env
)) {
492 return CP_ACCESS_TRAP_EL2
;
494 if (el
< 3 && (env
->cp15
.mdcr_el3
& MDCR_TDA
)) {
495 return CP_ACCESS_TRAP_EL3
;
500 /* Check for traps to performance monitor registers, which are controlled
501 * by MDCR_EL2.TPM for EL2 and MDCR_EL3.TPM for EL3.
503 static CPAccessResult
access_tpm(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
506 int el
= arm_current_el(env
);
508 if (el
< 2 && (env
->cp15
.mdcr_el2
& MDCR_TPM
)
509 && !arm_is_secure_below_el3(env
)) {
510 return CP_ACCESS_TRAP_EL2
;
512 if (el
< 3 && (env
->cp15
.mdcr_el3
& MDCR_TPM
)) {
513 return CP_ACCESS_TRAP_EL3
;
518 static void dacr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
520 ARMCPU
*cpu
= arm_env_get_cpu(env
);
522 raw_write(env
, ri
, value
);
523 tlb_flush(CPU(cpu
)); /* Flush TLB as domain not tracked in TLB */
526 static void fcse_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
528 ARMCPU
*cpu
= arm_env_get_cpu(env
);
530 if (raw_read(env
, ri
) != value
) {
531 /* Unlike real hardware the qemu TLB uses virtual addresses,
532 * not modified virtual addresses, so this causes a TLB flush.
535 raw_write(env
, ri
, value
);
539 static void contextidr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
542 ARMCPU
*cpu
= arm_env_get_cpu(env
);
544 if (raw_read(env
, ri
) != value
&& !arm_feature(env
, ARM_FEATURE_PMSA
)
545 && !extended_addresses_enabled(env
)) {
546 /* For VMSA (when not using the LPAE long descriptor page table
547 * format) this register includes the ASID, so do a TLB flush.
548 * For PMSA it is purely a process ID and no action is needed.
552 raw_write(env
, ri
, value
);
555 static void tlbiall_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
558 /* Invalidate all (TLBIALL) */
559 ARMCPU
*cpu
= arm_env_get_cpu(env
);
564 static void tlbimva_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
567 /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */
568 ARMCPU
*cpu
= arm_env_get_cpu(env
);
570 tlb_flush_page(CPU(cpu
), value
& TARGET_PAGE_MASK
);
573 static void tlbiasid_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
576 /* Invalidate by ASID (TLBIASID) */
577 ARMCPU
*cpu
= arm_env_get_cpu(env
);
582 static void tlbimvaa_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
585 /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */
586 ARMCPU
*cpu
= arm_env_get_cpu(env
);
588 tlb_flush_page(CPU(cpu
), value
& TARGET_PAGE_MASK
);
591 /* IS variants of TLB operations must affect all cores */
592 static void tlbiall_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
595 CPUState
*cs
= ENV_GET_CPU(env
);
597 tlb_flush_all_cpus_synced(cs
);
600 static void tlbiasid_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
603 CPUState
*cs
= ENV_GET_CPU(env
);
605 tlb_flush_all_cpus_synced(cs
);
608 static void tlbimva_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
611 CPUState
*cs
= ENV_GET_CPU(env
);
613 tlb_flush_page_all_cpus_synced(cs
, value
& TARGET_PAGE_MASK
);
616 static void tlbimvaa_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
619 CPUState
*cs
= ENV_GET_CPU(env
);
621 tlb_flush_page_all_cpus_synced(cs
, value
& TARGET_PAGE_MASK
);
624 static void tlbiall_nsnh_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
627 CPUState
*cs
= ENV_GET_CPU(env
);
629 tlb_flush_by_mmuidx(cs
,
630 ARMMMUIdxBit_S12NSE1
|
631 ARMMMUIdxBit_S12NSE0
|
635 static void tlbiall_nsnh_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
638 CPUState
*cs
= ENV_GET_CPU(env
);
640 tlb_flush_by_mmuidx_all_cpus_synced(cs
,
641 ARMMMUIdxBit_S12NSE1
|
642 ARMMMUIdxBit_S12NSE0
|
646 static void tlbiipas2_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
649 /* Invalidate by IPA. This has to invalidate any structures that
650 * contain only stage 2 translation information, but does not need
651 * to apply to structures that contain combined stage 1 and stage 2
652 * translation information.
653 * This must NOP if EL2 isn't implemented or SCR_EL3.NS is zero.
655 CPUState
*cs
= ENV_GET_CPU(env
);
658 if (!arm_feature(env
, ARM_FEATURE_EL2
) || !(env
->cp15
.scr_el3
& SCR_NS
)) {
662 pageaddr
= sextract64(value
<< 12, 0, 40);
664 tlb_flush_page_by_mmuidx(cs
, pageaddr
, ARMMMUIdxBit_S2NS
);
667 static void tlbiipas2_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
670 CPUState
*cs
= ENV_GET_CPU(env
);
673 if (!arm_feature(env
, ARM_FEATURE_EL2
) || !(env
->cp15
.scr_el3
& SCR_NS
)) {
677 pageaddr
= sextract64(value
<< 12, 0, 40);
679 tlb_flush_page_by_mmuidx_all_cpus_synced(cs
, pageaddr
,
683 static void tlbiall_hyp_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
686 CPUState
*cs
= ENV_GET_CPU(env
);
688 tlb_flush_by_mmuidx(cs
, ARMMMUIdxBit_S1E2
);
691 static void tlbiall_hyp_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
694 CPUState
*cs
= ENV_GET_CPU(env
);
696 tlb_flush_by_mmuidx_all_cpus_synced(cs
, ARMMMUIdxBit_S1E2
);
699 static void tlbimva_hyp_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
702 CPUState
*cs
= ENV_GET_CPU(env
);
703 uint64_t pageaddr
= value
& ~MAKE_64BIT_MASK(0, 12);
705 tlb_flush_page_by_mmuidx(cs
, pageaddr
, ARMMMUIdxBit_S1E2
);
708 static void tlbimva_hyp_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
711 CPUState
*cs
= ENV_GET_CPU(env
);
712 uint64_t pageaddr
= value
& ~MAKE_64BIT_MASK(0, 12);
714 tlb_flush_page_by_mmuidx_all_cpus_synced(cs
, pageaddr
,
718 static const ARMCPRegInfo cp_reginfo
[] = {
719 /* Define the secure and non-secure FCSE identifier CP registers
720 * separately because there is no secure bank in V8 (no _EL3). This allows
721 * the secure register to be properly reset and migrated. There is also no
722 * v8 EL1 version of the register so the non-secure instance stands alone.
725 .cp
= 15, .opc1
= 0, .crn
= 13, .crm
= 0, .opc2
= 0,
726 .access
= PL1_RW
, .secure
= ARM_CP_SECSTATE_NS
,
727 .fieldoffset
= offsetof(CPUARMState
, cp15
.fcseidr_ns
),
728 .resetvalue
= 0, .writefn
= fcse_write
, .raw_writefn
= raw_write
, },
729 { .name
= "FCSEIDR_S",
730 .cp
= 15, .opc1
= 0, .crn
= 13, .crm
= 0, .opc2
= 0,
731 .access
= PL1_RW
, .secure
= ARM_CP_SECSTATE_S
,
732 .fieldoffset
= offsetof(CPUARMState
, cp15
.fcseidr_s
),
733 .resetvalue
= 0, .writefn
= fcse_write
, .raw_writefn
= raw_write
, },
734 /* Define the secure and non-secure context identifier CP registers
735 * separately because there is no secure bank in V8 (no _EL3). This allows
736 * the secure register to be properly reset and migrated. In the
737 * non-secure case, the 32-bit register will have reset and migration
738 * disabled during registration as it is handled by the 64-bit instance.
740 { .name
= "CONTEXTIDR_EL1", .state
= ARM_CP_STATE_BOTH
,
741 .opc0
= 3, .opc1
= 0, .crn
= 13, .crm
= 0, .opc2
= 1,
742 .access
= PL1_RW
, .secure
= ARM_CP_SECSTATE_NS
,
743 .fieldoffset
= offsetof(CPUARMState
, cp15
.contextidr_el
[1]),
744 .resetvalue
= 0, .writefn
= contextidr_write
, .raw_writefn
= raw_write
, },
745 { .name
= "CONTEXTIDR_S", .state
= ARM_CP_STATE_AA32
,
746 .cp
= 15, .opc1
= 0, .crn
= 13, .crm
= 0, .opc2
= 1,
747 .access
= PL1_RW
, .secure
= ARM_CP_SECSTATE_S
,
748 .fieldoffset
= offsetof(CPUARMState
, cp15
.contextidr_s
),
749 .resetvalue
= 0, .writefn
= contextidr_write
, .raw_writefn
= raw_write
, },
753 static const ARMCPRegInfo not_v8_cp_reginfo
[] = {
754 /* NB: Some of these registers exist in v8 but with more precise
755 * definitions that don't use CP_ANY wildcards (mostly in v8_cp_reginfo[]).
757 /* MMU Domain access control / MPU write buffer control */
759 .cp
= 15, .opc1
= CP_ANY
, .crn
= 3, .crm
= CP_ANY
, .opc2
= CP_ANY
,
760 .access
= PL1_RW
, .resetvalue
= 0,
761 .writefn
= dacr_write
, .raw_writefn
= raw_write
,
762 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.dacr_s
),
763 offsetoflow32(CPUARMState
, cp15
.dacr_ns
) } },
764 /* ARMv7 allocates a range of implementation defined TLB LOCKDOWN regs.
765 * For v6 and v5, these mappings are overly broad.
767 { .name
= "TLB_LOCKDOWN", .cp
= 15, .crn
= 10, .crm
= 0,
768 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
769 { .name
= "TLB_LOCKDOWN", .cp
= 15, .crn
= 10, .crm
= 1,
770 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
771 { .name
= "TLB_LOCKDOWN", .cp
= 15, .crn
= 10, .crm
= 4,
772 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
773 { .name
= "TLB_LOCKDOWN", .cp
= 15, .crn
= 10, .crm
= 8,
774 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
775 /* Cache maintenance ops; some of this space may be overridden later. */
776 { .name
= "CACHEMAINT", .cp
= 15, .crn
= 7, .crm
= CP_ANY
,
777 .opc1
= 0, .opc2
= CP_ANY
, .access
= PL1_W
,
778 .type
= ARM_CP_NOP
| ARM_CP_OVERRIDE
},
782 static const ARMCPRegInfo not_v6_cp_reginfo
[] = {
783 /* Not all pre-v6 cores implemented this WFI, so this is slightly
786 { .name
= "WFI_v5", .cp
= 15, .crn
= 7, .crm
= 8, .opc1
= 0, .opc2
= 2,
787 .access
= PL1_W
, .type
= ARM_CP_WFI
},
791 static const ARMCPRegInfo not_v7_cp_reginfo
[] = {
792 /* Standard v6 WFI (also used in some pre-v6 cores); not in v7 (which
793 * is UNPREDICTABLE; we choose to NOP as most implementations do).
795 { .name
= "WFI_v6", .cp
= 15, .crn
= 7, .crm
= 0, .opc1
= 0, .opc2
= 4,
796 .access
= PL1_W
, .type
= ARM_CP_WFI
},
797 /* L1 cache lockdown. Not architectural in v6 and earlier but in practice
798 * implemented in 926, 946, 1026, 1136, 1176 and 11MPCore. StrongARM and
799 * OMAPCP will override this space.
801 { .name
= "DLOCKDOWN", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 0, .opc2
= 0,
802 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_data
),
804 { .name
= "ILOCKDOWN", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 0, .opc2
= 1,
805 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_insn
),
807 /* v6 doesn't have the cache ID registers but Linux reads them anyway */
808 { .name
= "DUMMY", .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 1, .opc2
= CP_ANY
,
809 .access
= PL1_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
811 /* We don't implement pre-v7 debug but most CPUs had at least a DBGDIDR;
812 * implementing it as RAZ means the "debug architecture version" bits
813 * will read as a reserved value, which should cause Linux to not try
814 * to use the debug hardware.
816 { .name
= "DBGDIDR", .cp
= 14, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 0,
817 .access
= PL0_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
818 /* MMU TLB control. Note that the wildcarding means we cover not just
819 * the unified TLB ops but also the dside/iside/inner-shareable variants.
821 { .name
= "TLBIALL", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
822 .opc1
= CP_ANY
, .opc2
= 0, .access
= PL1_W
, .writefn
= tlbiall_write
,
823 .type
= ARM_CP_NO_RAW
},
824 { .name
= "TLBIMVA", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
825 .opc1
= CP_ANY
, .opc2
= 1, .access
= PL1_W
, .writefn
= tlbimva_write
,
826 .type
= ARM_CP_NO_RAW
},
827 { .name
= "TLBIASID", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
828 .opc1
= CP_ANY
, .opc2
= 2, .access
= PL1_W
, .writefn
= tlbiasid_write
,
829 .type
= ARM_CP_NO_RAW
},
830 { .name
= "TLBIMVAA", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
831 .opc1
= CP_ANY
, .opc2
= 3, .access
= PL1_W
, .writefn
= tlbimvaa_write
,
832 .type
= ARM_CP_NO_RAW
},
833 { .name
= "PRRR", .cp
= 15, .crn
= 10, .crm
= 2,
834 .opc1
= 0, .opc2
= 0, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
835 { .name
= "NMRR", .cp
= 15, .crn
= 10, .crm
= 2,
836 .opc1
= 0, .opc2
= 1, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
840 static void cpacr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
845 /* In ARMv8 most bits of CPACR_EL1 are RES0. */
846 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
847 /* ARMv7 defines bits for unimplemented coprocessors as RAZ/WI.
848 * ASEDIS [31] and D32DIS [30] are both UNK/SBZP without VFP.
849 * TRCDIS [28] is RAZ/WI since we do not implement a trace macrocell.
851 if (arm_feature(env
, ARM_FEATURE_VFP
)) {
852 /* VFP coprocessor: cp10 & cp11 [23:20] */
853 mask
|= (1 << 31) | (1 << 30) | (0xf << 20);
855 if (!arm_feature(env
, ARM_FEATURE_NEON
)) {
856 /* ASEDIS [31] bit is RAO/WI */
860 /* VFPv3 and upwards with NEON implement 32 double precision
861 * registers (D0-D31).
863 if (!arm_feature(env
, ARM_FEATURE_NEON
) ||
864 !arm_feature(env
, ARM_FEATURE_VFP3
)) {
865 /* D32DIS [30] is RAO/WI if D16-31 are not implemented. */
871 env
->cp15
.cpacr_el1
= value
;
874 static void cpacr_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
876 /* Call cpacr_write() so that we reset with the correct RAO bits set
877 * for our CPU features.
879 cpacr_write(env
, ri
, 0);
882 static CPAccessResult
cpacr_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
885 if (arm_feature(env
, ARM_FEATURE_V8
)) {
886 /* Check if CPACR accesses are to be trapped to EL2 */
887 if (arm_current_el(env
) == 1 &&
888 (env
->cp15
.cptr_el
[2] & CPTR_TCPAC
) && !arm_is_secure(env
)) {
889 return CP_ACCESS_TRAP_EL2
;
890 /* Check if CPACR accesses are to be trapped to EL3 */
891 } else if (arm_current_el(env
) < 3 &&
892 (env
->cp15
.cptr_el
[3] & CPTR_TCPAC
)) {
893 return CP_ACCESS_TRAP_EL3
;
900 static CPAccessResult
cptr_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
903 /* Check if CPTR accesses are set to trap to EL3 */
904 if (arm_current_el(env
) == 2 && (env
->cp15
.cptr_el
[3] & CPTR_TCPAC
)) {
905 return CP_ACCESS_TRAP_EL3
;
911 static const ARMCPRegInfo v6_cp_reginfo
[] = {
912 /* prefetch by MVA in v6, NOP in v7 */
913 { .name
= "MVA_prefetch",
914 .cp
= 15, .crn
= 7, .crm
= 13, .opc1
= 0, .opc2
= 1,
915 .access
= PL1_W
, .type
= ARM_CP_NOP
},
916 /* We need to break the TB after ISB to execute self-modifying code
917 * correctly and also to take any pending interrupts immediately.
918 * So use arm_cp_write_ignore() function instead of ARM_CP_NOP flag.
920 { .name
= "ISB", .cp
= 15, .crn
= 7, .crm
= 5, .opc1
= 0, .opc2
= 4,
921 .access
= PL0_W
, .type
= ARM_CP_NO_RAW
, .writefn
= arm_cp_write_ignore
},
922 { .name
= "DSB", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 4,
923 .access
= PL0_W
, .type
= ARM_CP_NOP
},
924 { .name
= "DMB", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 5,
925 .access
= PL0_W
, .type
= ARM_CP_NOP
},
926 { .name
= "IFAR", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 2,
928 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ifar_s
),
929 offsetof(CPUARMState
, cp15
.ifar_ns
) },
931 /* Watchpoint Fault Address Register : should actually only be present
932 * for 1136, 1176, 11MPCore.
934 { .name
= "WFAR", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 1,
935 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0, },
936 { .name
= "CPACR", .state
= ARM_CP_STATE_BOTH
, .opc0
= 3,
937 .crn
= 1, .crm
= 0, .opc1
= 0, .opc2
= 2, .accessfn
= cpacr_access
,
938 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.cpacr_el1
),
939 .resetfn
= cpacr_reset
, .writefn
= cpacr_write
},
943 /* Definitions for the PMU registers */
944 #define PMCRN_MASK 0xf800
945 #define PMCRN_SHIFT 11
950 static inline uint32_t pmu_num_counters(CPUARMState
*env
)
952 return (env
->cp15
.c9_pmcr
& PMCRN_MASK
) >> PMCRN_SHIFT
;
955 /* Bits allowed to be set/cleared for PMCNTEN* and PMINTEN* */
956 static inline uint64_t pmu_counter_mask(CPUARMState
*env
)
958 return (1 << 31) | ((1 << pmu_num_counters(env
)) - 1);
961 static CPAccessResult
pmreg_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
964 /* Performance monitor registers user accessibility is controlled
965 * by PMUSERENR. MDCR_EL2.TPM and MDCR_EL3.TPM allow configurable
966 * trapping to EL2 or EL3 for other accesses.
968 int el
= arm_current_el(env
);
970 if (el
== 0 && !(env
->cp15
.c9_pmuserenr
& 1)) {
971 return CP_ACCESS_TRAP
;
973 if (el
< 2 && (env
->cp15
.mdcr_el2
& MDCR_TPM
)
974 && !arm_is_secure_below_el3(env
)) {
975 return CP_ACCESS_TRAP_EL2
;
977 if (el
< 3 && (env
->cp15
.mdcr_el3
& MDCR_TPM
)) {
978 return CP_ACCESS_TRAP_EL3
;
984 static CPAccessResult
pmreg_access_xevcntr(CPUARMState
*env
,
985 const ARMCPRegInfo
*ri
,
988 /* ER: event counter read trap control */
989 if (arm_feature(env
, ARM_FEATURE_V8
)
990 && arm_current_el(env
) == 0
991 && (env
->cp15
.c9_pmuserenr
& (1 << 3)) != 0
996 return pmreg_access(env
, ri
, isread
);
999 static CPAccessResult
pmreg_access_swinc(CPUARMState
*env
,
1000 const ARMCPRegInfo
*ri
,
1003 /* SW: software increment write trap control */
1004 if (arm_feature(env
, ARM_FEATURE_V8
)
1005 && arm_current_el(env
) == 0
1006 && (env
->cp15
.c9_pmuserenr
& (1 << 1)) != 0
1008 return CP_ACCESS_OK
;
1011 return pmreg_access(env
, ri
, isread
);
1014 #ifndef CONFIG_USER_ONLY
1016 static CPAccessResult
pmreg_access_selr(CPUARMState
*env
,
1017 const ARMCPRegInfo
*ri
,
1020 /* ER: event counter read trap control */
1021 if (arm_feature(env
, ARM_FEATURE_V8
)
1022 && arm_current_el(env
) == 0
1023 && (env
->cp15
.c9_pmuserenr
& (1 << 3)) != 0) {
1024 return CP_ACCESS_OK
;
1027 return pmreg_access(env
, ri
, isread
);
1030 static CPAccessResult
pmreg_access_ccntr(CPUARMState
*env
,
1031 const ARMCPRegInfo
*ri
,
1034 /* CR: cycle counter read trap control */
1035 if (arm_feature(env
, ARM_FEATURE_V8
)
1036 && arm_current_el(env
) == 0
1037 && (env
->cp15
.c9_pmuserenr
& (1 << 2)) != 0
1039 return CP_ACCESS_OK
;
1042 return pmreg_access(env
, ri
, isread
);
1045 static inline bool arm_ccnt_enabled(CPUARMState
*env
)
1047 /* This does not support checking PMCCFILTR_EL0 register */
1049 if (!(env
->cp15
.c9_pmcr
& PMCRE
) || !(env
->cp15
.c9_pmcnten
& (1 << 31))) {
1056 void pmccntr_sync(CPUARMState
*env
)
1058 uint64_t temp_ticks
;
1060 temp_ticks
= muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
),
1061 ARM_CPU_FREQ
, NANOSECONDS_PER_SECOND
);
1063 if (env
->cp15
.c9_pmcr
& PMCRD
) {
1064 /* Increment once every 64 processor clock cycles */
1068 if (arm_ccnt_enabled(env
)) {
1069 env
->cp15
.c15_ccnt
= temp_ticks
- env
->cp15
.c15_ccnt
;
1073 static void pmcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1078 if (value
& PMCRC
) {
1079 /* The counter has been reset */
1080 env
->cp15
.c15_ccnt
= 0;
1083 /* only the DP, X, D and E bits are writable */
1084 env
->cp15
.c9_pmcr
&= ~0x39;
1085 env
->cp15
.c9_pmcr
|= (value
& 0x39);
1090 static uint64_t pmccntr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1092 uint64_t total_ticks
;
1094 if (!arm_ccnt_enabled(env
)) {
1095 /* Counter is disabled, do not change value */
1096 return env
->cp15
.c15_ccnt
;
1099 total_ticks
= muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
),
1100 ARM_CPU_FREQ
, NANOSECONDS_PER_SECOND
);
1102 if (env
->cp15
.c9_pmcr
& PMCRD
) {
1103 /* Increment once every 64 processor clock cycles */
1106 return total_ticks
- env
->cp15
.c15_ccnt
;
1109 static void pmselr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1112 /* The value of PMSELR.SEL affects the behavior of PMXEVTYPER and
1113 * PMXEVCNTR. We allow [0..31] to be written to PMSELR here; in the
1114 * meanwhile, we check PMSELR.SEL when PMXEVTYPER and PMXEVCNTR are
1117 env
->cp15
.c9_pmselr
= value
& 0x1f;
1120 static void pmccntr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1123 uint64_t total_ticks
;
1125 if (!arm_ccnt_enabled(env
)) {
1126 /* Counter is disabled, set the absolute value */
1127 env
->cp15
.c15_ccnt
= value
;
1131 total_ticks
= muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
),
1132 ARM_CPU_FREQ
, NANOSECONDS_PER_SECOND
);
1134 if (env
->cp15
.c9_pmcr
& PMCRD
) {
1135 /* Increment once every 64 processor clock cycles */
1138 env
->cp15
.c15_ccnt
= total_ticks
- value
;
1141 static void pmccntr_write32(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1144 uint64_t cur_val
= pmccntr_read(env
, NULL
);
1146 pmccntr_write(env
, ri
, deposit64(cur_val
, 0, 32, value
));
1149 #else /* CONFIG_USER_ONLY */
1151 void pmccntr_sync(CPUARMState
*env
)
1157 static void pmccfiltr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1161 env
->cp15
.pmccfiltr_el0
= value
& 0xfc000000;
1165 static void pmcntenset_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1168 value
&= pmu_counter_mask(env
);
1169 env
->cp15
.c9_pmcnten
|= value
;
1172 static void pmcntenclr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1175 value
&= pmu_counter_mask(env
);
1176 env
->cp15
.c9_pmcnten
&= ~value
;
1179 static void pmovsr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1182 env
->cp15
.c9_pmovsr
&= ~value
;
1185 static void pmxevtyper_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1188 /* Attempts to access PMXEVTYPER are CONSTRAINED UNPREDICTABLE when
1189 * PMSELR value is equal to or greater than the number of implemented
1190 * counters, but not equal to 0x1f. We opt to behave as a RAZ/WI.
1192 if (env
->cp15
.c9_pmselr
== 0x1f) {
1193 pmccfiltr_write(env
, ri
, value
);
1197 static uint64_t pmxevtyper_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1199 /* We opt to behave as a RAZ/WI when attempts to access PMXEVTYPER
1200 * are CONSTRAINED UNPREDICTABLE. See comments in pmxevtyper_write().
1202 if (env
->cp15
.c9_pmselr
== 0x1f) {
1203 return env
->cp15
.pmccfiltr_el0
;
1209 static void pmuserenr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1212 if (arm_feature(env
, ARM_FEATURE_V8
)) {
1213 env
->cp15
.c9_pmuserenr
= value
& 0xf;
1215 env
->cp15
.c9_pmuserenr
= value
& 1;
1219 static void pmintenset_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1222 /* We have no event counters so only the C bit can be changed */
1223 value
&= pmu_counter_mask(env
);
1224 env
->cp15
.c9_pminten
|= value
;
1227 static void pmintenclr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1230 value
&= pmu_counter_mask(env
);
1231 env
->cp15
.c9_pminten
&= ~value
;
1234 static void vbar_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1237 /* Note that even though the AArch64 view of this register has bits
1238 * [10:0] all RES0 we can only mask the bottom 5, to comply with the
1239 * architectural requirements for bits which are RES0 only in some
1240 * contexts. (ARMv8 would permit us to do no masking at all, but ARMv7
1241 * requires the bottom five bits to be RAZ/WI because they're UNK/SBZP.)
1243 raw_write(env
, ri
, value
& ~0x1FULL
);
1246 static void scr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
1248 /* We only mask off bits that are RES0 both for AArch64 and AArch32.
1249 * For bits that vary between AArch32/64, code needs to check the
1250 * current execution mode before directly using the feature bit.
1252 uint32_t valid_mask
= SCR_AARCH64_MASK
| SCR_AARCH32_MASK
;
1254 if (!arm_feature(env
, ARM_FEATURE_EL2
)) {
1255 valid_mask
&= ~SCR_HCE
;
1257 /* On ARMv7, SMD (or SCD as it is called in v7) is only
1258 * supported if EL2 exists. The bit is UNK/SBZP when
1259 * EL2 is unavailable. In QEMU ARMv7, we force it to always zero
1260 * when EL2 is unavailable.
1261 * On ARMv8, this bit is always available.
1263 if (arm_feature(env
, ARM_FEATURE_V7
) &&
1264 !arm_feature(env
, ARM_FEATURE_V8
)) {
1265 valid_mask
&= ~SCR_SMD
;
1269 /* Clear all-context RES0 bits. */
1270 value
&= valid_mask
;
1271 raw_write(env
, ri
, value
);
1274 static uint64_t ccsidr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1276 ARMCPU
*cpu
= arm_env_get_cpu(env
);
1278 /* Acquire the CSSELR index from the bank corresponding to the CCSIDR
1281 uint32_t index
= A32_BANKED_REG_GET(env
, csselr
,
1282 ri
->secure
& ARM_CP_SECSTATE_S
);
1284 return cpu
->ccsidr
[index
];
1287 static void csselr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1290 raw_write(env
, ri
, value
& 0xf);
1293 static uint64_t isr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1295 CPUState
*cs
= ENV_GET_CPU(env
);
1298 if (cs
->interrupt_request
& CPU_INTERRUPT_HARD
) {
1301 if (cs
->interrupt_request
& CPU_INTERRUPT_FIQ
) {
1304 /* External aborts are not possible in QEMU so A bit is always clear */
1308 static const ARMCPRegInfo v7_cp_reginfo
[] = {
1309 /* the old v6 WFI, UNPREDICTABLE in v7 but we choose to NOP */
1310 { .name
= "NOP", .cp
= 15, .crn
= 7, .crm
= 0, .opc1
= 0, .opc2
= 4,
1311 .access
= PL1_W
, .type
= ARM_CP_NOP
},
1312 /* Performance monitors are implementation defined in v7,
1313 * but with an ARM recommended set of registers, which we
1314 * follow (although we don't actually implement any counters)
1316 * Performance registers fall into three categories:
1317 * (a) always UNDEF in PL0, RW in PL1 (PMINTENSET, PMINTENCLR)
1318 * (b) RO in PL0 (ie UNDEF on write), RW in PL1 (PMUSERENR)
1319 * (c) UNDEF in PL0 if PMUSERENR.EN==0, otherwise accessible (all others)
1320 * For the cases controlled by PMUSERENR we must set .access to PL0_RW
1321 * or PL0_RO as appropriate and then check PMUSERENR in the helper fn.
1323 { .name
= "PMCNTENSET", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 1,
1324 .access
= PL0_RW
, .type
= ARM_CP_ALIAS
,
1325 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmcnten
),
1326 .writefn
= pmcntenset_write
,
1327 .accessfn
= pmreg_access
,
1328 .raw_writefn
= raw_write
},
1329 { .name
= "PMCNTENSET_EL0", .state
= ARM_CP_STATE_AA64
,
1330 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 1,
1331 .access
= PL0_RW
, .accessfn
= pmreg_access
,
1332 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmcnten
), .resetvalue
= 0,
1333 .writefn
= pmcntenset_write
, .raw_writefn
= raw_write
},
1334 { .name
= "PMCNTENCLR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 2,
1336 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmcnten
),
1337 .accessfn
= pmreg_access
,
1338 .writefn
= pmcntenclr_write
,
1339 .type
= ARM_CP_ALIAS
},
1340 { .name
= "PMCNTENCLR_EL0", .state
= ARM_CP_STATE_AA64
,
1341 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 2,
1342 .access
= PL0_RW
, .accessfn
= pmreg_access
,
1343 .type
= ARM_CP_ALIAS
,
1344 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmcnten
),
1345 .writefn
= pmcntenclr_write
},
1346 { .name
= "PMOVSR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 3,
1348 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmovsr
),
1349 .accessfn
= pmreg_access
,
1350 .writefn
= pmovsr_write
,
1351 .raw_writefn
= raw_write
},
1352 { .name
= "PMOVSCLR_EL0", .state
= ARM_CP_STATE_AA64
,
1353 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 3,
1354 .access
= PL0_RW
, .accessfn
= pmreg_access
,
1355 .type
= ARM_CP_ALIAS
,
1356 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmovsr
),
1357 .writefn
= pmovsr_write
,
1358 .raw_writefn
= raw_write
},
1359 /* Unimplemented so WI. */
1360 { .name
= "PMSWINC", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 4,
1361 .access
= PL0_W
, .accessfn
= pmreg_access_swinc
, .type
= ARM_CP_NOP
},
1362 #ifndef CONFIG_USER_ONLY
1363 { .name
= "PMSELR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 5,
1364 .access
= PL0_RW
, .type
= ARM_CP_ALIAS
,
1365 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmselr
),
1366 .accessfn
= pmreg_access_selr
, .writefn
= pmselr_write
,
1367 .raw_writefn
= raw_write
},
1368 { .name
= "PMSELR_EL0", .state
= ARM_CP_STATE_AA64
,
1369 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 5,
1370 .access
= PL0_RW
, .accessfn
= pmreg_access_selr
,
1371 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmselr
),
1372 .writefn
= pmselr_write
, .raw_writefn
= raw_write
, },
1373 { .name
= "PMCCNTR", .cp
= 15, .crn
= 9, .crm
= 13, .opc1
= 0, .opc2
= 0,
1374 .access
= PL0_RW
, .resetvalue
= 0, .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
1375 .readfn
= pmccntr_read
, .writefn
= pmccntr_write32
,
1376 .accessfn
= pmreg_access_ccntr
},
1377 { .name
= "PMCCNTR_EL0", .state
= ARM_CP_STATE_AA64
,
1378 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 13, .opc2
= 0,
1379 .access
= PL0_RW
, .accessfn
= pmreg_access_ccntr
,
1381 .readfn
= pmccntr_read
, .writefn
= pmccntr_write
, },
1383 { .name
= "PMCCFILTR_EL0", .state
= ARM_CP_STATE_AA64
,
1384 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 15, .opc2
= 7,
1385 .writefn
= pmccfiltr_write
,
1386 .access
= PL0_RW
, .accessfn
= pmreg_access
,
1388 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmccfiltr_el0
),
1390 { .name
= "PMXEVTYPER", .cp
= 15, .crn
= 9, .crm
= 13, .opc1
= 0, .opc2
= 1,
1391 .access
= PL0_RW
, .type
= ARM_CP_NO_RAW
, .accessfn
= pmreg_access
,
1392 .writefn
= pmxevtyper_write
, .readfn
= pmxevtyper_read
},
1393 { .name
= "PMXEVTYPER_EL0", .state
= ARM_CP_STATE_AA64
,
1394 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 13, .opc2
= 1,
1395 .access
= PL0_RW
, .type
= ARM_CP_NO_RAW
, .accessfn
= pmreg_access
,
1396 .writefn
= pmxevtyper_write
, .readfn
= pmxevtyper_read
},
1397 /* Unimplemented, RAZ/WI. */
1398 { .name
= "PMXEVCNTR", .cp
= 15, .crn
= 9, .crm
= 13, .opc1
= 0, .opc2
= 2,
1399 .access
= PL0_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0,
1400 .accessfn
= pmreg_access_xevcntr
},
1401 { .name
= "PMUSERENR", .cp
= 15, .crn
= 9, .crm
= 14, .opc1
= 0, .opc2
= 0,
1402 .access
= PL0_R
| PL1_RW
, .accessfn
= access_tpm
,
1403 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmuserenr
),
1405 .writefn
= pmuserenr_write
, .raw_writefn
= raw_write
},
1406 { .name
= "PMUSERENR_EL0", .state
= ARM_CP_STATE_AA64
,
1407 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 14, .opc2
= 0,
1408 .access
= PL0_R
| PL1_RW
, .accessfn
= access_tpm
, .type
= ARM_CP_ALIAS
,
1409 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmuserenr
),
1411 .writefn
= pmuserenr_write
, .raw_writefn
= raw_write
},
1412 { .name
= "PMINTENSET", .cp
= 15, .crn
= 9, .crm
= 14, .opc1
= 0, .opc2
= 1,
1413 .access
= PL1_RW
, .accessfn
= access_tpm
,
1414 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
1415 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pminten
),
1417 .writefn
= pmintenset_write
, .raw_writefn
= raw_write
},
1418 { .name
= "PMINTENSET_EL1", .state
= ARM_CP_STATE_AA64
,
1419 .opc0
= 3, .opc1
= 0, .crn
= 9, .crm
= 14, .opc2
= 1,
1420 .access
= PL1_RW
, .accessfn
= access_tpm
,
1422 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pminten
),
1423 .writefn
= pmintenset_write
, .raw_writefn
= raw_write
,
1424 .resetvalue
= 0x0 },
1425 { .name
= "PMINTENCLR", .cp
= 15, .crn
= 9, .crm
= 14, .opc1
= 0, .opc2
= 2,
1426 .access
= PL1_RW
, .accessfn
= access_tpm
, .type
= ARM_CP_ALIAS
,
1427 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pminten
),
1428 .writefn
= pmintenclr_write
, },
1429 { .name
= "PMINTENCLR_EL1", .state
= ARM_CP_STATE_AA64
,
1430 .opc0
= 3, .opc1
= 0, .crn
= 9, .crm
= 14, .opc2
= 2,
1431 .access
= PL1_RW
, .accessfn
= access_tpm
, .type
= ARM_CP_ALIAS
,
1432 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pminten
),
1433 .writefn
= pmintenclr_write
},
1434 { .name
= "CCSIDR", .state
= ARM_CP_STATE_BOTH
,
1435 .opc0
= 3, .crn
= 0, .crm
= 0, .opc1
= 1, .opc2
= 0,
1436 .access
= PL1_R
, .readfn
= ccsidr_read
, .type
= ARM_CP_NO_RAW
},
1437 { .name
= "CSSELR", .state
= ARM_CP_STATE_BOTH
,
1438 .opc0
= 3, .crn
= 0, .crm
= 0, .opc1
= 2, .opc2
= 0,
1439 .access
= PL1_RW
, .writefn
= csselr_write
, .resetvalue
= 0,
1440 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.csselr_s
),
1441 offsetof(CPUARMState
, cp15
.csselr_ns
) } },
1442 /* Auxiliary ID register: this actually has an IMPDEF value but for now
1443 * just RAZ for all cores:
1445 { .name
= "AIDR", .state
= ARM_CP_STATE_BOTH
,
1446 .opc0
= 3, .opc1
= 1, .crn
= 0, .crm
= 0, .opc2
= 7,
1447 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
1448 /* Auxiliary fault status registers: these also are IMPDEF, and we
1449 * choose to RAZ/WI for all cores.
1451 { .name
= "AFSR0_EL1", .state
= ARM_CP_STATE_BOTH
,
1452 .opc0
= 3, .opc1
= 0, .crn
= 5, .crm
= 1, .opc2
= 0,
1453 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
1454 { .name
= "AFSR1_EL1", .state
= ARM_CP_STATE_BOTH
,
1455 .opc0
= 3, .opc1
= 0, .crn
= 5, .crm
= 1, .opc2
= 1,
1456 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
1457 /* MAIR can just read-as-written because we don't implement caches
1458 * and so don't need to care about memory attributes.
1460 { .name
= "MAIR_EL1", .state
= ARM_CP_STATE_AA64
,
1461 .opc0
= 3, .opc1
= 0, .crn
= 10, .crm
= 2, .opc2
= 0,
1462 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.mair_el
[1]),
1464 { .name
= "MAIR_EL3", .state
= ARM_CP_STATE_AA64
,
1465 .opc0
= 3, .opc1
= 6, .crn
= 10, .crm
= 2, .opc2
= 0,
1466 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.mair_el
[3]),
1468 /* For non-long-descriptor page tables these are PRRR and NMRR;
1469 * regardless they still act as reads-as-written for QEMU.
1471 /* MAIR0/1 are defined separately from their 64-bit counterpart which
1472 * allows them to assign the correct fieldoffset based on the endianness
1473 * handled in the field definitions.
1475 { .name
= "MAIR0", .state
= ARM_CP_STATE_AA32
,
1476 .cp
= 15, .opc1
= 0, .crn
= 10, .crm
= 2, .opc2
= 0, .access
= PL1_RW
,
1477 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.mair0_s
),
1478 offsetof(CPUARMState
, cp15
.mair0_ns
) },
1479 .resetfn
= arm_cp_reset_ignore
},
1480 { .name
= "MAIR1", .state
= ARM_CP_STATE_AA32
,
1481 .cp
= 15, .opc1
= 0, .crn
= 10, .crm
= 2, .opc2
= 1, .access
= PL1_RW
,
1482 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.mair1_s
),
1483 offsetof(CPUARMState
, cp15
.mair1_ns
) },
1484 .resetfn
= arm_cp_reset_ignore
},
1485 { .name
= "ISR_EL1", .state
= ARM_CP_STATE_BOTH
,
1486 .opc0
= 3, .opc1
= 0, .crn
= 12, .crm
= 1, .opc2
= 0,
1487 .type
= ARM_CP_NO_RAW
, .access
= PL1_R
, .readfn
= isr_read
},
1488 /* 32 bit ITLB invalidates */
1489 { .name
= "ITLBIALL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 0,
1490 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbiall_write
},
1491 { .name
= "ITLBIMVA", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 1,
1492 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbimva_write
},
1493 { .name
= "ITLBIASID", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 2,
1494 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbiasid_write
},
1495 /* 32 bit DTLB invalidates */
1496 { .name
= "DTLBIALL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 0,
1497 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbiall_write
},
1498 { .name
= "DTLBIMVA", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 1,
1499 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbimva_write
},
1500 { .name
= "DTLBIASID", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 2,
1501 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbiasid_write
},
1502 /* 32 bit TLB invalidates */
1503 { .name
= "TLBIALL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 0,
1504 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbiall_write
},
1505 { .name
= "TLBIMVA", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 1,
1506 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbimva_write
},
1507 { .name
= "TLBIASID", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 2,
1508 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbiasid_write
},
1509 { .name
= "TLBIMVAA", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 3,
1510 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbimvaa_write
},
1514 static const ARMCPRegInfo v7mp_cp_reginfo
[] = {
1515 /* 32 bit TLB invalidates, Inner Shareable */
1516 { .name
= "TLBIALLIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 0,
1517 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbiall_is_write
},
1518 { .name
= "TLBIMVAIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 1,
1519 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbimva_is_write
},
1520 { .name
= "TLBIASIDIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 2,
1521 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
,
1522 .writefn
= tlbiasid_is_write
},
1523 { .name
= "TLBIMVAAIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 3,
1524 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
,
1525 .writefn
= tlbimvaa_is_write
},
1529 static void teecr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1536 static CPAccessResult
teehbr_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1539 if (arm_current_el(env
) == 0 && (env
->teecr
& 1)) {
1540 return CP_ACCESS_TRAP
;
1542 return CP_ACCESS_OK
;
1545 static const ARMCPRegInfo t2ee_cp_reginfo
[] = {
1546 { .name
= "TEECR", .cp
= 14, .crn
= 0, .crm
= 0, .opc1
= 6, .opc2
= 0,
1547 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, teecr
),
1549 .writefn
= teecr_write
},
1550 { .name
= "TEEHBR", .cp
= 14, .crn
= 1, .crm
= 0, .opc1
= 6, .opc2
= 0,
1551 .access
= PL0_RW
, .fieldoffset
= offsetof(CPUARMState
, teehbr
),
1552 .accessfn
= teehbr_access
, .resetvalue
= 0 },
1556 static const ARMCPRegInfo v6k_cp_reginfo
[] = {
1557 { .name
= "TPIDR_EL0", .state
= ARM_CP_STATE_AA64
,
1558 .opc0
= 3, .opc1
= 3, .opc2
= 2, .crn
= 13, .crm
= 0,
1560 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidr_el
[0]), .resetvalue
= 0 },
1561 { .name
= "TPIDRURW", .cp
= 15, .crn
= 13, .crm
= 0, .opc1
= 0, .opc2
= 2,
1563 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.tpidrurw_s
),
1564 offsetoflow32(CPUARMState
, cp15
.tpidrurw_ns
) },
1565 .resetfn
= arm_cp_reset_ignore
},
1566 { .name
= "TPIDRRO_EL0", .state
= ARM_CP_STATE_AA64
,
1567 .opc0
= 3, .opc1
= 3, .opc2
= 3, .crn
= 13, .crm
= 0,
1568 .access
= PL0_R
|PL1_W
,
1569 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidrro_el
[0]),
1571 { .name
= "TPIDRURO", .cp
= 15, .crn
= 13, .crm
= 0, .opc1
= 0, .opc2
= 3,
1572 .access
= PL0_R
|PL1_W
,
1573 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.tpidruro_s
),
1574 offsetoflow32(CPUARMState
, cp15
.tpidruro_ns
) },
1575 .resetfn
= arm_cp_reset_ignore
},
1576 { .name
= "TPIDR_EL1", .state
= ARM_CP_STATE_AA64
,
1577 .opc0
= 3, .opc1
= 0, .opc2
= 4, .crn
= 13, .crm
= 0,
1579 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidr_el
[1]), .resetvalue
= 0 },
1580 { .name
= "TPIDRPRW", .opc1
= 0, .cp
= 15, .crn
= 13, .crm
= 0, .opc2
= 4,
1582 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.tpidrprw_s
),
1583 offsetoflow32(CPUARMState
, cp15
.tpidrprw_ns
) },
1588 #ifndef CONFIG_USER_ONLY
1590 static CPAccessResult
gt_cntfrq_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1593 /* CNTFRQ: not visible from PL0 if both PL0PCTEN and PL0VCTEN are zero.
1594 * Writable only at the highest implemented exception level.
1596 int el
= arm_current_el(env
);
1600 if (!extract32(env
->cp15
.c14_cntkctl
, 0, 2)) {
1601 return CP_ACCESS_TRAP
;
1605 if (!isread
&& ri
->state
== ARM_CP_STATE_AA32
&&
1606 arm_is_secure_below_el3(env
)) {
1607 /* Accesses from 32-bit Secure EL1 UNDEF (*not* trap to EL3!) */
1608 return CP_ACCESS_TRAP_UNCATEGORIZED
;
1616 if (!isread
&& el
< arm_highest_el(env
)) {
1617 return CP_ACCESS_TRAP_UNCATEGORIZED
;
1620 return CP_ACCESS_OK
;
1623 static CPAccessResult
gt_counter_access(CPUARMState
*env
, int timeridx
,
1626 unsigned int cur_el
= arm_current_el(env
);
1627 bool secure
= arm_is_secure(env
);
1629 /* CNT[PV]CT: not visible from PL0 if ELO[PV]CTEN is zero */
1631 !extract32(env
->cp15
.c14_cntkctl
, timeridx
, 1)) {
1632 return CP_ACCESS_TRAP
;
1635 if (arm_feature(env
, ARM_FEATURE_EL2
) &&
1636 timeridx
== GTIMER_PHYS
&& !secure
&& cur_el
< 2 &&
1637 !extract32(env
->cp15
.cnthctl_el2
, 0, 1)) {
1638 return CP_ACCESS_TRAP_EL2
;
1640 return CP_ACCESS_OK
;
1643 static CPAccessResult
gt_timer_access(CPUARMState
*env
, int timeridx
,
1646 unsigned int cur_el
= arm_current_el(env
);
1647 bool secure
= arm_is_secure(env
);
1649 /* CNT[PV]_CVAL, CNT[PV]_CTL, CNT[PV]_TVAL: not visible from PL0 if
1650 * EL0[PV]TEN is zero.
1653 !extract32(env
->cp15
.c14_cntkctl
, 9 - timeridx
, 1)) {
1654 return CP_ACCESS_TRAP
;
1657 if (arm_feature(env
, ARM_FEATURE_EL2
) &&
1658 timeridx
== GTIMER_PHYS
&& !secure
&& cur_el
< 2 &&
1659 !extract32(env
->cp15
.cnthctl_el2
, 1, 1)) {
1660 return CP_ACCESS_TRAP_EL2
;
1662 return CP_ACCESS_OK
;
1665 static CPAccessResult
gt_pct_access(CPUARMState
*env
,
1666 const ARMCPRegInfo
*ri
,
1669 return gt_counter_access(env
, GTIMER_PHYS
, isread
);
1672 static CPAccessResult
gt_vct_access(CPUARMState
*env
,
1673 const ARMCPRegInfo
*ri
,
1676 return gt_counter_access(env
, GTIMER_VIRT
, isread
);
1679 static CPAccessResult
gt_ptimer_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1682 return gt_timer_access(env
, GTIMER_PHYS
, isread
);
1685 static CPAccessResult
gt_vtimer_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1688 return gt_timer_access(env
, GTIMER_VIRT
, isread
);
1691 static CPAccessResult
gt_stimer_access(CPUARMState
*env
,
1692 const ARMCPRegInfo
*ri
,
1695 /* The AArch64 register view of the secure physical timer is
1696 * always accessible from EL3, and configurably accessible from
1699 switch (arm_current_el(env
)) {
1701 if (!arm_is_secure(env
)) {
1702 return CP_ACCESS_TRAP
;
1704 if (!(env
->cp15
.scr_el3
& SCR_ST
)) {
1705 return CP_ACCESS_TRAP_EL3
;
1707 return CP_ACCESS_OK
;
1710 return CP_ACCESS_TRAP
;
1712 return CP_ACCESS_OK
;
1714 g_assert_not_reached();
1718 static uint64_t gt_get_countervalue(CPUARMState
*env
)
1720 return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) / GTIMER_SCALE
;
1723 static void gt_recalc_timer(ARMCPU
*cpu
, int timeridx
)
1725 ARMGenericTimer
*gt
= &cpu
->env
.cp15
.c14_timer
[timeridx
];
1728 /* Timer enabled: calculate and set current ISTATUS, irq, and
1729 * reset timer to when ISTATUS next has to change
1731 uint64_t offset
= timeridx
== GTIMER_VIRT
?
1732 cpu
->env
.cp15
.cntvoff_el2
: 0;
1733 uint64_t count
= gt_get_countervalue(&cpu
->env
);
1734 /* Note that this must be unsigned 64 bit arithmetic: */
1735 int istatus
= count
- offset
>= gt
->cval
;
1739 gt
->ctl
= deposit32(gt
->ctl
, 2, 1, istatus
);
1741 irqstate
= (istatus
&& !(gt
->ctl
& 2));
1742 qemu_set_irq(cpu
->gt_timer_outputs
[timeridx
], irqstate
);
1745 /* Next transition is when count rolls back over to zero */
1746 nexttick
= UINT64_MAX
;
1748 /* Next transition is when we hit cval */
1749 nexttick
= gt
->cval
+ offset
;
1751 /* Note that the desired next expiry time might be beyond the
1752 * signed-64-bit range of a QEMUTimer -- in this case we just
1753 * set the timer for as far in the future as possible. When the
1754 * timer expires we will reset the timer for any remaining period.
1756 if (nexttick
> INT64_MAX
/ GTIMER_SCALE
) {
1757 nexttick
= INT64_MAX
/ GTIMER_SCALE
;
1759 timer_mod(cpu
->gt_timer
[timeridx
], nexttick
);
1760 trace_arm_gt_recalc(timeridx
, irqstate
, nexttick
);
1762 /* Timer disabled: ISTATUS and timer output always clear */
1764 qemu_set_irq(cpu
->gt_timer_outputs
[timeridx
], 0);
1765 timer_del(cpu
->gt_timer
[timeridx
]);
1766 trace_arm_gt_recalc_disabled(timeridx
);
1770 static void gt_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1773 ARMCPU
*cpu
= arm_env_get_cpu(env
);
1775 timer_del(cpu
->gt_timer
[timeridx
]);
1778 static uint64_t gt_cnt_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1780 return gt_get_countervalue(env
);
1783 static uint64_t gt_virt_cnt_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1785 return gt_get_countervalue(env
) - env
->cp15
.cntvoff_el2
;
1788 static void gt_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1792 trace_arm_gt_cval_write(timeridx
, value
);
1793 env
->cp15
.c14_timer
[timeridx
].cval
= value
;
1794 gt_recalc_timer(arm_env_get_cpu(env
), timeridx
);
1797 static uint64_t gt_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1800 uint64_t offset
= timeridx
== GTIMER_VIRT
? env
->cp15
.cntvoff_el2
: 0;
1802 return (uint32_t)(env
->cp15
.c14_timer
[timeridx
].cval
-
1803 (gt_get_countervalue(env
) - offset
));
1806 static void gt_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1810 uint64_t offset
= timeridx
== GTIMER_VIRT
? env
->cp15
.cntvoff_el2
: 0;
1812 trace_arm_gt_tval_write(timeridx
, value
);
1813 env
->cp15
.c14_timer
[timeridx
].cval
= gt_get_countervalue(env
) - offset
+
1814 sextract64(value
, 0, 32);
1815 gt_recalc_timer(arm_env_get_cpu(env
), timeridx
);
1818 static void gt_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1822 ARMCPU
*cpu
= arm_env_get_cpu(env
);
1823 uint32_t oldval
= env
->cp15
.c14_timer
[timeridx
].ctl
;
1825 trace_arm_gt_ctl_write(timeridx
, value
);
1826 env
->cp15
.c14_timer
[timeridx
].ctl
= deposit64(oldval
, 0, 2, value
);
1827 if ((oldval
^ value
) & 1) {
1828 /* Enable toggled */
1829 gt_recalc_timer(cpu
, timeridx
);
1830 } else if ((oldval
^ value
) & 2) {
1831 /* IMASK toggled: don't need to recalculate,
1832 * just set the interrupt line based on ISTATUS
1834 int irqstate
= (oldval
& 4) && !(value
& 2);
1836 trace_arm_gt_imask_toggle(timeridx
, irqstate
);
1837 qemu_set_irq(cpu
->gt_timer_outputs
[timeridx
], irqstate
);
1841 static void gt_phys_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1843 gt_timer_reset(env
, ri
, GTIMER_PHYS
);
1846 static void gt_phys_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1849 gt_cval_write(env
, ri
, GTIMER_PHYS
, value
);
1852 static uint64_t gt_phys_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1854 return gt_tval_read(env
, ri
, GTIMER_PHYS
);
1857 static void gt_phys_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1860 gt_tval_write(env
, ri
, GTIMER_PHYS
, value
);
1863 static void gt_phys_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1866 gt_ctl_write(env
, ri
, GTIMER_PHYS
, value
);
1869 static void gt_virt_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1871 gt_timer_reset(env
, ri
, GTIMER_VIRT
);
1874 static void gt_virt_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1877 gt_cval_write(env
, ri
, GTIMER_VIRT
, value
);
1880 static uint64_t gt_virt_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1882 return gt_tval_read(env
, ri
, GTIMER_VIRT
);
1885 static void gt_virt_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1888 gt_tval_write(env
, ri
, GTIMER_VIRT
, value
);
1891 static void gt_virt_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1894 gt_ctl_write(env
, ri
, GTIMER_VIRT
, value
);
1897 static void gt_cntvoff_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1900 ARMCPU
*cpu
= arm_env_get_cpu(env
);
1902 trace_arm_gt_cntvoff_write(value
);
1903 raw_write(env
, ri
, value
);
1904 gt_recalc_timer(cpu
, GTIMER_VIRT
);
1907 static void gt_hyp_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1909 gt_timer_reset(env
, ri
, GTIMER_HYP
);
1912 static void gt_hyp_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1915 gt_cval_write(env
, ri
, GTIMER_HYP
, value
);
1918 static uint64_t gt_hyp_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1920 return gt_tval_read(env
, ri
, GTIMER_HYP
);
1923 static void gt_hyp_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1926 gt_tval_write(env
, ri
, GTIMER_HYP
, value
);
1929 static void gt_hyp_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1932 gt_ctl_write(env
, ri
, GTIMER_HYP
, value
);
1935 static void gt_sec_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1937 gt_timer_reset(env
, ri
, GTIMER_SEC
);
1940 static void gt_sec_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1943 gt_cval_write(env
, ri
, GTIMER_SEC
, value
);
1946 static uint64_t gt_sec_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1948 return gt_tval_read(env
, ri
, GTIMER_SEC
);
1951 static void gt_sec_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1954 gt_tval_write(env
, ri
, GTIMER_SEC
, value
);
1957 static void gt_sec_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1960 gt_ctl_write(env
, ri
, GTIMER_SEC
, value
);
1963 void arm_gt_ptimer_cb(void *opaque
)
1965 ARMCPU
*cpu
= opaque
;
1967 gt_recalc_timer(cpu
, GTIMER_PHYS
);
1970 void arm_gt_vtimer_cb(void *opaque
)
1972 ARMCPU
*cpu
= opaque
;
1974 gt_recalc_timer(cpu
, GTIMER_VIRT
);
1977 void arm_gt_htimer_cb(void *opaque
)
1979 ARMCPU
*cpu
= opaque
;
1981 gt_recalc_timer(cpu
, GTIMER_HYP
);
1984 void arm_gt_stimer_cb(void *opaque
)
1986 ARMCPU
*cpu
= opaque
;
1988 gt_recalc_timer(cpu
, GTIMER_SEC
);
1991 static const ARMCPRegInfo generic_timer_cp_reginfo
[] = {
1992 /* Note that CNTFRQ is purely reads-as-written for the benefit
1993 * of software; writing it doesn't actually change the timer frequency.
1994 * Our reset value matches the fixed frequency we implement the timer at.
1996 { .name
= "CNTFRQ", .cp
= 15, .crn
= 14, .crm
= 0, .opc1
= 0, .opc2
= 0,
1997 .type
= ARM_CP_ALIAS
,
1998 .access
= PL1_RW
| PL0_R
, .accessfn
= gt_cntfrq_access
,
1999 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c14_cntfrq
),
2001 { .name
= "CNTFRQ_EL0", .state
= ARM_CP_STATE_AA64
,
2002 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 0,
2003 .access
= PL1_RW
| PL0_R
, .accessfn
= gt_cntfrq_access
,
2004 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_cntfrq
),
2005 .resetvalue
= (1000 * 1000 * 1000) / GTIMER_SCALE
,
2007 /* overall control: mostly access permissions */
2008 { .name
= "CNTKCTL", .state
= ARM_CP_STATE_BOTH
,
2009 .opc0
= 3, .opc1
= 0, .crn
= 14, .crm
= 1, .opc2
= 0,
2011 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_cntkctl
),
2014 /* per-timer control */
2015 { .name
= "CNTP_CTL", .cp
= 15, .crn
= 14, .crm
= 2, .opc1
= 0, .opc2
= 1,
2016 .secure
= ARM_CP_SECSTATE_NS
,
2017 .type
= ARM_CP_IO
| ARM_CP_ALIAS
, .access
= PL1_RW
| PL0_R
,
2018 .accessfn
= gt_ptimer_access
,
2019 .fieldoffset
= offsetoflow32(CPUARMState
,
2020 cp15
.c14_timer
[GTIMER_PHYS
].ctl
),
2021 .writefn
= gt_phys_ctl_write
, .raw_writefn
= raw_write
,
2023 { .name
= "CNTP_CTL_S",
2024 .cp
= 15, .crn
= 14, .crm
= 2, .opc1
= 0, .opc2
= 1,
2025 .secure
= ARM_CP_SECSTATE_S
,
2026 .type
= ARM_CP_IO
| ARM_CP_ALIAS
, .access
= PL1_RW
| PL0_R
,
2027 .accessfn
= gt_ptimer_access
,
2028 .fieldoffset
= offsetoflow32(CPUARMState
,
2029 cp15
.c14_timer
[GTIMER_SEC
].ctl
),
2030 .writefn
= gt_sec_ctl_write
, .raw_writefn
= raw_write
,
2032 { .name
= "CNTP_CTL_EL0", .state
= ARM_CP_STATE_AA64
,
2033 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 2, .opc2
= 1,
2034 .type
= ARM_CP_IO
, .access
= PL1_RW
| PL0_R
,
2035 .accessfn
= gt_ptimer_access
,
2036 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_PHYS
].ctl
),
2038 .writefn
= gt_phys_ctl_write
, .raw_writefn
= raw_write
,
2040 { .name
= "CNTV_CTL", .cp
= 15, .crn
= 14, .crm
= 3, .opc1
= 0, .opc2
= 1,
2041 .type
= ARM_CP_IO
| ARM_CP_ALIAS
, .access
= PL1_RW
| PL0_R
,
2042 .accessfn
= gt_vtimer_access
,
2043 .fieldoffset
= offsetoflow32(CPUARMState
,
2044 cp15
.c14_timer
[GTIMER_VIRT
].ctl
),
2045 .writefn
= gt_virt_ctl_write
, .raw_writefn
= raw_write
,
2047 { .name
= "CNTV_CTL_EL0", .state
= ARM_CP_STATE_AA64
,
2048 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 3, .opc2
= 1,
2049 .type
= ARM_CP_IO
, .access
= PL1_RW
| PL0_R
,
2050 .accessfn
= gt_vtimer_access
,
2051 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_VIRT
].ctl
),
2053 .writefn
= gt_virt_ctl_write
, .raw_writefn
= raw_write
,
2055 /* TimerValue views: a 32 bit downcounting view of the underlying state */
2056 { .name
= "CNTP_TVAL", .cp
= 15, .crn
= 14, .crm
= 2, .opc1
= 0, .opc2
= 0,
2057 .secure
= ARM_CP_SECSTATE_NS
,
2058 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL1_RW
| PL0_R
,
2059 .accessfn
= gt_ptimer_access
,
2060 .readfn
= gt_phys_tval_read
, .writefn
= gt_phys_tval_write
,
2062 { .name
= "CNTP_TVAL_S",
2063 .cp
= 15, .crn
= 14, .crm
= 2, .opc1
= 0, .opc2
= 0,
2064 .secure
= ARM_CP_SECSTATE_S
,
2065 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL1_RW
| PL0_R
,
2066 .accessfn
= gt_ptimer_access
,
2067 .readfn
= gt_sec_tval_read
, .writefn
= gt_sec_tval_write
,
2069 { .name
= "CNTP_TVAL_EL0", .state
= ARM_CP_STATE_AA64
,
2070 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 2, .opc2
= 0,
2071 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL1_RW
| PL0_R
,
2072 .accessfn
= gt_ptimer_access
, .resetfn
= gt_phys_timer_reset
,
2073 .readfn
= gt_phys_tval_read
, .writefn
= gt_phys_tval_write
,
2075 { .name
= "CNTV_TVAL", .cp
= 15, .crn
= 14, .crm
= 3, .opc1
= 0, .opc2
= 0,
2076 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL1_RW
| PL0_R
,
2077 .accessfn
= gt_vtimer_access
,
2078 .readfn
= gt_virt_tval_read
, .writefn
= gt_virt_tval_write
,
2080 { .name
= "CNTV_TVAL_EL0", .state
= ARM_CP_STATE_AA64
,
2081 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 3, .opc2
= 0,
2082 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL1_RW
| PL0_R
,
2083 .accessfn
= gt_vtimer_access
, .resetfn
= gt_virt_timer_reset
,
2084 .readfn
= gt_virt_tval_read
, .writefn
= gt_virt_tval_write
,
2086 /* The counter itself */
2087 { .name
= "CNTPCT", .cp
= 15, .crm
= 14, .opc1
= 0,
2088 .access
= PL0_R
, .type
= ARM_CP_64BIT
| ARM_CP_NO_RAW
| ARM_CP_IO
,
2089 .accessfn
= gt_pct_access
,
2090 .readfn
= gt_cnt_read
, .resetfn
= arm_cp_reset_ignore
,
2092 { .name
= "CNTPCT_EL0", .state
= ARM_CP_STATE_AA64
,
2093 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 1,
2094 .access
= PL0_R
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
2095 .accessfn
= gt_pct_access
, .readfn
= gt_cnt_read
,
2097 { .name
= "CNTVCT", .cp
= 15, .crm
= 14, .opc1
= 1,
2098 .access
= PL0_R
, .type
= ARM_CP_64BIT
| ARM_CP_NO_RAW
| ARM_CP_IO
,
2099 .accessfn
= gt_vct_access
,
2100 .readfn
= gt_virt_cnt_read
, .resetfn
= arm_cp_reset_ignore
,
2102 { .name
= "CNTVCT_EL0", .state
= ARM_CP_STATE_AA64
,
2103 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 2,
2104 .access
= PL0_R
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
2105 .accessfn
= gt_vct_access
, .readfn
= gt_virt_cnt_read
,
2107 /* Comparison value, indicating when the timer goes off */
2108 { .name
= "CNTP_CVAL", .cp
= 15, .crm
= 14, .opc1
= 2,
2109 .secure
= ARM_CP_SECSTATE_NS
,
2110 .access
= PL1_RW
| PL0_R
,
2111 .type
= ARM_CP_64BIT
| ARM_CP_IO
| ARM_CP_ALIAS
,
2112 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_PHYS
].cval
),
2113 .accessfn
= gt_ptimer_access
,
2114 .writefn
= gt_phys_cval_write
, .raw_writefn
= raw_write
,
2116 { .name
= "CNTP_CVAL_S", .cp
= 15, .crm
= 14, .opc1
= 2,
2117 .secure
= ARM_CP_SECSTATE_S
,
2118 .access
= PL1_RW
| PL0_R
,
2119 .type
= ARM_CP_64BIT
| ARM_CP_IO
| ARM_CP_ALIAS
,
2120 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_SEC
].cval
),
2121 .accessfn
= gt_ptimer_access
,
2122 .writefn
= gt_sec_cval_write
, .raw_writefn
= raw_write
,
2124 { .name
= "CNTP_CVAL_EL0", .state
= ARM_CP_STATE_AA64
,
2125 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 2, .opc2
= 2,
2126 .access
= PL1_RW
| PL0_R
,
2128 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_PHYS
].cval
),
2129 .resetvalue
= 0, .accessfn
= gt_ptimer_access
,
2130 .writefn
= gt_phys_cval_write
, .raw_writefn
= raw_write
,
2132 { .name
= "CNTV_CVAL", .cp
= 15, .crm
= 14, .opc1
= 3,
2133 .access
= PL1_RW
| PL0_R
,
2134 .type
= ARM_CP_64BIT
| ARM_CP_IO
| ARM_CP_ALIAS
,
2135 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_VIRT
].cval
),
2136 .accessfn
= gt_vtimer_access
,
2137 .writefn
= gt_virt_cval_write
, .raw_writefn
= raw_write
,
2139 { .name
= "CNTV_CVAL_EL0", .state
= ARM_CP_STATE_AA64
,
2140 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 3, .opc2
= 2,
2141 .access
= PL1_RW
| PL0_R
,
2143 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_VIRT
].cval
),
2144 .resetvalue
= 0, .accessfn
= gt_vtimer_access
,
2145 .writefn
= gt_virt_cval_write
, .raw_writefn
= raw_write
,
2147 /* Secure timer -- this is actually restricted to only EL3
2148 * and configurably Secure-EL1 via the accessfn.
2150 { .name
= "CNTPS_TVAL_EL1", .state
= ARM_CP_STATE_AA64
,
2151 .opc0
= 3, .opc1
= 7, .crn
= 14, .crm
= 2, .opc2
= 0,
2152 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL1_RW
,
2153 .accessfn
= gt_stimer_access
,
2154 .readfn
= gt_sec_tval_read
,
2155 .writefn
= gt_sec_tval_write
,
2156 .resetfn
= gt_sec_timer_reset
,
2158 { .name
= "CNTPS_CTL_EL1", .state
= ARM_CP_STATE_AA64
,
2159 .opc0
= 3, .opc1
= 7, .crn
= 14, .crm
= 2, .opc2
= 1,
2160 .type
= ARM_CP_IO
, .access
= PL1_RW
,
2161 .accessfn
= gt_stimer_access
,
2162 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_SEC
].ctl
),
2164 .writefn
= gt_sec_ctl_write
, .raw_writefn
= raw_write
,
2166 { .name
= "CNTPS_CVAL_EL1", .state
= ARM_CP_STATE_AA64
,
2167 .opc0
= 3, .opc1
= 7, .crn
= 14, .crm
= 2, .opc2
= 2,
2168 .type
= ARM_CP_IO
, .access
= PL1_RW
,
2169 .accessfn
= gt_stimer_access
,
2170 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_SEC
].cval
),
2171 .writefn
= gt_sec_cval_write
, .raw_writefn
= raw_write
,
2178 /* In user-mode most of the generic timer registers are inaccessible
2179 * however modern kernels (4.12+) allow access to cntvct_el0
2182 static uint64_t gt_virt_cnt_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2184 /* Currently we have no support for QEMUTimer in linux-user so we
2185 * can't call gt_get_countervalue(env), instead we directly
2186 * call the lower level functions.
2188 return cpu_get_clock() / GTIMER_SCALE
;
2191 static const ARMCPRegInfo generic_timer_cp_reginfo
[] = {
2192 { .name
= "CNTFRQ_EL0", .state
= ARM_CP_STATE_AA64
,
2193 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 0,
2194 .type
= ARM_CP_CONST
, .access
= PL0_R
/* no PL1_RW in linux-user */,
2195 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_cntfrq
),
2196 .resetvalue
= NANOSECONDS_PER_SECOND
/ GTIMER_SCALE
,
2198 { .name
= "CNTVCT_EL0", .state
= ARM_CP_STATE_AA64
,
2199 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 2,
2200 .access
= PL0_R
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
2201 .readfn
= gt_virt_cnt_read
,
2208 static void par_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
2210 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
2211 raw_write(env
, ri
, value
);
2212 } else if (arm_feature(env
, ARM_FEATURE_V7
)) {
2213 raw_write(env
, ri
, value
& 0xfffff6ff);
2215 raw_write(env
, ri
, value
& 0xfffff1ff);
2219 #ifndef CONFIG_USER_ONLY
2220 /* get_phys_addr() isn't present for user-mode-only targets */
2222 static CPAccessResult
ats_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2226 /* The ATS12NSO* operations must trap to EL3 if executed in
2227 * Secure EL1 (which can only happen if EL3 is AArch64).
2228 * They are simply UNDEF if executed from NS EL1.
2229 * They function normally from EL2 or EL3.
2231 if (arm_current_el(env
) == 1) {
2232 if (arm_is_secure_below_el3(env
)) {
2233 return CP_ACCESS_TRAP_UNCATEGORIZED_EL3
;
2235 return CP_ACCESS_TRAP_UNCATEGORIZED
;
2238 return CP_ACCESS_OK
;
2241 static uint64_t do_ats_write(CPUARMState
*env
, uint64_t value
,
2242 MMUAccessType access_type
, ARMMMUIdx mmu_idx
)
2245 target_ulong page_size
;
2249 bool format64
= false;
2250 MemTxAttrs attrs
= {};
2251 ARMMMUFaultInfo fi
= {};
2252 ARMCacheAttrs cacheattrs
= {};
2254 ret
= get_phys_addr(env
, value
, access_type
, mmu_idx
, &phys_addr
, &attrs
,
2255 &prot
, &page_size
, &fi
, &cacheattrs
);
2259 } else if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
2262 * * TTBCR.EAE determines whether the result is returned using the
2263 * 32-bit or the 64-bit PAR format
2264 * * Instructions executed in Hyp mode always use the 64bit format
2266 * ATS1S2NSOxx uses the 64bit format if any of the following is true:
2267 * * The Non-secure TTBCR.EAE bit is set to 1
2268 * * The implementation includes EL2, and the value of HCR.VM is 1
2270 * ATS1Hx always uses the 64bit format (not supported yet).
2272 format64
= arm_s1_regime_using_lpae_format(env
, mmu_idx
);
2274 if (arm_feature(env
, ARM_FEATURE_EL2
)) {
2275 if (mmu_idx
== ARMMMUIdx_S12NSE0
|| mmu_idx
== ARMMMUIdx_S12NSE1
) {
2276 format64
|= env
->cp15
.hcr_el2
& HCR_VM
;
2278 format64
|= arm_current_el(env
) == 2;
2284 /* Create a 64-bit PAR */
2285 par64
= (1 << 11); /* LPAE bit always set */
2287 par64
|= phys_addr
& ~0xfffULL
;
2288 if (!attrs
.secure
) {
2289 par64
|= (1 << 9); /* NS */
2291 par64
|= (uint64_t)cacheattrs
.attrs
<< 56; /* ATTR */
2292 par64
|= cacheattrs
.shareability
<< 7; /* SH */
2294 uint32_t fsr
= arm_fi_to_lfsc(&fi
);
2297 par64
|= (fsr
& 0x3f) << 1; /* FS */
2298 /* Note that S2WLK and FSTAGE are always zero, because we don't
2299 * implement virtualization and therefore there can't be a stage 2
2304 /* fsr is a DFSR/IFSR value for the short descriptor
2305 * translation table format (with WnR always clear).
2306 * Convert it to a 32-bit PAR.
2309 /* We do not set any attribute bits in the PAR */
2310 if (page_size
== (1 << 24)
2311 && arm_feature(env
, ARM_FEATURE_V7
)) {
2312 par64
= (phys_addr
& 0xff000000) | (1 << 1);
2314 par64
= phys_addr
& 0xfffff000;
2316 if (!attrs
.secure
) {
2317 par64
|= (1 << 9); /* NS */
2320 uint32_t fsr
= arm_fi_to_sfsc(&fi
);
2322 par64
= ((fsr
& (1 << 10)) >> 5) | ((fsr
& (1 << 12)) >> 6) |
2323 ((fsr
& 0xf) << 1) | 1;
2329 static void ats_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
2331 MMUAccessType access_type
= ri
->opc2
& 1 ? MMU_DATA_STORE
: MMU_DATA_LOAD
;
2334 int el
= arm_current_el(env
);
2335 bool secure
= arm_is_secure_below_el3(env
);
2337 switch (ri
->opc2
& 6) {
2339 /* stage 1 current state PL1: ATS1CPR, ATS1CPW */
2342 mmu_idx
= ARMMMUIdx_S1E3
;
2345 mmu_idx
= ARMMMUIdx_S1NSE1
;
2348 mmu_idx
= secure
? ARMMMUIdx_S1SE1
: ARMMMUIdx_S1NSE1
;
2351 g_assert_not_reached();
2355 /* stage 1 current state PL0: ATS1CUR, ATS1CUW */
2358 mmu_idx
= ARMMMUIdx_S1SE0
;
2361 mmu_idx
= ARMMMUIdx_S1NSE0
;
2364 mmu_idx
= secure
? ARMMMUIdx_S1SE0
: ARMMMUIdx_S1NSE0
;
2367 g_assert_not_reached();
2371 /* stage 1+2 NonSecure PL1: ATS12NSOPR, ATS12NSOPW */
2372 mmu_idx
= ARMMMUIdx_S12NSE1
;
2375 /* stage 1+2 NonSecure PL0: ATS12NSOUR, ATS12NSOUW */
2376 mmu_idx
= ARMMMUIdx_S12NSE0
;
2379 g_assert_not_reached();
2382 par64
= do_ats_write(env
, value
, access_type
, mmu_idx
);
2384 A32_BANKED_CURRENT_REG_SET(env
, par
, par64
);
2387 static void ats1h_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2390 MMUAccessType access_type
= ri
->opc2
& 1 ? MMU_DATA_STORE
: MMU_DATA_LOAD
;
2393 par64
= do_ats_write(env
, value
, access_type
, ARMMMUIdx_S2NS
);
2395 A32_BANKED_CURRENT_REG_SET(env
, par
, par64
);
2398 static CPAccessResult
at_s1e2_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2401 if (arm_current_el(env
) == 3 && !(env
->cp15
.scr_el3
& SCR_NS
)) {
2402 return CP_ACCESS_TRAP
;
2404 return CP_ACCESS_OK
;
2407 static void ats_write64(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2410 MMUAccessType access_type
= ri
->opc2
& 1 ? MMU_DATA_STORE
: MMU_DATA_LOAD
;
2412 int secure
= arm_is_secure_below_el3(env
);
2414 switch (ri
->opc2
& 6) {
2417 case 0: /* AT S1E1R, AT S1E1W */
2418 mmu_idx
= secure
? ARMMMUIdx_S1SE1
: ARMMMUIdx_S1NSE1
;
2420 case 4: /* AT S1E2R, AT S1E2W */
2421 mmu_idx
= ARMMMUIdx_S1E2
;
2423 case 6: /* AT S1E3R, AT S1E3W */
2424 mmu_idx
= ARMMMUIdx_S1E3
;
2427 g_assert_not_reached();
2430 case 2: /* AT S1E0R, AT S1E0W */
2431 mmu_idx
= secure
? ARMMMUIdx_S1SE0
: ARMMMUIdx_S1NSE0
;
2433 case 4: /* AT S12E1R, AT S12E1W */
2434 mmu_idx
= secure
? ARMMMUIdx_S1SE1
: ARMMMUIdx_S12NSE1
;
2436 case 6: /* AT S12E0R, AT S12E0W */
2437 mmu_idx
= secure
? ARMMMUIdx_S1SE0
: ARMMMUIdx_S12NSE0
;
2440 g_assert_not_reached();
2443 env
->cp15
.par_el
[1] = do_ats_write(env
, value
, access_type
, mmu_idx
);
2447 static const ARMCPRegInfo vapa_cp_reginfo
[] = {
2448 { .name
= "PAR", .cp
= 15, .crn
= 7, .crm
= 4, .opc1
= 0, .opc2
= 0,
2449 .access
= PL1_RW
, .resetvalue
= 0,
2450 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.par_s
),
2451 offsetoflow32(CPUARMState
, cp15
.par_ns
) },
2452 .writefn
= par_write
},
2453 #ifndef CONFIG_USER_ONLY
2454 /* This underdecoding is safe because the reginfo is NO_RAW. */
2455 { .name
= "ATS", .cp
= 15, .crn
= 7, .crm
= 8, .opc1
= 0, .opc2
= CP_ANY
,
2456 .access
= PL1_W
, .accessfn
= ats_access
,
2457 .writefn
= ats_write
, .type
= ARM_CP_NO_RAW
},
2462 /* Return basic MPU access permission bits. */
2463 static uint32_t simple_mpu_ap_bits(uint32_t val
)
2470 for (i
= 0; i
< 16; i
+= 2) {
2471 ret
|= (val
>> i
) & mask
;
2477 /* Pad basic MPU access permission bits to extended format. */
2478 static uint32_t extended_mpu_ap_bits(uint32_t val
)
2485 for (i
= 0; i
< 16; i
+= 2) {
2486 ret
|= (val
& mask
) << i
;
2492 static void pmsav5_data_ap_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2495 env
->cp15
.pmsav5_data_ap
= extended_mpu_ap_bits(value
);
2498 static uint64_t pmsav5_data_ap_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2500 return simple_mpu_ap_bits(env
->cp15
.pmsav5_data_ap
);
2503 static void pmsav5_insn_ap_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2506 env
->cp15
.pmsav5_insn_ap
= extended_mpu_ap_bits(value
);
2509 static uint64_t pmsav5_insn_ap_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2511 return simple_mpu_ap_bits(env
->cp15
.pmsav5_insn_ap
);
2514 static uint64_t pmsav7_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2516 uint32_t *u32p
= *(uint32_t **)raw_ptr(env
, ri
);
2522 u32p
+= env
->pmsav7
.rnr
[M_REG_NS
];
2526 static void pmsav7_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2529 ARMCPU
*cpu
= arm_env_get_cpu(env
);
2530 uint32_t *u32p
= *(uint32_t **)raw_ptr(env
, ri
);
2536 u32p
+= env
->pmsav7
.rnr
[M_REG_NS
];
2537 tlb_flush(CPU(cpu
)); /* Mappings may have changed - purge! */
2541 static void pmsav7_rgnr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2544 ARMCPU
*cpu
= arm_env_get_cpu(env
);
2545 uint32_t nrgs
= cpu
->pmsav7_dregion
;
2547 if (value
>= nrgs
) {
2548 qemu_log_mask(LOG_GUEST_ERROR
,
2549 "PMSAv7 RGNR write >= # supported regions, %" PRIu32
2550 " > %" PRIu32
"\n", (uint32_t)value
, nrgs
);
2554 raw_write(env
, ri
, value
);
2557 static const ARMCPRegInfo pmsav7_cp_reginfo
[] = {
2558 /* Reset for all these registers is handled in arm_cpu_reset(),
2559 * because the PMSAv7 is also used by M-profile CPUs, which do
2560 * not register cpregs but still need the state to be reset.
2562 { .name
= "DRBAR", .cp
= 15, .crn
= 6, .opc1
= 0, .crm
= 1, .opc2
= 0,
2563 .access
= PL1_RW
, .type
= ARM_CP_NO_RAW
,
2564 .fieldoffset
= offsetof(CPUARMState
, pmsav7
.drbar
),
2565 .readfn
= pmsav7_read
, .writefn
= pmsav7_write
,
2566 .resetfn
= arm_cp_reset_ignore
},
2567 { .name
= "DRSR", .cp
= 15, .crn
= 6, .opc1
= 0, .crm
= 1, .opc2
= 2,
2568 .access
= PL1_RW
, .type
= ARM_CP_NO_RAW
,
2569 .fieldoffset
= offsetof(CPUARMState
, pmsav7
.drsr
),
2570 .readfn
= pmsav7_read
, .writefn
= pmsav7_write
,
2571 .resetfn
= arm_cp_reset_ignore
},
2572 { .name
= "DRACR", .cp
= 15, .crn
= 6, .opc1
= 0, .crm
= 1, .opc2
= 4,
2573 .access
= PL1_RW
, .type
= ARM_CP_NO_RAW
,
2574 .fieldoffset
= offsetof(CPUARMState
, pmsav7
.dracr
),
2575 .readfn
= pmsav7_read
, .writefn
= pmsav7_write
,
2576 .resetfn
= arm_cp_reset_ignore
},
2577 { .name
= "RGNR", .cp
= 15, .crn
= 6, .opc1
= 0, .crm
= 2, .opc2
= 0,
2579 .fieldoffset
= offsetof(CPUARMState
, pmsav7
.rnr
[M_REG_NS
]),
2580 .writefn
= pmsav7_rgnr_write
,
2581 .resetfn
= arm_cp_reset_ignore
},
2585 static const ARMCPRegInfo pmsav5_cp_reginfo
[] = {
2586 { .name
= "DATA_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 0,
2587 .access
= PL1_RW
, .type
= ARM_CP_ALIAS
,
2588 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmsav5_data_ap
),
2589 .readfn
= pmsav5_data_ap_read
, .writefn
= pmsav5_data_ap_write
, },
2590 { .name
= "INSN_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 1,
2591 .access
= PL1_RW
, .type
= ARM_CP_ALIAS
,
2592 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmsav5_insn_ap
),
2593 .readfn
= pmsav5_insn_ap_read
, .writefn
= pmsav5_insn_ap_write
, },
2594 { .name
= "DATA_EXT_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 2,
2596 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmsav5_data_ap
),
2598 { .name
= "INSN_EXT_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 3,
2600 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmsav5_insn_ap
),
2602 { .name
= "DCACHE_CFG", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 0,
2604 .fieldoffset
= offsetof(CPUARMState
, cp15
.c2_data
), .resetvalue
= 0, },
2605 { .name
= "ICACHE_CFG", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 1,
2607 .fieldoffset
= offsetof(CPUARMState
, cp15
.c2_insn
), .resetvalue
= 0, },
2608 /* Protection region base and size registers */
2609 { .name
= "946_PRBS0", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0,
2610 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
2611 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[0]) },
2612 { .name
= "946_PRBS1", .cp
= 15, .crn
= 6, .crm
= 1, .opc1
= 0,
2613 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
2614 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[1]) },
2615 { .name
= "946_PRBS2", .cp
= 15, .crn
= 6, .crm
= 2, .opc1
= 0,
2616 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
2617 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[2]) },
2618 { .name
= "946_PRBS3", .cp
= 15, .crn
= 6, .crm
= 3, .opc1
= 0,
2619 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
2620 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[3]) },
2621 { .name
= "946_PRBS4", .cp
= 15, .crn
= 6, .crm
= 4, .opc1
= 0,
2622 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
2623 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[4]) },
2624 { .name
= "946_PRBS5", .cp
= 15, .crn
= 6, .crm
= 5, .opc1
= 0,
2625 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
2626 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[5]) },
2627 { .name
= "946_PRBS6", .cp
= 15, .crn
= 6, .crm
= 6, .opc1
= 0,
2628 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
2629 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[6]) },
2630 { .name
= "946_PRBS7", .cp
= 15, .crn
= 6, .crm
= 7, .opc1
= 0,
2631 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
2632 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[7]) },
2636 static void vmsa_ttbcr_raw_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2639 TCR
*tcr
= raw_ptr(env
, ri
);
2640 int maskshift
= extract32(value
, 0, 3);
2642 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
2643 if (arm_feature(env
, ARM_FEATURE_LPAE
) && (value
& TTBCR_EAE
)) {
2644 /* Pre ARMv8 bits [21:19], [15:14] and [6:3] are UNK/SBZP when
2645 * using Long-desciptor translation table format */
2646 value
&= ~((7 << 19) | (3 << 14) | (0xf << 3));
2647 } else if (arm_feature(env
, ARM_FEATURE_EL3
)) {
2648 /* In an implementation that includes the Security Extensions
2649 * TTBCR has additional fields PD0 [4] and PD1 [5] for
2650 * Short-descriptor translation table format.
2652 value
&= TTBCR_PD1
| TTBCR_PD0
| TTBCR_N
;
2658 /* Update the masks corresponding to the TCR bank being written
2659 * Note that we always calculate mask and base_mask, but
2660 * they are only used for short-descriptor tables (ie if EAE is 0);
2661 * for long-descriptor tables the TCR fields are used differently
2662 * and the mask and base_mask values are meaningless.
2664 tcr
->raw_tcr
= value
;
2665 tcr
->mask
= ~(((uint32_t)0xffffffffu
) >> maskshift
);
2666 tcr
->base_mask
= ~((uint32_t)0x3fffu
>> maskshift
);
2669 static void vmsa_ttbcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2672 ARMCPU
*cpu
= arm_env_get_cpu(env
);
2674 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
2675 /* With LPAE the TTBCR could result in a change of ASID
2676 * via the TTBCR.A1 bit, so do a TLB flush.
2678 tlb_flush(CPU(cpu
));
2680 vmsa_ttbcr_raw_write(env
, ri
, value
);
2683 static void vmsa_ttbcr_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2685 TCR
*tcr
= raw_ptr(env
, ri
);
2687 /* Reset both the TCR as well as the masks corresponding to the bank of
2688 * the TCR being reset.
2692 tcr
->base_mask
= 0xffffc000u
;
2695 static void vmsa_tcr_el1_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2698 ARMCPU
*cpu
= arm_env_get_cpu(env
);
2699 TCR
*tcr
= raw_ptr(env
, ri
);
2701 /* For AArch64 the A1 bit could result in a change of ASID, so TLB flush. */
2702 tlb_flush(CPU(cpu
));
2703 tcr
->raw_tcr
= value
;
2706 static void vmsa_ttbr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2709 /* 64 bit accesses to the TTBRs can change the ASID and so we
2710 * must flush the TLB.
2712 if (cpreg_field_is_64bit(ri
)) {
2713 ARMCPU
*cpu
= arm_env_get_cpu(env
);
2715 tlb_flush(CPU(cpu
));
2717 raw_write(env
, ri
, value
);
2720 static void vttbr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2723 ARMCPU
*cpu
= arm_env_get_cpu(env
);
2724 CPUState
*cs
= CPU(cpu
);
2726 /* Accesses to VTTBR may change the VMID so we must flush the TLB. */
2727 if (raw_read(env
, ri
) != value
) {
2728 tlb_flush_by_mmuidx(cs
,
2729 ARMMMUIdxBit_S12NSE1
|
2730 ARMMMUIdxBit_S12NSE0
|
2732 raw_write(env
, ri
, value
);
2736 static const ARMCPRegInfo vmsa_pmsa_cp_reginfo
[] = {
2737 { .name
= "DFSR", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 0,
2738 .access
= PL1_RW
, .type
= ARM_CP_ALIAS
,
2739 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.dfsr_s
),
2740 offsetoflow32(CPUARMState
, cp15
.dfsr_ns
) }, },
2741 { .name
= "IFSR", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 1,
2742 .access
= PL1_RW
, .resetvalue
= 0,
2743 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.ifsr_s
),
2744 offsetoflow32(CPUARMState
, cp15
.ifsr_ns
) } },
2745 { .name
= "DFAR", .cp
= 15, .opc1
= 0, .crn
= 6, .crm
= 0, .opc2
= 0,
2746 .access
= PL1_RW
, .resetvalue
= 0,
2747 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.dfar_s
),
2748 offsetof(CPUARMState
, cp15
.dfar_ns
) } },
2749 { .name
= "FAR_EL1", .state
= ARM_CP_STATE_AA64
,
2750 .opc0
= 3, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 0,
2751 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.far_el
[1]),
2756 static const ARMCPRegInfo vmsa_cp_reginfo
[] = {
2757 { .name
= "ESR_EL1", .state
= ARM_CP_STATE_AA64
,
2758 .opc0
= 3, .crn
= 5, .crm
= 2, .opc1
= 0, .opc2
= 0,
2760 .fieldoffset
= offsetof(CPUARMState
, cp15
.esr_el
[1]), .resetvalue
= 0, },
2761 { .name
= "TTBR0_EL1", .state
= ARM_CP_STATE_BOTH
,
2762 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 0, .opc2
= 0,
2763 .access
= PL1_RW
, .writefn
= vmsa_ttbr_write
, .resetvalue
= 0,
2764 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ttbr0_s
),
2765 offsetof(CPUARMState
, cp15
.ttbr0_ns
) } },
2766 { .name
= "TTBR1_EL1", .state
= ARM_CP_STATE_BOTH
,
2767 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 0, .opc2
= 1,
2768 .access
= PL1_RW
, .writefn
= vmsa_ttbr_write
, .resetvalue
= 0,
2769 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ttbr1_s
),
2770 offsetof(CPUARMState
, cp15
.ttbr1_ns
) } },
2771 { .name
= "TCR_EL1", .state
= ARM_CP_STATE_AA64
,
2772 .opc0
= 3, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 2,
2773 .access
= PL1_RW
, .writefn
= vmsa_tcr_el1_write
,
2774 .resetfn
= vmsa_ttbcr_reset
, .raw_writefn
= raw_write
,
2775 .fieldoffset
= offsetof(CPUARMState
, cp15
.tcr_el
[1]) },
2776 { .name
= "TTBCR", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 2,
2777 .access
= PL1_RW
, .type
= ARM_CP_ALIAS
, .writefn
= vmsa_ttbcr_write
,
2778 .raw_writefn
= vmsa_ttbcr_raw_write
,
2779 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.tcr_el
[3]),
2780 offsetoflow32(CPUARMState
, cp15
.tcr_el
[1])} },
2784 static void omap_ticonfig_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2787 env
->cp15
.c15_ticonfig
= value
& 0xe7;
2788 /* The OS_TYPE bit in this register changes the reported CPUID! */
2789 env
->cp15
.c0_cpuid
= (value
& (1 << 5)) ?
2790 ARM_CPUID_TI915T
: ARM_CPUID_TI925T
;
2793 static void omap_threadid_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2796 env
->cp15
.c15_threadid
= value
& 0xffff;
2799 static void omap_wfi_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2802 /* Wait-for-interrupt (deprecated) */
2803 cpu_interrupt(CPU(arm_env_get_cpu(env
)), CPU_INTERRUPT_HALT
);
2806 static void omap_cachemaint_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2809 /* On OMAP there are registers indicating the max/min index of dcache lines
2810 * containing a dirty line; cache flush operations have to reset these.
2812 env
->cp15
.c15_i_max
= 0x000;
2813 env
->cp15
.c15_i_min
= 0xff0;
2816 static const ARMCPRegInfo omap_cp_reginfo
[] = {
2817 { .name
= "DFSR", .cp
= 15, .crn
= 5, .crm
= CP_ANY
,
2818 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_OVERRIDE
,
2819 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.esr_el
[1]),
2821 { .name
= "", .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 0, .opc2
= 0,
2822 .access
= PL1_RW
, .type
= ARM_CP_NOP
},
2823 { .name
= "TICONFIG", .cp
= 15, .crn
= 15, .crm
= 1, .opc1
= 0, .opc2
= 0,
2825 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_ticonfig
), .resetvalue
= 0,
2826 .writefn
= omap_ticonfig_write
},
2827 { .name
= "IMAX", .cp
= 15, .crn
= 15, .crm
= 2, .opc1
= 0, .opc2
= 0,
2829 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_i_max
), .resetvalue
= 0, },
2830 { .name
= "IMIN", .cp
= 15, .crn
= 15, .crm
= 3, .opc1
= 0, .opc2
= 0,
2831 .access
= PL1_RW
, .resetvalue
= 0xff0,
2832 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_i_min
) },
2833 { .name
= "THREADID", .cp
= 15, .crn
= 15, .crm
= 4, .opc1
= 0, .opc2
= 0,
2835 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_threadid
), .resetvalue
= 0,
2836 .writefn
= omap_threadid_write
},
2837 { .name
= "TI925T_STATUS", .cp
= 15, .crn
= 15,
2838 .crm
= 8, .opc1
= 0, .opc2
= 0, .access
= PL1_RW
,
2839 .type
= ARM_CP_NO_RAW
,
2840 .readfn
= arm_cp_read_zero
, .writefn
= omap_wfi_write
, },
2841 /* TODO: Peripheral port remap register:
2842 * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt controller
2843 * base address at $rn & ~0xfff and map size of 0x200 << ($rn & 0xfff),
2846 { .name
= "OMAP_CACHEMAINT", .cp
= 15, .crn
= 7, .crm
= CP_ANY
,
2847 .opc1
= 0, .opc2
= CP_ANY
, .access
= PL1_W
,
2848 .type
= ARM_CP_OVERRIDE
| ARM_CP_NO_RAW
,
2849 .writefn
= omap_cachemaint_write
},
2850 { .name
= "C9", .cp
= 15, .crn
= 9,
2851 .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
,
2852 .type
= ARM_CP_CONST
| ARM_CP_OVERRIDE
, .resetvalue
= 0 },
2856 static void xscale_cpar_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2859 env
->cp15
.c15_cpar
= value
& 0x3fff;
2862 static const ARMCPRegInfo xscale_cp_reginfo
[] = {
2863 { .name
= "XSCALE_CPAR",
2864 .cp
= 15, .crn
= 15, .crm
= 1, .opc1
= 0, .opc2
= 0, .access
= PL1_RW
,
2865 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_cpar
), .resetvalue
= 0,
2866 .writefn
= xscale_cpar_write
, },
2867 { .name
= "XSCALE_AUXCR",
2868 .cp
= 15, .crn
= 1, .crm
= 0, .opc1
= 0, .opc2
= 1, .access
= PL1_RW
,
2869 .fieldoffset
= offsetof(CPUARMState
, cp15
.c1_xscaleauxcr
),
2871 /* XScale specific cache-lockdown: since we have no cache we NOP these
2872 * and hope the guest does not really rely on cache behaviour.
2874 { .name
= "XSCALE_LOCK_ICACHE_LINE",
2875 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 1, .opc2
= 0,
2876 .access
= PL1_W
, .type
= ARM_CP_NOP
},
2877 { .name
= "XSCALE_UNLOCK_ICACHE",
2878 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 1, .opc2
= 1,
2879 .access
= PL1_W
, .type
= ARM_CP_NOP
},
2880 { .name
= "XSCALE_DCACHE_LOCK",
2881 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 2, .opc2
= 0,
2882 .access
= PL1_RW
, .type
= ARM_CP_NOP
},
2883 { .name
= "XSCALE_UNLOCK_DCACHE",
2884 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 2, .opc2
= 1,
2885 .access
= PL1_W
, .type
= ARM_CP_NOP
},
2889 static const ARMCPRegInfo dummy_c15_cp_reginfo
[] = {
2890 /* RAZ/WI the whole crn=15 space, when we don't have a more specific
2891 * implementation of this implementation-defined space.
2892 * Ideally this should eventually disappear in favour of actually
2893 * implementing the correct behaviour for all cores.
2895 { .name
= "C15_IMPDEF", .cp
= 15, .crn
= 15,
2896 .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
,
2898 .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
| ARM_CP_OVERRIDE
,
2903 static const ARMCPRegInfo cache_dirty_status_cp_reginfo
[] = {
2904 /* Cache status: RAZ because we have no cache so it's always clean */
2905 { .name
= "CDSR", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 6,
2906 .access
= PL1_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
2911 static const ARMCPRegInfo cache_block_ops_cp_reginfo
[] = {
2912 /* We never have a a block transfer operation in progress */
2913 { .name
= "BXSR", .cp
= 15, .crn
= 7, .crm
= 12, .opc1
= 0, .opc2
= 4,
2914 .access
= PL0_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
2916 /* The cache ops themselves: these all NOP for QEMU */
2917 { .name
= "IICR", .cp
= 15, .crm
= 5, .opc1
= 0,
2918 .access
= PL1_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
2919 { .name
= "IDCR", .cp
= 15, .crm
= 6, .opc1
= 0,
2920 .access
= PL1_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
2921 { .name
= "CDCR", .cp
= 15, .crm
= 12, .opc1
= 0,
2922 .access
= PL0_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
2923 { .name
= "PIR", .cp
= 15, .crm
= 12, .opc1
= 1,
2924 .access
= PL0_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
2925 { .name
= "PDR", .cp
= 15, .crm
= 12, .opc1
= 2,
2926 .access
= PL0_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
2927 { .name
= "CIDCR", .cp
= 15, .crm
= 14, .opc1
= 0,
2928 .access
= PL1_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
2932 static const ARMCPRegInfo cache_test_clean_cp_reginfo
[] = {
2933 /* The cache test-and-clean instructions always return (1 << 30)
2934 * to indicate that there are no dirty cache lines.
2936 { .name
= "TC_DCACHE", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 3,
2937 .access
= PL0_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
2938 .resetvalue
= (1 << 30) },
2939 { .name
= "TCI_DCACHE", .cp
= 15, .crn
= 7, .crm
= 14, .opc1
= 0, .opc2
= 3,
2940 .access
= PL0_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
2941 .resetvalue
= (1 << 30) },
2945 static const ARMCPRegInfo strongarm_cp_reginfo
[] = {
2946 /* Ignore ReadBuffer accesses */
2947 { .name
= "C9_READBUFFER", .cp
= 15, .crn
= 9,
2948 .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
,
2949 .access
= PL1_RW
, .resetvalue
= 0,
2950 .type
= ARM_CP_CONST
| ARM_CP_OVERRIDE
| ARM_CP_NO_RAW
},
2954 static uint64_t midr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2956 ARMCPU
*cpu
= arm_env_get_cpu(env
);
2957 unsigned int cur_el
= arm_current_el(env
);
2958 bool secure
= arm_is_secure(env
);
2960 if (arm_feature(&cpu
->env
, ARM_FEATURE_EL2
) && !secure
&& cur_el
== 1) {
2961 return env
->cp15
.vpidr_el2
;
2963 return raw_read(env
, ri
);
2966 static uint64_t mpidr_read_val(CPUARMState
*env
)
2968 ARMCPU
*cpu
= ARM_CPU(arm_env_get_cpu(env
));
2969 uint64_t mpidr
= cpu
->mp_affinity
;
2971 if (arm_feature(env
, ARM_FEATURE_V7MP
)) {
2972 mpidr
|= (1U << 31);
2973 /* Cores which are uniprocessor (non-coherent)
2974 * but still implement the MP extensions set
2975 * bit 30. (For instance, Cortex-R5).
2977 if (cpu
->mp_is_up
) {
2978 mpidr
|= (1u << 30);
2984 static uint64_t mpidr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2986 unsigned int cur_el
= arm_current_el(env
);
2987 bool secure
= arm_is_secure(env
);
2989 if (arm_feature(env
, ARM_FEATURE_EL2
) && !secure
&& cur_el
== 1) {
2990 return env
->cp15
.vmpidr_el2
;
2992 return mpidr_read_val(env
);
2995 static const ARMCPRegInfo mpidr_cp_reginfo
[] = {
2996 { .name
= "MPIDR", .state
= ARM_CP_STATE_BOTH
,
2997 .opc0
= 3, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 5,
2998 .access
= PL1_R
, .readfn
= mpidr_read
, .type
= ARM_CP_NO_RAW
},
3002 static const ARMCPRegInfo lpae_cp_reginfo
[] = {
3004 { .name
= "AMAIR0", .state
= ARM_CP_STATE_BOTH
,
3005 .opc0
= 3, .crn
= 10, .crm
= 3, .opc1
= 0, .opc2
= 0,
3006 .access
= PL1_RW
, .type
= ARM_CP_CONST
,
3008 /* AMAIR1 is mapped to AMAIR_EL1[63:32] */
3009 { .name
= "AMAIR1", .cp
= 15, .crn
= 10, .crm
= 3, .opc1
= 0, .opc2
= 1,
3010 .access
= PL1_RW
, .type
= ARM_CP_CONST
,
3012 { .name
= "PAR", .cp
= 15, .crm
= 7, .opc1
= 0,
3013 .access
= PL1_RW
, .type
= ARM_CP_64BIT
, .resetvalue
= 0,
3014 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.par_s
),
3015 offsetof(CPUARMState
, cp15
.par_ns
)} },
3016 { .name
= "TTBR0", .cp
= 15, .crm
= 2, .opc1
= 0,
3017 .access
= PL1_RW
, .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
,
3018 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ttbr0_s
),
3019 offsetof(CPUARMState
, cp15
.ttbr0_ns
) },
3020 .writefn
= vmsa_ttbr_write
, },
3021 { .name
= "TTBR1", .cp
= 15, .crm
= 2, .opc1
= 1,
3022 .access
= PL1_RW
, .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
,
3023 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ttbr1_s
),
3024 offsetof(CPUARMState
, cp15
.ttbr1_ns
) },
3025 .writefn
= vmsa_ttbr_write
, },
3029 static uint64_t aa64_fpcr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3031 return vfp_get_fpcr(env
);
3034 static void aa64_fpcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3037 vfp_set_fpcr(env
, value
);
3040 static uint64_t aa64_fpsr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3042 return vfp_get_fpsr(env
);
3045 static void aa64_fpsr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3048 vfp_set_fpsr(env
, value
);
3051 static CPAccessResult
aa64_daif_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3054 if (arm_current_el(env
) == 0 && !(env
->cp15
.sctlr_el
[1] & SCTLR_UMA
)) {
3055 return CP_ACCESS_TRAP
;
3057 return CP_ACCESS_OK
;
3060 static void aa64_daif_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3063 env
->daif
= value
& PSTATE_DAIF
;
3066 static CPAccessResult
aa64_cacheop_access(CPUARMState
*env
,
3067 const ARMCPRegInfo
*ri
,
3070 /* Cache invalidate/clean: NOP, but EL0 must UNDEF unless
3071 * SCTLR_EL1.UCI is set.
3073 if (arm_current_el(env
) == 0 && !(env
->cp15
.sctlr_el
[1] & SCTLR_UCI
)) {
3074 return CP_ACCESS_TRAP
;
3076 return CP_ACCESS_OK
;
3079 /* See: D4.7.2 TLB maintenance requirements and the TLB maintenance instructions
3080 * Page D4-1736 (DDI0487A.b)
3083 static void tlbi_aa64_vmalle1_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3086 CPUState
*cs
= ENV_GET_CPU(env
);
3088 if (arm_is_secure_below_el3(env
)) {
3089 tlb_flush_by_mmuidx(cs
,
3090 ARMMMUIdxBit_S1SE1
|
3091 ARMMMUIdxBit_S1SE0
);
3093 tlb_flush_by_mmuidx(cs
,
3094 ARMMMUIdxBit_S12NSE1
|
3095 ARMMMUIdxBit_S12NSE0
);
3099 static void tlbi_aa64_vmalle1is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3102 CPUState
*cs
= ENV_GET_CPU(env
);
3103 bool sec
= arm_is_secure_below_el3(env
);
3106 tlb_flush_by_mmuidx_all_cpus_synced(cs
,
3107 ARMMMUIdxBit_S1SE1
|
3108 ARMMMUIdxBit_S1SE0
);
3110 tlb_flush_by_mmuidx_all_cpus_synced(cs
,
3111 ARMMMUIdxBit_S12NSE1
|
3112 ARMMMUIdxBit_S12NSE0
);
3116 static void tlbi_aa64_alle1_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3119 /* Note that the 'ALL' scope must invalidate both stage 1 and
3120 * stage 2 translations, whereas most other scopes only invalidate
3121 * stage 1 translations.
3123 ARMCPU
*cpu
= arm_env_get_cpu(env
);
3124 CPUState
*cs
= CPU(cpu
);
3126 if (arm_is_secure_below_el3(env
)) {
3127 tlb_flush_by_mmuidx(cs
,
3128 ARMMMUIdxBit_S1SE1
|
3129 ARMMMUIdxBit_S1SE0
);
3131 if (arm_feature(env
, ARM_FEATURE_EL2
)) {
3132 tlb_flush_by_mmuidx(cs
,
3133 ARMMMUIdxBit_S12NSE1
|
3134 ARMMMUIdxBit_S12NSE0
|
3137 tlb_flush_by_mmuidx(cs
,
3138 ARMMMUIdxBit_S12NSE1
|
3139 ARMMMUIdxBit_S12NSE0
);
3144 static void tlbi_aa64_alle2_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3147 ARMCPU
*cpu
= arm_env_get_cpu(env
);
3148 CPUState
*cs
= CPU(cpu
);
3150 tlb_flush_by_mmuidx(cs
, ARMMMUIdxBit_S1E2
);
3153 static void tlbi_aa64_alle3_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3156 ARMCPU
*cpu
= arm_env_get_cpu(env
);
3157 CPUState
*cs
= CPU(cpu
);
3159 tlb_flush_by_mmuidx(cs
, ARMMMUIdxBit_S1E3
);
3162 static void tlbi_aa64_alle1is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3165 /* Note that the 'ALL' scope must invalidate both stage 1 and
3166 * stage 2 translations, whereas most other scopes only invalidate
3167 * stage 1 translations.
3169 CPUState
*cs
= ENV_GET_CPU(env
);
3170 bool sec
= arm_is_secure_below_el3(env
);
3171 bool has_el2
= arm_feature(env
, ARM_FEATURE_EL2
);
3174 tlb_flush_by_mmuidx_all_cpus_synced(cs
,
3175 ARMMMUIdxBit_S1SE1
|
3176 ARMMMUIdxBit_S1SE0
);
3177 } else if (has_el2
) {
3178 tlb_flush_by_mmuidx_all_cpus_synced(cs
,
3179 ARMMMUIdxBit_S12NSE1
|
3180 ARMMMUIdxBit_S12NSE0
|
3183 tlb_flush_by_mmuidx_all_cpus_synced(cs
,
3184 ARMMMUIdxBit_S12NSE1
|
3185 ARMMMUIdxBit_S12NSE0
);
3189 static void tlbi_aa64_alle2is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3192 CPUState
*cs
= ENV_GET_CPU(env
);
3194 tlb_flush_by_mmuidx_all_cpus_synced(cs
, ARMMMUIdxBit_S1E2
);
3197 static void tlbi_aa64_alle3is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3200 CPUState
*cs
= ENV_GET_CPU(env
);
3202 tlb_flush_by_mmuidx_all_cpus_synced(cs
, ARMMMUIdxBit_S1E3
);
3205 static void tlbi_aa64_vae1_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3208 /* Invalidate by VA, EL1&0 (AArch64 version).
3209 * Currently handles all of VAE1, VAAE1, VAALE1 and VALE1,
3210 * since we don't support flush-for-specific-ASID-only or
3211 * flush-last-level-only.
3213 ARMCPU
*cpu
= arm_env_get_cpu(env
);
3214 CPUState
*cs
= CPU(cpu
);
3215 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
3217 if (arm_is_secure_below_el3(env
)) {
3218 tlb_flush_page_by_mmuidx(cs
, pageaddr
,
3219 ARMMMUIdxBit_S1SE1
|
3220 ARMMMUIdxBit_S1SE0
);
3222 tlb_flush_page_by_mmuidx(cs
, pageaddr
,
3223 ARMMMUIdxBit_S12NSE1
|
3224 ARMMMUIdxBit_S12NSE0
);
3228 static void tlbi_aa64_vae2_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3231 /* Invalidate by VA, EL2
3232 * Currently handles both VAE2 and VALE2, since we don't support
3233 * flush-last-level-only.
3235 ARMCPU
*cpu
= arm_env_get_cpu(env
);
3236 CPUState
*cs
= CPU(cpu
);
3237 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
3239 tlb_flush_page_by_mmuidx(cs
, pageaddr
, ARMMMUIdxBit_S1E2
);
3242 static void tlbi_aa64_vae3_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3245 /* Invalidate by VA, EL3
3246 * Currently handles both VAE3 and VALE3, since we don't support
3247 * flush-last-level-only.
3249 ARMCPU
*cpu
= arm_env_get_cpu(env
);
3250 CPUState
*cs
= CPU(cpu
);
3251 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
3253 tlb_flush_page_by_mmuidx(cs
, pageaddr
, ARMMMUIdxBit_S1E3
);
3256 static void tlbi_aa64_vae1is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3259 ARMCPU
*cpu
= arm_env_get_cpu(env
);
3260 CPUState
*cs
= CPU(cpu
);
3261 bool sec
= arm_is_secure_below_el3(env
);
3262 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
3265 tlb_flush_page_by_mmuidx_all_cpus_synced(cs
, pageaddr
,
3266 ARMMMUIdxBit_S1SE1
|
3267 ARMMMUIdxBit_S1SE0
);
3269 tlb_flush_page_by_mmuidx_all_cpus_synced(cs
, pageaddr
,
3270 ARMMMUIdxBit_S12NSE1
|
3271 ARMMMUIdxBit_S12NSE0
);
3275 static void tlbi_aa64_vae2is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3278 CPUState
*cs
= ENV_GET_CPU(env
);
3279 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
3281 tlb_flush_page_by_mmuidx_all_cpus_synced(cs
, pageaddr
,
3285 static void tlbi_aa64_vae3is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3288 CPUState
*cs
= ENV_GET_CPU(env
);
3289 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
3291 tlb_flush_page_by_mmuidx_all_cpus_synced(cs
, pageaddr
,
3295 static void tlbi_aa64_ipas2e1_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3298 /* Invalidate by IPA. This has to invalidate any structures that
3299 * contain only stage 2 translation information, but does not need
3300 * to apply to structures that contain combined stage 1 and stage 2
3301 * translation information.
3302 * This must NOP if EL2 isn't implemented or SCR_EL3.NS is zero.
3304 ARMCPU
*cpu
= arm_env_get_cpu(env
);
3305 CPUState
*cs
= CPU(cpu
);
3308 if (!arm_feature(env
, ARM_FEATURE_EL2
) || !(env
->cp15
.scr_el3
& SCR_NS
)) {
3312 pageaddr
= sextract64(value
<< 12, 0, 48);
3314 tlb_flush_page_by_mmuidx(cs
, pageaddr
, ARMMMUIdxBit_S2NS
);
3317 static void tlbi_aa64_ipas2e1is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3320 CPUState
*cs
= ENV_GET_CPU(env
);
3323 if (!arm_feature(env
, ARM_FEATURE_EL2
) || !(env
->cp15
.scr_el3
& SCR_NS
)) {
3327 pageaddr
= sextract64(value
<< 12, 0, 48);
3329 tlb_flush_page_by_mmuidx_all_cpus_synced(cs
, pageaddr
,
3333 static CPAccessResult
aa64_zva_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3336 /* We don't implement EL2, so the only control on DC ZVA is the
3337 * bit in the SCTLR which can prohibit access for EL0.
3339 if (arm_current_el(env
) == 0 && !(env
->cp15
.sctlr_el
[1] & SCTLR_DZE
)) {
3340 return CP_ACCESS_TRAP
;
3342 return CP_ACCESS_OK
;
3345 static uint64_t aa64_dczid_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3347 ARMCPU
*cpu
= arm_env_get_cpu(env
);
3348 int dzp_bit
= 1 << 4;
3350 /* DZP indicates whether DC ZVA access is allowed */
3351 if (aa64_zva_access(env
, NULL
, false) == CP_ACCESS_OK
) {
3354 return cpu
->dcz_blocksize
| dzp_bit
;
3357 static CPAccessResult
sp_el0_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3360 if (!(env
->pstate
& PSTATE_SP
)) {
3361 /* Access to SP_EL0 is undefined if it's being used as
3362 * the stack pointer.
3364 return CP_ACCESS_TRAP_UNCATEGORIZED
;
3366 return CP_ACCESS_OK
;
3369 static uint64_t spsel_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3371 return env
->pstate
& PSTATE_SP
;
3374 static void spsel_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t val
)
3376 update_spsel(env
, val
);
3379 static void sctlr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3382 ARMCPU
*cpu
= arm_env_get_cpu(env
);
3384 if (raw_read(env
, ri
) == value
) {
3385 /* Skip the TLB flush if nothing actually changed; Linux likes
3386 * to do a lot of pointless SCTLR writes.
3391 if (arm_feature(env
, ARM_FEATURE_PMSA
) && !cpu
->has_mpu
) {
3392 /* M bit is RAZ/WI for PMSA with no MPU implemented */
3396 raw_write(env
, ri
, value
);
3397 /* ??? Lots of these bits are not implemented. */
3398 /* This may enable/disable the MMU, so do a TLB flush. */
3399 tlb_flush(CPU(cpu
));
3402 static CPAccessResult
fpexc32_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3405 if ((env
->cp15
.cptr_el
[2] & CPTR_TFP
) && arm_current_el(env
) == 2) {
3406 return CP_ACCESS_TRAP_FP_EL2
;
3408 if (env
->cp15
.cptr_el
[3] & CPTR_TFP
) {
3409 return CP_ACCESS_TRAP_FP_EL3
;
3411 return CP_ACCESS_OK
;
3414 static void sdcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3417 env
->cp15
.mdcr_el3
= value
& SDCR_VALID_MASK
;
3420 static const ARMCPRegInfo v8_cp_reginfo
[] = {
3421 /* Minimal set of EL0-visible registers. This will need to be expanded
3422 * significantly for system emulation of AArch64 CPUs.
3424 { .name
= "NZCV", .state
= ARM_CP_STATE_AA64
,
3425 .opc0
= 3, .opc1
= 3, .opc2
= 0, .crn
= 4, .crm
= 2,
3426 .access
= PL0_RW
, .type
= ARM_CP_NZCV
},
3427 { .name
= "DAIF", .state
= ARM_CP_STATE_AA64
,
3428 .opc0
= 3, .opc1
= 3, .opc2
= 1, .crn
= 4, .crm
= 2,
3429 .type
= ARM_CP_NO_RAW
,
3430 .access
= PL0_RW
, .accessfn
= aa64_daif_access
,
3431 .fieldoffset
= offsetof(CPUARMState
, daif
),
3432 .writefn
= aa64_daif_write
, .resetfn
= arm_cp_reset_ignore
},
3433 { .name
= "FPCR", .state
= ARM_CP_STATE_AA64
,
3434 .opc0
= 3, .opc1
= 3, .opc2
= 0, .crn
= 4, .crm
= 4,
3435 .access
= PL0_RW
, .type
= ARM_CP_FPU
| ARM_CP_SUPPRESS_TB_END
,
3436 .readfn
= aa64_fpcr_read
, .writefn
= aa64_fpcr_write
},
3437 { .name
= "FPSR", .state
= ARM_CP_STATE_AA64
,
3438 .opc0
= 3, .opc1
= 3, .opc2
= 1, .crn
= 4, .crm
= 4,
3439 .access
= PL0_RW
, .type
= ARM_CP_FPU
| ARM_CP_SUPPRESS_TB_END
,
3440 .readfn
= aa64_fpsr_read
, .writefn
= aa64_fpsr_write
},
3441 { .name
= "DCZID_EL0", .state
= ARM_CP_STATE_AA64
,
3442 .opc0
= 3, .opc1
= 3, .opc2
= 7, .crn
= 0, .crm
= 0,
3443 .access
= PL0_R
, .type
= ARM_CP_NO_RAW
,
3444 .readfn
= aa64_dczid_read
},
3445 { .name
= "DC_ZVA", .state
= ARM_CP_STATE_AA64
,
3446 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 4, .opc2
= 1,
3447 .access
= PL0_W
, .type
= ARM_CP_DC_ZVA
,
3448 #ifndef CONFIG_USER_ONLY
3449 /* Avoid overhead of an access check that always passes in user-mode */
3450 .accessfn
= aa64_zva_access
,
3453 { .name
= "CURRENTEL", .state
= ARM_CP_STATE_AA64
,
3454 .opc0
= 3, .opc1
= 0, .opc2
= 2, .crn
= 4, .crm
= 2,
3455 .access
= PL1_R
, .type
= ARM_CP_CURRENTEL
},
3456 /* Cache ops: all NOPs since we don't emulate caches */
3457 { .name
= "IC_IALLUIS", .state
= ARM_CP_STATE_AA64
,
3458 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 1, .opc2
= 0,
3459 .access
= PL1_W
, .type
= ARM_CP_NOP
},
3460 { .name
= "IC_IALLU", .state
= ARM_CP_STATE_AA64
,
3461 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 0,
3462 .access
= PL1_W
, .type
= ARM_CP_NOP
},
3463 { .name
= "IC_IVAU", .state
= ARM_CP_STATE_AA64
,
3464 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 5, .opc2
= 1,
3465 .access
= PL0_W
, .type
= ARM_CP_NOP
,
3466 .accessfn
= aa64_cacheop_access
},
3467 { .name
= "DC_IVAC", .state
= ARM_CP_STATE_AA64
,
3468 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 1,
3469 .access
= PL1_W
, .type
= ARM_CP_NOP
},
3470 { .name
= "DC_ISW", .state
= ARM_CP_STATE_AA64
,
3471 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 2,
3472 .access
= PL1_W
, .type
= ARM_CP_NOP
},
3473 { .name
= "DC_CVAC", .state
= ARM_CP_STATE_AA64
,
3474 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 10, .opc2
= 1,
3475 .access
= PL0_W
, .type
= ARM_CP_NOP
,
3476 .accessfn
= aa64_cacheop_access
},
3477 { .name
= "DC_CSW", .state
= ARM_CP_STATE_AA64
,
3478 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 10, .opc2
= 2,
3479 .access
= PL1_W
, .type
= ARM_CP_NOP
},
3480 { .name
= "DC_CVAU", .state
= ARM_CP_STATE_AA64
,
3481 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 11, .opc2
= 1,
3482 .access
= PL0_W
, .type
= ARM_CP_NOP
,
3483 .accessfn
= aa64_cacheop_access
},
3484 { .name
= "DC_CIVAC", .state
= ARM_CP_STATE_AA64
,
3485 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 14, .opc2
= 1,
3486 .access
= PL0_W
, .type
= ARM_CP_NOP
,
3487 .accessfn
= aa64_cacheop_access
},
3488 { .name
= "DC_CISW", .state
= ARM_CP_STATE_AA64
,
3489 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 14, .opc2
= 2,
3490 .access
= PL1_W
, .type
= ARM_CP_NOP
},
3491 /* TLBI operations */
3492 { .name
= "TLBI_VMALLE1IS", .state
= ARM_CP_STATE_AA64
,
3493 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 0,
3494 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
3495 .writefn
= tlbi_aa64_vmalle1is_write
},
3496 { .name
= "TLBI_VAE1IS", .state
= ARM_CP_STATE_AA64
,
3497 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 1,
3498 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
3499 .writefn
= tlbi_aa64_vae1is_write
},
3500 { .name
= "TLBI_ASIDE1IS", .state
= ARM_CP_STATE_AA64
,
3501 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 2,
3502 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
3503 .writefn
= tlbi_aa64_vmalle1is_write
},
3504 { .name
= "TLBI_VAAE1IS", .state
= ARM_CP_STATE_AA64
,
3505 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 3,
3506 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
3507 .writefn
= tlbi_aa64_vae1is_write
},
3508 { .name
= "TLBI_VALE1IS", .state
= ARM_CP_STATE_AA64
,
3509 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 5,
3510 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
3511 .writefn
= tlbi_aa64_vae1is_write
},
3512 { .name
= "TLBI_VAALE1IS", .state
= ARM_CP_STATE_AA64
,
3513 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 7,
3514 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
3515 .writefn
= tlbi_aa64_vae1is_write
},
3516 { .name
= "TLBI_VMALLE1", .state
= ARM_CP_STATE_AA64
,
3517 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 0,
3518 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
3519 .writefn
= tlbi_aa64_vmalle1_write
},
3520 { .name
= "TLBI_VAE1", .state
= ARM_CP_STATE_AA64
,
3521 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 1,
3522 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
3523 .writefn
= tlbi_aa64_vae1_write
},
3524 { .name
= "TLBI_ASIDE1", .state
= ARM_CP_STATE_AA64
,
3525 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 2,
3526 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
3527 .writefn
= tlbi_aa64_vmalle1_write
},
3528 { .name
= "TLBI_VAAE1", .state
= ARM_CP_STATE_AA64
,
3529 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 3,
3530 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
3531 .writefn
= tlbi_aa64_vae1_write
},
3532 { .name
= "TLBI_VALE1", .state
= ARM_CP_STATE_AA64
,
3533 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 5,
3534 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
3535 .writefn
= tlbi_aa64_vae1_write
},
3536 { .name
= "TLBI_VAALE1", .state
= ARM_CP_STATE_AA64
,
3537 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 7,
3538 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
3539 .writefn
= tlbi_aa64_vae1_write
},
3540 { .name
= "TLBI_IPAS2E1IS", .state
= ARM_CP_STATE_AA64
,
3541 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 1,
3542 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
3543 .writefn
= tlbi_aa64_ipas2e1is_write
},
3544 { .name
= "TLBI_IPAS2LE1IS", .state
= ARM_CP_STATE_AA64
,
3545 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 5,
3546 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
3547 .writefn
= tlbi_aa64_ipas2e1is_write
},
3548 { .name
= "TLBI_ALLE1IS", .state
= ARM_CP_STATE_AA64
,
3549 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 4,
3550 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
3551 .writefn
= tlbi_aa64_alle1is_write
},
3552 { .name
= "TLBI_VMALLS12E1IS", .state
= ARM_CP_STATE_AA64
,
3553 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 6,
3554 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
3555 .writefn
= tlbi_aa64_alle1is_write
},
3556 { .name
= "TLBI_IPAS2E1", .state
= ARM_CP_STATE_AA64
,
3557 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 1,
3558 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
3559 .writefn
= tlbi_aa64_ipas2e1_write
},
3560 { .name
= "TLBI_IPAS2LE1", .state
= ARM_CP_STATE_AA64
,
3561 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 5,
3562 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
3563 .writefn
= tlbi_aa64_ipas2e1_write
},
3564 { .name
= "TLBI_ALLE1", .state
= ARM_CP_STATE_AA64
,
3565 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 4,
3566 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
3567 .writefn
= tlbi_aa64_alle1_write
},
3568 { .name
= "TLBI_VMALLS12E1", .state
= ARM_CP_STATE_AA64
,
3569 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 6,
3570 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
3571 .writefn
= tlbi_aa64_alle1is_write
},
3572 #ifndef CONFIG_USER_ONLY
3573 /* 64 bit address translation operations */
3574 { .name
= "AT_S1E1R", .state
= ARM_CP_STATE_AA64
,
3575 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 8, .opc2
= 0,
3576 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
, .writefn
= ats_write64
},
3577 { .name
= "AT_S1E1W", .state
= ARM_CP_STATE_AA64
,
3578 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 8, .opc2
= 1,
3579 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
, .writefn
= ats_write64
},
3580 { .name
= "AT_S1E0R", .state
= ARM_CP_STATE_AA64
,
3581 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 8, .opc2
= 2,
3582 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
, .writefn
= ats_write64
},
3583 { .name
= "AT_S1E0W", .state
= ARM_CP_STATE_AA64
,
3584 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 8, .opc2
= 3,
3585 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
, .writefn
= ats_write64
},
3586 { .name
= "AT_S12E1R", .state
= ARM_CP_STATE_AA64
,
3587 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 4,
3588 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
, .writefn
= ats_write64
},
3589 { .name
= "AT_S12E1W", .state
= ARM_CP_STATE_AA64
,
3590 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 5,
3591 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
, .writefn
= ats_write64
},
3592 { .name
= "AT_S12E0R", .state
= ARM_CP_STATE_AA64
,
3593 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 6,
3594 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
, .writefn
= ats_write64
},
3595 { .name
= "AT_S12E0W", .state
= ARM_CP_STATE_AA64
,
3596 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 7,
3597 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
, .writefn
= ats_write64
},
3598 /* AT S1E2* are elsewhere as they UNDEF from EL3 if EL2 is not present */
3599 { .name
= "AT_S1E3R", .state
= ARM_CP_STATE_AA64
,
3600 .opc0
= 1, .opc1
= 6, .crn
= 7, .crm
= 8, .opc2
= 0,
3601 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
, .writefn
= ats_write64
},
3602 { .name
= "AT_S1E3W", .state
= ARM_CP_STATE_AA64
,
3603 .opc0
= 1, .opc1
= 6, .crn
= 7, .crm
= 8, .opc2
= 1,
3604 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
, .writefn
= ats_write64
},
3605 { .name
= "PAR_EL1", .state
= ARM_CP_STATE_AA64
,
3606 .type
= ARM_CP_ALIAS
,
3607 .opc0
= 3, .opc1
= 0, .crn
= 7, .crm
= 4, .opc2
= 0,
3608 .access
= PL1_RW
, .resetvalue
= 0,
3609 .fieldoffset
= offsetof(CPUARMState
, cp15
.par_el
[1]),
3610 .writefn
= par_write
},
3612 /* TLB invalidate last level of translation table walk */
3613 { .name
= "TLBIMVALIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 5,
3614 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbimva_is_write
},
3615 { .name
= "TLBIMVAALIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 7,
3616 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
,
3617 .writefn
= tlbimvaa_is_write
},
3618 { .name
= "TLBIMVAL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 5,
3619 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbimva_write
},
3620 { .name
= "TLBIMVAAL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 7,
3621 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbimvaa_write
},
3622 { .name
= "TLBIMVALH", .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 5,
3623 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
3624 .writefn
= tlbimva_hyp_write
},
3625 { .name
= "TLBIMVALHIS",
3626 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 5,
3627 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
3628 .writefn
= tlbimva_hyp_is_write
},
3629 { .name
= "TLBIIPAS2",
3630 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 1,
3631 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
3632 .writefn
= tlbiipas2_write
},
3633 { .name
= "TLBIIPAS2IS",
3634 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 1,
3635 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
3636 .writefn
= tlbiipas2_is_write
},
3637 { .name
= "TLBIIPAS2L",
3638 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 5,
3639 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
3640 .writefn
= tlbiipas2_write
},
3641 { .name
= "TLBIIPAS2LIS",
3642 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 5,
3643 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
3644 .writefn
= tlbiipas2_is_write
},
3645 /* 32 bit cache operations */
3646 { .name
= "ICIALLUIS", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 1, .opc2
= 0,
3647 .type
= ARM_CP_NOP
, .access
= PL1_W
},
3648 { .name
= "BPIALLUIS", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 1, .opc2
= 6,
3649 .type
= ARM_CP_NOP
, .access
= PL1_W
},
3650 { .name
= "ICIALLU", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 0,
3651 .type
= ARM_CP_NOP
, .access
= PL1_W
},
3652 { .name
= "ICIMVAU", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 1,
3653 .type
= ARM_CP_NOP
, .access
= PL1_W
},
3654 { .name
= "BPIALL", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 6,
3655 .type
= ARM_CP_NOP
, .access
= PL1_W
},
3656 { .name
= "BPIMVA", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 7,
3657 .type
= ARM_CP_NOP
, .access
= PL1_W
},
3658 { .name
= "DCIMVAC", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 1,
3659 .type
= ARM_CP_NOP
, .access
= PL1_W
},
3660 { .name
= "DCISW", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 2,
3661 .type
= ARM_CP_NOP
, .access
= PL1_W
},
3662 { .name
= "DCCMVAC", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 10, .opc2
= 1,
3663 .type
= ARM_CP_NOP
, .access
= PL1_W
},
3664 { .name
= "DCCSW", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 10, .opc2
= 2,
3665 .type
= ARM_CP_NOP
, .access
= PL1_W
},
3666 { .name
= "DCCMVAU", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 11, .opc2
= 1,
3667 .type
= ARM_CP_NOP
, .access
= PL1_W
},
3668 { .name
= "DCCIMVAC", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 14, .opc2
= 1,
3669 .type
= ARM_CP_NOP
, .access
= PL1_W
},
3670 { .name
= "DCCISW", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 14, .opc2
= 2,
3671 .type
= ARM_CP_NOP
, .access
= PL1_W
},
3672 /* MMU Domain access control / MPU write buffer control */
3673 { .name
= "DACR", .cp
= 15, .opc1
= 0, .crn
= 3, .crm
= 0, .opc2
= 0,
3674 .access
= PL1_RW
, .resetvalue
= 0,
3675 .writefn
= dacr_write
, .raw_writefn
= raw_write
,
3676 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.dacr_s
),
3677 offsetoflow32(CPUARMState
, cp15
.dacr_ns
) } },
3678 { .name
= "ELR_EL1", .state
= ARM_CP_STATE_AA64
,
3679 .type
= ARM_CP_ALIAS
,
3680 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 0, .opc2
= 1,
3682 .fieldoffset
= offsetof(CPUARMState
, elr_el
[1]) },
3683 { .name
= "SPSR_EL1", .state
= ARM_CP_STATE_AA64
,
3684 .type
= ARM_CP_ALIAS
,
3685 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 0, .opc2
= 0,
3687 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_SVC
]) },
3688 /* We rely on the access checks not allowing the guest to write to the
3689 * state field when SPSel indicates that it's being used as the stack
3692 { .name
= "SP_EL0", .state
= ARM_CP_STATE_AA64
,
3693 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 1, .opc2
= 0,
3694 .access
= PL1_RW
, .accessfn
= sp_el0_access
,
3695 .type
= ARM_CP_ALIAS
,
3696 .fieldoffset
= offsetof(CPUARMState
, sp_el
[0]) },
3697 { .name
= "SP_EL1", .state
= ARM_CP_STATE_AA64
,
3698 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 1, .opc2
= 0,
3699 .access
= PL2_RW
, .type
= ARM_CP_ALIAS
,
3700 .fieldoffset
= offsetof(CPUARMState
, sp_el
[1]) },
3701 { .name
= "SPSel", .state
= ARM_CP_STATE_AA64
,
3702 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 2, .opc2
= 0,
3703 .type
= ARM_CP_NO_RAW
,
3704 .access
= PL1_RW
, .readfn
= spsel_read
, .writefn
= spsel_write
},
3705 { .name
= "FPEXC32_EL2", .state
= ARM_CP_STATE_AA64
,
3706 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 3, .opc2
= 0,
3707 .type
= ARM_CP_ALIAS
,
3708 .fieldoffset
= offsetof(CPUARMState
, vfp
.xregs
[ARM_VFP_FPEXC
]),
3709 .access
= PL2_RW
, .accessfn
= fpexc32_access
},
3710 { .name
= "DACR32_EL2", .state
= ARM_CP_STATE_AA64
,
3711 .opc0
= 3, .opc1
= 4, .crn
= 3, .crm
= 0, .opc2
= 0,
3712 .access
= PL2_RW
, .resetvalue
= 0,
3713 .writefn
= dacr_write
, .raw_writefn
= raw_write
,
3714 .fieldoffset
= offsetof(CPUARMState
, cp15
.dacr32_el2
) },
3715 { .name
= "IFSR32_EL2", .state
= ARM_CP_STATE_AA64
,
3716 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 0, .opc2
= 1,
3717 .access
= PL2_RW
, .resetvalue
= 0,
3718 .fieldoffset
= offsetof(CPUARMState
, cp15
.ifsr32_el2
) },
3719 { .name
= "SPSR_IRQ", .state
= ARM_CP_STATE_AA64
,
3720 .type
= ARM_CP_ALIAS
,
3721 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 3, .opc2
= 0,
3723 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_IRQ
]) },
3724 { .name
= "SPSR_ABT", .state
= ARM_CP_STATE_AA64
,
3725 .type
= ARM_CP_ALIAS
,
3726 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 3, .opc2
= 1,
3728 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_ABT
]) },
3729 { .name
= "SPSR_UND", .state
= ARM_CP_STATE_AA64
,
3730 .type
= ARM_CP_ALIAS
,
3731 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 3, .opc2
= 2,
3733 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_UND
]) },
3734 { .name
= "SPSR_FIQ", .state
= ARM_CP_STATE_AA64
,
3735 .type
= ARM_CP_ALIAS
,
3736 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 3, .opc2
= 3,
3738 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_FIQ
]) },
3739 { .name
= "MDCR_EL3", .state
= ARM_CP_STATE_AA64
,
3740 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 3, .opc2
= 1,
3742 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.mdcr_el3
) },
3743 { .name
= "SDCR", .type
= ARM_CP_ALIAS
,
3744 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 3, .opc2
= 1,
3745 .access
= PL1_RW
, .accessfn
= access_trap_aa32s_el1
,
3746 .writefn
= sdcr_write
,
3747 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.mdcr_el3
) },
3751 /* Used to describe the behaviour of EL2 regs when EL2 does not exist. */
3752 static const ARMCPRegInfo el3_no_el2_cp_reginfo
[] = {
3753 { .name
= "VBAR_EL2", .state
= ARM_CP_STATE_BOTH
,
3754 .opc0
= 3, .opc1
= 4, .crn
= 12, .crm
= 0, .opc2
= 0,
3756 .readfn
= arm_cp_read_zero
, .writefn
= arm_cp_write_ignore
},
3757 { .name
= "HCR_EL2", .state
= ARM_CP_STATE_BOTH
,
3758 .type
= ARM_CP_NO_RAW
,
3759 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 0,
3761 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
3762 { .name
= "ESR_EL2", .state
= ARM_CP_STATE_BOTH
,
3763 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 2, .opc2
= 0,
3765 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
3766 { .name
= "CPTR_EL2", .state
= ARM_CP_STATE_BOTH
,
3767 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 2,
3768 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
3769 { .name
= "MAIR_EL2", .state
= ARM_CP_STATE_BOTH
,
3770 .opc0
= 3, .opc1
= 4, .crn
= 10, .crm
= 2, .opc2
= 0,
3771 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
3773 { .name
= "HMAIR1", .state
= ARM_CP_STATE_AA32
,
3774 .cp
= 15, .opc1
= 4, .crn
= 10, .crm
= 2, .opc2
= 1,
3775 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
3776 { .name
= "AMAIR_EL2", .state
= ARM_CP_STATE_BOTH
,
3777 .opc0
= 3, .opc1
= 4, .crn
= 10, .crm
= 3, .opc2
= 0,
3778 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
3780 { .name
= "HAMAIR1", .state
= ARM_CP_STATE_AA32
,
3781 .cp
= 15, .opc1
= 4, .crn
= 10, .crm
= 3, .opc2
= 1,
3782 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
3784 { .name
= "AFSR0_EL2", .state
= ARM_CP_STATE_BOTH
,
3785 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 1, .opc2
= 0,
3786 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
3788 { .name
= "AFSR1_EL2", .state
= ARM_CP_STATE_BOTH
,
3789 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 1, .opc2
= 1,
3790 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
3792 { .name
= "TCR_EL2", .state
= ARM_CP_STATE_BOTH
,
3793 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 0, .opc2
= 2,
3794 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
3795 { .name
= "VTCR_EL2", .state
= ARM_CP_STATE_BOTH
,
3796 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 1, .opc2
= 2,
3797 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns_aa64any
,
3798 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
3799 { .name
= "VTTBR", .state
= ARM_CP_STATE_AA32
,
3800 .cp
= 15, .opc1
= 6, .crm
= 2,
3801 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
3802 .type
= ARM_CP_CONST
| ARM_CP_64BIT
, .resetvalue
= 0 },
3803 { .name
= "VTTBR_EL2", .state
= ARM_CP_STATE_AA64
,
3804 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 1, .opc2
= 0,
3805 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
3806 { .name
= "SCTLR_EL2", .state
= ARM_CP_STATE_BOTH
,
3807 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 0, .opc2
= 0,
3808 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
3809 { .name
= "TPIDR_EL2", .state
= ARM_CP_STATE_BOTH
,
3810 .opc0
= 3, .opc1
= 4, .crn
= 13, .crm
= 0, .opc2
= 2,
3811 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
3812 { .name
= "TTBR0_EL2", .state
= ARM_CP_STATE_AA64
,
3813 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 0, .opc2
= 0,
3814 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
3815 { .name
= "HTTBR", .cp
= 15, .opc1
= 4, .crm
= 2,
3816 .access
= PL2_RW
, .type
= ARM_CP_64BIT
| ARM_CP_CONST
,
3818 { .name
= "CNTHCTL_EL2", .state
= ARM_CP_STATE_BOTH
,
3819 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 1, .opc2
= 0,
3820 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
3821 { .name
= "CNTVOFF_EL2", .state
= ARM_CP_STATE_AA64
,
3822 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 0, .opc2
= 3,
3823 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
3824 { .name
= "CNTVOFF", .cp
= 15, .opc1
= 4, .crm
= 14,
3825 .access
= PL2_RW
, .type
= ARM_CP_64BIT
| ARM_CP_CONST
,
3827 { .name
= "CNTHP_CVAL_EL2", .state
= ARM_CP_STATE_AA64
,
3828 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 2, .opc2
= 2,
3829 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
3830 { .name
= "CNTHP_CVAL", .cp
= 15, .opc1
= 6, .crm
= 14,
3831 .access
= PL2_RW
, .type
= ARM_CP_64BIT
| ARM_CP_CONST
,
3833 { .name
= "CNTHP_TVAL_EL2", .state
= ARM_CP_STATE_BOTH
,
3834 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 2, .opc2
= 0,
3835 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
3836 { .name
= "CNTHP_CTL_EL2", .state
= ARM_CP_STATE_BOTH
,
3837 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 2, .opc2
= 1,
3838 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
3839 { .name
= "MDCR_EL2", .state
= ARM_CP_STATE_BOTH
,
3840 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 1,
3841 .access
= PL2_RW
, .accessfn
= access_tda
,
3842 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
3843 { .name
= "HPFAR_EL2", .state
= ARM_CP_STATE_BOTH
,
3844 .opc0
= 3, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 4,
3845 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns_aa64any
,
3846 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
3847 { .name
= "HSTR_EL2", .state
= ARM_CP_STATE_BOTH
,
3848 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 3,
3849 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
3850 { .name
= "FAR_EL2", .state
= ARM_CP_STATE_BOTH
,
3851 .opc0
= 3, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 0,
3852 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
3853 { .name
= "HIFAR", .state
= ARM_CP_STATE_AA32
,
3854 .type
= ARM_CP_CONST
,
3855 .cp
= 15, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 2,
3856 .access
= PL2_RW
, .resetvalue
= 0 },
3860 /* Ditto, but for registers which exist in ARMv8 but not v7 */
3861 static const ARMCPRegInfo el3_no_el2_v8_cp_reginfo
[] = {
3862 { .name
= "HCR2", .state
= ARM_CP_STATE_AA32
,
3863 .cp
= 15, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 4,
3865 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
3869 static void hcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
3871 ARMCPU
*cpu
= arm_env_get_cpu(env
);
3872 uint64_t valid_mask
= HCR_MASK
;
3874 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
3875 valid_mask
&= ~HCR_HCD
;
3876 } else if (cpu
->psci_conduit
!= QEMU_PSCI_CONDUIT_SMC
) {
3877 /* Architecturally HCR.TSC is RES0 if EL3 is not implemented.
3878 * However, if we're using the SMC PSCI conduit then QEMU is
3879 * effectively acting like EL3 firmware and so the guest at
3880 * EL2 should retain the ability to prevent EL1 from being
3881 * able to make SMC calls into the ersatz firmware, so in
3882 * that case HCR.TSC should be read/write.
3884 valid_mask
&= ~HCR_TSC
;
3887 /* Clear RES0 bits. */
3888 value
&= valid_mask
;
3890 /* These bits change the MMU setup:
3891 * HCR_VM enables stage 2 translation
3892 * HCR_PTW forbids certain page-table setups
3893 * HCR_DC Disables stage1 and enables stage2 translation
3895 if ((env
->cp15
.hcr_el2
^ value
) & (HCR_VM
| HCR_PTW
| HCR_DC
)) {
3896 tlb_flush(CPU(cpu
));
3898 env
->cp15
.hcr_el2
= value
;
3901 static void hcr_writehigh(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3904 /* Handle HCR2 write, i.e. write to high half of HCR_EL2 */
3905 value
= deposit64(env
->cp15
.hcr_el2
, 32, 32, value
);
3906 hcr_write(env
, NULL
, value
);
3909 static void hcr_writelow(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3912 /* Handle HCR write, i.e. write to low half of HCR_EL2 */
3913 value
= deposit64(env
->cp15
.hcr_el2
, 0, 32, value
);
3914 hcr_write(env
, NULL
, value
);
3917 static const ARMCPRegInfo el2_cp_reginfo
[] = {
3918 { .name
= "HCR_EL2", .state
= ARM_CP_STATE_AA64
,
3919 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 0,
3920 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.hcr_el2
),
3921 .writefn
= hcr_write
},
3922 { .name
= "HCR", .state
= ARM_CP_STATE_AA32
,
3923 .type
= ARM_CP_ALIAS
,
3924 .cp
= 15, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 0,
3925 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.hcr_el2
),
3926 .writefn
= hcr_writelow
},
3927 { .name
= "ELR_EL2", .state
= ARM_CP_STATE_AA64
,
3928 .type
= ARM_CP_ALIAS
,
3929 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 0, .opc2
= 1,
3931 .fieldoffset
= offsetof(CPUARMState
, elr_el
[2]) },
3932 { .name
= "ESR_EL2", .state
= ARM_CP_STATE_BOTH
,
3933 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 2, .opc2
= 0,
3934 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.esr_el
[2]) },
3935 { .name
= "FAR_EL2", .state
= ARM_CP_STATE_BOTH
,
3936 .opc0
= 3, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 0,
3937 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.far_el
[2]) },
3938 { .name
= "HIFAR", .state
= ARM_CP_STATE_AA32
,
3939 .type
= ARM_CP_ALIAS
,
3940 .cp
= 15, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 2,
3942 .fieldoffset
= offsetofhigh32(CPUARMState
, cp15
.far_el
[2]) },
3943 { .name
= "SPSR_EL2", .state
= ARM_CP_STATE_AA64
,
3944 .type
= ARM_CP_ALIAS
,
3945 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 0, .opc2
= 0,
3947 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_HYP
]) },
3948 { .name
= "VBAR_EL2", .state
= ARM_CP_STATE_BOTH
,
3949 .opc0
= 3, .opc1
= 4, .crn
= 12, .crm
= 0, .opc2
= 0,
3950 .access
= PL2_RW
, .writefn
= vbar_write
,
3951 .fieldoffset
= offsetof(CPUARMState
, cp15
.vbar_el
[2]),
3953 { .name
= "SP_EL2", .state
= ARM_CP_STATE_AA64
,
3954 .opc0
= 3, .opc1
= 6, .crn
= 4, .crm
= 1, .opc2
= 0,
3955 .access
= PL3_RW
, .type
= ARM_CP_ALIAS
,
3956 .fieldoffset
= offsetof(CPUARMState
, sp_el
[2]) },
3957 { .name
= "CPTR_EL2", .state
= ARM_CP_STATE_BOTH
,
3958 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 2,
3959 .access
= PL2_RW
, .accessfn
= cptr_access
, .resetvalue
= 0,
3960 .fieldoffset
= offsetof(CPUARMState
, cp15
.cptr_el
[2]) },
3961 { .name
= "MAIR_EL2", .state
= ARM_CP_STATE_BOTH
,
3962 .opc0
= 3, .opc1
= 4, .crn
= 10, .crm
= 2, .opc2
= 0,
3963 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.mair_el
[2]),
3965 { .name
= "HMAIR1", .state
= ARM_CP_STATE_AA32
,
3966 .cp
= 15, .opc1
= 4, .crn
= 10, .crm
= 2, .opc2
= 1,
3967 .access
= PL2_RW
, .type
= ARM_CP_ALIAS
,
3968 .fieldoffset
= offsetofhigh32(CPUARMState
, cp15
.mair_el
[2]) },
3969 { .name
= "AMAIR_EL2", .state
= ARM_CP_STATE_BOTH
,
3970 .opc0
= 3, .opc1
= 4, .crn
= 10, .crm
= 3, .opc2
= 0,
3971 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
3973 /* HAMAIR1 is mapped to AMAIR_EL2[63:32] */
3974 { .name
= "HAMAIR1", .state
= ARM_CP_STATE_AA32
,
3975 .cp
= 15, .opc1
= 4, .crn
= 10, .crm
= 3, .opc2
= 1,
3976 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
3978 { .name
= "AFSR0_EL2", .state
= ARM_CP_STATE_BOTH
,
3979 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 1, .opc2
= 0,
3980 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
3982 { .name
= "AFSR1_EL2", .state
= ARM_CP_STATE_BOTH
,
3983 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 1, .opc2
= 1,
3984 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
3986 { .name
= "TCR_EL2", .state
= ARM_CP_STATE_BOTH
,
3987 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 0, .opc2
= 2,
3989 /* no .writefn needed as this can't cause an ASID change;
3990 * no .raw_writefn or .resetfn needed as we never use mask/base_mask
3992 .fieldoffset
= offsetof(CPUARMState
, cp15
.tcr_el
[2]) },
3993 { .name
= "VTCR", .state
= ARM_CP_STATE_AA32
,
3994 .cp
= 15, .opc1
= 4, .crn
= 2, .crm
= 1, .opc2
= 2,
3995 .type
= ARM_CP_ALIAS
,
3996 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
3997 .fieldoffset
= offsetof(CPUARMState
, cp15
.vtcr_el2
) },
3998 { .name
= "VTCR_EL2", .state
= ARM_CP_STATE_AA64
,
3999 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 1, .opc2
= 2,
4001 /* no .writefn needed as this can't cause an ASID change;
4002 * no .raw_writefn or .resetfn needed as we never use mask/base_mask
4004 .fieldoffset
= offsetof(CPUARMState
, cp15
.vtcr_el2
) },
4005 { .name
= "VTTBR", .state
= ARM_CP_STATE_AA32
,
4006 .cp
= 15, .opc1
= 6, .crm
= 2,
4007 .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
,
4008 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
4009 .fieldoffset
= offsetof(CPUARMState
, cp15
.vttbr_el2
),
4010 .writefn
= vttbr_write
},
4011 { .name
= "VTTBR_EL2", .state
= ARM_CP_STATE_AA64
,
4012 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 1, .opc2
= 0,
4013 .access
= PL2_RW
, .writefn
= vttbr_write
,
4014 .fieldoffset
= offsetof(CPUARMState
, cp15
.vttbr_el2
) },
4015 { .name
= "SCTLR_EL2", .state
= ARM_CP_STATE_BOTH
,
4016 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 0, .opc2
= 0,
4017 .access
= PL2_RW
, .raw_writefn
= raw_write
, .writefn
= sctlr_write
,
4018 .fieldoffset
= offsetof(CPUARMState
, cp15
.sctlr_el
[2]) },
4019 { .name
= "TPIDR_EL2", .state
= ARM_CP_STATE_BOTH
,
4020 .opc0
= 3, .opc1
= 4, .crn
= 13, .crm
= 0, .opc2
= 2,
4021 .access
= PL2_RW
, .resetvalue
= 0,
4022 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidr_el
[2]) },
4023 { .name
= "TTBR0_EL2", .state
= ARM_CP_STATE_AA64
,
4024 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 0, .opc2
= 0,
4025 .access
= PL2_RW
, .resetvalue
= 0,
4026 .fieldoffset
= offsetof(CPUARMState
, cp15
.ttbr0_el
[2]) },
4027 { .name
= "HTTBR", .cp
= 15, .opc1
= 4, .crm
= 2,
4028 .access
= PL2_RW
, .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
,
4029 .fieldoffset
= offsetof(CPUARMState
, cp15
.ttbr0_el
[2]) },
4030 { .name
= "TLBIALLNSNH",
4031 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 4,
4032 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
4033 .writefn
= tlbiall_nsnh_write
},
4034 { .name
= "TLBIALLNSNHIS",
4035 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 4,
4036 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
4037 .writefn
= tlbiall_nsnh_is_write
},
4038 { .name
= "TLBIALLH", .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 0,
4039 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
4040 .writefn
= tlbiall_hyp_write
},
4041 { .name
= "TLBIALLHIS", .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 0,
4042 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
4043 .writefn
= tlbiall_hyp_is_write
},
4044 { .name
= "TLBIMVAH", .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 1,
4045 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
4046 .writefn
= tlbimva_hyp_write
},
4047 { .name
= "TLBIMVAHIS", .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 1,
4048 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
4049 .writefn
= tlbimva_hyp_is_write
},
4050 { .name
= "TLBI_ALLE2", .state
= ARM_CP_STATE_AA64
,
4051 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 0,
4052 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
4053 .writefn
= tlbi_aa64_alle2_write
},
4054 { .name
= "TLBI_VAE2", .state
= ARM_CP_STATE_AA64
,
4055 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 1,
4056 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
4057 .writefn
= tlbi_aa64_vae2_write
},
4058 { .name
= "TLBI_VALE2", .state
= ARM_CP_STATE_AA64
,
4059 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 5,
4060 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
4061 .writefn
= tlbi_aa64_vae2_write
},
4062 { .name
= "TLBI_ALLE2IS", .state
= ARM_CP_STATE_AA64
,
4063 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 0,
4064 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
4065 .writefn
= tlbi_aa64_alle2is_write
},
4066 { .name
= "TLBI_VAE2IS", .state
= ARM_CP_STATE_AA64
,
4067 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 1,
4068 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
4069 .writefn
= tlbi_aa64_vae2is_write
},
4070 { .name
= "TLBI_VALE2IS", .state
= ARM_CP_STATE_AA64
,
4071 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 5,
4072 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
4073 .writefn
= tlbi_aa64_vae2is_write
},
4074 #ifndef CONFIG_USER_ONLY
4075 /* Unlike the other EL2-related AT operations, these must
4076 * UNDEF from EL3 if EL2 is not implemented, which is why we
4077 * define them here rather than with the rest of the AT ops.
4079 { .name
= "AT_S1E2R", .state
= ARM_CP_STATE_AA64
,
4080 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 0,
4081 .access
= PL2_W
, .accessfn
= at_s1e2_access
,
4082 .type
= ARM_CP_NO_RAW
, .writefn
= ats_write64
},
4083 { .name
= "AT_S1E2W", .state
= ARM_CP_STATE_AA64
,
4084 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 1,
4085 .access
= PL2_W
, .accessfn
= at_s1e2_access
,
4086 .type
= ARM_CP_NO_RAW
, .writefn
= ats_write64
},
4087 /* The AArch32 ATS1H* operations are CONSTRAINED UNPREDICTABLE
4088 * if EL2 is not implemented; we choose to UNDEF. Behaviour at EL3
4089 * with SCR.NS == 0 outside Monitor mode is UNPREDICTABLE; we choose
4090 * to behave as if SCR.NS was 1.
4092 { .name
= "ATS1HR", .cp
= 15, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 0,
4094 .writefn
= ats1h_write
, .type
= ARM_CP_NO_RAW
},
4095 { .name
= "ATS1HW", .cp
= 15, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 1,
4097 .writefn
= ats1h_write
, .type
= ARM_CP_NO_RAW
},
4098 { .name
= "CNTHCTL_EL2", .state
= ARM_CP_STATE_BOTH
,
4099 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 1, .opc2
= 0,
4100 /* ARMv7 requires bit 0 and 1 to reset to 1. ARMv8 defines the
4101 * reset values as IMPDEF. We choose to reset to 3 to comply with
4102 * both ARMv7 and ARMv8.
4104 .access
= PL2_RW
, .resetvalue
= 3,
4105 .fieldoffset
= offsetof(CPUARMState
, cp15
.cnthctl_el2
) },
4106 { .name
= "CNTVOFF_EL2", .state
= ARM_CP_STATE_AA64
,
4107 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 0, .opc2
= 3,
4108 .access
= PL2_RW
, .type
= ARM_CP_IO
, .resetvalue
= 0,
4109 .writefn
= gt_cntvoff_write
,
4110 .fieldoffset
= offsetof(CPUARMState
, cp15
.cntvoff_el2
) },
4111 { .name
= "CNTVOFF", .cp
= 15, .opc1
= 4, .crm
= 14,
4112 .access
= PL2_RW
, .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
| ARM_CP_IO
,
4113 .writefn
= gt_cntvoff_write
,
4114 .fieldoffset
= offsetof(CPUARMState
, cp15
.cntvoff_el2
) },
4115 { .name
= "CNTHP_CVAL_EL2", .state
= ARM_CP_STATE_AA64
,
4116 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 2, .opc2
= 2,
4117 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_HYP
].cval
),
4118 .type
= ARM_CP_IO
, .access
= PL2_RW
,
4119 .writefn
= gt_hyp_cval_write
, .raw_writefn
= raw_write
},
4120 { .name
= "CNTHP_CVAL", .cp
= 15, .opc1
= 6, .crm
= 14,
4121 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_HYP
].cval
),
4122 .access
= PL2_RW
, .type
= ARM_CP_64BIT
| ARM_CP_IO
,
4123 .writefn
= gt_hyp_cval_write
, .raw_writefn
= raw_write
},
4124 { .name
= "CNTHP_TVAL_EL2", .state
= ARM_CP_STATE_BOTH
,
4125 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 2, .opc2
= 0,
4126 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL2_RW
,
4127 .resetfn
= gt_hyp_timer_reset
,
4128 .readfn
= gt_hyp_tval_read
, .writefn
= gt_hyp_tval_write
},
4129 { .name
= "CNTHP_CTL_EL2", .state
= ARM_CP_STATE_BOTH
,
4131 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 2, .opc2
= 1,
4133 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_HYP
].ctl
),
4135 .writefn
= gt_hyp_ctl_write
, .raw_writefn
= raw_write
},
4137 /* The only field of MDCR_EL2 that has a defined architectural reset value
4138 * is MDCR_EL2.HPMN which should reset to the value of PMCR_EL0.N; but we
4139 * don't impelment any PMU event counters, so using zero as a reset
4140 * value for MDCR_EL2 is okay
4142 { .name
= "MDCR_EL2", .state
= ARM_CP_STATE_BOTH
,
4143 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 1,
4144 .access
= PL2_RW
, .resetvalue
= 0,
4145 .fieldoffset
= offsetof(CPUARMState
, cp15
.mdcr_el2
), },
4146 { .name
= "HPFAR", .state
= ARM_CP_STATE_AA32
,
4147 .cp
= 15, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 4,
4148 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
4149 .fieldoffset
= offsetof(CPUARMState
, cp15
.hpfar_el2
) },
4150 { .name
= "HPFAR_EL2", .state
= ARM_CP_STATE_AA64
,
4151 .opc0
= 3, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 4,
4153 .fieldoffset
= offsetof(CPUARMState
, cp15
.hpfar_el2
) },
4154 { .name
= "HSTR_EL2", .state
= ARM_CP_STATE_BOTH
,
4155 .cp
= 15, .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 3,
4157 .fieldoffset
= offsetof(CPUARMState
, cp15
.hstr_el2
) },
4161 static const ARMCPRegInfo el2_v8_cp_reginfo
[] = {
4162 { .name
= "HCR2", .state
= ARM_CP_STATE_AA32
,
4163 .type
= ARM_CP_ALIAS
,
4164 .cp
= 15, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 4,
4166 .fieldoffset
= offsetofhigh32(CPUARMState
, cp15
.hcr_el2
),
4167 .writefn
= hcr_writehigh
},
4171 static CPAccessResult
nsacr_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4174 /* The NSACR is RW at EL3, and RO for NS EL1 and NS EL2.
4175 * At Secure EL1 it traps to EL3.
4177 if (arm_current_el(env
) == 3) {
4178 return CP_ACCESS_OK
;
4180 if (arm_is_secure_below_el3(env
)) {
4181 return CP_ACCESS_TRAP_EL3
;
4183 /* Accesses from EL1 NS and EL2 NS are UNDEF for write but allow reads. */
4185 return CP_ACCESS_OK
;
4187 return CP_ACCESS_TRAP_UNCATEGORIZED
;
4190 static const ARMCPRegInfo el3_cp_reginfo
[] = {
4191 { .name
= "SCR_EL3", .state
= ARM_CP_STATE_AA64
,
4192 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 1, .opc2
= 0,
4193 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.scr_el3
),
4194 .resetvalue
= 0, .writefn
= scr_write
},
4195 { .name
= "SCR", .type
= ARM_CP_ALIAS
,
4196 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 0,
4197 .access
= PL1_RW
, .accessfn
= access_trap_aa32s_el1
,
4198 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.scr_el3
),
4199 .writefn
= scr_write
},
4200 { .name
= "SDER32_EL3", .state
= ARM_CP_STATE_AA64
,
4201 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 1, .opc2
= 1,
4202 .access
= PL3_RW
, .resetvalue
= 0,
4203 .fieldoffset
= offsetof(CPUARMState
, cp15
.sder
) },
4205 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 1,
4206 .access
= PL3_RW
, .resetvalue
= 0,
4207 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.sder
) },
4208 { .name
= "MVBAR", .cp
= 15, .opc1
= 0, .crn
= 12, .crm
= 0, .opc2
= 1,
4209 .access
= PL1_RW
, .accessfn
= access_trap_aa32s_el1
,
4210 .writefn
= vbar_write
, .resetvalue
= 0,
4211 .fieldoffset
= offsetof(CPUARMState
, cp15
.mvbar
) },
4212 { .name
= "TTBR0_EL3", .state
= ARM_CP_STATE_AA64
,
4213 .opc0
= 3, .opc1
= 6, .crn
= 2, .crm
= 0, .opc2
= 0,
4214 .access
= PL3_RW
, .writefn
= vmsa_ttbr_write
, .resetvalue
= 0,
4215 .fieldoffset
= offsetof(CPUARMState
, cp15
.ttbr0_el
[3]) },
4216 { .name
= "TCR_EL3", .state
= ARM_CP_STATE_AA64
,
4217 .opc0
= 3, .opc1
= 6, .crn
= 2, .crm
= 0, .opc2
= 2,
4219 /* no .writefn needed as this can't cause an ASID change;
4220 * we must provide a .raw_writefn and .resetfn because we handle
4221 * reset and migration for the AArch32 TTBCR(S), which might be
4222 * using mask and base_mask.
4224 .resetfn
= vmsa_ttbcr_reset
, .raw_writefn
= vmsa_ttbcr_raw_write
,
4225 .fieldoffset
= offsetof(CPUARMState
, cp15
.tcr_el
[3]) },
4226 { .name
= "ELR_EL3", .state
= ARM_CP_STATE_AA64
,
4227 .type
= ARM_CP_ALIAS
,
4228 .opc0
= 3, .opc1
= 6, .crn
= 4, .crm
= 0, .opc2
= 1,
4230 .fieldoffset
= offsetof(CPUARMState
, elr_el
[3]) },
4231 { .name
= "ESR_EL3", .state
= ARM_CP_STATE_AA64
,
4232 .opc0
= 3, .opc1
= 6, .crn
= 5, .crm
= 2, .opc2
= 0,
4233 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.esr_el
[3]) },
4234 { .name
= "FAR_EL3", .state
= ARM_CP_STATE_AA64
,
4235 .opc0
= 3, .opc1
= 6, .crn
= 6, .crm
= 0, .opc2
= 0,
4236 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.far_el
[3]) },
4237 { .name
= "SPSR_EL3", .state
= ARM_CP_STATE_AA64
,
4238 .type
= ARM_CP_ALIAS
,
4239 .opc0
= 3, .opc1
= 6, .crn
= 4, .crm
= 0, .opc2
= 0,
4241 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_MON
]) },
4242 { .name
= "VBAR_EL3", .state
= ARM_CP_STATE_AA64
,
4243 .opc0
= 3, .opc1
= 6, .crn
= 12, .crm
= 0, .opc2
= 0,
4244 .access
= PL3_RW
, .writefn
= vbar_write
,
4245 .fieldoffset
= offsetof(CPUARMState
, cp15
.vbar_el
[3]),
4247 { .name
= "CPTR_EL3", .state
= ARM_CP_STATE_AA64
,
4248 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 1, .opc2
= 2,
4249 .access
= PL3_RW
, .accessfn
= cptr_access
, .resetvalue
= 0,
4250 .fieldoffset
= offsetof(CPUARMState
, cp15
.cptr_el
[3]) },
4251 { .name
= "TPIDR_EL3", .state
= ARM_CP_STATE_AA64
,
4252 .opc0
= 3, .opc1
= 6, .crn
= 13, .crm
= 0, .opc2
= 2,
4253 .access
= PL3_RW
, .resetvalue
= 0,
4254 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidr_el
[3]) },
4255 { .name
= "AMAIR_EL3", .state
= ARM_CP_STATE_AA64
,
4256 .opc0
= 3, .opc1
= 6, .crn
= 10, .crm
= 3, .opc2
= 0,
4257 .access
= PL3_RW
, .type
= ARM_CP_CONST
,
4259 { .name
= "AFSR0_EL3", .state
= ARM_CP_STATE_BOTH
,
4260 .opc0
= 3, .opc1
= 6, .crn
= 5, .crm
= 1, .opc2
= 0,
4261 .access
= PL3_RW
, .type
= ARM_CP_CONST
,
4263 { .name
= "AFSR1_EL3", .state
= ARM_CP_STATE_BOTH
,
4264 .opc0
= 3, .opc1
= 6, .crn
= 5, .crm
= 1, .opc2
= 1,
4265 .access
= PL3_RW
, .type
= ARM_CP_CONST
,
4267 { .name
= "TLBI_ALLE3IS", .state
= ARM_CP_STATE_AA64
,
4268 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 3, .opc2
= 0,
4269 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
4270 .writefn
= tlbi_aa64_alle3is_write
},
4271 { .name
= "TLBI_VAE3IS", .state
= ARM_CP_STATE_AA64
,
4272 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 3, .opc2
= 1,
4273 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
4274 .writefn
= tlbi_aa64_vae3is_write
},
4275 { .name
= "TLBI_VALE3IS", .state
= ARM_CP_STATE_AA64
,
4276 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 3, .opc2
= 5,
4277 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
4278 .writefn
= tlbi_aa64_vae3is_write
},
4279 { .name
= "TLBI_ALLE3", .state
= ARM_CP_STATE_AA64
,
4280 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 7, .opc2
= 0,
4281 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
4282 .writefn
= tlbi_aa64_alle3_write
},
4283 { .name
= "TLBI_VAE3", .state
= ARM_CP_STATE_AA64
,
4284 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 7, .opc2
= 1,
4285 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
4286 .writefn
= tlbi_aa64_vae3_write
},
4287 { .name
= "TLBI_VALE3", .state
= ARM_CP_STATE_AA64
,
4288 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 7, .opc2
= 5,
4289 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
4290 .writefn
= tlbi_aa64_vae3_write
},
4294 static CPAccessResult
ctr_el0_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4297 /* Only accessible in EL0 if SCTLR.UCT is set (and only in AArch64,
4298 * but the AArch32 CTR has its own reginfo struct)
4300 if (arm_current_el(env
) == 0 && !(env
->cp15
.sctlr_el
[1] & SCTLR_UCT
)) {
4301 return CP_ACCESS_TRAP
;
4303 return CP_ACCESS_OK
;
4306 static void oslar_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4309 /* Writes to OSLAR_EL1 may update the OS lock status, which can be
4310 * read via a bit in OSLSR_EL1.
4314 if (ri
->state
== ARM_CP_STATE_AA32
) {
4315 oslock
= (value
== 0xC5ACCE55);
4320 env
->cp15
.oslsr_el1
= deposit32(env
->cp15
.oslsr_el1
, 1, 1, oslock
);
4323 static const ARMCPRegInfo debug_cp_reginfo
[] = {
4324 /* DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped
4325 * debug components. The AArch64 version of DBGDRAR is named MDRAR_EL1;
4326 * unlike DBGDRAR it is never accessible from EL0.
4327 * DBGDSAR is deprecated and must RAZ from v8 anyway, so it has no AArch64
4330 { .name
= "DBGDRAR", .cp
= 14, .crn
= 1, .crm
= 0, .opc1
= 0, .opc2
= 0,
4331 .access
= PL0_R
, .accessfn
= access_tdra
,
4332 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4333 { .name
= "MDRAR_EL1", .state
= ARM_CP_STATE_AA64
,
4334 .opc0
= 2, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 0,
4335 .access
= PL1_R
, .accessfn
= access_tdra
,
4336 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4337 { .name
= "DBGDSAR", .cp
= 14, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 0,
4338 .access
= PL0_R
, .accessfn
= access_tdra
,
4339 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4340 /* Monitor debug system control register; the 32-bit alias is DBGDSCRext. */
4341 { .name
= "MDSCR_EL1", .state
= ARM_CP_STATE_BOTH
,
4342 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 2,
4343 .access
= PL1_RW
, .accessfn
= access_tda
,
4344 .fieldoffset
= offsetof(CPUARMState
, cp15
.mdscr_el1
),
4346 /* MDCCSR_EL0, aka DBGDSCRint. This is a read-only mirror of MDSCR_EL1.
4347 * We don't implement the configurable EL0 access.
4349 { .name
= "MDCCSR_EL0", .state
= ARM_CP_STATE_BOTH
,
4350 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 0,
4351 .type
= ARM_CP_ALIAS
,
4352 .access
= PL1_R
, .accessfn
= access_tda
,
4353 .fieldoffset
= offsetof(CPUARMState
, cp15
.mdscr_el1
), },
4354 { .name
= "OSLAR_EL1", .state
= ARM_CP_STATE_BOTH
,
4355 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 4,
4356 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
4357 .accessfn
= access_tdosa
,
4358 .writefn
= oslar_write
},
4359 { .name
= "OSLSR_EL1", .state
= ARM_CP_STATE_BOTH
,
4360 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 4,
4361 .access
= PL1_R
, .resetvalue
= 10,
4362 .accessfn
= access_tdosa
,
4363 .fieldoffset
= offsetof(CPUARMState
, cp15
.oslsr_el1
) },
4364 /* Dummy OSDLR_EL1: 32-bit Linux will read this */
4365 { .name
= "OSDLR_EL1", .state
= ARM_CP_STATE_BOTH
,
4366 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 1, .crm
= 3, .opc2
= 4,
4367 .access
= PL1_RW
, .accessfn
= access_tdosa
,
4368 .type
= ARM_CP_NOP
},
4369 /* Dummy DBGVCR: Linux wants to clear this on startup, but we don't
4370 * implement vector catch debug events yet.
4373 .cp
= 14, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 0,
4374 .access
= PL1_RW
, .accessfn
= access_tda
,
4375 .type
= ARM_CP_NOP
},
4376 /* Dummy DBGVCR32_EL2 (which is only for a 64-bit hypervisor
4377 * to save and restore a 32-bit guest's DBGVCR)
4379 { .name
= "DBGVCR32_EL2", .state
= ARM_CP_STATE_AA64
,
4380 .opc0
= 2, .opc1
= 4, .crn
= 0, .crm
= 7, .opc2
= 0,
4381 .access
= PL2_RW
, .accessfn
= access_tda
,
4382 .type
= ARM_CP_NOP
},
4383 /* Dummy MDCCINT_EL1, since we don't implement the Debug Communications
4384 * Channel but Linux may try to access this register. The 32-bit
4385 * alias is DBGDCCINT.
4387 { .name
= "MDCCINT_EL1", .state
= ARM_CP_STATE_BOTH
,
4388 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 0,
4389 .access
= PL1_RW
, .accessfn
= access_tda
,
4390 .type
= ARM_CP_NOP
},
4394 static const ARMCPRegInfo debug_lpae_cp_reginfo
[] = {
4395 /* 64 bit access versions of the (dummy) debug registers */
4396 { .name
= "DBGDRAR", .cp
= 14, .crm
= 1, .opc1
= 0,
4397 .access
= PL0_R
, .type
= ARM_CP_CONST
|ARM_CP_64BIT
, .resetvalue
= 0 },
4398 { .name
= "DBGDSAR", .cp
= 14, .crm
= 2, .opc1
= 0,
4399 .access
= PL0_R
, .type
= ARM_CP_CONST
|ARM_CP_64BIT
, .resetvalue
= 0 },
4403 /* Return the exception level to which exceptions should be taken
4404 * via SVEAccessTrap. If an exception should be routed through
4405 * AArch64.AdvSIMDFPAccessTrap, return 0; fp_exception_el should
4406 * take care of raising that exception.
4407 * C.f. the ARM pseudocode function CheckSVEEnabled.
4409 int sve_exception_el(CPUARMState
*env
, int el
)
4411 #ifndef CONFIG_USER_ONLY
4413 bool disabled
= false;
4415 /* The CPACR.ZEN controls traps to EL1:
4416 * 0, 2 : trap EL0 and EL1 accesses
4417 * 1 : trap only EL0 accesses
4418 * 3 : trap no accesses
4420 if (!extract32(env
->cp15
.cpacr_el1
, 16, 1)) {
4422 } else if (!extract32(env
->cp15
.cpacr_el1
, 17, 1)) {
4427 return (arm_feature(env
, ARM_FEATURE_EL2
)
4428 && !arm_is_secure(env
)
4429 && (env
->cp15
.hcr_el2
& HCR_TGE
) ? 2 : 1);
4432 /* Check CPACR.FPEN. */
4433 if (!extract32(env
->cp15
.cpacr_el1
, 20, 1)) {
4435 } else if (!extract32(env
->cp15
.cpacr_el1
, 21, 1)) {
4443 /* CPTR_EL2. Since TZ and TFP are positive,
4444 * they will be zero when EL2 is not present.
4446 if (el
<= 2 && !arm_is_secure_below_el3(env
)) {
4447 if (env
->cp15
.cptr_el
[2] & CPTR_TZ
) {
4450 if (env
->cp15
.cptr_el
[2] & CPTR_TFP
) {
4455 /* CPTR_EL3. Since EZ is negative we must check for EL3. */
4456 if (arm_feature(env
, ARM_FEATURE_EL3
)
4457 && !(env
->cp15
.cptr_el
[3] & CPTR_EZ
)) {
4465 * Given that SVE is enabled, return the vector length for EL.
4467 uint32_t sve_zcr_len_for_el(CPUARMState
*env
, int el
)
4469 ARMCPU
*cpu
= arm_env_get_cpu(env
);
4470 uint32_t zcr_len
= cpu
->sve_max_vq
- 1;
4473 zcr_len
= MIN(zcr_len
, 0xf & (uint32_t)env
->vfp
.zcr_el
[1]);
4475 if (el
< 2 && arm_feature(env
, ARM_FEATURE_EL2
)) {
4476 zcr_len
= MIN(zcr_len
, 0xf & (uint32_t)env
->vfp
.zcr_el
[2]);
4478 if (el
< 3 && arm_feature(env
, ARM_FEATURE_EL3
)) {
4479 zcr_len
= MIN(zcr_len
, 0xf & (uint32_t)env
->vfp
.zcr_el
[3]);
4484 static void zcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4487 int cur_el
= arm_current_el(env
);
4488 int old_len
= sve_zcr_len_for_el(env
, cur_el
);
4491 /* Bits other than [3:0] are RAZ/WI. */
4492 raw_write(env
, ri
, value
& 0xf);
4495 * Because we arrived here, we know both FP and SVE are enabled;
4496 * otherwise we would have trapped access to the ZCR_ELn register.
4498 new_len
= sve_zcr_len_for_el(env
, cur_el
);
4499 if (new_len
< old_len
) {
4500 aarch64_sve_narrow_vq(env
, new_len
+ 1);
4504 static const ARMCPRegInfo zcr_el1_reginfo
= {
4505 .name
= "ZCR_EL1", .state
= ARM_CP_STATE_AA64
,
4506 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 2, .opc2
= 0,
4507 .access
= PL1_RW
, .type
= ARM_CP_SVE
,
4508 .fieldoffset
= offsetof(CPUARMState
, vfp
.zcr_el
[1]),
4509 .writefn
= zcr_write
, .raw_writefn
= raw_write
4512 static const ARMCPRegInfo zcr_el2_reginfo
= {
4513 .name
= "ZCR_EL2", .state
= ARM_CP_STATE_AA64
,
4514 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 2, .opc2
= 0,
4515 .access
= PL2_RW
, .type
= ARM_CP_SVE
,
4516 .fieldoffset
= offsetof(CPUARMState
, vfp
.zcr_el
[2]),
4517 .writefn
= zcr_write
, .raw_writefn
= raw_write
4520 static const ARMCPRegInfo zcr_no_el2_reginfo
= {
4521 .name
= "ZCR_EL2", .state
= ARM_CP_STATE_AA64
,
4522 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 2, .opc2
= 0,
4523 .access
= PL2_RW
, .type
= ARM_CP_SVE
,
4524 .readfn
= arm_cp_read_zero
, .writefn
= arm_cp_write_ignore
4527 static const ARMCPRegInfo zcr_el3_reginfo
= {
4528 .name
= "ZCR_EL3", .state
= ARM_CP_STATE_AA64
,
4529 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 2, .opc2
= 0,
4530 .access
= PL3_RW
, .type
= ARM_CP_SVE
,
4531 .fieldoffset
= offsetof(CPUARMState
, vfp
.zcr_el
[3]),
4532 .writefn
= zcr_write
, .raw_writefn
= raw_write
4535 void hw_watchpoint_update(ARMCPU
*cpu
, int n
)
4537 CPUARMState
*env
= &cpu
->env
;
4539 vaddr wvr
= env
->cp15
.dbgwvr
[n
];
4540 uint64_t wcr
= env
->cp15
.dbgwcr
[n
];
4542 int flags
= BP_CPU
| BP_STOP_BEFORE_ACCESS
;
4544 if (env
->cpu_watchpoint
[n
]) {
4545 cpu_watchpoint_remove_by_ref(CPU(cpu
), env
->cpu_watchpoint
[n
]);
4546 env
->cpu_watchpoint
[n
] = NULL
;
4549 if (!extract64(wcr
, 0, 1)) {
4550 /* E bit clear : watchpoint disabled */
4554 switch (extract64(wcr
, 3, 2)) {
4556 /* LSC 00 is reserved and must behave as if the wp is disabled */
4559 flags
|= BP_MEM_READ
;
4562 flags
|= BP_MEM_WRITE
;
4565 flags
|= BP_MEM_ACCESS
;
4569 /* Attempts to use both MASK and BAS fields simultaneously are
4570 * CONSTRAINED UNPREDICTABLE; we opt to ignore BAS in this case,
4571 * thus generating a watchpoint for every byte in the masked region.
4573 mask
= extract64(wcr
, 24, 4);
4574 if (mask
== 1 || mask
== 2) {
4575 /* Reserved values of MASK; we must act as if the mask value was
4576 * some non-reserved value, or as if the watchpoint were disabled.
4577 * We choose the latter.
4581 /* Watchpoint covers an aligned area up to 2GB in size */
4583 /* If masked bits in WVR are not zero it's CONSTRAINED UNPREDICTABLE
4584 * whether the watchpoint fires when the unmasked bits match; we opt
4585 * to generate the exceptions.
4589 /* Watchpoint covers bytes defined by the byte address select bits */
4590 int bas
= extract64(wcr
, 5, 8);
4594 /* This must act as if the watchpoint is disabled */
4598 if (extract64(wvr
, 2, 1)) {
4599 /* Deprecated case of an only 4-aligned address. BAS[7:4] are
4600 * ignored, and BAS[3:0] define which bytes to watch.
4604 /* The BAS bits are supposed to be programmed to indicate a contiguous
4605 * range of bytes. Otherwise it is CONSTRAINED UNPREDICTABLE whether
4606 * we fire for each byte in the word/doubleword addressed by the WVR.
4607 * We choose to ignore any non-zero bits after the first range of 1s.
4609 basstart
= ctz32(bas
);
4610 len
= cto32(bas
>> basstart
);
4614 cpu_watchpoint_insert(CPU(cpu
), wvr
, len
, flags
,
4615 &env
->cpu_watchpoint
[n
]);
4618 void hw_watchpoint_update_all(ARMCPU
*cpu
)
4621 CPUARMState
*env
= &cpu
->env
;
4623 /* Completely clear out existing QEMU watchpoints and our array, to
4624 * avoid possible stale entries following migration load.
4626 cpu_watchpoint_remove_all(CPU(cpu
), BP_CPU
);
4627 memset(env
->cpu_watchpoint
, 0, sizeof(env
->cpu_watchpoint
));
4629 for (i
= 0; i
< ARRAY_SIZE(cpu
->env
.cpu_watchpoint
); i
++) {
4630 hw_watchpoint_update(cpu
, i
);
4634 static void dbgwvr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4637 ARMCPU
*cpu
= arm_env_get_cpu(env
);
4640 /* Bits [63:49] are hardwired to the value of bit [48]; that is, the
4641 * register reads and behaves as if values written are sign extended.
4642 * Bits [1:0] are RES0.
4644 value
= sextract64(value
, 0, 49) & ~3ULL;
4646 raw_write(env
, ri
, value
);
4647 hw_watchpoint_update(cpu
, i
);
4650 static void dbgwcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4653 ARMCPU
*cpu
= arm_env_get_cpu(env
);
4656 raw_write(env
, ri
, value
);
4657 hw_watchpoint_update(cpu
, i
);
4660 void hw_breakpoint_update(ARMCPU
*cpu
, int n
)
4662 CPUARMState
*env
= &cpu
->env
;
4663 uint64_t bvr
= env
->cp15
.dbgbvr
[n
];
4664 uint64_t bcr
= env
->cp15
.dbgbcr
[n
];
4669 if (env
->cpu_breakpoint
[n
]) {
4670 cpu_breakpoint_remove_by_ref(CPU(cpu
), env
->cpu_breakpoint
[n
]);
4671 env
->cpu_breakpoint
[n
] = NULL
;
4674 if (!extract64(bcr
, 0, 1)) {
4675 /* E bit clear : watchpoint disabled */
4679 bt
= extract64(bcr
, 20, 4);
4682 case 4: /* unlinked address mismatch (reserved if AArch64) */
4683 case 5: /* linked address mismatch (reserved if AArch64) */
4684 qemu_log_mask(LOG_UNIMP
,
4685 "arm: address mismatch breakpoint types not implemented\n");
4687 case 0: /* unlinked address match */
4688 case 1: /* linked address match */
4690 /* Bits [63:49] are hardwired to the value of bit [48]; that is,
4691 * we behave as if the register was sign extended. Bits [1:0] are
4692 * RES0. The BAS field is used to allow setting breakpoints on 16
4693 * bit wide instructions; it is CONSTRAINED UNPREDICTABLE whether
4694 * a bp will fire if the addresses covered by the bp and the addresses
4695 * covered by the insn overlap but the insn doesn't start at the
4696 * start of the bp address range. We choose to require the insn and
4697 * the bp to have the same address. The constraints on writing to
4698 * BAS enforced in dbgbcr_write mean we have only four cases:
4699 * 0b0000 => no breakpoint
4700 * 0b0011 => breakpoint on addr
4701 * 0b1100 => breakpoint on addr + 2
4702 * 0b1111 => breakpoint on addr
4703 * See also figure D2-3 in the v8 ARM ARM (DDI0487A.c).
4705 int bas
= extract64(bcr
, 5, 4);
4706 addr
= sextract64(bvr
, 0, 49) & ~3ULL;
4715 case 2: /* unlinked context ID match */
4716 case 8: /* unlinked VMID match (reserved if no EL2) */
4717 case 10: /* unlinked context ID and VMID match (reserved if no EL2) */
4718 qemu_log_mask(LOG_UNIMP
,
4719 "arm: unlinked context breakpoint types not implemented\n");
4721 case 9: /* linked VMID match (reserved if no EL2) */
4722 case 11: /* linked context ID and VMID match (reserved if no EL2) */
4723 case 3: /* linked context ID match */
4725 /* We must generate no events for Linked context matches (unless
4726 * they are linked to by some other bp/wp, which is handled in
4727 * updates for the linking bp/wp). We choose to also generate no events
4728 * for reserved values.
4733 cpu_breakpoint_insert(CPU(cpu
), addr
, flags
, &env
->cpu_breakpoint
[n
]);
4736 void hw_breakpoint_update_all(ARMCPU
*cpu
)
4739 CPUARMState
*env
= &cpu
->env
;
4741 /* Completely clear out existing QEMU breakpoints and our array, to
4742 * avoid possible stale entries following migration load.
4744 cpu_breakpoint_remove_all(CPU(cpu
), BP_CPU
);
4745 memset(env
->cpu_breakpoint
, 0, sizeof(env
->cpu_breakpoint
));
4747 for (i
= 0; i
< ARRAY_SIZE(cpu
->env
.cpu_breakpoint
); i
++) {
4748 hw_breakpoint_update(cpu
, i
);
4752 static void dbgbvr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4755 ARMCPU
*cpu
= arm_env_get_cpu(env
);
4758 raw_write(env
, ri
, value
);
4759 hw_breakpoint_update(cpu
, i
);
4762 static void dbgbcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4765 ARMCPU
*cpu
= arm_env_get_cpu(env
);
4768 /* BAS[3] is a read-only copy of BAS[2], and BAS[1] a read-only
4771 value
= deposit64(value
, 6, 1, extract64(value
, 5, 1));
4772 value
= deposit64(value
, 8, 1, extract64(value
, 7, 1));
4774 raw_write(env
, ri
, value
);
4775 hw_breakpoint_update(cpu
, i
);
4778 static void define_debug_regs(ARMCPU
*cpu
)
4780 /* Define v7 and v8 architectural debug registers.
4781 * These are just dummy implementations for now.
4784 int wrps
, brps
, ctx_cmps
;
4785 ARMCPRegInfo dbgdidr
= {
4786 .name
= "DBGDIDR", .cp
= 14, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 0,
4787 .access
= PL0_R
, .accessfn
= access_tda
,
4788 .type
= ARM_CP_CONST
, .resetvalue
= cpu
->dbgdidr
,
4791 /* Note that all these register fields hold "number of Xs minus 1". */
4792 brps
= extract32(cpu
->dbgdidr
, 24, 4);
4793 wrps
= extract32(cpu
->dbgdidr
, 28, 4);
4794 ctx_cmps
= extract32(cpu
->dbgdidr
, 20, 4);
4796 assert(ctx_cmps
<= brps
);
4798 /* The DBGDIDR and ID_AA64DFR0_EL1 define various properties
4799 * of the debug registers such as number of breakpoints;
4800 * check that if they both exist then they agree.
4802 if (arm_feature(&cpu
->env
, ARM_FEATURE_AARCH64
)) {
4803 assert(extract32(cpu
->id_aa64dfr0
, 12, 4) == brps
);
4804 assert(extract32(cpu
->id_aa64dfr0
, 20, 4) == wrps
);
4805 assert(extract32(cpu
->id_aa64dfr0
, 28, 4) == ctx_cmps
);
4808 define_one_arm_cp_reg(cpu
, &dbgdidr
);
4809 define_arm_cp_regs(cpu
, debug_cp_reginfo
);
4811 if (arm_feature(&cpu
->env
, ARM_FEATURE_LPAE
)) {
4812 define_arm_cp_regs(cpu
, debug_lpae_cp_reginfo
);
4815 for (i
= 0; i
< brps
+ 1; i
++) {
4816 ARMCPRegInfo dbgregs
[] = {
4817 { .name
= "DBGBVR", .state
= ARM_CP_STATE_BOTH
,
4818 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= i
, .opc2
= 4,
4819 .access
= PL1_RW
, .accessfn
= access_tda
,
4820 .fieldoffset
= offsetof(CPUARMState
, cp15
.dbgbvr
[i
]),
4821 .writefn
= dbgbvr_write
, .raw_writefn
= raw_write
4823 { .name
= "DBGBCR", .state
= ARM_CP_STATE_BOTH
,
4824 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= i
, .opc2
= 5,
4825 .access
= PL1_RW
, .accessfn
= access_tda
,
4826 .fieldoffset
= offsetof(CPUARMState
, cp15
.dbgbcr
[i
]),
4827 .writefn
= dbgbcr_write
, .raw_writefn
= raw_write
4831 define_arm_cp_regs(cpu
, dbgregs
);
4834 for (i
= 0; i
< wrps
+ 1; i
++) {
4835 ARMCPRegInfo dbgregs
[] = {
4836 { .name
= "DBGWVR", .state
= ARM_CP_STATE_BOTH
,
4837 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= i
, .opc2
= 6,
4838 .access
= PL1_RW
, .accessfn
= access_tda
,
4839 .fieldoffset
= offsetof(CPUARMState
, cp15
.dbgwvr
[i
]),
4840 .writefn
= dbgwvr_write
, .raw_writefn
= raw_write
4842 { .name
= "DBGWCR", .state
= ARM_CP_STATE_BOTH
,
4843 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= i
, .opc2
= 7,
4844 .access
= PL1_RW
, .accessfn
= access_tda
,
4845 .fieldoffset
= offsetof(CPUARMState
, cp15
.dbgwcr
[i
]),
4846 .writefn
= dbgwcr_write
, .raw_writefn
= raw_write
4850 define_arm_cp_regs(cpu
, dbgregs
);
4854 /* We don't know until after realize whether there's a GICv3
4855 * attached, and that is what registers the gicv3 sysregs.
4856 * So we have to fill in the GIC fields in ID_PFR/ID_PFR1_EL1/ID_AA64PFR0_EL1
4859 static uint64_t id_pfr1_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4861 ARMCPU
*cpu
= arm_env_get_cpu(env
);
4862 uint64_t pfr1
= cpu
->id_pfr1
;
4864 if (env
->gicv3state
) {
4870 static uint64_t id_aa64pfr0_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4872 ARMCPU
*cpu
= arm_env_get_cpu(env
);
4873 uint64_t pfr0
= cpu
->id_aa64pfr0
;
4875 if (env
->gicv3state
) {
4881 void register_cp_regs_for_features(ARMCPU
*cpu
)
4883 /* Register all the coprocessor registers based on feature bits */
4884 CPUARMState
*env
= &cpu
->env
;
4885 if (arm_feature(env
, ARM_FEATURE_M
)) {
4886 /* M profile has no coprocessor registers */
4890 define_arm_cp_regs(cpu
, cp_reginfo
);
4891 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
4892 /* Must go early as it is full of wildcards that may be
4893 * overridden by later definitions.
4895 define_arm_cp_regs(cpu
, not_v8_cp_reginfo
);
4898 if (arm_feature(env
, ARM_FEATURE_V6
)) {
4899 /* The ID registers all have impdef reset values */
4900 ARMCPRegInfo v6_idregs
[] = {
4901 { .name
= "ID_PFR0", .state
= ARM_CP_STATE_BOTH
,
4902 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 0,
4903 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4904 .resetvalue
= cpu
->id_pfr0
},
4905 /* ID_PFR1 is not a plain ARM_CP_CONST because we don't know
4906 * the value of the GIC field until after we define these regs.
4908 { .name
= "ID_PFR1", .state
= ARM_CP_STATE_BOTH
,
4909 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 1,
4910 .access
= PL1_R
, .type
= ARM_CP_NO_RAW
,
4911 .readfn
= id_pfr1_read
,
4912 .writefn
= arm_cp_write_ignore
},
4913 { .name
= "ID_DFR0", .state
= ARM_CP_STATE_BOTH
,
4914 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 2,
4915 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4916 .resetvalue
= cpu
->id_dfr0
},
4917 { .name
= "ID_AFR0", .state
= ARM_CP_STATE_BOTH
,
4918 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 3,
4919 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4920 .resetvalue
= cpu
->id_afr0
},
4921 { .name
= "ID_MMFR0", .state
= ARM_CP_STATE_BOTH
,
4922 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 4,
4923 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4924 .resetvalue
= cpu
->id_mmfr0
},
4925 { .name
= "ID_MMFR1", .state
= ARM_CP_STATE_BOTH
,
4926 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 5,
4927 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4928 .resetvalue
= cpu
->id_mmfr1
},
4929 { .name
= "ID_MMFR2", .state
= ARM_CP_STATE_BOTH
,
4930 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 6,
4931 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4932 .resetvalue
= cpu
->id_mmfr2
},
4933 { .name
= "ID_MMFR3", .state
= ARM_CP_STATE_BOTH
,
4934 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 7,
4935 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4936 .resetvalue
= cpu
->id_mmfr3
},
4937 { .name
= "ID_ISAR0", .state
= ARM_CP_STATE_BOTH
,
4938 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 0,
4939 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4940 .resetvalue
= cpu
->id_isar0
},
4941 { .name
= "ID_ISAR1", .state
= ARM_CP_STATE_BOTH
,
4942 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 1,
4943 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4944 .resetvalue
= cpu
->id_isar1
},
4945 { .name
= "ID_ISAR2", .state
= ARM_CP_STATE_BOTH
,
4946 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 2,
4947 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4948 .resetvalue
= cpu
->id_isar2
},
4949 { .name
= "ID_ISAR3", .state
= ARM_CP_STATE_BOTH
,
4950 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 3,
4951 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4952 .resetvalue
= cpu
->id_isar3
},
4953 { .name
= "ID_ISAR4", .state
= ARM_CP_STATE_BOTH
,
4954 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 4,
4955 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4956 .resetvalue
= cpu
->id_isar4
},
4957 { .name
= "ID_ISAR5", .state
= ARM_CP_STATE_BOTH
,
4958 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 5,
4959 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4960 .resetvalue
= cpu
->id_isar5
},
4961 { .name
= "ID_MMFR4", .state
= ARM_CP_STATE_BOTH
,
4962 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 6,
4963 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4964 .resetvalue
= cpu
->id_mmfr4
},
4965 { .name
= "ID_ISAR6", .state
= ARM_CP_STATE_BOTH
,
4966 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 7,
4967 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4968 .resetvalue
= cpu
->id_isar6
},
4971 define_arm_cp_regs(cpu
, v6_idregs
);
4972 define_arm_cp_regs(cpu
, v6_cp_reginfo
);
4974 define_arm_cp_regs(cpu
, not_v6_cp_reginfo
);
4976 if (arm_feature(env
, ARM_FEATURE_V6K
)) {
4977 define_arm_cp_regs(cpu
, v6k_cp_reginfo
);
4979 if (arm_feature(env
, ARM_FEATURE_V7MP
) &&
4980 !arm_feature(env
, ARM_FEATURE_PMSA
)) {
4981 define_arm_cp_regs(cpu
, v7mp_cp_reginfo
);
4983 if (arm_feature(env
, ARM_FEATURE_V7
)) {
4984 /* v7 performance monitor control register: same implementor
4985 * field as main ID register, and we implement only the cycle
4988 #ifndef CONFIG_USER_ONLY
4989 ARMCPRegInfo pmcr
= {
4990 .name
= "PMCR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 0,
4992 .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
4993 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmcr
),
4994 .accessfn
= pmreg_access
, .writefn
= pmcr_write
,
4995 .raw_writefn
= raw_write
,
4997 ARMCPRegInfo pmcr64
= {
4998 .name
= "PMCR_EL0", .state
= ARM_CP_STATE_AA64
,
4999 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 0,
5000 .access
= PL0_RW
, .accessfn
= pmreg_access
,
5002 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmcr
),
5003 .resetvalue
= cpu
->midr
& 0xff000000,
5004 .writefn
= pmcr_write
, .raw_writefn
= raw_write
,
5006 define_one_arm_cp_reg(cpu
, &pmcr
);
5007 define_one_arm_cp_reg(cpu
, &pmcr64
);
5009 ARMCPRegInfo clidr
= {
5010 .name
= "CLIDR", .state
= ARM_CP_STATE_BOTH
,
5011 .opc0
= 3, .crn
= 0, .crm
= 0, .opc1
= 1, .opc2
= 1,
5012 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= cpu
->clidr
5014 define_one_arm_cp_reg(cpu
, &clidr
);
5015 define_arm_cp_regs(cpu
, v7_cp_reginfo
);
5016 define_debug_regs(cpu
);
5018 define_arm_cp_regs(cpu
, not_v7_cp_reginfo
);
5020 if (arm_feature(env
, ARM_FEATURE_V8
)) {
5021 /* AArch64 ID registers, which all have impdef reset values.
5022 * Note that within the ID register ranges the unused slots
5023 * must all RAZ, not UNDEF; future architecture versions may
5024 * define new registers here.
5026 ARMCPRegInfo v8_idregs
[] = {
5027 /* ID_AA64PFR0_EL1 is not a plain ARM_CP_CONST because we don't
5028 * know the right value for the GIC field until after we
5029 * define these regs.
5031 { .name
= "ID_AA64PFR0_EL1", .state
= ARM_CP_STATE_AA64
,
5032 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 0,
5033 .access
= PL1_R
, .type
= ARM_CP_NO_RAW
,
5034 .readfn
= id_aa64pfr0_read
,
5035 .writefn
= arm_cp_write_ignore
},
5036 { .name
= "ID_AA64PFR1_EL1", .state
= ARM_CP_STATE_AA64
,
5037 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 1,
5038 .access
= PL1_R
, .type
= ARM_CP_CONST
,
5039 .resetvalue
= cpu
->id_aa64pfr1
},
5040 { .name
= "ID_AA64PFR2_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
5041 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 2,
5042 .access
= PL1_R
, .type
= ARM_CP_CONST
,
5044 { .name
= "ID_AA64PFR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
5045 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 3,
5046 .access
= PL1_R
, .type
= ARM_CP_CONST
,
5048 { .name
= "ID_AA64ZFR0_EL1", .state
= ARM_CP_STATE_AA64
,
5049 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 4,
5050 .access
= PL1_R
, .type
= ARM_CP_CONST
,
5051 /* At present, only SVEver == 0 is defined anyway. */
5053 { .name
= "ID_AA64PFR5_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
5054 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 5,
5055 .access
= PL1_R
, .type
= ARM_CP_CONST
,
5057 { .name
= "ID_AA64PFR6_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
5058 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 6,
5059 .access
= PL1_R
, .type
= ARM_CP_CONST
,
5061 { .name
= "ID_AA64PFR7_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
5062 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 7,
5063 .access
= PL1_R
, .type
= ARM_CP_CONST
,
5065 { .name
= "ID_AA64DFR0_EL1", .state
= ARM_CP_STATE_AA64
,
5066 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 0,
5067 .access
= PL1_R
, .type
= ARM_CP_CONST
,
5068 .resetvalue
= cpu
->id_aa64dfr0
},
5069 { .name
= "ID_AA64DFR1_EL1", .state
= ARM_CP_STATE_AA64
,
5070 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 1,
5071 .access
= PL1_R
, .type
= ARM_CP_CONST
,
5072 .resetvalue
= cpu
->id_aa64dfr1
},
5073 { .name
= "ID_AA64DFR2_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
5074 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 2,
5075 .access
= PL1_R
, .type
= ARM_CP_CONST
,
5077 { .name
= "ID_AA64DFR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
5078 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 3,
5079 .access
= PL1_R
, .type
= ARM_CP_CONST
,
5081 { .name
= "ID_AA64AFR0_EL1", .state
= ARM_CP_STATE_AA64
,
5082 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 4,
5083 .access
= PL1_R
, .type
= ARM_CP_CONST
,
5084 .resetvalue
= cpu
->id_aa64afr0
},
5085 { .name
= "ID_AA64AFR1_EL1", .state
= ARM_CP_STATE_AA64
,
5086 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 5,
5087 .access
= PL1_R
, .type
= ARM_CP_CONST
,
5088 .resetvalue
= cpu
->id_aa64afr1
},
5089 { .name
= "ID_AA64AFR2_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
5090 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 6,
5091 .access
= PL1_R
, .type
= ARM_CP_CONST
,
5093 { .name
= "ID_AA64AFR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
5094 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 7,
5095 .access
= PL1_R
, .type
= ARM_CP_CONST
,
5097 { .name
= "ID_AA64ISAR0_EL1", .state
= ARM_CP_STATE_AA64
,
5098 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 0,
5099 .access
= PL1_R
, .type
= ARM_CP_CONST
,
5100 .resetvalue
= cpu
->id_aa64isar0
},
5101 { .name
= "ID_AA64ISAR1_EL1", .state
= ARM_CP_STATE_AA64
,
5102 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 1,
5103 .access
= PL1_R
, .type
= ARM_CP_CONST
,
5104 .resetvalue
= cpu
->id_aa64isar1
},
5105 { .name
= "ID_AA64ISAR2_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
5106 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 2,
5107 .access
= PL1_R
, .type
= ARM_CP_CONST
,
5109 { .name
= "ID_AA64ISAR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
5110 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 3,
5111 .access
= PL1_R
, .type
= ARM_CP_CONST
,
5113 { .name
= "ID_AA64ISAR4_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
5114 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 4,
5115 .access
= PL1_R
, .type
= ARM_CP_CONST
,
5117 { .name
= "ID_AA64ISAR5_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
5118 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 5,
5119 .access
= PL1_R
, .type
= ARM_CP_CONST
,
5121 { .name
= "ID_AA64ISAR6_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
5122 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 6,
5123 .access
= PL1_R
, .type
= ARM_CP_CONST
,
5125 { .name
= "ID_AA64ISAR7_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
5126 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 7,
5127 .access
= PL1_R
, .type
= ARM_CP_CONST
,
5129 { .name
= "ID_AA64MMFR0_EL1", .state
= ARM_CP_STATE_AA64
,
5130 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 0,
5131 .access
= PL1_R
, .type
= ARM_CP_CONST
,
5132 .resetvalue
= cpu
->id_aa64mmfr0
},
5133 { .name
= "ID_AA64MMFR1_EL1", .state
= ARM_CP_STATE_AA64
,
5134 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 1,
5135 .access
= PL1_R
, .type
= ARM_CP_CONST
,
5136 .resetvalue
= cpu
->id_aa64mmfr1
},
5137 { .name
= "ID_AA64MMFR2_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
5138 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 2,
5139 .access
= PL1_R
, .type
= ARM_CP_CONST
,
5141 { .name
= "ID_AA64MMFR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
5142 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 3,
5143 .access
= PL1_R
, .type
= ARM_CP_CONST
,
5145 { .name
= "ID_AA64MMFR4_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
5146 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 4,
5147 .access
= PL1_R
, .type
= ARM_CP_CONST
,
5149 { .name
= "ID_AA64MMFR5_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
5150 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 5,
5151 .access
= PL1_R
, .type
= ARM_CP_CONST
,
5153 { .name
= "ID_AA64MMFR6_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
5154 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 6,
5155 .access
= PL1_R
, .type
= ARM_CP_CONST
,
5157 { .name
= "ID_AA64MMFR7_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
5158 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 7,
5159 .access
= PL1_R
, .type
= ARM_CP_CONST
,
5161 { .name
= "MVFR0_EL1", .state
= ARM_CP_STATE_AA64
,
5162 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 0,
5163 .access
= PL1_R
, .type
= ARM_CP_CONST
,
5164 .resetvalue
= cpu
->mvfr0
},
5165 { .name
= "MVFR1_EL1", .state
= ARM_CP_STATE_AA64
,
5166 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 1,
5167 .access
= PL1_R
, .type
= ARM_CP_CONST
,
5168 .resetvalue
= cpu
->mvfr1
},
5169 { .name
= "MVFR2_EL1", .state
= ARM_CP_STATE_AA64
,
5170 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 2,
5171 .access
= PL1_R
, .type
= ARM_CP_CONST
,
5172 .resetvalue
= cpu
->mvfr2
},
5173 { .name
= "MVFR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
5174 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 3,
5175 .access
= PL1_R
, .type
= ARM_CP_CONST
,
5177 { .name
= "MVFR4_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
5178 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 4,
5179 .access
= PL1_R
, .type
= ARM_CP_CONST
,
5181 { .name
= "MVFR5_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
5182 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 5,
5183 .access
= PL1_R
, .type
= ARM_CP_CONST
,
5185 { .name
= "MVFR6_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
5186 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 6,
5187 .access
= PL1_R
, .type
= ARM_CP_CONST
,
5189 { .name
= "MVFR7_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
5190 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 7,
5191 .access
= PL1_R
, .type
= ARM_CP_CONST
,
5193 { .name
= "PMCEID0", .state
= ARM_CP_STATE_AA32
,
5194 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 12, .opc2
= 6,
5195 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
5196 .resetvalue
= cpu
->pmceid0
},
5197 { .name
= "PMCEID0_EL0", .state
= ARM_CP_STATE_AA64
,
5198 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 6,
5199 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
5200 .resetvalue
= cpu
->pmceid0
},
5201 { .name
= "PMCEID1", .state
= ARM_CP_STATE_AA32
,
5202 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 12, .opc2
= 7,
5203 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
5204 .resetvalue
= cpu
->pmceid1
},
5205 { .name
= "PMCEID1_EL0", .state
= ARM_CP_STATE_AA64
,
5206 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 7,
5207 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
5208 .resetvalue
= cpu
->pmceid1
},
5211 /* RVBAR_EL1 is only implemented if EL1 is the highest EL */
5212 if (!arm_feature(env
, ARM_FEATURE_EL3
) &&
5213 !arm_feature(env
, ARM_FEATURE_EL2
)) {
5214 ARMCPRegInfo rvbar
= {
5215 .name
= "RVBAR_EL1", .state
= ARM_CP_STATE_AA64
,
5216 .opc0
= 3, .opc1
= 0, .crn
= 12, .crm
= 0, .opc2
= 1,
5217 .type
= ARM_CP_CONST
, .access
= PL1_R
, .resetvalue
= cpu
->rvbar
5219 define_one_arm_cp_reg(cpu
, &rvbar
);
5221 define_arm_cp_regs(cpu
, v8_idregs
);
5222 define_arm_cp_regs(cpu
, v8_cp_reginfo
);
5224 if (arm_feature(env
, ARM_FEATURE_EL2
)) {
5225 uint64_t vmpidr_def
= mpidr_read_val(env
);
5226 ARMCPRegInfo vpidr_regs
[] = {
5227 { .name
= "VPIDR", .state
= ARM_CP_STATE_AA32
,
5228 .cp
= 15, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 0,
5229 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
5230 .resetvalue
= cpu
->midr
, .type
= ARM_CP_ALIAS
,
5231 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.vpidr_el2
) },
5232 { .name
= "VPIDR_EL2", .state
= ARM_CP_STATE_AA64
,
5233 .opc0
= 3, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 0,
5234 .access
= PL2_RW
, .resetvalue
= cpu
->midr
,
5235 .fieldoffset
= offsetof(CPUARMState
, cp15
.vpidr_el2
) },
5236 { .name
= "VMPIDR", .state
= ARM_CP_STATE_AA32
,
5237 .cp
= 15, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 5,
5238 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
5239 .resetvalue
= vmpidr_def
, .type
= ARM_CP_ALIAS
,
5240 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.vmpidr_el2
) },
5241 { .name
= "VMPIDR_EL2", .state
= ARM_CP_STATE_AA64
,
5242 .opc0
= 3, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 5,
5244 .resetvalue
= vmpidr_def
,
5245 .fieldoffset
= offsetof(CPUARMState
, cp15
.vmpidr_el2
) },
5248 define_arm_cp_regs(cpu
, vpidr_regs
);
5249 define_arm_cp_regs(cpu
, el2_cp_reginfo
);
5250 if (arm_feature(env
, ARM_FEATURE_V8
)) {
5251 define_arm_cp_regs(cpu
, el2_v8_cp_reginfo
);
5253 /* RVBAR_EL2 is only implemented if EL2 is the highest EL */
5254 if (!arm_feature(env
, ARM_FEATURE_EL3
)) {
5255 ARMCPRegInfo rvbar
= {
5256 .name
= "RVBAR_EL2", .state
= ARM_CP_STATE_AA64
,
5257 .opc0
= 3, .opc1
= 4, .crn
= 12, .crm
= 0, .opc2
= 1,
5258 .type
= ARM_CP_CONST
, .access
= PL2_R
, .resetvalue
= cpu
->rvbar
5260 define_one_arm_cp_reg(cpu
, &rvbar
);
5263 /* If EL2 is missing but higher ELs are enabled, we need to
5264 * register the no_el2 reginfos.
5266 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
5267 /* When EL3 exists but not EL2, VPIDR and VMPIDR take the value
5268 * of MIDR_EL1 and MPIDR_EL1.
5270 ARMCPRegInfo vpidr_regs
[] = {
5271 { .name
= "VPIDR_EL2", .state
= ARM_CP_STATE_BOTH
,
5272 .opc0
= 3, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 0,
5273 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns_aa64any
,
5274 .type
= ARM_CP_CONST
, .resetvalue
= cpu
->midr
,
5275 .fieldoffset
= offsetof(CPUARMState
, cp15
.vpidr_el2
) },
5276 { .name
= "VMPIDR_EL2", .state
= ARM_CP_STATE_BOTH
,
5277 .opc0
= 3, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 5,
5278 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns_aa64any
,
5279 .type
= ARM_CP_NO_RAW
,
5280 .writefn
= arm_cp_write_ignore
, .readfn
= mpidr_read
},
5283 define_arm_cp_regs(cpu
, vpidr_regs
);
5284 define_arm_cp_regs(cpu
, el3_no_el2_cp_reginfo
);
5285 if (arm_feature(env
, ARM_FEATURE_V8
)) {
5286 define_arm_cp_regs(cpu
, el3_no_el2_v8_cp_reginfo
);
5290 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
5291 define_arm_cp_regs(cpu
, el3_cp_reginfo
);
5292 ARMCPRegInfo el3_regs
[] = {
5293 { .name
= "RVBAR_EL3", .state
= ARM_CP_STATE_AA64
,
5294 .opc0
= 3, .opc1
= 6, .crn
= 12, .crm
= 0, .opc2
= 1,
5295 .type
= ARM_CP_CONST
, .access
= PL3_R
, .resetvalue
= cpu
->rvbar
},
5296 { .name
= "SCTLR_EL3", .state
= ARM_CP_STATE_AA64
,
5297 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 0, .opc2
= 0,
5299 .raw_writefn
= raw_write
, .writefn
= sctlr_write
,
5300 .fieldoffset
= offsetof(CPUARMState
, cp15
.sctlr_el
[3]),
5301 .resetvalue
= cpu
->reset_sctlr
},
5305 define_arm_cp_regs(cpu
, el3_regs
);
5307 /* The behaviour of NSACR is sufficiently various that we don't
5308 * try to describe it in a single reginfo:
5309 * if EL3 is 64 bit, then trap to EL3 from S EL1,
5310 * reads as constant 0xc00 from NS EL1 and NS EL2
5311 * if EL3 is 32 bit, then RW at EL3, RO at NS EL1 and NS EL2
5312 * if v7 without EL3, register doesn't exist
5313 * if v8 without EL3, reads as constant 0xc00 from NS EL1 and NS EL2
5315 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
5316 if (arm_feature(env
, ARM_FEATURE_AARCH64
)) {
5317 ARMCPRegInfo nsacr
= {
5318 .name
= "NSACR", .type
= ARM_CP_CONST
,
5319 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 2,
5320 .access
= PL1_RW
, .accessfn
= nsacr_access
,
5323 define_one_arm_cp_reg(cpu
, &nsacr
);
5325 ARMCPRegInfo nsacr
= {
5327 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 2,
5328 .access
= PL3_RW
| PL1_R
,
5330 .fieldoffset
= offsetof(CPUARMState
, cp15
.nsacr
)
5332 define_one_arm_cp_reg(cpu
, &nsacr
);
5335 if (arm_feature(env
, ARM_FEATURE_V8
)) {
5336 ARMCPRegInfo nsacr
= {
5337 .name
= "NSACR", .type
= ARM_CP_CONST
,
5338 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 2,
5342 define_one_arm_cp_reg(cpu
, &nsacr
);
5346 if (arm_feature(env
, ARM_FEATURE_PMSA
)) {
5347 if (arm_feature(env
, ARM_FEATURE_V6
)) {
5348 /* PMSAv6 not implemented */
5349 assert(arm_feature(env
, ARM_FEATURE_V7
));
5350 define_arm_cp_regs(cpu
, vmsa_pmsa_cp_reginfo
);
5351 define_arm_cp_regs(cpu
, pmsav7_cp_reginfo
);
5353 define_arm_cp_regs(cpu
, pmsav5_cp_reginfo
);
5356 define_arm_cp_regs(cpu
, vmsa_pmsa_cp_reginfo
);
5357 define_arm_cp_regs(cpu
, vmsa_cp_reginfo
);
5359 if (arm_feature(env
, ARM_FEATURE_THUMB2EE
)) {
5360 define_arm_cp_regs(cpu
, t2ee_cp_reginfo
);
5362 if (arm_feature(env
, ARM_FEATURE_GENERIC_TIMER
)) {
5363 define_arm_cp_regs(cpu
, generic_timer_cp_reginfo
);
5365 if (arm_feature(env
, ARM_FEATURE_VAPA
)) {
5366 define_arm_cp_regs(cpu
, vapa_cp_reginfo
);
5368 if (arm_feature(env
, ARM_FEATURE_CACHE_TEST_CLEAN
)) {
5369 define_arm_cp_regs(cpu
, cache_test_clean_cp_reginfo
);
5371 if (arm_feature(env
, ARM_FEATURE_CACHE_DIRTY_REG
)) {
5372 define_arm_cp_regs(cpu
, cache_dirty_status_cp_reginfo
);
5374 if (arm_feature(env
, ARM_FEATURE_CACHE_BLOCK_OPS
)) {
5375 define_arm_cp_regs(cpu
, cache_block_ops_cp_reginfo
);
5377 if (arm_feature(env
, ARM_FEATURE_OMAPCP
)) {
5378 define_arm_cp_regs(cpu
, omap_cp_reginfo
);
5380 if (arm_feature(env
, ARM_FEATURE_STRONGARM
)) {
5381 define_arm_cp_regs(cpu
, strongarm_cp_reginfo
);
5383 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
5384 define_arm_cp_regs(cpu
, xscale_cp_reginfo
);
5386 if (arm_feature(env
, ARM_FEATURE_DUMMY_C15_REGS
)) {
5387 define_arm_cp_regs(cpu
, dummy_c15_cp_reginfo
);
5389 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
5390 define_arm_cp_regs(cpu
, lpae_cp_reginfo
);
5392 /* Slightly awkwardly, the OMAP and StrongARM cores need all of
5393 * cp15 crn=0 to be writes-ignored, whereas for other cores they should
5394 * be read-only (ie write causes UNDEF exception).
5397 ARMCPRegInfo id_pre_v8_midr_cp_reginfo
[] = {
5398 /* Pre-v8 MIDR space.
5399 * Note that the MIDR isn't a simple constant register because
5400 * of the TI925 behaviour where writes to another register can
5401 * cause the MIDR value to change.
5403 * Unimplemented registers in the c15 0 0 0 space default to
5404 * MIDR. Define MIDR first as this entire space, then CTR, TCMTR
5405 * and friends override accordingly.
5408 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= CP_ANY
,
5409 .access
= PL1_R
, .resetvalue
= cpu
->midr
,
5410 .writefn
= arm_cp_write_ignore
, .raw_writefn
= raw_write
,
5411 .readfn
= midr_read
,
5412 .fieldoffset
= offsetof(CPUARMState
, cp15
.c0_cpuid
),
5413 .type
= ARM_CP_OVERRIDE
},
5414 /* crn = 0 op1 = 0 crm = 3..7 : currently unassigned; we RAZ. */
5416 .cp
= 15, .crn
= 0, .crm
= 3, .opc1
= 0, .opc2
= CP_ANY
,
5417 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
5419 .cp
= 15, .crn
= 0, .crm
= 4, .opc1
= 0, .opc2
= CP_ANY
,
5420 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
5422 .cp
= 15, .crn
= 0, .crm
= 5, .opc1
= 0, .opc2
= CP_ANY
,
5423 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
5425 .cp
= 15, .crn
= 0, .crm
= 6, .opc1
= 0, .opc2
= CP_ANY
,
5426 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
5428 .cp
= 15, .crn
= 0, .crm
= 7, .opc1
= 0, .opc2
= CP_ANY
,
5429 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
5432 ARMCPRegInfo id_v8_midr_cp_reginfo
[] = {
5433 { .name
= "MIDR_EL1", .state
= ARM_CP_STATE_BOTH
,
5434 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 0, .opc2
= 0,
5435 .access
= PL1_R
, .type
= ARM_CP_NO_RAW
, .resetvalue
= cpu
->midr
,
5436 .fieldoffset
= offsetof(CPUARMState
, cp15
.c0_cpuid
),
5437 .readfn
= midr_read
},
5438 /* crn = 0 op1 = 0 crm = 0 op2 = 4,7 : AArch32 aliases of MIDR */
5439 { .name
= "MIDR", .type
= ARM_CP_ALIAS
| ARM_CP_CONST
,
5440 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 4,
5441 .access
= PL1_R
, .resetvalue
= cpu
->midr
},
5442 { .name
= "MIDR", .type
= ARM_CP_ALIAS
| ARM_CP_CONST
,
5443 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 7,
5444 .access
= PL1_R
, .resetvalue
= cpu
->midr
},
5445 { .name
= "REVIDR_EL1", .state
= ARM_CP_STATE_BOTH
,
5446 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 0, .opc2
= 6,
5447 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= cpu
->revidr
},
5450 ARMCPRegInfo id_cp_reginfo
[] = {
5451 /* These are common to v8 and pre-v8 */
5453 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 1,
5454 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= cpu
->ctr
},
5455 { .name
= "CTR_EL0", .state
= ARM_CP_STATE_AA64
,
5456 .opc0
= 3, .opc1
= 3, .opc2
= 1, .crn
= 0, .crm
= 0,
5457 .access
= PL0_R
, .accessfn
= ctr_el0_access
,
5458 .type
= ARM_CP_CONST
, .resetvalue
= cpu
->ctr
},
5459 /* TCMTR and TLBTR exist in v8 but have no 64-bit versions */
5461 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 2,
5462 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
5465 /* TLBTR is specific to VMSA */
5466 ARMCPRegInfo id_tlbtr_reginfo
= {
5468 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 3,
5469 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0,
5471 /* MPUIR is specific to PMSA V6+ */
5472 ARMCPRegInfo id_mpuir_reginfo
= {
5474 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 4,
5475 .access
= PL1_R
, .type
= ARM_CP_CONST
,
5476 .resetvalue
= cpu
->pmsav7_dregion
<< 8
5478 ARMCPRegInfo crn0_wi_reginfo
= {
5479 .name
= "CRN0_WI", .cp
= 15, .crn
= 0, .crm
= CP_ANY
,
5480 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_W
,
5481 .type
= ARM_CP_NOP
| ARM_CP_OVERRIDE
5483 if (arm_feature(env
, ARM_FEATURE_OMAPCP
) ||
5484 arm_feature(env
, ARM_FEATURE_STRONGARM
)) {
5486 /* Register the blanket "writes ignored" value first to cover the
5487 * whole space. Then update the specific ID registers to allow write
5488 * access, so that they ignore writes rather than causing them to
5491 define_one_arm_cp_reg(cpu
, &crn0_wi_reginfo
);
5492 for (r
= id_pre_v8_midr_cp_reginfo
;
5493 r
->type
!= ARM_CP_SENTINEL
; r
++) {
5496 for (r
= id_cp_reginfo
; r
->type
!= ARM_CP_SENTINEL
; r
++) {
5499 id_mpuir_reginfo
.access
= PL1_RW
;
5500 id_tlbtr_reginfo
.access
= PL1_RW
;
5502 if (arm_feature(env
, ARM_FEATURE_V8
)) {
5503 define_arm_cp_regs(cpu
, id_v8_midr_cp_reginfo
);
5505 define_arm_cp_regs(cpu
, id_pre_v8_midr_cp_reginfo
);
5507 define_arm_cp_regs(cpu
, id_cp_reginfo
);
5508 if (!arm_feature(env
, ARM_FEATURE_PMSA
)) {
5509 define_one_arm_cp_reg(cpu
, &id_tlbtr_reginfo
);
5510 } else if (arm_feature(env
, ARM_FEATURE_V7
)) {
5511 define_one_arm_cp_reg(cpu
, &id_mpuir_reginfo
);
5515 if (arm_feature(env
, ARM_FEATURE_MPIDR
)) {
5516 define_arm_cp_regs(cpu
, mpidr_cp_reginfo
);
5519 if (arm_feature(env
, ARM_FEATURE_AUXCR
)) {
5520 ARMCPRegInfo auxcr_reginfo
[] = {
5521 { .name
= "ACTLR_EL1", .state
= ARM_CP_STATE_BOTH
,
5522 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 1,
5523 .access
= PL1_RW
, .type
= ARM_CP_CONST
,
5524 .resetvalue
= cpu
->reset_auxcr
},
5525 { .name
= "ACTLR_EL2", .state
= ARM_CP_STATE_BOTH
,
5526 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 0, .opc2
= 1,
5527 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
5529 { .name
= "ACTLR_EL3", .state
= ARM_CP_STATE_AA64
,
5530 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 0, .opc2
= 1,
5531 .access
= PL3_RW
, .type
= ARM_CP_CONST
,
5535 define_arm_cp_regs(cpu
, auxcr_reginfo
);
5536 if (arm_feature(env
, ARM_FEATURE_V8
)) {
5537 /* HACTLR2 maps to ACTLR_EL2[63:32] and is not in ARMv7 */
5538 ARMCPRegInfo hactlr2_reginfo
= {
5539 .name
= "HACTLR2", .state
= ARM_CP_STATE_AA32
,
5540 .cp
= 15, .opc1
= 4, .crn
= 1, .crm
= 0, .opc2
= 3,
5541 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
5544 define_one_arm_cp_reg(cpu
, &hactlr2_reginfo
);
5548 if (arm_feature(env
, ARM_FEATURE_CBAR
)) {
5549 if (arm_feature(env
, ARM_FEATURE_AARCH64
)) {
5550 /* 32 bit view is [31:18] 0...0 [43:32]. */
5551 uint32_t cbar32
= (extract64(cpu
->reset_cbar
, 18, 14) << 18)
5552 | extract64(cpu
->reset_cbar
, 32, 12);
5553 ARMCPRegInfo cbar_reginfo
[] = {
5555 .type
= ARM_CP_CONST
,
5556 .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 4, .opc2
= 0,
5557 .access
= PL1_R
, .resetvalue
= cpu
->reset_cbar
},
5558 { .name
= "CBAR_EL1", .state
= ARM_CP_STATE_AA64
,
5559 .type
= ARM_CP_CONST
,
5560 .opc0
= 3, .opc1
= 1, .crn
= 15, .crm
= 3, .opc2
= 0,
5561 .access
= PL1_R
, .resetvalue
= cbar32
},
5564 /* We don't implement a r/w 64 bit CBAR currently */
5565 assert(arm_feature(env
, ARM_FEATURE_CBAR_RO
));
5566 define_arm_cp_regs(cpu
, cbar_reginfo
);
5568 ARMCPRegInfo cbar
= {
5570 .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 4, .opc2
= 0,
5571 .access
= PL1_R
|PL3_W
, .resetvalue
= cpu
->reset_cbar
,
5572 .fieldoffset
= offsetof(CPUARMState
,
5573 cp15
.c15_config_base_address
)
5575 if (arm_feature(env
, ARM_FEATURE_CBAR_RO
)) {
5576 cbar
.access
= PL1_R
;
5577 cbar
.fieldoffset
= 0;
5578 cbar
.type
= ARM_CP_CONST
;
5580 define_one_arm_cp_reg(cpu
, &cbar
);
5584 if (arm_feature(env
, ARM_FEATURE_VBAR
)) {
5585 ARMCPRegInfo vbar_cp_reginfo
[] = {
5586 { .name
= "VBAR", .state
= ARM_CP_STATE_BOTH
,
5587 .opc0
= 3, .crn
= 12, .crm
= 0, .opc1
= 0, .opc2
= 0,
5588 .access
= PL1_RW
, .writefn
= vbar_write
,
5589 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.vbar_s
),
5590 offsetof(CPUARMState
, cp15
.vbar_ns
) },
5594 define_arm_cp_regs(cpu
, vbar_cp_reginfo
);
5597 /* Generic registers whose values depend on the implementation */
5599 ARMCPRegInfo sctlr
= {
5600 .name
= "SCTLR", .state
= ARM_CP_STATE_BOTH
,
5601 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 0,
5603 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.sctlr_s
),
5604 offsetof(CPUARMState
, cp15
.sctlr_ns
) },
5605 .writefn
= sctlr_write
, .resetvalue
= cpu
->reset_sctlr
,
5606 .raw_writefn
= raw_write
,
5608 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
5609 /* Normally we would always end the TB on an SCTLR write, but Linux
5610 * arch/arm/mach-pxa/sleep.S expects two instructions following
5611 * an MMU enable to execute from cache. Imitate this behaviour.
5613 sctlr
.type
|= ARM_CP_SUPPRESS_TB_END
;
5615 define_one_arm_cp_reg(cpu
, &sctlr
);
5618 if (arm_feature(env
, ARM_FEATURE_SVE
)) {
5619 define_one_arm_cp_reg(cpu
, &zcr_el1_reginfo
);
5620 if (arm_feature(env
, ARM_FEATURE_EL2
)) {
5621 define_one_arm_cp_reg(cpu
, &zcr_el2_reginfo
);
5623 define_one_arm_cp_reg(cpu
, &zcr_no_el2_reginfo
);
5625 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
5626 define_one_arm_cp_reg(cpu
, &zcr_el3_reginfo
);
5631 void arm_cpu_register_gdb_regs_for_features(ARMCPU
*cpu
)
5633 CPUState
*cs
= CPU(cpu
);
5634 CPUARMState
*env
= &cpu
->env
;
5636 if (arm_feature(env
, ARM_FEATURE_AARCH64
)) {
5637 gdb_register_coprocessor(cs
, aarch64_fpu_gdb_get_reg
,
5638 aarch64_fpu_gdb_set_reg
,
5639 34, "aarch64-fpu.xml", 0);
5640 } else if (arm_feature(env
, ARM_FEATURE_NEON
)) {
5641 gdb_register_coprocessor(cs
, vfp_gdb_get_reg
, vfp_gdb_set_reg
,
5642 51, "arm-neon.xml", 0);
5643 } else if (arm_feature(env
, ARM_FEATURE_VFP3
)) {
5644 gdb_register_coprocessor(cs
, vfp_gdb_get_reg
, vfp_gdb_set_reg
,
5645 35, "arm-vfp3.xml", 0);
5646 } else if (arm_feature(env
, ARM_FEATURE_VFP
)) {
5647 gdb_register_coprocessor(cs
, vfp_gdb_get_reg
, vfp_gdb_set_reg
,
5648 19, "arm-vfp.xml", 0);
5650 gdb_register_coprocessor(cs
, arm_gdb_get_sysreg
, arm_gdb_set_sysreg
,
5651 arm_gen_dynamic_xml(cs
),
5652 "system-registers.xml", 0);
5655 /* Sort alphabetically by type name, except for "any". */
5656 static gint
arm_cpu_list_compare(gconstpointer a
, gconstpointer b
)
5658 ObjectClass
*class_a
= (ObjectClass
*)a
;
5659 ObjectClass
*class_b
= (ObjectClass
*)b
;
5660 const char *name_a
, *name_b
;
5662 name_a
= object_class_get_name(class_a
);
5663 name_b
= object_class_get_name(class_b
);
5664 if (strcmp(name_a
, "any-" TYPE_ARM_CPU
) == 0) {
5666 } else if (strcmp(name_b
, "any-" TYPE_ARM_CPU
) == 0) {
5669 return strcmp(name_a
, name_b
);
5673 static void arm_cpu_list_entry(gpointer data
, gpointer user_data
)
5675 ObjectClass
*oc
= data
;
5676 CPUListState
*s
= user_data
;
5677 const char *typename
;
5680 typename
= object_class_get_name(oc
);
5681 name
= g_strndup(typename
, strlen(typename
) - strlen("-" TYPE_ARM_CPU
));
5682 (*s
->cpu_fprintf
)(s
->file
, " %s\n",
5687 void arm_cpu_list(FILE *f
, fprintf_function cpu_fprintf
)
5691 .cpu_fprintf
= cpu_fprintf
,
5695 list
= object_class_get_list(TYPE_ARM_CPU
, false);
5696 list
= g_slist_sort(list
, arm_cpu_list_compare
);
5697 (*cpu_fprintf
)(f
, "Available CPUs:\n");
5698 g_slist_foreach(list
, arm_cpu_list_entry
, &s
);
5702 static void arm_cpu_add_definition(gpointer data
, gpointer user_data
)
5704 ObjectClass
*oc
= data
;
5705 CpuDefinitionInfoList
**cpu_list
= user_data
;
5706 CpuDefinitionInfoList
*entry
;
5707 CpuDefinitionInfo
*info
;
5708 const char *typename
;
5710 typename
= object_class_get_name(oc
);
5711 info
= g_malloc0(sizeof(*info
));
5712 info
->name
= g_strndup(typename
,
5713 strlen(typename
) - strlen("-" TYPE_ARM_CPU
));
5714 info
->q_typename
= g_strdup(typename
);
5716 entry
= g_malloc0(sizeof(*entry
));
5717 entry
->value
= info
;
5718 entry
->next
= *cpu_list
;
5722 CpuDefinitionInfoList
*arch_query_cpu_definitions(Error
**errp
)
5724 CpuDefinitionInfoList
*cpu_list
= NULL
;
5727 list
= object_class_get_list(TYPE_ARM_CPU
, false);
5728 g_slist_foreach(list
, arm_cpu_add_definition
, &cpu_list
);
5734 static void add_cpreg_to_hashtable(ARMCPU
*cpu
, const ARMCPRegInfo
*r
,
5735 void *opaque
, int state
, int secstate
,
5736 int crm
, int opc1
, int opc2
,
5739 /* Private utility function for define_one_arm_cp_reg_with_opaque():
5740 * add a single reginfo struct to the hash table.
5742 uint32_t *key
= g_new(uint32_t, 1);
5743 ARMCPRegInfo
*r2
= g_memdup(r
, sizeof(ARMCPRegInfo
));
5744 int is64
= (r
->type
& ARM_CP_64BIT
) ? 1 : 0;
5745 int ns
= (secstate
& ARM_CP_SECSTATE_NS
) ? 1 : 0;
5747 r2
->name
= g_strdup(name
);
5748 /* Reset the secure state to the specific incoming state. This is
5749 * necessary as the register may have been defined with both states.
5751 r2
->secure
= secstate
;
5753 if (r
->bank_fieldoffsets
[0] && r
->bank_fieldoffsets
[1]) {
5754 /* Register is banked (using both entries in array).
5755 * Overwriting fieldoffset as the array is only used to define
5756 * banked registers but later only fieldoffset is used.
5758 r2
->fieldoffset
= r
->bank_fieldoffsets
[ns
];
5761 if (state
== ARM_CP_STATE_AA32
) {
5762 if (r
->bank_fieldoffsets
[0] && r
->bank_fieldoffsets
[1]) {
5763 /* If the register is banked then we don't need to migrate or
5764 * reset the 32-bit instance in certain cases:
5766 * 1) If the register has both 32-bit and 64-bit instances then we
5767 * can count on the 64-bit instance taking care of the
5769 * 2) If ARMv8 is enabled then we can count on a 64-bit version
5770 * taking care of the secure bank. This requires that separate
5771 * 32 and 64-bit definitions are provided.
5773 if ((r
->state
== ARM_CP_STATE_BOTH
&& ns
) ||
5774 (arm_feature(&cpu
->env
, ARM_FEATURE_V8
) && !ns
)) {
5775 r2
->type
|= ARM_CP_ALIAS
;
5777 } else if ((secstate
!= r
->secure
) && !ns
) {
5778 /* The register is not banked so we only want to allow migration of
5779 * the non-secure instance.
5781 r2
->type
|= ARM_CP_ALIAS
;
5784 if (r
->state
== ARM_CP_STATE_BOTH
) {
5785 /* We assume it is a cp15 register if the .cp field is left unset.
5791 #ifdef HOST_WORDS_BIGENDIAN
5792 if (r2
->fieldoffset
) {
5793 r2
->fieldoffset
+= sizeof(uint32_t);
5798 if (state
== ARM_CP_STATE_AA64
) {
5799 /* To allow abbreviation of ARMCPRegInfo
5800 * definitions, we treat cp == 0 as equivalent to
5801 * the value for "standard guest-visible sysreg".
5802 * STATE_BOTH definitions are also always "standard
5803 * sysreg" in their AArch64 view (the .cp value may
5804 * be non-zero for the benefit of the AArch32 view).
5806 if (r
->cp
== 0 || r
->state
== ARM_CP_STATE_BOTH
) {
5807 r2
->cp
= CP_REG_ARM64_SYSREG_CP
;
5809 *key
= ENCODE_AA64_CP_REG(r2
->cp
, r2
->crn
, crm
,
5810 r2
->opc0
, opc1
, opc2
);
5812 *key
= ENCODE_CP_REG(r2
->cp
, is64
, ns
, r2
->crn
, crm
, opc1
, opc2
);
5815 r2
->opaque
= opaque
;
5817 /* reginfo passed to helpers is correct for the actual access,
5818 * and is never ARM_CP_STATE_BOTH:
5821 /* Make sure reginfo passed to helpers for wildcarded regs
5822 * has the correct crm/opc1/opc2 for this reg, not CP_ANY:
5827 /* By convention, for wildcarded registers only the first
5828 * entry is used for migration; the others are marked as
5829 * ALIAS so we don't try to transfer the register
5830 * multiple times. Special registers (ie NOP/WFI) are
5831 * never migratable and not even raw-accessible.
5833 if ((r
->type
& ARM_CP_SPECIAL
)) {
5834 r2
->type
|= ARM_CP_NO_RAW
;
5836 if (((r
->crm
== CP_ANY
) && crm
!= 0) ||
5837 ((r
->opc1
== CP_ANY
) && opc1
!= 0) ||
5838 ((r
->opc2
== CP_ANY
) && opc2
!= 0)) {
5839 r2
->type
|= ARM_CP_ALIAS
| ARM_CP_NO_GDB
;
5842 /* Check that raw accesses are either forbidden or handled. Note that
5843 * we can't assert this earlier because the setup of fieldoffset for
5844 * banked registers has to be done first.
5846 if (!(r2
->type
& ARM_CP_NO_RAW
)) {
5847 assert(!raw_accessors_invalid(r2
));
5850 /* Overriding of an existing definition must be explicitly
5853 if (!(r
->type
& ARM_CP_OVERRIDE
)) {
5854 ARMCPRegInfo
*oldreg
;
5855 oldreg
= g_hash_table_lookup(cpu
->cp_regs
, key
);
5856 if (oldreg
&& !(oldreg
->type
& ARM_CP_OVERRIDE
)) {
5857 fprintf(stderr
, "Register redefined: cp=%d %d bit "
5858 "crn=%d crm=%d opc1=%d opc2=%d, "
5859 "was %s, now %s\n", r2
->cp
, 32 + 32 * is64
,
5860 r2
->crn
, r2
->crm
, r2
->opc1
, r2
->opc2
,
5861 oldreg
->name
, r2
->name
);
5862 g_assert_not_reached();
5865 g_hash_table_insert(cpu
->cp_regs
, key
, r2
);
5869 void define_one_arm_cp_reg_with_opaque(ARMCPU
*cpu
,
5870 const ARMCPRegInfo
*r
, void *opaque
)
5872 /* Define implementations of coprocessor registers.
5873 * We store these in a hashtable because typically
5874 * there are less than 150 registers in a space which
5875 * is 16*16*16*8*8 = 262144 in size.
5876 * Wildcarding is supported for the crm, opc1 and opc2 fields.
5877 * If a register is defined twice then the second definition is
5878 * used, so this can be used to define some generic registers and
5879 * then override them with implementation specific variations.
5880 * At least one of the original and the second definition should
5881 * include ARM_CP_OVERRIDE in its type bits -- this is just a guard
5882 * against accidental use.
5884 * The state field defines whether the register is to be
5885 * visible in the AArch32 or AArch64 execution state. If the
5886 * state is set to ARM_CP_STATE_BOTH then we synthesise a
5887 * reginfo structure for the AArch32 view, which sees the lower
5888 * 32 bits of the 64 bit register.
5890 * Only registers visible in AArch64 may set r->opc0; opc0 cannot
5891 * be wildcarded. AArch64 registers are always considered to be 64
5892 * bits; the ARM_CP_64BIT* flag applies only to the AArch32 view of
5893 * the register, if any.
5895 int crm
, opc1
, opc2
, state
;
5896 int crmmin
= (r
->crm
== CP_ANY
) ? 0 : r
->crm
;
5897 int crmmax
= (r
->crm
== CP_ANY
) ? 15 : r
->crm
;
5898 int opc1min
= (r
->opc1
== CP_ANY
) ? 0 : r
->opc1
;
5899 int opc1max
= (r
->opc1
== CP_ANY
) ? 7 : r
->opc1
;
5900 int opc2min
= (r
->opc2
== CP_ANY
) ? 0 : r
->opc2
;
5901 int opc2max
= (r
->opc2
== CP_ANY
) ? 7 : r
->opc2
;
5902 /* 64 bit registers have only CRm and Opc1 fields */
5903 assert(!((r
->type
& ARM_CP_64BIT
) && (r
->opc2
|| r
->crn
)));
5904 /* op0 only exists in the AArch64 encodings */
5905 assert((r
->state
!= ARM_CP_STATE_AA32
) || (r
->opc0
== 0));
5906 /* AArch64 regs are all 64 bit so ARM_CP_64BIT is meaningless */
5907 assert((r
->state
!= ARM_CP_STATE_AA64
) || !(r
->type
& ARM_CP_64BIT
));
5908 /* The AArch64 pseudocode CheckSystemAccess() specifies that op1
5909 * encodes a minimum access level for the register. We roll this
5910 * runtime check into our general permission check code, so check
5911 * here that the reginfo's specified permissions are strict enough
5912 * to encompass the generic architectural permission check.
5914 if (r
->state
!= ARM_CP_STATE_AA32
) {
5917 case 0: case 1: case 2:
5930 /* unallocated encoding, so not possible */
5938 /* min_EL EL1, secure mode only (we don't check the latter) */
5942 /* broken reginfo with out-of-range opc1 */
5946 /* assert our permissions are not too lax (stricter is fine) */
5947 assert((r
->access
& ~mask
) == 0);
5950 /* Check that the register definition has enough info to handle
5951 * reads and writes if they are permitted.
5953 if (!(r
->type
& (ARM_CP_SPECIAL
|ARM_CP_CONST
))) {
5954 if (r
->access
& PL3_R
) {
5955 assert((r
->fieldoffset
||
5956 (r
->bank_fieldoffsets
[0] && r
->bank_fieldoffsets
[1])) ||
5959 if (r
->access
& PL3_W
) {
5960 assert((r
->fieldoffset
||
5961 (r
->bank_fieldoffsets
[0] && r
->bank_fieldoffsets
[1])) ||
5965 /* Bad type field probably means missing sentinel at end of reg list */
5966 assert(cptype_valid(r
->type
));
5967 for (crm
= crmmin
; crm
<= crmmax
; crm
++) {
5968 for (opc1
= opc1min
; opc1
<= opc1max
; opc1
++) {
5969 for (opc2
= opc2min
; opc2
<= opc2max
; opc2
++) {
5970 for (state
= ARM_CP_STATE_AA32
;
5971 state
<= ARM_CP_STATE_AA64
; state
++) {
5972 if (r
->state
!= state
&& r
->state
!= ARM_CP_STATE_BOTH
) {
5975 if (state
== ARM_CP_STATE_AA32
) {
5976 /* Under AArch32 CP registers can be common
5977 * (same for secure and non-secure world) or banked.
5981 switch (r
->secure
) {
5982 case ARM_CP_SECSTATE_S
:
5983 case ARM_CP_SECSTATE_NS
:
5984 add_cpreg_to_hashtable(cpu
, r
, opaque
, state
,
5985 r
->secure
, crm
, opc1
, opc2
,
5989 name
= g_strdup_printf("%s_S", r
->name
);
5990 add_cpreg_to_hashtable(cpu
, r
, opaque
, state
,
5992 crm
, opc1
, opc2
, name
);
5994 add_cpreg_to_hashtable(cpu
, r
, opaque
, state
,
5996 crm
, opc1
, opc2
, r
->name
);
6000 /* AArch64 registers get mapped to non-secure instance
6002 add_cpreg_to_hashtable(cpu
, r
, opaque
, state
,
6004 crm
, opc1
, opc2
, r
->name
);
6012 void define_arm_cp_regs_with_opaque(ARMCPU
*cpu
,
6013 const ARMCPRegInfo
*regs
, void *opaque
)
6015 /* Define a whole list of registers */
6016 const ARMCPRegInfo
*r
;
6017 for (r
= regs
; r
->type
!= ARM_CP_SENTINEL
; r
++) {
6018 define_one_arm_cp_reg_with_opaque(cpu
, r
, opaque
);
6022 const ARMCPRegInfo
*get_arm_cp_reginfo(GHashTable
*cpregs
, uint32_t encoded_cp
)
6024 return g_hash_table_lookup(cpregs
, &encoded_cp
);
6027 void arm_cp_write_ignore(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6030 /* Helper coprocessor write function for write-ignore registers */
6033 uint64_t arm_cp_read_zero(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
6035 /* Helper coprocessor write function for read-as-zero registers */
6039 void arm_cp_reset_ignore(CPUARMState
*env
, const ARMCPRegInfo
*opaque
)
6041 /* Helper coprocessor reset function for do-nothing-on-reset registers */
6044 static int bad_mode_switch(CPUARMState
*env
, int mode
, CPSRWriteType write_type
)
6046 /* Return true if it is not valid for us to switch to
6047 * this CPU mode (ie all the UNPREDICTABLE cases in
6048 * the ARM ARM CPSRWriteByInstr pseudocode).
6051 /* Changes to or from Hyp via MSR and CPS are illegal. */
6052 if (write_type
== CPSRWriteByInstr
&&
6053 ((env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_HYP
||
6054 mode
== ARM_CPU_MODE_HYP
)) {
6059 case ARM_CPU_MODE_USR
:
6061 case ARM_CPU_MODE_SYS
:
6062 case ARM_CPU_MODE_SVC
:
6063 case ARM_CPU_MODE_ABT
:
6064 case ARM_CPU_MODE_UND
:
6065 case ARM_CPU_MODE_IRQ
:
6066 case ARM_CPU_MODE_FIQ
:
6067 /* Note that we don't implement the IMPDEF NSACR.RFR which in v7
6068 * allows FIQ mode to be Secure-only. (In v8 this doesn't exist.)
6070 /* If HCR.TGE is set then changes from Monitor to NS PL1 via MSR
6071 * and CPS are treated as illegal mode changes.
6073 if (write_type
== CPSRWriteByInstr
&&
6074 (env
->cp15
.hcr_el2
& HCR_TGE
) &&
6075 (env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_MON
&&
6076 !arm_is_secure_below_el3(env
)) {
6080 case ARM_CPU_MODE_HYP
:
6081 return !arm_feature(env
, ARM_FEATURE_EL2
)
6082 || arm_current_el(env
) < 2 || arm_is_secure(env
);
6083 case ARM_CPU_MODE_MON
:
6084 return arm_current_el(env
) < 3;
6090 uint32_t cpsr_read(CPUARMState
*env
)
6093 ZF
= (env
->ZF
== 0);
6094 return env
->uncached_cpsr
| (env
->NF
& 0x80000000) | (ZF
<< 30) |
6095 (env
->CF
<< 29) | ((env
->VF
& 0x80000000) >> 3) | (env
->QF
<< 27)
6096 | (env
->thumb
<< 5) | ((env
->condexec_bits
& 3) << 25)
6097 | ((env
->condexec_bits
& 0xfc) << 8)
6098 | (env
->GE
<< 16) | (env
->daif
& CPSR_AIF
);
6101 void cpsr_write(CPUARMState
*env
, uint32_t val
, uint32_t mask
,
6102 CPSRWriteType write_type
)
6104 uint32_t changed_daif
;
6106 if (mask
& CPSR_NZCV
) {
6107 env
->ZF
= (~val
) & CPSR_Z
;
6109 env
->CF
= (val
>> 29) & 1;
6110 env
->VF
= (val
<< 3) & 0x80000000;
6113 env
->QF
= ((val
& CPSR_Q
) != 0);
6115 env
->thumb
= ((val
& CPSR_T
) != 0);
6116 if (mask
& CPSR_IT_0_1
) {
6117 env
->condexec_bits
&= ~3;
6118 env
->condexec_bits
|= (val
>> 25) & 3;
6120 if (mask
& CPSR_IT_2_7
) {
6121 env
->condexec_bits
&= 3;
6122 env
->condexec_bits
|= (val
>> 8) & 0xfc;
6124 if (mask
& CPSR_GE
) {
6125 env
->GE
= (val
>> 16) & 0xf;
6128 /* In a V7 implementation that includes the security extensions but does
6129 * not include Virtualization Extensions the SCR.FW and SCR.AW bits control
6130 * whether non-secure software is allowed to change the CPSR_F and CPSR_A
6131 * bits respectively.
6133 * In a V8 implementation, it is permitted for privileged software to
6134 * change the CPSR A/F bits regardless of the SCR.AW/FW bits.
6136 if (write_type
!= CPSRWriteRaw
&& !arm_feature(env
, ARM_FEATURE_V8
) &&
6137 arm_feature(env
, ARM_FEATURE_EL3
) &&
6138 !arm_feature(env
, ARM_FEATURE_EL2
) &&
6139 !arm_is_secure(env
)) {
6141 changed_daif
= (env
->daif
^ val
) & mask
;
6143 if (changed_daif
& CPSR_A
) {
6144 /* Check to see if we are allowed to change the masking of async
6145 * abort exceptions from a non-secure state.
6147 if (!(env
->cp15
.scr_el3
& SCR_AW
)) {
6148 qemu_log_mask(LOG_GUEST_ERROR
,
6149 "Ignoring attempt to switch CPSR_A flag from "
6150 "non-secure world with SCR.AW bit clear\n");
6155 if (changed_daif
& CPSR_F
) {
6156 /* Check to see if we are allowed to change the masking of FIQ
6157 * exceptions from a non-secure state.
6159 if (!(env
->cp15
.scr_el3
& SCR_FW
)) {
6160 qemu_log_mask(LOG_GUEST_ERROR
,
6161 "Ignoring attempt to switch CPSR_F flag from "
6162 "non-secure world with SCR.FW bit clear\n");
6166 /* Check whether non-maskable FIQ (NMFI) support is enabled.
6167 * If this bit is set software is not allowed to mask
6168 * FIQs, but is allowed to set CPSR_F to 0.
6170 if ((A32_BANKED_CURRENT_REG_GET(env
, sctlr
) & SCTLR_NMFI
) &&
6172 qemu_log_mask(LOG_GUEST_ERROR
,
6173 "Ignoring attempt to enable CPSR_F flag "
6174 "(non-maskable FIQ [NMFI] support enabled)\n");
6180 env
->daif
&= ~(CPSR_AIF
& mask
);
6181 env
->daif
|= val
& CPSR_AIF
& mask
;
6183 if (write_type
!= CPSRWriteRaw
&&
6184 ((env
->uncached_cpsr
^ val
) & mask
& CPSR_M
)) {
6185 if ((env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_USR
) {
6186 /* Note that we can only get here in USR mode if this is a
6187 * gdb stub write; for this case we follow the architectural
6188 * behaviour for guest writes in USR mode of ignoring an attempt
6189 * to switch mode. (Those are caught by translate.c for writes
6190 * triggered by guest instructions.)
6193 } else if (bad_mode_switch(env
, val
& CPSR_M
, write_type
)) {
6194 /* Attempt to switch to an invalid mode: this is UNPREDICTABLE in
6195 * v7, and has defined behaviour in v8:
6196 * + leave CPSR.M untouched
6197 * + allow changes to the other CPSR fields
6199 * For user changes via the GDB stub, we don't set PSTATE.IL,
6200 * as this would be unnecessarily harsh for a user error.
6203 if (write_type
!= CPSRWriteByGDBStub
&&
6204 arm_feature(env
, ARM_FEATURE_V8
)) {
6209 switch_mode(env
, val
& CPSR_M
);
6212 mask
&= ~CACHED_CPSR_BITS
;
6213 env
->uncached_cpsr
= (env
->uncached_cpsr
& ~mask
) | (val
& mask
);
6216 /* Sign/zero extend */
6217 uint32_t HELPER(sxtb16
)(uint32_t x
)
6220 res
= (uint16_t)(int8_t)x
;
6221 res
|= (uint32_t)(int8_t)(x
>> 16) << 16;
6225 uint32_t HELPER(uxtb16
)(uint32_t x
)
6228 res
= (uint16_t)(uint8_t)x
;
6229 res
|= (uint32_t)(uint8_t)(x
>> 16) << 16;
6233 int32_t HELPER(sdiv
)(int32_t num
, int32_t den
)
6237 if (num
== INT_MIN
&& den
== -1)
6242 uint32_t HELPER(udiv
)(uint32_t num
, uint32_t den
)
6249 uint32_t HELPER(rbit
)(uint32_t x
)
6254 #if defined(CONFIG_USER_ONLY)
6256 /* These should probably raise undefined insn exceptions. */
6257 void HELPER(v7m_msr
)(CPUARMState
*env
, uint32_t reg
, uint32_t val
)
6259 ARMCPU
*cpu
= arm_env_get_cpu(env
);
6261 cpu_abort(CPU(cpu
), "v7m_msr %d\n", reg
);
6264 uint32_t HELPER(v7m_mrs
)(CPUARMState
*env
, uint32_t reg
)
6266 ARMCPU
*cpu
= arm_env_get_cpu(env
);
6268 cpu_abort(CPU(cpu
), "v7m_mrs %d\n", reg
);
6272 void HELPER(v7m_bxns
)(CPUARMState
*env
, uint32_t dest
)
6274 /* translate.c should never generate calls here in user-only mode */
6275 g_assert_not_reached();
6278 void HELPER(v7m_blxns
)(CPUARMState
*env
, uint32_t dest
)
6280 /* translate.c should never generate calls here in user-only mode */
6281 g_assert_not_reached();
6284 uint32_t HELPER(v7m_tt
)(CPUARMState
*env
, uint32_t addr
, uint32_t op
)
6286 /* The TT instructions can be used by unprivileged code, but in
6287 * user-only emulation we don't have the MPU.
6288 * Luckily since we know we are NonSecure unprivileged (and that in
6289 * turn means that the A flag wasn't specified), all the bits in the
6290 * register must be zero:
6291 * IREGION: 0 because IRVALID is 0
6292 * IRVALID: 0 because NS
6294 * NSRW: 0 because NS
6296 * RW: 0 because unpriv and A flag not set
6297 * R: 0 because unpriv and A flag not set
6298 * SRVALID: 0 because NS
6299 * MRVALID: 0 because unpriv and A flag not set
6300 * SREGION: 0 becaus SRVALID is 0
6301 * MREGION: 0 because MRVALID is 0
6306 void switch_mode(CPUARMState
*env
, int mode
)
6308 ARMCPU
*cpu
= arm_env_get_cpu(env
);
6310 if (mode
!= ARM_CPU_MODE_USR
) {
6311 cpu_abort(CPU(cpu
), "Tried to switch out of user mode\n");
6315 uint32_t arm_phys_excp_target_el(CPUState
*cs
, uint32_t excp_idx
,
6316 uint32_t cur_el
, bool secure
)
6321 void aarch64_sync_64_to_32(CPUARMState
*env
)
6323 g_assert_not_reached();
6328 void switch_mode(CPUARMState
*env
, int mode
)
6333 old_mode
= env
->uncached_cpsr
& CPSR_M
;
6334 if (mode
== old_mode
)
6337 if (old_mode
== ARM_CPU_MODE_FIQ
) {
6338 memcpy (env
->fiq_regs
, env
->regs
+ 8, 5 * sizeof(uint32_t));
6339 memcpy (env
->regs
+ 8, env
->usr_regs
, 5 * sizeof(uint32_t));
6340 } else if (mode
== ARM_CPU_MODE_FIQ
) {
6341 memcpy (env
->usr_regs
, env
->regs
+ 8, 5 * sizeof(uint32_t));
6342 memcpy (env
->regs
+ 8, env
->fiq_regs
, 5 * sizeof(uint32_t));
6345 i
= bank_number(old_mode
);
6346 env
->banked_r13
[i
] = env
->regs
[13];
6347 env
->banked_r14
[i
] = env
->regs
[14];
6348 env
->banked_spsr
[i
] = env
->spsr
;
6350 i
= bank_number(mode
);
6351 env
->regs
[13] = env
->banked_r13
[i
];
6352 env
->regs
[14] = env
->banked_r14
[i
];
6353 env
->spsr
= env
->banked_spsr
[i
];
6356 /* Physical Interrupt Target EL Lookup Table
6358 * [ From ARM ARM section G1.13.4 (Table G1-15) ]
6360 * The below multi-dimensional table is used for looking up the target
6361 * exception level given numerous condition criteria. Specifically, the
6362 * target EL is based on SCR and HCR routing controls as well as the
6363 * currently executing EL and secure state.
6366 * target_el_table[2][2][2][2][2][4]
6367 * | | | | | +--- Current EL
6368 * | | | | +------ Non-secure(0)/Secure(1)
6369 * | | | +--------- HCR mask override
6370 * | | +------------ SCR exec state control
6371 * | +--------------- SCR mask override
6372 * +------------------ 32-bit(0)/64-bit(1) EL3
6374 * The table values are as such:
6378 * The ARM ARM target EL table includes entries indicating that an "exception
6379 * is not taken". The two cases where this is applicable are:
6380 * 1) An exception is taken from EL3 but the SCR does not have the exception
6382 * 2) An exception is taken from EL2 but the HCR does not have the exception
6384 * In these two cases, the below table contain a target of EL1. This value is
6385 * returned as it is expected that the consumer of the table data will check
6386 * for "target EL >= current EL" to ensure the exception is not taken.
6390 * BIT IRQ IMO Non-secure Secure
6391 * EL3 FIQ RW FMO EL0 EL1 EL2 EL3 EL0 EL1 EL2 EL3
6393 static const int8_t target_el_table
[2][2][2][2][2][4] = {
6394 {{{{/* 0 0 0 0 */{ 1, 1, 2, -1 },{ 3, -1, -1, 3 },},
6395 {/* 0 0 0 1 */{ 2, 2, 2, -1 },{ 3, -1, -1, 3 },},},
6396 {{/* 0 0 1 0 */{ 1, 1, 2, -1 },{ 3, -1, -1, 3 },},
6397 {/* 0 0 1 1 */{ 2, 2, 2, -1 },{ 3, -1, -1, 3 },},},},
6398 {{{/* 0 1 0 0 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},
6399 {/* 0 1 0 1 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},},
6400 {{/* 0 1 1 0 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},
6401 {/* 0 1 1 1 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},},},},
6402 {{{{/* 1 0 0 0 */{ 1, 1, 2, -1 },{ 1, 1, -1, 1 },},
6403 {/* 1 0 0 1 */{ 2, 2, 2, -1 },{ 1, 1, -1, 1 },},},
6404 {{/* 1 0 1 0 */{ 1, 1, 1, -1 },{ 1, 1, -1, 1 },},
6405 {/* 1 0 1 1 */{ 2, 2, 2, -1 },{ 1, 1, -1, 1 },},},},
6406 {{{/* 1 1 0 0 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},
6407 {/* 1 1 0 1 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},},
6408 {{/* 1 1 1 0 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},
6409 {/* 1 1 1 1 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},},},},
6413 * Determine the target EL for physical exceptions
6415 uint32_t arm_phys_excp_target_el(CPUState
*cs
, uint32_t excp_idx
,
6416 uint32_t cur_el
, bool secure
)
6418 CPUARMState
*env
= cs
->env_ptr
;
6423 /* Is the highest EL AArch64? */
6424 int is64
= arm_feature(env
, ARM_FEATURE_AARCH64
);
6426 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
6427 rw
= ((env
->cp15
.scr_el3
& SCR_RW
) == SCR_RW
);
6429 /* Either EL2 is the highest EL (and so the EL2 register width
6430 * is given by is64); or there is no EL2 or EL3, in which case
6431 * the value of 'rw' does not affect the table lookup anyway.
6438 scr
= ((env
->cp15
.scr_el3
& SCR_IRQ
) == SCR_IRQ
);
6439 hcr
= arm_hcr_el2_imo(env
);
6442 scr
= ((env
->cp15
.scr_el3
& SCR_FIQ
) == SCR_FIQ
);
6443 hcr
= arm_hcr_el2_fmo(env
);
6446 scr
= ((env
->cp15
.scr_el3
& SCR_EA
) == SCR_EA
);
6447 hcr
= arm_hcr_el2_amo(env
);
6451 /* If HCR.TGE is set then HCR is treated as being 1 */
6452 hcr
|= ((env
->cp15
.hcr_el2
& HCR_TGE
) == HCR_TGE
);
6454 /* Perform a table-lookup for the target EL given the current state */
6455 target_el
= target_el_table
[is64
][scr
][rw
][hcr
][secure
][cur_el
];
6457 assert(target_el
> 0);
6462 static bool v7m_stack_write(ARMCPU
*cpu
, uint32_t addr
, uint32_t value
,
6463 ARMMMUIdx mmu_idx
, bool ignfault
)
6465 CPUState
*cs
= CPU(cpu
);
6466 CPUARMState
*env
= &cpu
->env
;
6467 MemTxAttrs attrs
= {};
6469 target_ulong page_size
;
6473 bool secure
= mmu_idx
& ARM_MMU_IDX_M_S
;
6477 if (get_phys_addr(env
, addr
, MMU_DATA_STORE
, mmu_idx
, &physaddr
,
6478 &attrs
, &prot
, &page_size
, &fi
, NULL
)) {
6479 /* MPU/SAU lookup failed */
6480 if (fi
.type
== ARMFault_QEMU_SFault
) {
6481 qemu_log_mask(CPU_LOG_INT
,
6482 "...SecureFault with SFSR.AUVIOL during stacking\n");
6483 env
->v7m
.sfsr
|= R_V7M_SFSR_AUVIOL_MASK
| R_V7M_SFSR_SFARVALID_MASK
;
6484 env
->v7m
.sfar
= addr
;
6485 exc
= ARMV7M_EXCP_SECURE
;
6488 qemu_log_mask(CPU_LOG_INT
, "...MemManageFault with CFSR.MSTKERR\n");
6489 env
->v7m
.cfsr
[secure
] |= R_V7M_CFSR_MSTKERR_MASK
;
6490 exc
= ARMV7M_EXCP_MEM
;
6491 exc_secure
= secure
;
6495 address_space_stl_le(arm_addressspace(cs
, attrs
), physaddr
, value
,
6497 if (txres
!= MEMTX_OK
) {
6498 /* BusFault trying to write the data */
6499 qemu_log_mask(CPU_LOG_INT
, "...BusFault with BFSR.STKERR\n");
6500 env
->v7m
.cfsr
[M_REG_NS
] |= R_V7M_CFSR_STKERR_MASK
;
6501 exc
= ARMV7M_EXCP_BUS
;
6508 /* By pending the exception at this point we are making
6509 * the IMPDEF choice "overridden exceptions pended" (see the
6510 * MergeExcInfo() pseudocode). The other choice would be to not
6511 * pend them now and then make a choice about which to throw away
6512 * later if we have two derived exceptions.
6513 * The only case when we must not pend the exception but instead
6514 * throw it away is if we are doing the push of the callee registers
6515 * and we've already generated a derived exception. Even in this
6516 * case we will still update the fault status registers.
6519 armv7m_nvic_set_pending_derived(env
->nvic
, exc
, exc_secure
);
6524 static bool v7m_stack_read(ARMCPU
*cpu
, uint32_t *dest
, uint32_t addr
,
6527 CPUState
*cs
= CPU(cpu
);
6528 CPUARMState
*env
= &cpu
->env
;
6529 MemTxAttrs attrs
= {};
6531 target_ulong page_size
;
6535 bool secure
= mmu_idx
& ARM_MMU_IDX_M_S
;
6540 if (get_phys_addr(env
, addr
, MMU_DATA_LOAD
, mmu_idx
, &physaddr
,
6541 &attrs
, &prot
, &page_size
, &fi
, NULL
)) {
6542 /* MPU/SAU lookup failed */
6543 if (fi
.type
== ARMFault_QEMU_SFault
) {
6544 qemu_log_mask(CPU_LOG_INT
,
6545 "...SecureFault with SFSR.AUVIOL during unstack\n");
6546 env
->v7m
.sfsr
|= R_V7M_SFSR_AUVIOL_MASK
| R_V7M_SFSR_SFARVALID_MASK
;
6547 env
->v7m
.sfar
= addr
;
6548 exc
= ARMV7M_EXCP_SECURE
;
6551 qemu_log_mask(CPU_LOG_INT
,
6552 "...MemManageFault with CFSR.MUNSTKERR\n");
6553 env
->v7m
.cfsr
[secure
] |= R_V7M_CFSR_MUNSTKERR_MASK
;
6554 exc
= ARMV7M_EXCP_MEM
;
6555 exc_secure
= secure
;
6560 value
= address_space_ldl(arm_addressspace(cs
, attrs
), physaddr
,
6562 if (txres
!= MEMTX_OK
) {
6563 /* BusFault trying to read the data */
6564 qemu_log_mask(CPU_LOG_INT
, "...BusFault with BFSR.UNSTKERR\n");
6565 env
->v7m
.cfsr
[M_REG_NS
] |= R_V7M_CFSR_UNSTKERR_MASK
;
6566 exc
= ARMV7M_EXCP_BUS
;
6575 /* By pending the exception at this point we are making
6576 * the IMPDEF choice "overridden exceptions pended" (see the
6577 * MergeExcInfo() pseudocode). The other choice would be to not
6578 * pend them now and then make a choice about which to throw away
6579 * later if we have two derived exceptions.
6581 armv7m_nvic_set_pending(env
->nvic
, exc
, exc_secure
);
6585 /* Return true if we're using the process stack pointer (not the MSP) */
6586 static bool v7m_using_psp(CPUARMState
*env
)
6588 /* Handler mode always uses the main stack; for thread mode
6589 * the CONTROL.SPSEL bit determines the answer.
6590 * Note that in v7M it is not possible to be in Handler mode with
6591 * CONTROL.SPSEL non-zero, but in v8M it is, so we must check both.
6593 return !arm_v7m_is_handler_mode(env
) &&
6594 env
->v7m
.control
[env
->v7m
.secure
] & R_V7M_CONTROL_SPSEL_MASK
;
6597 /* Write to v7M CONTROL.SPSEL bit for the specified security bank.
6598 * This may change the current stack pointer between Main and Process
6599 * stack pointers if it is done for the CONTROL register for the current
6602 static void write_v7m_control_spsel_for_secstate(CPUARMState
*env
,
6606 bool old_is_psp
= v7m_using_psp(env
);
6608 env
->v7m
.control
[secstate
] =
6609 deposit32(env
->v7m
.control
[secstate
],
6610 R_V7M_CONTROL_SPSEL_SHIFT
,
6611 R_V7M_CONTROL_SPSEL_LENGTH
, new_spsel
);
6613 if (secstate
== env
->v7m
.secure
) {
6614 bool new_is_psp
= v7m_using_psp(env
);
6617 if (old_is_psp
!= new_is_psp
) {
6618 tmp
= env
->v7m
.other_sp
;
6619 env
->v7m
.other_sp
= env
->regs
[13];
6620 env
->regs
[13] = tmp
;
6625 /* Write to v7M CONTROL.SPSEL bit. This may change the current
6626 * stack pointer between Main and Process stack pointers.
6628 static void write_v7m_control_spsel(CPUARMState
*env
, bool new_spsel
)
6630 write_v7m_control_spsel_for_secstate(env
, new_spsel
, env
->v7m
.secure
);
6633 void write_v7m_exception(CPUARMState
*env
, uint32_t new_exc
)
6635 /* Write a new value to v7m.exception, thus transitioning into or out
6636 * of Handler mode; this may result in a change of active stack pointer.
6638 bool new_is_psp
, old_is_psp
= v7m_using_psp(env
);
6641 env
->v7m
.exception
= new_exc
;
6643 new_is_psp
= v7m_using_psp(env
);
6645 if (old_is_psp
!= new_is_psp
) {
6646 tmp
= env
->v7m
.other_sp
;
6647 env
->v7m
.other_sp
= env
->regs
[13];
6648 env
->regs
[13] = tmp
;
6652 /* Switch M profile security state between NS and S */
6653 static void switch_v7m_security_state(CPUARMState
*env
, bool new_secstate
)
6655 uint32_t new_ss_msp
, new_ss_psp
;
6657 if (env
->v7m
.secure
== new_secstate
) {
6661 /* All the banked state is accessed by looking at env->v7m.secure
6662 * except for the stack pointer; rearrange the SP appropriately.
6664 new_ss_msp
= env
->v7m
.other_ss_msp
;
6665 new_ss_psp
= env
->v7m
.other_ss_psp
;
6667 if (v7m_using_psp(env
)) {
6668 env
->v7m
.other_ss_psp
= env
->regs
[13];
6669 env
->v7m
.other_ss_msp
= env
->v7m
.other_sp
;
6671 env
->v7m
.other_ss_msp
= env
->regs
[13];
6672 env
->v7m
.other_ss_psp
= env
->v7m
.other_sp
;
6675 env
->v7m
.secure
= new_secstate
;
6677 if (v7m_using_psp(env
)) {
6678 env
->regs
[13] = new_ss_psp
;
6679 env
->v7m
.other_sp
= new_ss_msp
;
6681 env
->regs
[13] = new_ss_msp
;
6682 env
->v7m
.other_sp
= new_ss_psp
;
6686 void HELPER(v7m_bxns
)(CPUARMState
*env
, uint32_t dest
)
6689 * - if the return value is a magic value, do exception return (like BX)
6690 * - otherwise bit 0 of the return value is the target security state
6694 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
6695 /* Covers FNC_RETURN and EXC_RETURN magic */
6696 min_magic
= FNC_RETURN_MIN_MAGIC
;
6698 /* EXC_RETURN magic only */
6699 min_magic
= EXC_RETURN_MIN_MAGIC
;
6702 if (dest
>= min_magic
) {
6703 /* This is an exception return magic value; put it where
6704 * do_v7m_exception_exit() expects and raise EXCEPTION_EXIT.
6705 * Note that if we ever add gen_ss_advance() singlestep support to
6706 * M profile this should count as an "instruction execution complete"
6707 * event (compare gen_bx_excret_final_code()).
6709 env
->regs
[15] = dest
& ~1;
6710 env
->thumb
= dest
& 1;
6711 HELPER(exception_internal
)(env
, EXCP_EXCEPTION_EXIT
);
6715 /* translate.c should have made BXNS UNDEF unless we're secure */
6716 assert(env
->v7m
.secure
);
6718 switch_v7m_security_state(env
, dest
& 1);
6720 env
->regs
[15] = dest
& ~1;
6723 void HELPER(v7m_blxns
)(CPUARMState
*env
, uint32_t dest
)
6725 /* Handle v7M BLXNS:
6726 * - bit 0 of the destination address is the target security state
6729 /* At this point regs[15] is the address just after the BLXNS */
6730 uint32_t nextinst
= env
->regs
[15] | 1;
6731 uint32_t sp
= env
->regs
[13] - 8;
6734 /* translate.c will have made BLXNS UNDEF unless we're secure */
6735 assert(env
->v7m
.secure
);
6738 /* target is Secure, so this is just a normal BLX,
6739 * except that the low bit doesn't indicate Thumb/not.
6741 env
->regs
[14] = nextinst
;
6743 env
->regs
[15] = dest
& ~1;
6747 /* Target is non-secure: first push a stack frame */
6748 if (!QEMU_IS_ALIGNED(sp
, 8)) {
6749 qemu_log_mask(LOG_GUEST_ERROR
,
6750 "BLXNS with misaligned SP is UNPREDICTABLE\n");
6753 saved_psr
= env
->v7m
.exception
;
6754 if (env
->v7m
.control
[M_REG_S
] & R_V7M_CONTROL_SFPA_MASK
) {
6755 saved_psr
|= XPSR_SFPA
;
6758 /* Note that these stores can throw exceptions on MPU faults */
6759 cpu_stl_data(env
, sp
, nextinst
);
6760 cpu_stl_data(env
, sp
+ 4, saved_psr
);
6763 env
->regs
[14] = 0xfeffffff;
6764 if (arm_v7m_is_handler_mode(env
)) {
6765 /* Write a dummy value to IPSR, to avoid leaking the current secure
6766 * exception number to non-secure code. This is guaranteed not
6767 * to cause write_v7m_exception() to actually change stacks.
6769 write_v7m_exception(env
, 1);
6771 switch_v7m_security_state(env
, 0);
6773 env
->regs
[15] = dest
;
6776 static uint32_t *get_v7m_sp_ptr(CPUARMState
*env
, bool secure
, bool threadmode
,
6779 /* Return a pointer to the location where we currently store the
6780 * stack pointer for the requested security state and thread mode.
6781 * This pointer will become invalid if the CPU state is updated
6782 * such that the stack pointers are switched around (eg changing
6783 * the SPSEL control bit).
6784 * Compare the v8M ARM ARM pseudocode LookUpSP_with_security_mode().
6785 * Unlike that pseudocode, we require the caller to pass us in the
6786 * SPSEL control bit value; this is because we also use this
6787 * function in handling of pushing of the callee-saves registers
6788 * part of the v8M stack frame (pseudocode PushCalleeStack()),
6789 * and in the tailchain codepath the SPSEL bit comes from the exception
6790 * return magic LR value from the previous exception. The pseudocode
6791 * opencodes the stack-selection in PushCalleeStack(), but we prefer
6792 * to make this utility function generic enough to do the job.
6794 bool want_psp
= threadmode
&& spsel
;
6796 if (secure
== env
->v7m
.secure
) {
6797 if (want_psp
== v7m_using_psp(env
)) {
6798 return &env
->regs
[13];
6800 return &env
->v7m
.other_sp
;
6804 return &env
->v7m
.other_ss_psp
;
6806 return &env
->v7m
.other_ss_msp
;
6811 static bool arm_v7m_load_vector(ARMCPU
*cpu
, int exc
, bool targets_secure
,
6814 CPUState
*cs
= CPU(cpu
);
6815 CPUARMState
*env
= &cpu
->env
;
6817 uint32_t addr
= env
->v7m
.vecbase
[targets_secure
] + exc
* 4;
6818 uint32_t vector_entry
;
6819 MemTxAttrs attrs
= {};
6823 mmu_idx
= arm_v7m_mmu_idx_for_secstate_and_priv(env
, targets_secure
, true);
6825 /* We don't do a get_phys_addr() here because the rules for vector
6826 * loads are special: they always use the default memory map, and
6827 * the default memory map permits reads from all addresses.
6828 * Since there's no easy way to pass through to pmsav8_mpu_lookup()
6829 * that we want this special case which would always say "yes",
6830 * we just do the SAU lookup here followed by a direct physical load.
6832 attrs
.secure
= targets_secure
;
6835 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
6836 V8M_SAttributes sattrs
= {};
6838 v8m_security_lookup(env
, addr
, MMU_DATA_LOAD
, mmu_idx
, &sattrs
);
6840 attrs
.secure
= false;
6841 } else if (!targets_secure
) {
6842 /* NS access to S memory */
6847 vector_entry
= address_space_ldl(arm_addressspace(cs
, attrs
), addr
,
6849 if (result
!= MEMTX_OK
) {
6852 *pvec
= vector_entry
;
6856 /* All vector table fetch fails are reported as HardFault, with
6857 * HFSR.VECTTBL and .FORCED set. (FORCED is set because
6858 * technically the underlying exception is a MemManage or BusFault
6859 * that is escalated to HardFault.) This is a terminal exception,
6860 * so we will either take the HardFault immediately or else enter
6861 * lockup (the latter case is handled in armv7m_nvic_set_pending_derived()).
6863 exc_secure
= targets_secure
||
6864 !(cpu
->env
.v7m
.aircr
& R_V7M_AIRCR_BFHFNMINS_MASK
);
6865 env
->v7m
.hfsr
|= R_V7M_HFSR_VECTTBL_MASK
| R_V7M_HFSR_FORCED_MASK
;
6866 armv7m_nvic_set_pending_derived(env
->nvic
, ARMV7M_EXCP_HARD
, exc_secure
);
6870 static bool v7m_push_callee_stack(ARMCPU
*cpu
, uint32_t lr
, bool dotailchain
,
6873 /* For v8M, push the callee-saves register part of the stack frame.
6874 * Compare the v8M pseudocode PushCalleeStack().
6875 * In the tailchaining case this may not be the current stack.
6877 CPUARMState
*env
= &cpu
->env
;
6878 uint32_t *frame_sp_p
;
6884 bool mode
= lr
& R_V7M_EXCRET_MODE_MASK
;
6885 bool priv
= !(env
->v7m
.control
[M_REG_S
] & R_V7M_CONTROL_NPRIV_MASK
) ||
6888 mmu_idx
= arm_v7m_mmu_idx_for_secstate_and_priv(env
, M_REG_S
, priv
);
6889 frame_sp_p
= get_v7m_sp_ptr(env
, M_REG_S
, mode
,
6890 lr
& R_V7M_EXCRET_SPSEL_MASK
);
6892 mmu_idx
= core_to_arm_mmu_idx(env
, cpu_mmu_index(env
, false));
6893 frame_sp_p
= &env
->regs
[13];
6896 frameptr
= *frame_sp_p
- 0x28;
6898 /* Write as much of the stack frame as we can. A write failure may
6899 * cause us to pend a derived exception.
6902 v7m_stack_write(cpu
, frameptr
, 0xfefa125b, mmu_idx
, ignore_faults
) &&
6903 v7m_stack_write(cpu
, frameptr
+ 0x8, env
->regs
[4], mmu_idx
,
6905 v7m_stack_write(cpu
, frameptr
+ 0xc, env
->regs
[5], mmu_idx
,
6907 v7m_stack_write(cpu
, frameptr
+ 0x10, env
->regs
[6], mmu_idx
,
6909 v7m_stack_write(cpu
, frameptr
+ 0x14, env
->regs
[7], mmu_idx
,
6911 v7m_stack_write(cpu
, frameptr
+ 0x18, env
->regs
[8], mmu_idx
,
6913 v7m_stack_write(cpu
, frameptr
+ 0x1c, env
->regs
[9], mmu_idx
,
6915 v7m_stack_write(cpu
, frameptr
+ 0x20, env
->regs
[10], mmu_idx
,
6917 v7m_stack_write(cpu
, frameptr
+ 0x24, env
->regs
[11], mmu_idx
,
6920 /* Update SP regardless of whether any of the stack accesses failed.
6921 * When we implement v8M stack limit checking then this attempt to
6922 * update SP might also fail and result in a derived exception.
6924 *frame_sp_p
= frameptr
;
6929 static void v7m_exception_taken(ARMCPU
*cpu
, uint32_t lr
, bool dotailchain
,
6930 bool ignore_stackfaults
)
6932 /* Do the "take the exception" parts of exception entry,
6933 * but not the pushing of state to the stack. This is
6934 * similar to the pseudocode ExceptionTaken() function.
6936 CPUARMState
*env
= &cpu
->env
;
6938 bool targets_secure
;
6940 bool push_failed
= false;
6942 armv7m_nvic_get_pending_irq_info(env
->nvic
, &exc
, &targets_secure
);
6943 qemu_log_mask(CPU_LOG_INT
, "...taking pending %s exception %d\n",
6944 targets_secure
? "secure" : "nonsecure", exc
);
6946 if (arm_feature(env
, ARM_FEATURE_V8
)) {
6947 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
) &&
6948 (lr
& R_V7M_EXCRET_S_MASK
)) {
6949 /* The background code (the owner of the registers in the
6950 * exception frame) is Secure. This means it may either already
6951 * have or now needs to push callee-saves registers.
6953 if (targets_secure
) {
6954 if (dotailchain
&& !(lr
& R_V7M_EXCRET_ES_MASK
)) {
6955 /* We took an exception from Secure to NonSecure
6956 * (which means the callee-saved registers got stacked)
6957 * and are now tailchaining to a Secure exception.
6958 * Clear DCRS so eventual return from this Secure
6959 * exception unstacks the callee-saved registers.
6961 lr
&= ~R_V7M_EXCRET_DCRS_MASK
;
6964 /* We're going to a non-secure exception; push the
6965 * callee-saves registers to the stack now, if they're
6966 * not already saved.
6968 if (lr
& R_V7M_EXCRET_DCRS_MASK
&&
6969 !(dotailchain
&& !(lr
& R_V7M_EXCRET_ES_MASK
))) {
6970 push_failed
= v7m_push_callee_stack(cpu
, lr
, dotailchain
,
6971 ignore_stackfaults
);
6973 lr
|= R_V7M_EXCRET_DCRS_MASK
;
6977 lr
&= ~R_V7M_EXCRET_ES_MASK
;
6978 if (targets_secure
|| !arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
6979 lr
|= R_V7M_EXCRET_ES_MASK
;
6981 lr
&= ~R_V7M_EXCRET_SPSEL_MASK
;
6982 if (env
->v7m
.control
[targets_secure
] & R_V7M_CONTROL_SPSEL_MASK
) {
6983 lr
|= R_V7M_EXCRET_SPSEL_MASK
;
6986 /* Clear registers if necessary to prevent non-secure exception
6987 * code being able to see register values from secure code.
6988 * Where register values become architecturally UNKNOWN we leave
6989 * them with their previous values.
6991 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
6992 if (!targets_secure
) {
6993 /* Always clear the caller-saved registers (they have been
6994 * pushed to the stack earlier in v7m_push_stack()).
6995 * Clear callee-saved registers if the background code is
6996 * Secure (in which case these regs were saved in
6997 * v7m_push_callee_stack()).
7001 for (i
= 0; i
< 13; i
++) {
7002 /* r4..r11 are callee-saves, zero only if EXCRET.S == 1 */
7003 if (i
< 4 || i
> 11 || (lr
& R_V7M_EXCRET_S_MASK
)) {
7008 xpsr_write(env
, 0, XPSR_NZCV
| XPSR_Q
| XPSR_GE
| XPSR_IT
);
7013 if (push_failed
&& !ignore_stackfaults
) {
7014 /* Derived exception on callee-saves register stacking:
7015 * we might now want to take a different exception which
7016 * targets a different security state, so try again from the top.
7018 qemu_log_mask(CPU_LOG_INT
,
7019 "...derived exception on callee-saves register stacking");
7020 v7m_exception_taken(cpu
, lr
, true, true);
7024 if (!arm_v7m_load_vector(cpu
, exc
, targets_secure
, &addr
)) {
7025 /* Vector load failed: derived exception */
7026 qemu_log_mask(CPU_LOG_INT
, "...derived exception on vector table load");
7027 v7m_exception_taken(cpu
, lr
, true, true);
7031 /* Now we've done everything that might cause a derived exception
7032 * we can go ahead and activate whichever exception we're going to
7033 * take (which might now be the derived exception).
7035 armv7m_nvic_acknowledge_irq(env
->nvic
);
7037 /* Switch to target security state -- must do this before writing SPSEL */
7038 switch_v7m_security_state(env
, targets_secure
);
7039 write_v7m_control_spsel(env
, 0);
7040 arm_clear_exclusive(env
);
7042 env
->condexec_bits
= 0;
7044 env
->regs
[15] = addr
& 0xfffffffe;
7045 env
->thumb
= addr
& 1;
7048 static bool v7m_push_stack(ARMCPU
*cpu
)
7050 /* Do the "set up stack frame" part of exception entry,
7051 * similar to pseudocode PushStack().
7052 * Return true if we generate a derived exception (and so
7053 * should ignore further stack faults trying to process
7054 * that derived exception.)
7057 CPUARMState
*env
= &cpu
->env
;
7058 uint32_t xpsr
= xpsr_read(env
);
7059 uint32_t frameptr
= env
->regs
[13];
7060 ARMMMUIdx mmu_idx
= core_to_arm_mmu_idx(env
, cpu_mmu_index(env
, false));
7062 /* Align stack pointer if the guest wants that */
7063 if ((frameptr
& 4) &&
7064 (env
->v7m
.ccr
[env
->v7m
.secure
] & R_V7M_CCR_STKALIGN_MASK
)) {
7066 xpsr
|= XPSR_SPREALIGN
;
7071 /* Write as much of the stack frame as we can. If we fail a stack
7072 * write this will result in a derived exception being pended
7073 * (which may be taken in preference to the one we started with
7074 * if it has higher priority).
7077 v7m_stack_write(cpu
, frameptr
, env
->regs
[0], mmu_idx
, false) &&
7078 v7m_stack_write(cpu
, frameptr
+ 4, env
->regs
[1], mmu_idx
, false) &&
7079 v7m_stack_write(cpu
, frameptr
+ 8, env
->regs
[2], mmu_idx
, false) &&
7080 v7m_stack_write(cpu
, frameptr
+ 12, env
->regs
[3], mmu_idx
, false) &&
7081 v7m_stack_write(cpu
, frameptr
+ 16, env
->regs
[12], mmu_idx
, false) &&
7082 v7m_stack_write(cpu
, frameptr
+ 20, env
->regs
[14], mmu_idx
, false) &&
7083 v7m_stack_write(cpu
, frameptr
+ 24, env
->regs
[15], mmu_idx
, false) &&
7084 v7m_stack_write(cpu
, frameptr
+ 28, xpsr
, mmu_idx
, false);
7086 /* Update SP regardless of whether any of the stack accesses failed.
7087 * When we implement v8M stack limit checking then this attempt to
7088 * update SP might also fail and result in a derived exception.
7090 env
->regs
[13] = frameptr
;
7095 static void do_v7m_exception_exit(ARMCPU
*cpu
)
7097 CPUARMState
*env
= &cpu
->env
;
7100 bool ufault
= false;
7101 bool sfault
= false;
7102 bool return_to_sp_process
;
7103 bool return_to_handler
;
7104 bool rettobase
= false;
7105 bool exc_secure
= false;
7106 bool return_to_secure
;
7108 /* If we're not in Handler mode then jumps to magic exception-exit
7109 * addresses don't have magic behaviour. However for the v8M
7110 * security extensions the magic secure-function-return has to
7111 * work in thread mode too, so to avoid doing an extra check in
7112 * the generated code we allow exception-exit magic to also cause the
7113 * internal exception and bring us here in thread mode. Correct code
7114 * will never try to do this (the following insn fetch will always
7115 * fault) so we the overhead of having taken an unnecessary exception
7118 if (!arm_v7m_is_handler_mode(env
)) {
7122 /* In the spec pseudocode ExceptionReturn() is called directly
7123 * from BXWritePC() and gets the full target PC value including
7124 * bit zero. In QEMU's implementation we treat it as a normal
7125 * jump-to-register (which is then caught later on), and so split
7126 * the target value up between env->regs[15] and env->thumb in
7127 * gen_bx(). Reconstitute it.
7129 excret
= env
->regs
[15];
7134 qemu_log_mask(CPU_LOG_INT
, "Exception return: magic PC %" PRIx32
7135 " previous exception %d\n",
7136 excret
, env
->v7m
.exception
);
7138 if ((excret
& R_V7M_EXCRET_RES1_MASK
) != R_V7M_EXCRET_RES1_MASK
) {
7139 qemu_log_mask(LOG_GUEST_ERROR
, "M profile: zero high bits in exception "
7140 "exit PC value 0x%" PRIx32
" are UNPREDICTABLE\n",
7144 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
7145 /* EXC_RETURN.ES validation check (R_SMFL). We must do this before
7146 * we pick which FAULTMASK to clear.
7148 if (!env
->v7m
.secure
&&
7149 ((excret
& R_V7M_EXCRET_ES_MASK
) ||
7150 !(excret
& R_V7M_EXCRET_DCRS_MASK
))) {
7152 /* For all other purposes, treat ES as 0 (R_HXSR) */
7153 excret
&= ~R_V7M_EXCRET_ES_MASK
;
7155 exc_secure
= excret
& R_V7M_EXCRET_ES_MASK
;
7158 if (env
->v7m
.exception
!= ARMV7M_EXCP_NMI
) {
7159 /* Auto-clear FAULTMASK on return from other than NMI.
7160 * If the security extension is implemented then this only
7161 * happens if the raw execution priority is >= 0; the
7162 * value of the ES bit in the exception return value indicates
7163 * which security state's faultmask to clear. (v8M ARM ARM R_KBNF.)
7165 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
7166 if (armv7m_nvic_raw_execution_priority(env
->nvic
) >= 0) {
7167 env
->v7m
.faultmask
[exc_secure
] = 0;
7170 env
->v7m
.faultmask
[M_REG_NS
] = 0;
7174 switch (armv7m_nvic_complete_irq(env
->nvic
, env
->v7m
.exception
,
7177 /* attempt to exit an exception that isn't active */
7181 /* still an irq active now */
7184 /* we returned to base exception level, no nesting.
7185 * (In the pseudocode this is written using "NestedActivation != 1"
7186 * where we have 'rettobase == false'.)
7191 g_assert_not_reached();
7194 return_to_handler
= !(excret
& R_V7M_EXCRET_MODE_MASK
);
7195 return_to_sp_process
= excret
& R_V7M_EXCRET_SPSEL_MASK
;
7196 return_to_secure
= arm_feature(env
, ARM_FEATURE_M_SECURITY
) &&
7197 (excret
& R_V7M_EXCRET_S_MASK
);
7199 if (arm_feature(env
, ARM_FEATURE_V8
)) {
7200 if (!arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
7201 /* UNPREDICTABLE if S == 1 or DCRS == 0 or ES == 1 (R_XLCP);
7202 * we choose to take the UsageFault.
7204 if ((excret
& R_V7M_EXCRET_S_MASK
) ||
7205 (excret
& R_V7M_EXCRET_ES_MASK
) ||
7206 !(excret
& R_V7M_EXCRET_DCRS_MASK
)) {
7210 if (excret
& R_V7M_EXCRET_RES0_MASK
) {
7214 /* For v7M we only recognize certain combinations of the low bits */
7215 switch (excret
& 0xf) {
7216 case 1: /* Return to Handler */
7218 case 13: /* Return to Thread using Process stack */
7219 case 9: /* Return to Thread using Main stack */
7220 /* We only need to check NONBASETHRDENA for v7M, because in
7221 * v8M this bit does not exist (it is RES1).
7224 !(env
->v7m
.ccr
[env
->v7m
.secure
] &
7225 R_V7M_CCR_NONBASETHRDENA_MASK
)) {
7235 * Set CONTROL.SPSEL from excret.SPSEL. Since we're still in
7236 * Handler mode (and will be until we write the new XPSR.Interrupt
7237 * field) this does not switch around the current stack pointer.
7238 * We must do this before we do any kind of tailchaining, including
7239 * for the derived exceptions on integrity check failures, or we will
7240 * give the guest an incorrect EXCRET.SPSEL value on exception entry.
7242 write_v7m_control_spsel_for_secstate(env
, return_to_sp_process
, exc_secure
);
7245 env
->v7m
.sfsr
|= R_V7M_SFSR_INVER_MASK
;
7246 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_SECURE
, false);
7247 qemu_log_mask(CPU_LOG_INT
, "...taking SecureFault on existing "
7248 "stackframe: failed EXC_RETURN.ES validity check\n");
7249 v7m_exception_taken(cpu
, excret
, true, false);
7254 /* Bad exception return: instead of popping the exception
7255 * stack, directly take a usage fault on the current stack.
7257 env
->v7m
.cfsr
[env
->v7m
.secure
] |= R_V7M_CFSR_INVPC_MASK
;
7258 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_USAGE
, env
->v7m
.secure
);
7259 qemu_log_mask(CPU_LOG_INT
, "...taking UsageFault on existing "
7260 "stackframe: failed exception return integrity check\n");
7261 v7m_exception_taken(cpu
, excret
, true, false);
7266 * Tailchaining: if there is currently a pending exception that
7267 * is high enough priority to preempt execution at the level we're
7268 * about to return to, then just directly take that exception now,
7269 * avoiding an unstack-and-then-stack. Note that now we have
7270 * deactivated the previous exception by calling armv7m_nvic_complete_irq()
7271 * our current execution priority is already the execution priority we are
7272 * returning to -- none of the state we would unstack or set based on
7273 * the EXCRET value affects it.
7275 if (armv7m_nvic_can_take_pending_exception(env
->nvic
)) {
7276 qemu_log_mask(CPU_LOG_INT
, "...tailchaining to pending exception\n");
7277 v7m_exception_taken(cpu
, excret
, true, false);
7281 switch_v7m_security_state(env
, return_to_secure
);
7284 /* The stack pointer we should be reading the exception frame from
7285 * depends on bits in the magic exception return type value (and
7286 * for v8M isn't necessarily the stack pointer we will eventually
7287 * end up resuming execution with). Get a pointer to the location
7288 * in the CPU state struct where the SP we need is currently being
7289 * stored; we will use and modify it in place.
7290 * We use this limited C variable scope so we don't accidentally
7291 * use 'frame_sp_p' after we do something that makes it invalid.
7293 uint32_t *frame_sp_p
= get_v7m_sp_ptr(env
,
7296 return_to_sp_process
);
7297 uint32_t frameptr
= *frame_sp_p
;
7300 bool return_to_priv
= return_to_handler
||
7301 !(env
->v7m
.control
[return_to_secure
] & R_V7M_CONTROL_NPRIV_MASK
);
7303 mmu_idx
= arm_v7m_mmu_idx_for_secstate_and_priv(env
, return_to_secure
,
7306 if (!QEMU_IS_ALIGNED(frameptr
, 8) &&
7307 arm_feature(env
, ARM_FEATURE_V8
)) {
7308 qemu_log_mask(LOG_GUEST_ERROR
,
7309 "M profile exception return with non-8-aligned SP "
7310 "for destination state is UNPREDICTABLE\n");
7313 /* Do we need to pop callee-saved registers? */
7314 if (return_to_secure
&&
7315 ((excret
& R_V7M_EXCRET_ES_MASK
) == 0 ||
7316 (excret
& R_V7M_EXCRET_DCRS_MASK
) == 0)) {
7317 uint32_t expected_sig
= 0xfefa125b;
7318 uint32_t actual_sig
;
7320 pop_ok
= v7m_stack_read(cpu
, &actual_sig
, frameptr
, mmu_idx
);
7322 if (pop_ok
&& expected_sig
!= actual_sig
) {
7323 /* Take a SecureFault on the current stack */
7324 env
->v7m
.sfsr
|= R_V7M_SFSR_INVIS_MASK
;
7325 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_SECURE
, false);
7326 qemu_log_mask(CPU_LOG_INT
, "...taking SecureFault on existing "
7327 "stackframe: failed exception return integrity "
7328 "signature check\n");
7329 v7m_exception_taken(cpu
, excret
, true, false);
7334 v7m_stack_read(cpu
, &env
->regs
[4], frameptr
+ 0x8, mmu_idx
) &&
7335 v7m_stack_read(cpu
, &env
->regs
[5], frameptr
+ 0xc, mmu_idx
) &&
7336 v7m_stack_read(cpu
, &env
->regs
[6], frameptr
+ 0x10, mmu_idx
) &&
7337 v7m_stack_read(cpu
, &env
->regs
[7], frameptr
+ 0x14, mmu_idx
) &&
7338 v7m_stack_read(cpu
, &env
->regs
[8], frameptr
+ 0x18, mmu_idx
) &&
7339 v7m_stack_read(cpu
, &env
->regs
[9], frameptr
+ 0x1c, mmu_idx
) &&
7340 v7m_stack_read(cpu
, &env
->regs
[10], frameptr
+ 0x20, mmu_idx
) &&
7341 v7m_stack_read(cpu
, &env
->regs
[11], frameptr
+ 0x24, mmu_idx
);
7348 v7m_stack_read(cpu
, &env
->regs
[0], frameptr
, mmu_idx
) &&
7349 v7m_stack_read(cpu
, &env
->regs
[1], frameptr
+ 0x4, mmu_idx
) &&
7350 v7m_stack_read(cpu
, &env
->regs
[2], frameptr
+ 0x8, mmu_idx
) &&
7351 v7m_stack_read(cpu
, &env
->regs
[3], frameptr
+ 0xc, mmu_idx
) &&
7352 v7m_stack_read(cpu
, &env
->regs
[12], frameptr
+ 0x10, mmu_idx
) &&
7353 v7m_stack_read(cpu
, &env
->regs
[14], frameptr
+ 0x14, mmu_idx
) &&
7354 v7m_stack_read(cpu
, &env
->regs
[15], frameptr
+ 0x18, mmu_idx
) &&
7355 v7m_stack_read(cpu
, &xpsr
, frameptr
+ 0x1c, mmu_idx
);
7358 /* v7m_stack_read() pended a fault, so take it (as a tail
7359 * chained exception on the same stack frame)
7361 qemu_log_mask(CPU_LOG_INT
, "...derived exception on unstacking\n");
7362 v7m_exception_taken(cpu
, excret
, true, false);
7366 /* Returning from an exception with a PC with bit 0 set is defined
7367 * behaviour on v8M (bit 0 is ignored), but for v7M it was specified
7368 * to be UNPREDICTABLE. In practice actual v7M hardware seems to ignore
7369 * the lsbit, and there are several RTOSes out there which incorrectly
7370 * assume the r15 in the stack frame should be a Thumb-style "lsbit
7371 * indicates ARM/Thumb" value, so ignore the bit on v7M as well, but
7372 * complain about the badly behaved guest.
7374 if (env
->regs
[15] & 1) {
7375 env
->regs
[15] &= ~1U;
7376 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
7377 qemu_log_mask(LOG_GUEST_ERROR
,
7378 "M profile return from interrupt with misaligned "
7379 "PC is UNPREDICTABLE on v7M\n");
7383 if (arm_feature(env
, ARM_FEATURE_V8
)) {
7384 /* For v8M we have to check whether the xPSR exception field
7385 * matches the EXCRET value for return to handler/thread
7386 * before we commit to changing the SP and xPSR.
7388 bool will_be_handler
= (xpsr
& XPSR_EXCP
) != 0;
7389 if (return_to_handler
!= will_be_handler
) {
7390 /* Take an INVPC UsageFault on the current stack.
7391 * By this point we will have switched to the security state
7392 * for the background state, so this UsageFault will target
7395 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_USAGE
,
7397 env
->v7m
.cfsr
[env
->v7m
.secure
] |= R_V7M_CFSR_INVPC_MASK
;
7398 qemu_log_mask(CPU_LOG_INT
, "...taking UsageFault on existing "
7399 "stackframe: failed exception return integrity "
7401 v7m_exception_taken(cpu
, excret
, true, false);
7406 /* Commit to consuming the stack frame */
7408 /* Undo stack alignment (the SPREALIGN bit indicates that the original
7409 * pre-exception SP was not 8-aligned and we added a padding word to
7410 * align it, so we undo this by ORing in the bit that increases it
7411 * from the current 8-aligned value to the 8-unaligned value. (Adding 4
7412 * would work too but a logical OR is how the pseudocode specifies it.)
7414 if (xpsr
& XPSR_SPREALIGN
) {
7417 *frame_sp_p
= frameptr
;
7419 /* This xpsr_write() will invalidate frame_sp_p as it may switch stack */
7420 xpsr_write(env
, xpsr
, ~XPSR_SPREALIGN
);
7422 /* The restored xPSR exception field will be zero if we're
7423 * resuming in Thread mode. If that doesn't match what the
7424 * exception return excret specified then this is a UsageFault.
7425 * v7M requires we make this check here; v8M did it earlier.
7427 if (return_to_handler
!= arm_v7m_is_handler_mode(env
)) {
7428 /* Take an INVPC UsageFault by pushing the stack again;
7429 * we know we're v7M so this is never a Secure UsageFault.
7431 bool ignore_stackfaults
;
7433 assert(!arm_feature(env
, ARM_FEATURE_V8
));
7434 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_USAGE
, false);
7435 env
->v7m
.cfsr
[env
->v7m
.secure
] |= R_V7M_CFSR_INVPC_MASK
;
7436 ignore_stackfaults
= v7m_push_stack(cpu
);
7437 qemu_log_mask(CPU_LOG_INT
, "...taking UsageFault on new stackframe: "
7438 "failed exception return integrity check\n");
7439 v7m_exception_taken(cpu
, excret
, false, ignore_stackfaults
);
7443 /* Otherwise, we have a successful exception exit. */
7444 arm_clear_exclusive(env
);
7445 qemu_log_mask(CPU_LOG_INT
, "...successful exception return\n");
7448 static bool do_v7m_function_return(ARMCPU
*cpu
)
7450 /* v8M security extensions magic function return.
7452 * (1) throw an exception (longjump)
7453 * (2) return true if we successfully handled the function return
7454 * (3) return false if we failed a consistency check and have
7455 * pended a UsageFault that needs to be taken now
7457 * At this point the magic return value is split between env->regs[15]
7458 * and env->thumb. We don't bother to reconstitute it because we don't
7459 * need it (all values are handled the same way).
7461 CPUARMState
*env
= &cpu
->env
;
7462 uint32_t newpc
, newpsr
, newpsr_exc
;
7464 qemu_log_mask(CPU_LOG_INT
, "...really v7M secure function return\n");
7467 bool threadmode
, spsel
;
7470 uint32_t *frame_sp_p
;
7473 /* Pull the return address and IPSR from the Secure stack */
7474 threadmode
= !arm_v7m_is_handler_mode(env
);
7475 spsel
= env
->v7m
.control
[M_REG_S
] & R_V7M_CONTROL_SPSEL_MASK
;
7477 frame_sp_p
= get_v7m_sp_ptr(env
, true, threadmode
, spsel
);
7478 frameptr
= *frame_sp_p
;
7480 /* These loads may throw an exception (for MPU faults). We want to
7481 * do them as secure, so work out what MMU index that is.
7483 mmu_idx
= arm_v7m_mmu_idx_for_secstate(env
, true);
7484 oi
= make_memop_idx(MO_LE
, arm_to_core_mmu_idx(mmu_idx
));
7485 newpc
= helper_le_ldul_mmu(env
, frameptr
, oi
, 0);
7486 newpsr
= helper_le_ldul_mmu(env
, frameptr
+ 4, oi
, 0);
7488 /* Consistency checks on new IPSR */
7489 newpsr_exc
= newpsr
& XPSR_EXCP
;
7490 if (!((env
->v7m
.exception
== 0 && newpsr_exc
== 0) ||
7491 (env
->v7m
.exception
== 1 && newpsr_exc
!= 0))) {
7492 /* Pend the fault and tell our caller to take it */
7493 env
->v7m
.cfsr
[env
->v7m
.secure
] |= R_V7M_CFSR_INVPC_MASK
;
7494 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_USAGE
,
7496 qemu_log_mask(CPU_LOG_INT
,
7497 "...taking INVPC UsageFault: "
7498 "IPSR consistency check failed\n");
7502 *frame_sp_p
= frameptr
+ 8;
7505 /* This invalidates frame_sp_p */
7506 switch_v7m_security_state(env
, true);
7507 env
->v7m
.exception
= newpsr_exc
;
7508 env
->v7m
.control
[M_REG_S
] &= ~R_V7M_CONTROL_SFPA_MASK
;
7509 if (newpsr
& XPSR_SFPA
) {
7510 env
->v7m
.control
[M_REG_S
] |= R_V7M_CONTROL_SFPA_MASK
;
7512 xpsr_write(env
, 0, XPSR_IT
);
7513 env
->thumb
= newpc
& 1;
7514 env
->regs
[15] = newpc
& ~1;
7516 qemu_log_mask(CPU_LOG_INT
, "...function return successful\n");
7520 static void arm_log_exception(int idx
)
7522 if (qemu_loglevel_mask(CPU_LOG_INT
)) {
7523 const char *exc
= NULL
;
7524 static const char * const excnames
[] = {
7525 [EXCP_UDEF
] = "Undefined Instruction",
7527 [EXCP_PREFETCH_ABORT
] = "Prefetch Abort",
7528 [EXCP_DATA_ABORT
] = "Data Abort",
7531 [EXCP_BKPT
] = "Breakpoint",
7532 [EXCP_EXCEPTION_EXIT
] = "QEMU v7M exception exit",
7533 [EXCP_KERNEL_TRAP
] = "QEMU intercept of kernel commpage",
7534 [EXCP_HVC
] = "Hypervisor Call",
7535 [EXCP_HYP_TRAP
] = "Hypervisor Trap",
7536 [EXCP_SMC
] = "Secure Monitor Call",
7537 [EXCP_VIRQ
] = "Virtual IRQ",
7538 [EXCP_VFIQ
] = "Virtual FIQ",
7539 [EXCP_SEMIHOST
] = "Semihosting call",
7540 [EXCP_NOCP
] = "v7M NOCP UsageFault",
7541 [EXCP_INVSTATE
] = "v7M INVSTATE UsageFault",
7542 [EXCP_STKOF
] = "v8M STKOF UsageFault",
7545 if (idx
>= 0 && idx
< ARRAY_SIZE(excnames
)) {
7546 exc
= excnames
[idx
];
7551 qemu_log_mask(CPU_LOG_INT
, "Taking exception %d [%s]\n", idx
, exc
);
7555 static bool v7m_read_half_insn(ARMCPU
*cpu
, ARMMMUIdx mmu_idx
,
7556 uint32_t addr
, uint16_t *insn
)
7558 /* Load a 16-bit portion of a v7M instruction, returning true on success,
7559 * or false on failure (in which case we will have pended the appropriate
7561 * We need to do the instruction fetch's MPU and SAU checks
7562 * like this because there is no MMU index that would allow
7563 * doing the load with a single function call. Instead we must
7564 * first check that the security attributes permit the load
7565 * and that they don't mismatch on the two halves of the instruction,
7566 * and then we do the load as a secure load (ie using the security
7567 * attributes of the address, not the CPU, as architecturally required).
7569 CPUState
*cs
= CPU(cpu
);
7570 CPUARMState
*env
= &cpu
->env
;
7571 V8M_SAttributes sattrs
= {};
7572 MemTxAttrs attrs
= {};
7573 ARMMMUFaultInfo fi
= {};
7575 target_ulong page_size
;
7579 v8m_security_lookup(env
, addr
, MMU_INST_FETCH
, mmu_idx
, &sattrs
);
7580 if (!sattrs
.nsc
|| sattrs
.ns
) {
7581 /* This must be the second half of the insn, and it straddles a
7582 * region boundary with the second half not being S&NSC.
7584 env
->v7m
.sfsr
|= R_V7M_SFSR_INVEP_MASK
;
7585 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_SECURE
, false);
7586 qemu_log_mask(CPU_LOG_INT
,
7587 "...really SecureFault with SFSR.INVEP\n");
7590 if (get_phys_addr(env
, addr
, MMU_INST_FETCH
, mmu_idx
,
7591 &physaddr
, &attrs
, &prot
, &page_size
, &fi
, NULL
)) {
7592 /* the MPU lookup failed */
7593 env
->v7m
.cfsr
[env
->v7m
.secure
] |= R_V7M_CFSR_IACCVIOL_MASK
;
7594 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_MEM
, env
->v7m
.secure
);
7595 qemu_log_mask(CPU_LOG_INT
, "...really MemManage with CFSR.IACCVIOL\n");
7598 *insn
= address_space_lduw_le(arm_addressspace(cs
, attrs
), physaddr
,
7600 if (txres
!= MEMTX_OK
) {
7601 env
->v7m
.cfsr
[M_REG_NS
] |= R_V7M_CFSR_IBUSERR_MASK
;
7602 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_BUS
, false);
7603 qemu_log_mask(CPU_LOG_INT
, "...really BusFault with CFSR.IBUSERR\n");
7609 static bool v7m_handle_execute_nsc(ARMCPU
*cpu
)
7611 /* Check whether this attempt to execute code in a Secure & NS-Callable
7612 * memory region is for an SG instruction; if so, then emulate the
7613 * effect of the SG instruction and return true. Otherwise pend
7614 * the correct kind of exception and return false.
7616 CPUARMState
*env
= &cpu
->env
;
7620 /* We should never get here unless get_phys_addr_pmsav8() caused
7621 * an exception for NS executing in S&NSC memory.
7623 assert(!env
->v7m
.secure
);
7624 assert(arm_feature(env
, ARM_FEATURE_M_SECURITY
));
7626 /* We want to do the MPU lookup as secure; work out what mmu_idx that is */
7627 mmu_idx
= arm_v7m_mmu_idx_for_secstate(env
, true);
7629 if (!v7m_read_half_insn(cpu
, mmu_idx
, env
->regs
[15], &insn
)) {
7637 if (insn
!= 0xe97f) {
7638 /* Not an SG instruction first half (we choose the IMPDEF
7639 * early-SG-check option).
7644 if (!v7m_read_half_insn(cpu
, mmu_idx
, env
->regs
[15] + 2, &insn
)) {
7648 if (insn
!= 0xe97f) {
7649 /* Not an SG instruction second half (yes, both halves of the SG
7650 * insn have the same hex value)
7655 /* OK, we have confirmed that we really have an SG instruction.
7656 * We know we're NS in S memory so don't need to repeat those checks.
7658 qemu_log_mask(CPU_LOG_INT
, "...really an SG instruction at 0x%08" PRIx32
7659 ", executing it\n", env
->regs
[15]);
7660 env
->regs
[14] &= ~1;
7661 switch_v7m_security_state(env
, true);
7662 xpsr_write(env
, 0, XPSR_IT
);
7667 env
->v7m
.sfsr
|= R_V7M_SFSR_INVEP_MASK
;
7668 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_SECURE
, false);
7669 qemu_log_mask(CPU_LOG_INT
,
7670 "...really SecureFault with SFSR.INVEP\n");
7674 void arm_v7m_cpu_do_interrupt(CPUState
*cs
)
7676 ARMCPU
*cpu
= ARM_CPU(cs
);
7677 CPUARMState
*env
= &cpu
->env
;
7679 bool ignore_stackfaults
;
7681 arm_log_exception(cs
->exception_index
);
7683 /* For exceptions we just mark as pending on the NVIC, and let that
7685 switch (cs
->exception_index
) {
7687 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_USAGE
, env
->v7m
.secure
);
7688 env
->v7m
.cfsr
[env
->v7m
.secure
] |= R_V7M_CFSR_UNDEFINSTR_MASK
;
7691 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_USAGE
, env
->v7m
.secure
);
7692 env
->v7m
.cfsr
[env
->v7m
.secure
] |= R_V7M_CFSR_NOCP_MASK
;
7695 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_USAGE
, env
->v7m
.secure
);
7696 env
->v7m
.cfsr
[env
->v7m
.secure
] |= R_V7M_CFSR_INVSTATE_MASK
;
7699 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_USAGE
, env
->v7m
.secure
);
7700 env
->v7m
.cfsr
[env
->v7m
.secure
] |= R_V7M_CFSR_STKOF_MASK
;
7703 /* The PC already points to the next instruction. */
7704 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_SVC
, env
->v7m
.secure
);
7706 case EXCP_PREFETCH_ABORT
:
7707 case EXCP_DATA_ABORT
:
7708 /* Note that for M profile we don't have a guest facing FSR, but
7709 * the env->exception.fsr will be populated by the code that
7710 * raises the fault, in the A profile short-descriptor format.
7712 switch (env
->exception
.fsr
& 0xf) {
7713 case M_FAKE_FSR_NSC_EXEC
:
7714 /* Exception generated when we try to execute code at an address
7715 * which is marked as Secure & Non-Secure Callable and the CPU
7716 * is in the Non-Secure state. The only instruction which can
7717 * be executed like this is SG (and that only if both halves of
7718 * the SG instruction have the same security attributes.)
7719 * Everything else must generate an INVEP SecureFault, so we
7720 * emulate the SG instruction here.
7722 if (v7m_handle_execute_nsc(cpu
)) {
7726 case M_FAKE_FSR_SFAULT
:
7727 /* Various flavours of SecureFault for attempts to execute or
7728 * access data in the wrong security state.
7730 switch (cs
->exception_index
) {
7731 case EXCP_PREFETCH_ABORT
:
7732 if (env
->v7m
.secure
) {
7733 env
->v7m
.sfsr
|= R_V7M_SFSR_INVTRAN_MASK
;
7734 qemu_log_mask(CPU_LOG_INT
,
7735 "...really SecureFault with SFSR.INVTRAN\n");
7737 env
->v7m
.sfsr
|= R_V7M_SFSR_INVEP_MASK
;
7738 qemu_log_mask(CPU_LOG_INT
,
7739 "...really SecureFault with SFSR.INVEP\n");
7742 case EXCP_DATA_ABORT
:
7743 /* This must be an NS access to S memory */
7744 env
->v7m
.sfsr
|= R_V7M_SFSR_AUVIOL_MASK
;
7745 qemu_log_mask(CPU_LOG_INT
,
7746 "...really SecureFault with SFSR.AUVIOL\n");
7749 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_SECURE
, false);
7751 case 0x8: /* External Abort */
7752 switch (cs
->exception_index
) {
7753 case EXCP_PREFETCH_ABORT
:
7754 env
->v7m
.cfsr
[M_REG_NS
] |= R_V7M_CFSR_IBUSERR_MASK
;
7755 qemu_log_mask(CPU_LOG_INT
, "...with CFSR.IBUSERR\n");
7757 case EXCP_DATA_ABORT
:
7758 env
->v7m
.cfsr
[M_REG_NS
] |=
7759 (R_V7M_CFSR_PRECISERR_MASK
| R_V7M_CFSR_BFARVALID_MASK
);
7760 env
->v7m
.bfar
= env
->exception
.vaddress
;
7761 qemu_log_mask(CPU_LOG_INT
,
7762 "...with CFSR.PRECISERR and BFAR 0x%x\n",
7766 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_BUS
, false);
7769 /* All other FSR values are either MPU faults or "can't happen
7770 * for M profile" cases.
7772 switch (cs
->exception_index
) {
7773 case EXCP_PREFETCH_ABORT
:
7774 env
->v7m
.cfsr
[env
->v7m
.secure
] |= R_V7M_CFSR_IACCVIOL_MASK
;
7775 qemu_log_mask(CPU_LOG_INT
, "...with CFSR.IACCVIOL\n");
7777 case EXCP_DATA_ABORT
:
7778 env
->v7m
.cfsr
[env
->v7m
.secure
] |=
7779 (R_V7M_CFSR_DACCVIOL_MASK
| R_V7M_CFSR_MMARVALID_MASK
);
7780 env
->v7m
.mmfar
[env
->v7m
.secure
] = env
->exception
.vaddress
;
7781 qemu_log_mask(CPU_LOG_INT
,
7782 "...with CFSR.DACCVIOL and MMFAR 0x%x\n",
7783 env
->v7m
.mmfar
[env
->v7m
.secure
]);
7786 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_MEM
,
7792 if (semihosting_enabled()) {
7794 nr
= arm_lduw_code(env
, env
->regs
[15], arm_sctlr_b(env
)) & 0xff;
7797 qemu_log_mask(CPU_LOG_INT
,
7798 "...handling as semihosting call 0x%x\n",
7800 env
->regs
[0] = do_arm_semihosting(env
);
7804 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_DEBUG
, false);
7808 case EXCP_EXCEPTION_EXIT
:
7809 if (env
->regs
[15] < EXC_RETURN_MIN_MAGIC
) {
7810 /* Must be v8M security extension function return */
7811 assert(env
->regs
[15] >= FNC_RETURN_MIN_MAGIC
);
7812 assert(arm_feature(env
, ARM_FEATURE_M_SECURITY
));
7813 if (do_v7m_function_return(cpu
)) {
7817 do_v7m_exception_exit(cpu
);
7822 cpu_abort(cs
, "Unhandled exception 0x%x\n", cs
->exception_index
);
7823 return; /* Never happens. Keep compiler happy. */
7826 if (arm_feature(env
, ARM_FEATURE_V8
)) {
7827 lr
= R_V7M_EXCRET_RES1_MASK
|
7828 R_V7M_EXCRET_DCRS_MASK
|
7829 R_V7M_EXCRET_FTYPE_MASK
;
7830 /* The S bit indicates whether we should return to Secure
7831 * or NonSecure (ie our current state).
7832 * The ES bit indicates whether we're taking this exception
7833 * to Secure or NonSecure (ie our target state). We set it
7834 * later, in v7m_exception_taken().
7835 * The SPSEL bit is also set in v7m_exception_taken() for v8M.
7836 * This corresponds to the ARM ARM pseudocode for v8M setting
7837 * some LR bits in PushStack() and some in ExceptionTaken();
7838 * the distinction matters for the tailchain cases where we
7839 * can take an exception without pushing the stack.
7841 if (env
->v7m
.secure
) {
7842 lr
|= R_V7M_EXCRET_S_MASK
;
7845 lr
= R_V7M_EXCRET_RES1_MASK
|
7846 R_V7M_EXCRET_S_MASK
|
7847 R_V7M_EXCRET_DCRS_MASK
|
7848 R_V7M_EXCRET_FTYPE_MASK
|
7849 R_V7M_EXCRET_ES_MASK
;
7850 if (env
->v7m
.control
[M_REG_NS
] & R_V7M_CONTROL_SPSEL_MASK
) {
7851 lr
|= R_V7M_EXCRET_SPSEL_MASK
;
7854 if (!arm_v7m_is_handler_mode(env
)) {
7855 lr
|= R_V7M_EXCRET_MODE_MASK
;
7858 ignore_stackfaults
= v7m_push_stack(cpu
);
7859 v7m_exception_taken(cpu
, lr
, false, ignore_stackfaults
);
7862 /* Function used to synchronize QEMU's AArch64 register set with AArch32
7863 * register set. This is necessary when switching between AArch32 and AArch64
7866 void aarch64_sync_32_to_64(CPUARMState
*env
)
7869 uint32_t mode
= env
->uncached_cpsr
& CPSR_M
;
7871 /* We can blanket copy R[0:7] to X[0:7] */
7872 for (i
= 0; i
< 8; i
++) {
7873 env
->xregs
[i
] = env
->regs
[i
];
7876 /* Unless we are in FIQ mode, x8-x12 come from the user registers r8-r12.
7877 * Otherwise, they come from the banked user regs.
7879 if (mode
== ARM_CPU_MODE_FIQ
) {
7880 for (i
= 8; i
< 13; i
++) {
7881 env
->xregs
[i
] = env
->usr_regs
[i
- 8];
7884 for (i
= 8; i
< 13; i
++) {
7885 env
->xregs
[i
] = env
->regs
[i
];
7889 /* Registers x13-x23 are the various mode SP and FP registers. Registers
7890 * r13 and r14 are only copied if we are in that mode, otherwise we copy
7891 * from the mode banked register.
7893 if (mode
== ARM_CPU_MODE_USR
|| mode
== ARM_CPU_MODE_SYS
) {
7894 env
->xregs
[13] = env
->regs
[13];
7895 env
->xregs
[14] = env
->regs
[14];
7897 env
->xregs
[13] = env
->banked_r13
[bank_number(ARM_CPU_MODE_USR
)];
7898 /* HYP is an exception in that it is copied from r14 */
7899 if (mode
== ARM_CPU_MODE_HYP
) {
7900 env
->xregs
[14] = env
->regs
[14];
7902 env
->xregs
[14] = env
->banked_r14
[bank_number(ARM_CPU_MODE_USR
)];
7906 if (mode
== ARM_CPU_MODE_HYP
) {
7907 env
->xregs
[15] = env
->regs
[13];
7909 env
->xregs
[15] = env
->banked_r13
[bank_number(ARM_CPU_MODE_HYP
)];
7912 if (mode
== ARM_CPU_MODE_IRQ
) {
7913 env
->xregs
[16] = env
->regs
[14];
7914 env
->xregs
[17] = env
->regs
[13];
7916 env
->xregs
[16] = env
->banked_r14
[bank_number(ARM_CPU_MODE_IRQ
)];
7917 env
->xregs
[17] = env
->banked_r13
[bank_number(ARM_CPU_MODE_IRQ
)];
7920 if (mode
== ARM_CPU_MODE_SVC
) {
7921 env
->xregs
[18] = env
->regs
[14];
7922 env
->xregs
[19] = env
->regs
[13];
7924 env
->xregs
[18] = env
->banked_r14
[bank_number(ARM_CPU_MODE_SVC
)];
7925 env
->xregs
[19] = env
->banked_r13
[bank_number(ARM_CPU_MODE_SVC
)];
7928 if (mode
== ARM_CPU_MODE_ABT
) {
7929 env
->xregs
[20] = env
->regs
[14];
7930 env
->xregs
[21] = env
->regs
[13];
7932 env
->xregs
[20] = env
->banked_r14
[bank_number(ARM_CPU_MODE_ABT
)];
7933 env
->xregs
[21] = env
->banked_r13
[bank_number(ARM_CPU_MODE_ABT
)];
7936 if (mode
== ARM_CPU_MODE_UND
) {
7937 env
->xregs
[22] = env
->regs
[14];
7938 env
->xregs
[23] = env
->regs
[13];
7940 env
->xregs
[22] = env
->banked_r14
[bank_number(ARM_CPU_MODE_UND
)];
7941 env
->xregs
[23] = env
->banked_r13
[bank_number(ARM_CPU_MODE_UND
)];
7944 /* Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in FIQ
7945 * mode, then we can copy from r8-r14. Otherwise, we copy from the
7946 * FIQ bank for r8-r14.
7948 if (mode
== ARM_CPU_MODE_FIQ
) {
7949 for (i
= 24; i
< 31; i
++) {
7950 env
->xregs
[i
] = env
->regs
[i
- 16]; /* X[24:30] <- R[8:14] */
7953 for (i
= 24; i
< 29; i
++) {
7954 env
->xregs
[i
] = env
->fiq_regs
[i
- 24];
7956 env
->xregs
[29] = env
->banked_r13
[bank_number(ARM_CPU_MODE_FIQ
)];
7957 env
->xregs
[30] = env
->banked_r14
[bank_number(ARM_CPU_MODE_FIQ
)];
7960 env
->pc
= env
->regs
[15];
7963 /* Function used to synchronize QEMU's AArch32 register set with AArch64
7964 * register set. This is necessary when switching between AArch32 and AArch64
7967 void aarch64_sync_64_to_32(CPUARMState
*env
)
7970 uint32_t mode
= env
->uncached_cpsr
& CPSR_M
;
7972 /* We can blanket copy X[0:7] to R[0:7] */
7973 for (i
= 0; i
< 8; i
++) {
7974 env
->regs
[i
] = env
->xregs
[i
];
7977 /* Unless we are in FIQ mode, r8-r12 come from the user registers x8-x12.
7978 * Otherwise, we copy x8-x12 into the banked user regs.
7980 if (mode
== ARM_CPU_MODE_FIQ
) {
7981 for (i
= 8; i
< 13; i
++) {
7982 env
->usr_regs
[i
- 8] = env
->xregs
[i
];
7985 for (i
= 8; i
< 13; i
++) {
7986 env
->regs
[i
] = env
->xregs
[i
];
7990 /* Registers r13 & r14 depend on the current mode.
7991 * If we are in a given mode, we copy the corresponding x registers to r13
7992 * and r14. Otherwise, we copy the x register to the banked r13 and r14
7995 if (mode
== ARM_CPU_MODE_USR
|| mode
== ARM_CPU_MODE_SYS
) {
7996 env
->regs
[13] = env
->xregs
[13];
7997 env
->regs
[14] = env
->xregs
[14];
7999 env
->banked_r13
[bank_number(ARM_CPU_MODE_USR
)] = env
->xregs
[13];
8001 /* HYP is an exception in that it does not have its own banked r14 but
8002 * shares the USR r14
8004 if (mode
== ARM_CPU_MODE_HYP
) {
8005 env
->regs
[14] = env
->xregs
[14];
8007 env
->banked_r14
[bank_number(ARM_CPU_MODE_USR
)] = env
->xregs
[14];
8011 if (mode
== ARM_CPU_MODE_HYP
) {
8012 env
->regs
[13] = env
->xregs
[15];
8014 env
->banked_r13
[bank_number(ARM_CPU_MODE_HYP
)] = env
->xregs
[15];
8017 if (mode
== ARM_CPU_MODE_IRQ
) {
8018 env
->regs
[14] = env
->xregs
[16];
8019 env
->regs
[13] = env
->xregs
[17];
8021 env
->banked_r14
[bank_number(ARM_CPU_MODE_IRQ
)] = env
->xregs
[16];
8022 env
->banked_r13
[bank_number(ARM_CPU_MODE_IRQ
)] = env
->xregs
[17];
8025 if (mode
== ARM_CPU_MODE_SVC
) {
8026 env
->regs
[14] = env
->xregs
[18];
8027 env
->regs
[13] = env
->xregs
[19];
8029 env
->banked_r14
[bank_number(ARM_CPU_MODE_SVC
)] = env
->xregs
[18];
8030 env
->banked_r13
[bank_number(ARM_CPU_MODE_SVC
)] = env
->xregs
[19];
8033 if (mode
== ARM_CPU_MODE_ABT
) {
8034 env
->regs
[14] = env
->xregs
[20];
8035 env
->regs
[13] = env
->xregs
[21];
8037 env
->banked_r14
[bank_number(ARM_CPU_MODE_ABT
)] = env
->xregs
[20];
8038 env
->banked_r13
[bank_number(ARM_CPU_MODE_ABT
)] = env
->xregs
[21];
8041 if (mode
== ARM_CPU_MODE_UND
) {
8042 env
->regs
[14] = env
->xregs
[22];
8043 env
->regs
[13] = env
->xregs
[23];
8045 env
->banked_r14
[bank_number(ARM_CPU_MODE_UND
)] = env
->xregs
[22];
8046 env
->banked_r13
[bank_number(ARM_CPU_MODE_UND
)] = env
->xregs
[23];
8049 /* Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in FIQ
8050 * mode, then we can copy to r8-r14. Otherwise, we copy to the
8051 * FIQ bank for r8-r14.
8053 if (mode
== ARM_CPU_MODE_FIQ
) {
8054 for (i
= 24; i
< 31; i
++) {
8055 env
->regs
[i
- 16] = env
->xregs
[i
]; /* X[24:30] -> R[8:14] */
8058 for (i
= 24; i
< 29; i
++) {
8059 env
->fiq_regs
[i
- 24] = env
->xregs
[i
];
8061 env
->banked_r13
[bank_number(ARM_CPU_MODE_FIQ
)] = env
->xregs
[29];
8062 env
->banked_r14
[bank_number(ARM_CPU_MODE_FIQ
)] = env
->xregs
[30];
8065 env
->regs
[15] = env
->pc
;
8068 static void take_aarch32_exception(CPUARMState
*env
, int new_mode
,
8069 uint32_t mask
, uint32_t offset
,
8072 /* Change the CPU state so as to actually take the exception. */
8073 switch_mode(env
, new_mode
);
8075 * For exceptions taken to AArch32 we must clear the SS bit in both
8076 * PSTATE and in the old-state value we save to SPSR_<mode>, so zero it now.
8078 env
->uncached_cpsr
&= ~PSTATE_SS
;
8079 env
->spsr
= cpsr_read(env
);
8080 /* Clear IT bits. */
8081 env
->condexec_bits
= 0;
8082 /* Switch to the new mode, and to the correct instruction set. */
8083 env
->uncached_cpsr
= (env
->uncached_cpsr
& ~CPSR_M
) | new_mode
;
8084 /* Set new mode endianness */
8085 env
->uncached_cpsr
&= ~CPSR_E
;
8086 if (env
->cp15
.sctlr_el
[arm_current_el(env
)] & SCTLR_EE
) {
8087 env
->uncached_cpsr
|= CPSR_E
;
8089 /* J and IL must always be cleared for exception entry */
8090 env
->uncached_cpsr
&= ~(CPSR_IL
| CPSR_J
);
8093 if (new_mode
== ARM_CPU_MODE_HYP
) {
8094 env
->thumb
= (env
->cp15
.sctlr_el
[2] & SCTLR_TE
) != 0;
8095 env
->elr_el
[2] = env
->regs
[15];
8098 * this is a lie, as there was no c1_sys on V4T/V5, but who cares
8099 * and we should just guard the thumb mode on V4
8101 if (arm_feature(env
, ARM_FEATURE_V4T
)) {
8103 (A32_BANKED_CURRENT_REG_GET(env
, sctlr
) & SCTLR_TE
) != 0;
8105 env
->regs
[14] = env
->regs
[15] + offset
;
8107 env
->regs
[15] = newpc
;
8110 static void arm_cpu_do_interrupt_aarch32_hyp(CPUState
*cs
)
8113 * Handle exception entry to Hyp mode; this is sufficiently
8114 * different to entry to other AArch32 modes that we handle it
8117 * The vector table entry used is always the 0x14 Hyp mode entry point,
8118 * unless this is an UNDEF/HVC/abort taken from Hyp to Hyp.
8119 * The offset applied to the preferred return address is always zero
8120 * (see DDI0487C.a section G1.12.3).
8121 * PSTATE A/I/F masks are set based only on the SCR.EA/IRQ/FIQ values.
8123 uint32_t addr
, mask
;
8124 ARMCPU
*cpu
= ARM_CPU(cs
);
8125 CPUARMState
*env
= &cpu
->env
;
8127 switch (cs
->exception_index
) {
8135 /* Fall through to prefetch abort. */
8136 case EXCP_PREFETCH_ABORT
:
8137 env
->cp15
.ifar_s
= env
->exception
.vaddress
;
8138 qemu_log_mask(CPU_LOG_INT
, "...with HIFAR 0x%x\n",
8139 (uint32_t)env
->exception
.vaddress
);
8142 case EXCP_DATA_ABORT
:
8143 env
->cp15
.dfar_s
= env
->exception
.vaddress
;
8144 qemu_log_mask(CPU_LOG_INT
, "...with HDFAR 0x%x\n",
8145 (uint32_t)env
->exception
.vaddress
);
8160 cpu_abort(cs
, "Unhandled exception 0x%x\n", cs
->exception_index
);
8163 if (cs
->exception_index
!= EXCP_IRQ
&& cs
->exception_index
!= EXCP_FIQ
) {
8164 env
->cp15
.esr_el
[2] = env
->exception
.syndrome
;
8167 if (arm_current_el(env
) != 2 && addr
< 0x14) {
8172 if (!(env
->cp15
.scr_el3
& SCR_EA
)) {
8175 if (!(env
->cp15
.scr_el3
& SCR_IRQ
)) {
8178 if (!(env
->cp15
.scr_el3
& SCR_FIQ
)) {
8182 addr
+= env
->cp15
.hvbar
;
8184 take_aarch32_exception(env
, ARM_CPU_MODE_HYP
, mask
, 0, addr
);
8187 static void arm_cpu_do_interrupt_aarch32(CPUState
*cs
)
8189 ARMCPU
*cpu
= ARM_CPU(cs
);
8190 CPUARMState
*env
= &cpu
->env
;
8197 /* If this is a debug exception we must update the DBGDSCR.MOE bits */
8198 switch (env
->exception
.syndrome
>> ARM_EL_EC_SHIFT
) {
8200 case EC_BREAKPOINT_SAME_EL
:
8204 case EC_WATCHPOINT_SAME_EL
:
8210 case EC_VECTORCATCH
:
8219 env
->cp15
.mdscr_el1
= deposit64(env
->cp15
.mdscr_el1
, 2, 4, moe
);
8222 if (env
->exception
.target_el
== 2) {
8223 arm_cpu_do_interrupt_aarch32_hyp(cs
);
8227 /* TODO: Vectored interrupt controller. */
8228 switch (cs
->exception_index
) {
8230 new_mode
= ARM_CPU_MODE_UND
;
8239 new_mode
= ARM_CPU_MODE_SVC
;
8242 /* The PC already points to the next instruction. */
8246 /* Fall through to prefetch abort. */
8247 case EXCP_PREFETCH_ABORT
:
8248 A32_BANKED_CURRENT_REG_SET(env
, ifsr
, env
->exception
.fsr
);
8249 A32_BANKED_CURRENT_REG_SET(env
, ifar
, env
->exception
.vaddress
);
8250 qemu_log_mask(CPU_LOG_INT
, "...with IFSR 0x%x IFAR 0x%x\n",
8251 env
->exception
.fsr
, (uint32_t)env
->exception
.vaddress
);
8252 new_mode
= ARM_CPU_MODE_ABT
;
8254 mask
= CPSR_A
| CPSR_I
;
8257 case EXCP_DATA_ABORT
:
8258 A32_BANKED_CURRENT_REG_SET(env
, dfsr
, env
->exception
.fsr
);
8259 A32_BANKED_CURRENT_REG_SET(env
, dfar
, env
->exception
.vaddress
);
8260 qemu_log_mask(CPU_LOG_INT
, "...with DFSR 0x%x DFAR 0x%x\n",
8262 (uint32_t)env
->exception
.vaddress
);
8263 new_mode
= ARM_CPU_MODE_ABT
;
8265 mask
= CPSR_A
| CPSR_I
;
8269 new_mode
= ARM_CPU_MODE_IRQ
;
8271 /* Disable IRQ and imprecise data aborts. */
8272 mask
= CPSR_A
| CPSR_I
;
8274 if (env
->cp15
.scr_el3
& SCR_IRQ
) {
8275 /* IRQ routed to monitor mode */
8276 new_mode
= ARM_CPU_MODE_MON
;
8281 new_mode
= ARM_CPU_MODE_FIQ
;
8283 /* Disable FIQ, IRQ and imprecise data aborts. */
8284 mask
= CPSR_A
| CPSR_I
| CPSR_F
;
8285 if (env
->cp15
.scr_el3
& SCR_FIQ
) {
8286 /* FIQ routed to monitor mode */
8287 new_mode
= ARM_CPU_MODE_MON
;
8292 new_mode
= ARM_CPU_MODE_IRQ
;
8294 /* Disable IRQ and imprecise data aborts. */
8295 mask
= CPSR_A
| CPSR_I
;
8299 new_mode
= ARM_CPU_MODE_FIQ
;
8301 /* Disable FIQ, IRQ and imprecise data aborts. */
8302 mask
= CPSR_A
| CPSR_I
| CPSR_F
;
8306 new_mode
= ARM_CPU_MODE_MON
;
8308 mask
= CPSR_A
| CPSR_I
| CPSR_F
;
8312 cpu_abort(cs
, "Unhandled exception 0x%x\n", cs
->exception_index
);
8313 return; /* Never happens. Keep compiler happy. */
8316 if (new_mode
== ARM_CPU_MODE_MON
) {
8317 addr
+= env
->cp15
.mvbar
;
8318 } else if (A32_BANKED_CURRENT_REG_GET(env
, sctlr
) & SCTLR_V
) {
8319 /* High vectors. When enabled, base address cannot be remapped. */
8322 /* ARM v7 architectures provide a vector base address register to remap
8323 * the interrupt vector table.
8324 * This register is only followed in non-monitor mode, and is banked.
8325 * Note: only bits 31:5 are valid.
8327 addr
+= A32_BANKED_CURRENT_REG_GET(env
, vbar
);
8330 if ((env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_MON
) {
8331 env
->cp15
.scr_el3
&= ~SCR_NS
;
8334 take_aarch32_exception(env
, new_mode
, mask
, offset
, addr
);
8337 /* Handle exception entry to a target EL which is using AArch64 */
8338 static void arm_cpu_do_interrupt_aarch64(CPUState
*cs
)
8340 ARMCPU
*cpu
= ARM_CPU(cs
);
8341 CPUARMState
*env
= &cpu
->env
;
8342 unsigned int new_el
= env
->exception
.target_el
;
8343 target_ulong addr
= env
->cp15
.vbar_el
[new_el
];
8344 unsigned int new_mode
= aarch64_pstate_mode(new_el
, true);
8345 unsigned int cur_el
= arm_current_el(env
);
8347 aarch64_sve_change_el(env
, cur_el
, new_el
);
8349 if (cur_el
< new_el
) {
8350 /* Entry vector offset depends on whether the implemented EL
8351 * immediately lower than the target level is using AArch32 or AArch64
8357 is_aa64
= (env
->cp15
.scr_el3
& SCR_RW
) != 0;
8360 is_aa64
= (env
->cp15
.hcr_el2
& HCR_RW
) != 0;
8363 is_aa64
= is_a64(env
);
8366 g_assert_not_reached();
8374 } else if (pstate_read(env
) & PSTATE_SP
) {
8378 switch (cs
->exception_index
) {
8379 case EXCP_PREFETCH_ABORT
:
8380 case EXCP_DATA_ABORT
:
8381 env
->cp15
.far_el
[new_el
] = env
->exception
.vaddress
;
8382 qemu_log_mask(CPU_LOG_INT
, "...with FAR 0x%" PRIx64
"\n",
8383 env
->cp15
.far_el
[new_el
]);
8391 env
->cp15
.esr_el
[new_el
] = env
->exception
.syndrome
;
8402 qemu_log_mask(CPU_LOG_INT
,
8403 "...handling as semihosting call 0x%" PRIx64
"\n",
8405 env
->xregs
[0] = do_arm_semihosting(env
);
8408 cpu_abort(cs
, "Unhandled exception 0x%x\n", cs
->exception_index
);
8412 env
->banked_spsr
[aarch64_banked_spsr_index(new_el
)] = pstate_read(env
);
8413 aarch64_save_sp(env
, arm_current_el(env
));
8414 env
->elr_el
[new_el
] = env
->pc
;
8416 env
->banked_spsr
[aarch64_banked_spsr_index(new_el
)] = cpsr_read(env
);
8417 env
->elr_el
[new_el
] = env
->regs
[15];
8419 aarch64_sync_32_to_64(env
);
8421 env
->condexec_bits
= 0;
8423 qemu_log_mask(CPU_LOG_INT
, "...with ELR 0x%" PRIx64
"\n",
8424 env
->elr_el
[new_el
]);
8426 pstate_write(env
, PSTATE_DAIF
| new_mode
);
8428 aarch64_restore_sp(env
, new_el
);
8432 qemu_log_mask(CPU_LOG_INT
, "...to EL%d PC 0x%" PRIx64
" PSTATE 0x%x\n",
8433 new_el
, env
->pc
, pstate_read(env
));
8436 static inline bool check_for_semihosting(CPUState
*cs
)
8438 /* Check whether this exception is a semihosting call; if so
8439 * then handle it and return true; otherwise return false.
8441 ARMCPU
*cpu
= ARM_CPU(cs
);
8442 CPUARMState
*env
= &cpu
->env
;
8445 if (cs
->exception_index
== EXCP_SEMIHOST
) {
8446 /* This is always the 64-bit semihosting exception.
8447 * The "is this usermode" and "is semihosting enabled"
8448 * checks have been done at translate time.
8450 qemu_log_mask(CPU_LOG_INT
,
8451 "...handling as semihosting call 0x%" PRIx64
"\n",
8453 env
->xregs
[0] = do_arm_semihosting(env
);
8460 /* Only intercept calls from privileged modes, to provide some
8461 * semblance of security.
8463 if (cs
->exception_index
!= EXCP_SEMIHOST
&&
8464 (!semihosting_enabled() ||
8465 ((env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_USR
))) {
8469 switch (cs
->exception_index
) {
8471 /* This is always a semihosting call; the "is this usermode"
8472 * and "is semihosting enabled" checks have been done at
8477 /* Check for semihosting interrupt. */
8479 imm
= arm_lduw_code(env
, env
->regs
[15] - 2, arm_sctlr_b(env
))
8485 imm
= arm_ldl_code(env
, env
->regs
[15] - 4, arm_sctlr_b(env
))
8487 if (imm
== 0x123456) {
8493 /* See if this is a semihosting syscall. */
8495 imm
= arm_lduw_code(env
, env
->regs
[15], arm_sctlr_b(env
))
8507 qemu_log_mask(CPU_LOG_INT
,
8508 "...handling as semihosting call 0x%x\n",
8510 env
->regs
[0] = do_arm_semihosting(env
);
8515 /* Handle a CPU exception for A and R profile CPUs.
8516 * Do any appropriate logging, handle PSCI calls, and then hand off
8517 * to the AArch64-entry or AArch32-entry function depending on the
8518 * target exception level's register width.
8520 void arm_cpu_do_interrupt(CPUState
*cs
)
8522 ARMCPU
*cpu
= ARM_CPU(cs
);
8523 CPUARMState
*env
= &cpu
->env
;
8524 unsigned int new_el
= env
->exception
.target_el
;
8526 assert(!arm_feature(env
, ARM_FEATURE_M
));
8528 arm_log_exception(cs
->exception_index
);
8529 qemu_log_mask(CPU_LOG_INT
, "...from EL%d to EL%d\n", arm_current_el(env
),
8531 if (qemu_loglevel_mask(CPU_LOG_INT
)
8532 && !excp_is_internal(cs
->exception_index
)) {
8533 qemu_log_mask(CPU_LOG_INT
, "...with ESR 0x%x/0x%" PRIx32
"\n",
8534 env
->exception
.syndrome
>> ARM_EL_EC_SHIFT
,
8535 env
->exception
.syndrome
);
8538 if (arm_is_psci_call(cpu
, cs
->exception_index
)) {
8539 arm_handle_psci_call(cpu
);
8540 qemu_log_mask(CPU_LOG_INT
, "...handled as PSCI call\n");
8544 /* Semihosting semantics depend on the register width of the
8545 * code that caused the exception, not the target exception level,
8546 * so must be handled here.
8548 if (check_for_semihosting(cs
)) {
8552 /* Hooks may change global state so BQL should be held, also the
8553 * BQL needs to be held for any modification of
8554 * cs->interrupt_request.
8556 g_assert(qemu_mutex_iothread_locked());
8558 arm_call_pre_el_change_hook(cpu
);
8560 assert(!excp_is_internal(cs
->exception_index
));
8561 if (arm_el_is_aa64(env
, new_el
)) {
8562 arm_cpu_do_interrupt_aarch64(cs
);
8564 arm_cpu_do_interrupt_aarch32(cs
);
8567 arm_call_el_change_hook(cpu
);
8569 if (!kvm_enabled()) {
8570 cs
->interrupt_request
|= CPU_INTERRUPT_EXITTB
;
8574 /* Return the exception level which controls this address translation regime */
8575 static inline uint32_t regime_el(CPUARMState
*env
, ARMMMUIdx mmu_idx
)
8578 case ARMMMUIdx_S2NS
:
8579 case ARMMMUIdx_S1E2
:
8581 case ARMMMUIdx_S1E3
:
8583 case ARMMMUIdx_S1SE0
:
8584 return arm_el_is_aa64(env
, 3) ? 1 : 3;
8585 case ARMMMUIdx_S1SE1
:
8586 case ARMMMUIdx_S1NSE0
:
8587 case ARMMMUIdx_S1NSE1
:
8588 case ARMMMUIdx_MPrivNegPri
:
8589 case ARMMMUIdx_MUserNegPri
:
8590 case ARMMMUIdx_MPriv
:
8591 case ARMMMUIdx_MUser
:
8592 case ARMMMUIdx_MSPrivNegPri
:
8593 case ARMMMUIdx_MSUserNegPri
:
8594 case ARMMMUIdx_MSPriv
:
8595 case ARMMMUIdx_MSUser
:
8598 g_assert_not_reached();
8602 /* Return the SCTLR value which controls this address translation regime */
8603 static inline uint32_t regime_sctlr(CPUARMState
*env
, ARMMMUIdx mmu_idx
)
8605 return env
->cp15
.sctlr_el
[regime_el(env
, mmu_idx
)];
8608 /* Return true if the specified stage of address translation is disabled */
8609 static inline bool regime_translation_disabled(CPUARMState
*env
,
8612 if (arm_feature(env
, ARM_FEATURE_M
)) {
8613 switch (env
->v7m
.mpu_ctrl
[regime_is_secure(env
, mmu_idx
)] &
8614 (R_V7M_MPU_CTRL_ENABLE_MASK
| R_V7M_MPU_CTRL_HFNMIENA_MASK
)) {
8615 case R_V7M_MPU_CTRL_ENABLE_MASK
:
8616 /* Enabled, but not for HardFault and NMI */
8617 return mmu_idx
& ARM_MMU_IDX_M_NEGPRI
;
8618 case R_V7M_MPU_CTRL_ENABLE_MASK
| R_V7M_MPU_CTRL_HFNMIENA_MASK
:
8619 /* Enabled for all cases */
8623 /* HFNMIENA set and ENABLE clear is UNPREDICTABLE, but
8624 * we warned about that in armv7m_nvic.c when the guest set it.
8630 if (mmu_idx
== ARMMMUIdx_S2NS
) {
8631 return (env
->cp15
.hcr_el2
& HCR_VM
) == 0;
8634 if (env
->cp15
.hcr_el2
& HCR_TGE
) {
8635 /* TGE means that NS EL0/1 act as if SCTLR_EL1.M is zero */
8636 if (!regime_is_secure(env
, mmu_idx
) && regime_el(env
, mmu_idx
) == 1) {
8641 return (regime_sctlr(env
, mmu_idx
) & SCTLR_M
) == 0;
8644 static inline bool regime_translation_big_endian(CPUARMState
*env
,
8647 return (regime_sctlr(env
, mmu_idx
) & SCTLR_EE
) != 0;
8650 /* Return the TCR controlling this translation regime */
8651 static inline TCR
*regime_tcr(CPUARMState
*env
, ARMMMUIdx mmu_idx
)
8653 if (mmu_idx
== ARMMMUIdx_S2NS
) {
8654 return &env
->cp15
.vtcr_el2
;
8656 return &env
->cp15
.tcr_el
[regime_el(env
, mmu_idx
)];
8659 /* Convert a possible stage1+2 MMU index into the appropriate
8662 static inline ARMMMUIdx
stage_1_mmu_idx(ARMMMUIdx mmu_idx
)
8664 if (mmu_idx
== ARMMMUIdx_S12NSE0
|| mmu_idx
== ARMMMUIdx_S12NSE1
) {
8665 mmu_idx
+= (ARMMMUIdx_S1NSE0
- ARMMMUIdx_S12NSE0
);
8670 /* Returns TBI0 value for current regime el */
8671 uint32_t arm_regime_tbi0(CPUARMState
*env
, ARMMMUIdx mmu_idx
)
8676 /* For EL0 and EL1, TBI is controlled by stage 1's TCR, so convert
8677 * a stage 1+2 mmu index into the appropriate stage 1 mmu index.
8679 mmu_idx
= stage_1_mmu_idx(mmu_idx
);
8681 tcr
= regime_tcr(env
, mmu_idx
);
8682 el
= regime_el(env
, mmu_idx
);
8685 return extract64(tcr
->raw_tcr
, 20, 1);
8687 return extract64(tcr
->raw_tcr
, 37, 1);
8691 /* Returns TBI1 value for current regime el */
8692 uint32_t arm_regime_tbi1(CPUARMState
*env
, ARMMMUIdx mmu_idx
)
8697 /* For EL0 and EL1, TBI is controlled by stage 1's TCR, so convert
8698 * a stage 1+2 mmu index into the appropriate stage 1 mmu index.
8700 mmu_idx
= stage_1_mmu_idx(mmu_idx
);
8702 tcr
= regime_tcr(env
, mmu_idx
);
8703 el
= regime_el(env
, mmu_idx
);
8708 return extract64(tcr
->raw_tcr
, 38, 1);
8712 /* Return the TTBR associated with this translation regime */
8713 static inline uint64_t regime_ttbr(CPUARMState
*env
, ARMMMUIdx mmu_idx
,
8716 if (mmu_idx
== ARMMMUIdx_S2NS
) {
8717 return env
->cp15
.vttbr_el2
;
8720 return env
->cp15
.ttbr0_el
[regime_el(env
, mmu_idx
)];
8722 return env
->cp15
.ttbr1_el
[regime_el(env
, mmu_idx
)];
8726 /* Return true if the translation regime is using LPAE format page tables */
8727 static inline bool regime_using_lpae_format(CPUARMState
*env
,
8730 int el
= regime_el(env
, mmu_idx
);
8731 if (el
== 2 || arm_el_is_aa64(env
, el
)) {
8734 if (arm_feature(env
, ARM_FEATURE_LPAE
)
8735 && (regime_tcr(env
, mmu_idx
)->raw_tcr
& TTBCR_EAE
)) {
8741 /* Returns true if the stage 1 translation regime is using LPAE format page
8742 * tables. Used when raising alignment exceptions, whose FSR changes depending
8743 * on whether the long or short descriptor format is in use. */
8744 bool arm_s1_regime_using_lpae_format(CPUARMState
*env
, ARMMMUIdx mmu_idx
)
8746 mmu_idx
= stage_1_mmu_idx(mmu_idx
);
8748 return regime_using_lpae_format(env
, mmu_idx
);
8751 static inline bool regime_is_user(CPUARMState
*env
, ARMMMUIdx mmu_idx
)
8754 case ARMMMUIdx_S1SE0
:
8755 case ARMMMUIdx_S1NSE0
:
8756 case ARMMMUIdx_MUser
:
8757 case ARMMMUIdx_MSUser
:
8758 case ARMMMUIdx_MUserNegPri
:
8759 case ARMMMUIdx_MSUserNegPri
:
8763 case ARMMMUIdx_S12NSE0
:
8764 case ARMMMUIdx_S12NSE1
:
8765 g_assert_not_reached();
8769 /* Translate section/page access permissions to page
8770 * R/W protection flags
8773 * @mmu_idx: MMU index indicating required translation regime
8774 * @ap: The 3-bit access permissions (AP[2:0])
8775 * @domain_prot: The 2-bit domain access permissions
8777 static inline int ap_to_rw_prot(CPUARMState
*env
, ARMMMUIdx mmu_idx
,
8778 int ap
, int domain_prot
)
8780 bool is_user
= regime_is_user(env
, mmu_idx
);
8782 if (domain_prot
== 3) {
8783 return PAGE_READ
| PAGE_WRITE
;
8788 if (arm_feature(env
, ARM_FEATURE_V7
)) {
8791 switch (regime_sctlr(env
, mmu_idx
) & (SCTLR_S
| SCTLR_R
)) {
8793 return is_user
? 0 : PAGE_READ
;
8800 return is_user
? 0 : PAGE_READ
| PAGE_WRITE
;
8805 return PAGE_READ
| PAGE_WRITE
;
8808 return PAGE_READ
| PAGE_WRITE
;
8809 case 4: /* Reserved. */
8812 return is_user
? 0 : PAGE_READ
;
8816 if (!arm_feature(env
, ARM_FEATURE_V6K
)) {
8821 g_assert_not_reached();
8825 /* Translate section/page access permissions to page
8826 * R/W protection flags.
8828 * @ap: The 2-bit simple AP (AP[2:1])
8829 * @is_user: TRUE if accessing from PL0
8831 static inline int simple_ap_to_rw_prot_is_user(int ap
, bool is_user
)
8835 return is_user
? 0 : PAGE_READ
| PAGE_WRITE
;
8837 return PAGE_READ
| PAGE_WRITE
;
8839 return is_user
? 0 : PAGE_READ
;
8843 g_assert_not_reached();
8848 simple_ap_to_rw_prot(CPUARMState
*env
, ARMMMUIdx mmu_idx
, int ap
)
8850 return simple_ap_to_rw_prot_is_user(ap
, regime_is_user(env
, mmu_idx
));
8853 /* Translate S2 section/page access permissions to protection flags
8856 * @s2ap: The 2-bit stage2 access permissions (S2AP)
8857 * @xn: XN (execute-never) bit
8859 static int get_S2prot(CPUARMState
*env
, int s2ap
, int xn
)
8870 if (arm_el_is_aa64(env
, 2) || prot
& PAGE_READ
) {
8877 /* Translate section/page access permissions to protection flags
8880 * @mmu_idx: MMU index indicating required translation regime
8881 * @is_aa64: TRUE if AArch64
8882 * @ap: The 2-bit simple AP (AP[2:1])
8883 * @ns: NS (non-secure) bit
8884 * @xn: XN (execute-never) bit
8885 * @pxn: PXN (privileged execute-never) bit
8887 static int get_S1prot(CPUARMState
*env
, ARMMMUIdx mmu_idx
, bool is_aa64
,
8888 int ap
, int ns
, int xn
, int pxn
)
8890 bool is_user
= regime_is_user(env
, mmu_idx
);
8891 int prot_rw
, user_rw
;
8895 assert(mmu_idx
!= ARMMMUIdx_S2NS
);
8897 user_rw
= simple_ap_to_rw_prot_is_user(ap
, true);
8901 prot_rw
= simple_ap_to_rw_prot_is_user(ap
, false);
8904 if (ns
&& arm_is_secure(env
) && (env
->cp15
.scr_el3
& SCR_SIF
)) {
8908 /* TODO have_wxn should be replaced with
8909 * ARM_FEATURE_V8 || (ARM_FEATURE_V7 && ARM_FEATURE_EL2)
8910 * when ARM_FEATURE_EL2 starts getting set. For now we assume all LPAE
8911 * compatible processors have EL2, which is required for [U]WXN.
8913 have_wxn
= arm_feature(env
, ARM_FEATURE_LPAE
);
8916 wxn
= regime_sctlr(env
, mmu_idx
) & SCTLR_WXN
;
8920 switch (regime_el(env
, mmu_idx
)) {
8923 xn
= pxn
|| (user_rw
& PAGE_WRITE
);
8930 } else if (arm_feature(env
, ARM_FEATURE_V7
)) {
8931 switch (regime_el(env
, mmu_idx
)) {
8935 xn
= xn
|| !(user_rw
& PAGE_READ
);
8939 uwxn
= regime_sctlr(env
, mmu_idx
) & SCTLR_UWXN
;
8941 xn
= xn
|| !(prot_rw
& PAGE_READ
) || pxn
||
8942 (uwxn
&& (user_rw
& PAGE_WRITE
));
8952 if (xn
|| (wxn
&& (prot_rw
& PAGE_WRITE
))) {
8955 return prot_rw
| PAGE_EXEC
;
8958 static bool get_level1_table_address(CPUARMState
*env
, ARMMMUIdx mmu_idx
,
8959 uint32_t *table
, uint32_t address
)
8961 /* Note that we can only get here for an AArch32 PL0/PL1 lookup */
8962 TCR
*tcr
= regime_tcr(env
, mmu_idx
);
8964 if (address
& tcr
->mask
) {
8965 if (tcr
->raw_tcr
& TTBCR_PD1
) {
8966 /* Translation table walk disabled for TTBR1 */
8969 *table
= regime_ttbr(env
, mmu_idx
, 1) & 0xffffc000;
8971 if (tcr
->raw_tcr
& TTBCR_PD0
) {
8972 /* Translation table walk disabled for TTBR0 */
8975 *table
= regime_ttbr(env
, mmu_idx
, 0) & tcr
->base_mask
;
8977 *table
|= (address
>> 18) & 0x3ffc;
8981 /* Translate a S1 pagetable walk through S2 if needed. */
8982 static hwaddr
S1_ptw_translate(CPUARMState
*env
, ARMMMUIdx mmu_idx
,
8983 hwaddr addr
, MemTxAttrs txattrs
,
8984 ARMMMUFaultInfo
*fi
)
8986 if ((mmu_idx
== ARMMMUIdx_S1NSE0
|| mmu_idx
== ARMMMUIdx_S1NSE1
) &&
8987 !regime_translation_disabled(env
, ARMMMUIdx_S2NS
)) {
8988 target_ulong s2size
;
8993 ret
= get_phys_addr_lpae(env
, addr
, 0, ARMMMUIdx_S2NS
, &s2pa
,
8994 &txattrs
, &s2prot
, &s2size
, fi
, NULL
);
8996 assert(fi
->type
!= ARMFault_None
);
9007 /* All loads done in the course of a page table walk go through here. */
9008 static uint32_t arm_ldl_ptw(CPUState
*cs
, hwaddr addr
, bool is_secure
,
9009 ARMMMUIdx mmu_idx
, ARMMMUFaultInfo
*fi
)
9011 ARMCPU
*cpu
= ARM_CPU(cs
);
9012 CPUARMState
*env
= &cpu
->env
;
9013 MemTxAttrs attrs
= {};
9014 MemTxResult result
= MEMTX_OK
;
9018 attrs
.secure
= is_secure
;
9019 as
= arm_addressspace(cs
, attrs
);
9020 addr
= S1_ptw_translate(env
, mmu_idx
, addr
, attrs
, fi
);
9024 if (regime_translation_big_endian(env
, mmu_idx
)) {
9025 data
= address_space_ldl_be(as
, addr
, attrs
, &result
);
9027 data
= address_space_ldl_le(as
, addr
, attrs
, &result
);
9029 if (result
== MEMTX_OK
) {
9032 fi
->type
= ARMFault_SyncExternalOnWalk
;
9033 fi
->ea
= arm_extabort_type(result
);
9037 static uint64_t arm_ldq_ptw(CPUState
*cs
, hwaddr addr
, bool is_secure
,
9038 ARMMMUIdx mmu_idx
, ARMMMUFaultInfo
*fi
)
9040 ARMCPU
*cpu
= ARM_CPU(cs
);
9041 CPUARMState
*env
= &cpu
->env
;
9042 MemTxAttrs attrs
= {};
9043 MemTxResult result
= MEMTX_OK
;
9047 attrs
.secure
= is_secure
;
9048 as
= arm_addressspace(cs
, attrs
);
9049 addr
= S1_ptw_translate(env
, mmu_idx
, addr
, attrs
, fi
);
9053 if (regime_translation_big_endian(env
, mmu_idx
)) {
9054 data
= address_space_ldq_be(as
, addr
, attrs
, &result
);
9056 data
= address_space_ldq_le(as
, addr
, attrs
, &result
);
9058 if (result
== MEMTX_OK
) {
9061 fi
->type
= ARMFault_SyncExternalOnWalk
;
9062 fi
->ea
= arm_extabort_type(result
);
9066 static bool get_phys_addr_v5(CPUARMState
*env
, uint32_t address
,
9067 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
9068 hwaddr
*phys_ptr
, int *prot
,
9069 target_ulong
*page_size
,
9070 ARMMMUFaultInfo
*fi
)
9072 CPUState
*cs
= CPU(arm_env_get_cpu(env
));
9083 /* Pagetable walk. */
9084 /* Lookup l1 descriptor. */
9085 if (!get_level1_table_address(env
, mmu_idx
, &table
, address
)) {
9086 /* Section translation fault if page walk is disabled by PD0 or PD1 */
9087 fi
->type
= ARMFault_Translation
;
9090 desc
= arm_ldl_ptw(cs
, table
, regime_is_secure(env
, mmu_idx
),
9092 if (fi
->type
!= ARMFault_None
) {
9096 domain
= (desc
>> 5) & 0x0f;
9097 if (regime_el(env
, mmu_idx
) == 1) {
9098 dacr
= env
->cp15
.dacr_ns
;
9100 dacr
= env
->cp15
.dacr_s
;
9102 domain_prot
= (dacr
>> (domain
* 2)) & 3;
9104 /* Section translation fault. */
9105 fi
->type
= ARMFault_Translation
;
9111 if (domain_prot
== 0 || domain_prot
== 2) {
9112 fi
->type
= ARMFault_Domain
;
9117 phys_addr
= (desc
& 0xfff00000) | (address
& 0x000fffff);
9118 ap
= (desc
>> 10) & 3;
9119 *page_size
= 1024 * 1024;
9121 /* Lookup l2 entry. */
9123 /* Coarse pagetable. */
9124 table
= (desc
& 0xfffffc00) | ((address
>> 10) & 0x3fc);
9126 /* Fine pagetable. */
9127 table
= (desc
& 0xfffff000) | ((address
>> 8) & 0xffc);
9129 desc
= arm_ldl_ptw(cs
, table
, regime_is_secure(env
, mmu_idx
),
9131 if (fi
->type
!= ARMFault_None
) {
9135 case 0: /* Page translation fault. */
9136 fi
->type
= ARMFault_Translation
;
9138 case 1: /* 64k page. */
9139 phys_addr
= (desc
& 0xffff0000) | (address
& 0xffff);
9140 ap
= (desc
>> (4 + ((address
>> 13) & 6))) & 3;
9141 *page_size
= 0x10000;
9143 case 2: /* 4k page. */
9144 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
9145 ap
= (desc
>> (4 + ((address
>> 9) & 6))) & 3;
9146 *page_size
= 0x1000;
9148 case 3: /* 1k page, or ARMv6/XScale "extended small (4k) page" */
9150 /* ARMv6/XScale extended small page format */
9151 if (arm_feature(env
, ARM_FEATURE_XSCALE
)
9152 || arm_feature(env
, ARM_FEATURE_V6
)) {
9153 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
9154 *page_size
= 0x1000;
9156 /* UNPREDICTABLE in ARMv5; we choose to take a
9157 * page translation fault.
9159 fi
->type
= ARMFault_Translation
;
9163 phys_addr
= (desc
& 0xfffffc00) | (address
& 0x3ff);
9166 ap
= (desc
>> 4) & 3;
9169 /* Never happens, but compiler isn't smart enough to tell. */
9173 *prot
= ap_to_rw_prot(env
, mmu_idx
, ap
, domain_prot
);
9174 *prot
|= *prot
? PAGE_EXEC
: 0;
9175 if (!(*prot
& (1 << access_type
))) {
9176 /* Access permission fault. */
9177 fi
->type
= ARMFault_Permission
;
9180 *phys_ptr
= phys_addr
;
9183 fi
->domain
= domain
;
9188 static bool get_phys_addr_v6(CPUARMState
*env
, uint32_t address
,
9189 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
9190 hwaddr
*phys_ptr
, MemTxAttrs
*attrs
, int *prot
,
9191 target_ulong
*page_size
, ARMMMUFaultInfo
*fi
)
9193 CPUState
*cs
= CPU(arm_env_get_cpu(env
));
9207 /* Pagetable walk. */
9208 /* Lookup l1 descriptor. */
9209 if (!get_level1_table_address(env
, mmu_idx
, &table
, address
)) {
9210 /* Section translation fault if page walk is disabled by PD0 or PD1 */
9211 fi
->type
= ARMFault_Translation
;
9214 desc
= arm_ldl_ptw(cs
, table
, regime_is_secure(env
, mmu_idx
),
9216 if (fi
->type
!= ARMFault_None
) {
9220 if (type
== 0 || (type
== 3 && !arm_feature(env
, ARM_FEATURE_PXN
))) {
9221 /* Section translation fault, or attempt to use the encoding
9222 * which is Reserved on implementations without PXN.
9224 fi
->type
= ARMFault_Translation
;
9227 if ((type
== 1) || !(desc
& (1 << 18))) {
9228 /* Page or Section. */
9229 domain
= (desc
>> 5) & 0x0f;
9231 if (regime_el(env
, mmu_idx
) == 1) {
9232 dacr
= env
->cp15
.dacr_ns
;
9234 dacr
= env
->cp15
.dacr_s
;
9239 domain_prot
= (dacr
>> (domain
* 2)) & 3;
9240 if (domain_prot
== 0 || domain_prot
== 2) {
9241 /* Section or Page domain fault */
9242 fi
->type
= ARMFault_Domain
;
9246 if (desc
& (1 << 18)) {
9248 phys_addr
= (desc
& 0xff000000) | (address
& 0x00ffffff);
9249 phys_addr
|= (uint64_t)extract32(desc
, 20, 4) << 32;
9250 phys_addr
|= (uint64_t)extract32(desc
, 5, 4) << 36;
9251 *page_size
= 0x1000000;
9254 phys_addr
= (desc
& 0xfff00000) | (address
& 0x000fffff);
9255 *page_size
= 0x100000;
9257 ap
= ((desc
>> 10) & 3) | ((desc
>> 13) & 4);
9258 xn
= desc
& (1 << 4);
9260 ns
= extract32(desc
, 19, 1);
9262 if (arm_feature(env
, ARM_FEATURE_PXN
)) {
9263 pxn
= (desc
>> 2) & 1;
9265 ns
= extract32(desc
, 3, 1);
9266 /* Lookup l2 entry. */
9267 table
= (desc
& 0xfffffc00) | ((address
>> 10) & 0x3fc);
9268 desc
= arm_ldl_ptw(cs
, table
, regime_is_secure(env
, mmu_idx
),
9270 if (fi
->type
!= ARMFault_None
) {
9273 ap
= ((desc
>> 4) & 3) | ((desc
>> 7) & 4);
9275 case 0: /* Page translation fault. */
9276 fi
->type
= ARMFault_Translation
;
9278 case 1: /* 64k page. */
9279 phys_addr
= (desc
& 0xffff0000) | (address
& 0xffff);
9280 xn
= desc
& (1 << 15);
9281 *page_size
= 0x10000;
9283 case 2: case 3: /* 4k page. */
9284 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
9286 *page_size
= 0x1000;
9289 /* Never happens, but compiler isn't smart enough to tell. */
9293 if (domain_prot
== 3) {
9294 *prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
9296 if (pxn
&& !regime_is_user(env
, mmu_idx
)) {
9299 if (xn
&& access_type
== MMU_INST_FETCH
) {
9300 fi
->type
= ARMFault_Permission
;
9304 if (arm_feature(env
, ARM_FEATURE_V6K
) &&
9305 (regime_sctlr(env
, mmu_idx
) & SCTLR_AFE
)) {
9306 /* The simplified model uses AP[0] as an access control bit. */
9307 if ((ap
& 1) == 0) {
9308 /* Access flag fault. */
9309 fi
->type
= ARMFault_AccessFlag
;
9312 *prot
= simple_ap_to_rw_prot(env
, mmu_idx
, ap
>> 1);
9314 *prot
= ap_to_rw_prot(env
, mmu_idx
, ap
, domain_prot
);
9319 if (!(*prot
& (1 << access_type
))) {
9320 /* Access permission fault. */
9321 fi
->type
= ARMFault_Permission
;
9326 /* The NS bit will (as required by the architecture) have no effect if
9327 * the CPU doesn't support TZ or this is a non-secure translation
9328 * regime, because the attribute will already be non-secure.
9330 attrs
->secure
= false;
9332 *phys_ptr
= phys_addr
;
9335 fi
->domain
= domain
;
9341 * check_s2_mmu_setup
9343 * @is_aa64: True if the translation regime is in AArch64 state
9344 * @startlevel: Suggested starting level
9345 * @inputsize: Bitsize of IPAs
9346 * @stride: Page-table stride (See the ARM ARM)
9348 * Returns true if the suggested S2 translation parameters are OK and
9351 static bool check_s2_mmu_setup(ARMCPU
*cpu
, bool is_aa64
, int level
,
9352 int inputsize
, int stride
)
9354 const int grainsize
= stride
+ 3;
9357 /* Negative levels are never allowed. */
9362 startsizecheck
= inputsize
- ((3 - level
) * stride
+ grainsize
);
9363 if (startsizecheck
< 1 || startsizecheck
> stride
+ 4) {
9368 CPUARMState
*env
= &cpu
->env
;
9369 unsigned int pamax
= arm_pamax(cpu
);
9372 case 13: /* 64KB Pages. */
9373 if (level
== 0 || (level
== 1 && pamax
<= 42)) {
9377 case 11: /* 16KB Pages. */
9378 if (level
== 0 || (level
== 1 && pamax
<= 40)) {
9382 case 9: /* 4KB Pages. */
9383 if (level
== 0 && pamax
<= 42) {
9388 g_assert_not_reached();
9391 /* Inputsize checks. */
9392 if (inputsize
> pamax
&&
9393 (arm_el_is_aa64(env
, 1) || inputsize
> 40)) {
9394 /* This is CONSTRAINED UNPREDICTABLE and we choose to fault. */
9398 /* AArch32 only supports 4KB pages. Assert on that. */
9399 assert(stride
== 9);
9408 /* Translate from the 4-bit stage 2 representation of
9409 * memory attributes (without cache-allocation hints) to
9410 * the 8-bit representation of the stage 1 MAIR registers
9411 * (which includes allocation hints).
9413 * ref: shared/translation/attrs/S2AttrDecode()
9414 * .../S2ConvertAttrsHints()
9416 static uint8_t convert_stage2_attrs(CPUARMState
*env
, uint8_t s2attrs
)
9418 uint8_t hiattr
= extract32(s2attrs
, 2, 2);
9419 uint8_t loattr
= extract32(s2attrs
, 0, 2);
9420 uint8_t hihint
= 0, lohint
= 0;
9422 if (hiattr
!= 0) { /* normal memory */
9423 if ((env
->cp15
.hcr_el2
& HCR_CD
) != 0) { /* cache disabled */
9424 hiattr
= loattr
= 1; /* non-cacheable */
9426 if (hiattr
!= 1) { /* Write-through or write-back */
9427 hihint
= 3; /* RW allocate */
9429 if (loattr
!= 1) { /* Write-through or write-back */
9430 lohint
= 3; /* RW allocate */
9435 return (hiattr
<< 6) | (hihint
<< 4) | (loattr
<< 2) | lohint
;
9438 static bool get_phys_addr_lpae(CPUARMState
*env
, target_ulong address
,
9439 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
9440 hwaddr
*phys_ptr
, MemTxAttrs
*txattrs
, int *prot
,
9441 target_ulong
*page_size_ptr
,
9442 ARMMMUFaultInfo
*fi
, ARMCacheAttrs
*cacheattrs
)
9444 ARMCPU
*cpu
= arm_env_get_cpu(env
);
9445 CPUState
*cs
= CPU(cpu
);
9446 /* Read an LPAE long-descriptor translation table. */
9447 ARMFaultType fault_type
= ARMFault_Translation
;
9454 hwaddr descaddr
, indexmask
, indexmask_grainsize
;
9455 uint32_t tableattrs
;
9456 target_ulong page_size
;
9462 TCR
*tcr
= regime_tcr(env
, mmu_idx
);
9463 int ap
, ns
, xn
, pxn
;
9464 uint32_t el
= regime_el(env
, mmu_idx
);
9465 bool ttbr1_valid
= true;
9466 uint64_t descaddrmask
;
9467 bool aarch64
= arm_el_is_aa64(env
, el
);
9470 * This code does not handle the different format TCR for VTCR_EL2.
9471 * This code also does not support shareability levels.
9472 * Attribute and permission bit handling should also be checked when adding
9473 * support for those page table walks.
9479 if (mmu_idx
!= ARMMMUIdx_S2NS
) {
9480 tbi
= extract64(tcr
->raw_tcr
, 20, 1);
9483 if (extract64(address
, 55, 1)) {
9484 tbi
= extract64(tcr
->raw_tcr
, 38, 1);
9486 tbi
= extract64(tcr
->raw_tcr
, 37, 1);
9491 /* If we are in 64-bit EL2 or EL3 then there is no TTBR1, so mark it
9495 ttbr1_valid
= false;
9500 /* There is no TTBR1 for EL2 */
9502 ttbr1_valid
= false;
9506 /* Determine whether this address is in the region controlled by
9507 * TTBR0 or TTBR1 (or if it is in neither region and should fault).
9508 * This is a Non-secure PL0/1 stage 1 translation, so controlled by
9509 * TTBCR/TTBR0/TTBR1 in accordance with ARM ARM DDI0406C table B-32:
9512 /* AArch64 translation. */
9513 t0sz
= extract32(tcr
->raw_tcr
, 0, 6);
9514 t0sz
= MIN(t0sz
, 39);
9515 t0sz
= MAX(t0sz
, 16);
9516 } else if (mmu_idx
!= ARMMMUIdx_S2NS
) {
9517 /* AArch32 stage 1 translation. */
9518 t0sz
= extract32(tcr
->raw_tcr
, 0, 3);
9520 /* AArch32 stage 2 translation. */
9521 bool sext
= extract32(tcr
->raw_tcr
, 4, 1);
9522 bool sign
= extract32(tcr
->raw_tcr
, 3, 1);
9523 /* Address size is 40-bit for a stage 2 translation,
9524 * and t0sz can be negative (from -8 to 7),
9525 * so we need to adjust it to use the TTBR selecting logic below.
9528 t0sz
= sextract32(tcr
->raw_tcr
, 0, 4) + 8;
9530 /* If the sign-extend bit is not the same as t0sz[3], the result
9531 * is unpredictable. Flag this as a guest error. */
9533 qemu_log_mask(LOG_GUEST_ERROR
,
9534 "AArch32: VTCR.S / VTCR.T0SZ[3] mismatch\n");
9537 t1sz
= extract32(tcr
->raw_tcr
, 16, 6);
9539 t1sz
= MIN(t1sz
, 39);
9540 t1sz
= MAX(t1sz
, 16);
9542 if (t0sz
&& !extract64(address
, addrsize
- t0sz
, t0sz
- tbi
)) {
9543 /* there is a ttbr0 region and we are in it (high bits all zero) */
9545 } else if (ttbr1_valid
&& t1sz
&&
9546 !extract64(~address
, addrsize
- t1sz
, t1sz
- tbi
)) {
9547 /* there is a ttbr1 region and we are in it (high bits all one) */
9550 /* ttbr0 region is "everything not in the ttbr1 region" */
9552 } else if (!t1sz
&& ttbr1_valid
) {
9553 /* ttbr1 region is "everything not in the ttbr0 region" */
9556 /* in the gap between the two regions, this is a Translation fault */
9557 fault_type
= ARMFault_Translation
;
9561 /* Note that QEMU ignores shareability and cacheability attributes,
9562 * so we don't need to do anything with the SH, ORGN, IRGN fields
9563 * in the TTBCR. Similarly, TTBCR:A1 selects whether we get the
9564 * ASID from TTBR0 or TTBR1, but QEMU's TLB doesn't currently
9565 * implement any ASID-like capability so we can ignore it (instead
9566 * we will always flush the TLB any time the ASID is changed).
9568 if (ttbr_select
== 0) {
9569 ttbr
= regime_ttbr(env
, mmu_idx
, 0);
9571 epd
= extract32(tcr
->raw_tcr
, 7, 1);
9573 inputsize
= addrsize
- t0sz
;
9575 tg
= extract32(tcr
->raw_tcr
, 14, 2);
9576 if (tg
== 1) { /* 64KB pages */
9579 if (tg
== 2) { /* 16KB pages */
9583 /* We should only be here if TTBR1 is valid */
9584 assert(ttbr1_valid
);
9586 ttbr
= regime_ttbr(env
, mmu_idx
, 1);
9587 epd
= extract32(tcr
->raw_tcr
, 23, 1);
9588 inputsize
= addrsize
- t1sz
;
9590 tg
= extract32(tcr
->raw_tcr
, 30, 2);
9591 if (tg
== 3) { /* 64KB pages */
9594 if (tg
== 1) { /* 16KB pages */
9599 /* Here we should have set up all the parameters for the translation:
9600 * inputsize, ttbr, epd, stride, tbi
9604 /* Translation table walk disabled => Translation fault on TLB miss
9605 * Note: This is always 0 on 64-bit EL2 and EL3.
9610 if (mmu_idx
!= ARMMMUIdx_S2NS
) {
9611 /* The starting level depends on the virtual address size (which can
9612 * be up to 48 bits) and the translation granule size. It indicates
9613 * the number of strides (stride bits at a time) needed to
9614 * consume the bits of the input address. In the pseudocode this is:
9615 * level = 4 - RoundUp((inputsize - grainsize) / stride)
9616 * where their 'inputsize' is our 'inputsize', 'grainsize' is
9617 * our 'stride + 3' and 'stride' is our 'stride'.
9618 * Applying the usual "rounded up m/n is (m+n-1)/n" and simplifying:
9619 * = 4 - (inputsize - stride - 3 + stride - 1) / stride
9620 * = 4 - (inputsize - 4) / stride;
9622 level
= 4 - (inputsize
- 4) / stride
;
9624 /* For stage 2 translations the starting level is specified by the
9625 * VTCR_EL2.SL0 field (whose interpretation depends on the page size)
9627 uint32_t sl0
= extract32(tcr
->raw_tcr
, 6, 2);
9628 uint32_t startlevel
;
9631 if (!aarch64
|| stride
== 9) {
9632 /* AArch32 or 4KB pages */
9633 startlevel
= 2 - sl0
;
9635 /* 16KB or 64KB pages */
9636 startlevel
= 3 - sl0
;
9639 /* Check that the starting level is valid. */
9640 ok
= check_s2_mmu_setup(cpu
, aarch64
, startlevel
,
9643 fault_type
= ARMFault_Translation
;
9649 indexmask_grainsize
= (1ULL << (stride
+ 3)) - 1;
9650 indexmask
= (1ULL << (inputsize
- (stride
* (4 - level
)))) - 1;
9652 /* Now we can extract the actual base address from the TTBR */
9653 descaddr
= extract64(ttbr
, 0, 48);
9654 descaddr
&= ~indexmask
;
9656 /* The address field in the descriptor goes up to bit 39 for ARMv7
9657 * but up to bit 47 for ARMv8, but we use the descaddrmask
9658 * up to bit 39 for AArch32, because we don't need other bits in that case
9659 * to construct next descriptor address (anyway they should be all zeroes).
9661 descaddrmask
= ((1ull << (aarch64
? 48 : 40)) - 1) &
9662 ~indexmask_grainsize
;
9664 /* Secure accesses start with the page table in secure memory and
9665 * can be downgraded to non-secure at any step. Non-secure accesses
9666 * remain non-secure. We implement this by just ORing in the NSTable/NS
9667 * bits at each step.
9669 tableattrs
= regime_is_secure(env
, mmu_idx
) ? 0 : (1 << 4);
9671 uint64_t descriptor
;
9674 descaddr
|= (address
>> (stride
* (4 - level
))) & indexmask
;
9676 nstable
= extract32(tableattrs
, 4, 1);
9677 descriptor
= arm_ldq_ptw(cs
, descaddr
, !nstable
, mmu_idx
, fi
);
9678 if (fi
->type
!= ARMFault_None
) {
9682 if (!(descriptor
& 1) ||
9683 (!(descriptor
& 2) && (level
== 3))) {
9684 /* Invalid, or the Reserved level 3 encoding */
9687 descaddr
= descriptor
& descaddrmask
;
9689 if ((descriptor
& 2) && (level
< 3)) {
9690 /* Table entry. The top five bits are attributes which may
9691 * propagate down through lower levels of the table (and
9692 * which are all arranged so that 0 means "no effect", so
9693 * we can gather them up by ORing in the bits at each level).
9695 tableattrs
|= extract64(descriptor
, 59, 5);
9697 indexmask
= indexmask_grainsize
;
9700 /* Block entry at level 1 or 2, or page entry at level 3.
9701 * These are basically the same thing, although the number
9702 * of bits we pull in from the vaddr varies.
9704 page_size
= (1ULL << ((stride
* (4 - level
)) + 3));
9705 descaddr
|= (address
& (page_size
- 1));
9706 /* Extract attributes from the descriptor */
9707 attrs
= extract64(descriptor
, 2, 10)
9708 | (extract64(descriptor
, 52, 12) << 10);
9710 if (mmu_idx
== ARMMMUIdx_S2NS
) {
9711 /* Stage 2 table descriptors do not include any attribute fields */
9714 /* Merge in attributes from table descriptors */
9715 attrs
|= extract32(tableattrs
, 0, 2) << 11; /* XN, PXN */
9716 attrs
|= extract32(tableattrs
, 3, 1) << 5; /* APTable[1] => AP[2] */
9717 /* The sense of AP[1] vs APTable[0] is reversed, as APTable[0] == 1
9718 * means "force PL1 access only", which means forcing AP[1] to 0.
9720 if (extract32(tableattrs
, 2, 1)) {
9723 attrs
|= nstable
<< 3; /* NS */
9726 /* Here descaddr is the final physical address, and attributes
9729 fault_type
= ARMFault_AccessFlag
;
9730 if ((attrs
& (1 << 8)) == 0) {
9735 ap
= extract32(attrs
, 4, 2);
9736 xn
= extract32(attrs
, 12, 1);
9738 if (mmu_idx
== ARMMMUIdx_S2NS
) {
9740 *prot
= get_S2prot(env
, ap
, xn
);
9742 ns
= extract32(attrs
, 3, 1);
9743 pxn
= extract32(attrs
, 11, 1);
9744 *prot
= get_S1prot(env
, mmu_idx
, aarch64
, ap
, ns
, xn
, pxn
);
9747 fault_type
= ARMFault_Permission
;
9748 if (!(*prot
& (1 << access_type
))) {
9753 /* The NS bit will (as required by the architecture) have no effect if
9754 * the CPU doesn't support TZ or this is a non-secure translation
9755 * regime, because the attribute will already be non-secure.
9757 txattrs
->secure
= false;
9760 if (cacheattrs
!= NULL
) {
9761 if (mmu_idx
== ARMMMUIdx_S2NS
) {
9762 cacheattrs
->attrs
= convert_stage2_attrs(env
,
9763 extract32(attrs
, 0, 4));
9765 /* Index into MAIR registers for cache attributes */
9766 uint8_t attrindx
= extract32(attrs
, 0, 3);
9767 uint64_t mair
= env
->cp15
.mair_el
[regime_el(env
, mmu_idx
)];
9768 assert(attrindx
<= 7);
9769 cacheattrs
->attrs
= extract64(mair
, attrindx
* 8, 8);
9771 cacheattrs
->shareability
= extract32(attrs
, 6, 2);
9774 *phys_ptr
= descaddr
;
9775 *page_size_ptr
= page_size
;
9779 fi
->type
= fault_type
;
9781 /* Tag the error as S2 for failed S1 PTW at S2 or ordinary S2. */
9782 fi
->stage2
= fi
->s1ptw
|| (mmu_idx
== ARMMMUIdx_S2NS
);
9786 static inline void get_phys_addr_pmsav7_default(CPUARMState
*env
,
9788 int32_t address
, int *prot
)
9790 if (!arm_feature(env
, ARM_FEATURE_M
)) {
9791 *prot
= PAGE_READ
| PAGE_WRITE
;
9793 case 0xF0000000 ... 0xFFFFFFFF:
9794 if (regime_sctlr(env
, mmu_idx
) & SCTLR_V
) {
9795 /* hivecs execing is ok */
9799 case 0x00000000 ... 0x7FFFFFFF:
9804 /* Default system address map for M profile cores.
9805 * The architecture specifies which regions are execute-never;
9806 * at the MPU level no other checks are defined.
9809 case 0x00000000 ... 0x1fffffff: /* ROM */
9810 case 0x20000000 ... 0x3fffffff: /* SRAM */
9811 case 0x60000000 ... 0x7fffffff: /* RAM */
9812 case 0x80000000 ... 0x9fffffff: /* RAM */
9813 *prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
9815 case 0x40000000 ... 0x5fffffff: /* Peripheral */
9816 case 0xa0000000 ... 0xbfffffff: /* Device */
9817 case 0xc0000000 ... 0xdfffffff: /* Device */
9818 case 0xe0000000 ... 0xffffffff: /* System */
9819 *prot
= PAGE_READ
| PAGE_WRITE
;
9822 g_assert_not_reached();
9827 static bool pmsav7_use_background_region(ARMCPU
*cpu
,
9828 ARMMMUIdx mmu_idx
, bool is_user
)
9830 /* Return true if we should use the default memory map as a
9831 * "background" region if there are no hits against any MPU regions.
9833 CPUARMState
*env
= &cpu
->env
;
9839 if (arm_feature(env
, ARM_FEATURE_M
)) {
9840 return env
->v7m
.mpu_ctrl
[regime_is_secure(env
, mmu_idx
)]
9841 & R_V7M_MPU_CTRL_PRIVDEFENA_MASK
;
9843 return regime_sctlr(env
, mmu_idx
) & SCTLR_BR
;
9847 static inline bool m_is_ppb_region(CPUARMState
*env
, uint32_t address
)
9849 /* True if address is in the M profile PPB region 0xe0000000 - 0xe00fffff */
9850 return arm_feature(env
, ARM_FEATURE_M
) &&
9851 extract32(address
, 20, 12) == 0xe00;
9854 static inline bool m_is_system_region(CPUARMState
*env
, uint32_t address
)
9856 /* True if address is in the M profile system region
9857 * 0xe0000000 - 0xffffffff
9859 return arm_feature(env
, ARM_FEATURE_M
) && extract32(address
, 29, 3) == 0x7;
9862 static bool get_phys_addr_pmsav7(CPUARMState
*env
, uint32_t address
,
9863 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
9864 hwaddr
*phys_ptr
, int *prot
,
9865 target_ulong
*page_size
,
9866 ARMMMUFaultInfo
*fi
)
9868 ARMCPU
*cpu
= arm_env_get_cpu(env
);
9870 bool is_user
= regime_is_user(env
, mmu_idx
);
9872 *phys_ptr
= address
;
9873 *page_size
= TARGET_PAGE_SIZE
;
9876 if (regime_translation_disabled(env
, mmu_idx
) ||
9877 m_is_ppb_region(env
, address
)) {
9878 /* MPU disabled or M profile PPB access: use default memory map.
9879 * The other case which uses the default memory map in the
9880 * v7M ARM ARM pseudocode is exception vector reads from the vector
9881 * table. In QEMU those accesses are done in arm_v7m_load_vector(),
9882 * which always does a direct read using address_space_ldl(), rather
9883 * than going via this function, so we don't need to check that here.
9885 get_phys_addr_pmsav7_default(env
, mmu_idx
, address
, prot
);
9886 } else { /* MPU enabled */
9887 for (n
= (int)cpu
->pmsav7_dregion
- 1; n
>= 0; n
--) {
9889 uint32_t base
= env
->pmsav7
.drbar
[n
];
9890 uint32_t rsize
= extract32(env
->pmsav7
.drsr
[n
], 1, 5);
9894 if (!(env
->pmsav7
.drsr
[n
] & 0x1)) {
9899 qemu_log_mask(LOG_GUEST_ERROR
,
9900 "DRSR[%d]: Rsize field cannot be 0\n", n
);
9904 rmask
= (1ull << rsize
) - 1;
9907 qemu_log_mask(LOG_GUEST_ERROR
,
9908 "DRBAR[%d]: 0x%" PRIx32
" misaligned "
9909 "to DRSR region size, mask = 0x%" PRIx32
"\n",
9914 if (address
< base
|| address
> base
+ rmask
) {
9916 * Address not in this region. We must check whether the
9917 * region covers addresses in the same page as our address.
9918 * In that case we must not report a size that covers the
9919 * whole page for a subsequent hit against a different MPU
9920 * region or the background region, because it would result in
9921 * incorrect TLB hits for subsequent accesses to addresses that
9922 * are in this MPU region.
9924 if (ranges_overlap(base
, rmask
,
9925 address
& TARGET_PAGE_MASK
,
9926 TARGET_PAGE_SIZE
)) {
9932 /* Region matched */
9934 if (rsize
>= 8) { /* no subregions for regions < 256 bytes */
9936 uint32_t srdis_mask
;
9938 rsize
-= 3; /* sub region size (power of 2) */
9939 snd
= ((address
- base
) >> rsize
) & 0x7;
9940 srdis
= extract32(env
->pmsav7
.drsr
[n
], snd
+ 8, 1);
9942 srdis_mask
= srdis
? 0x3 : 0x0;
9943 for (i
= 2; i
<= 8 && rsize
< TARGET_PAGE_BITS
; i
*= 2) {
9944 /* This will check in groups of 2, 4 and then 8, whether
9945 * the subregion bits are consistent. rsize is incremented
9946 * back up to give the region size, considering consistent
9947 * adjacent subregions as one region. Stop testing if rsize
9948 * is already big enough for an entire QEMU page.
9950 int snd_rounded
= snd
& ~(i
- 1);
9951 uint32_t srdis_multi
= extract32(env
->pmsav7
.drsr
[n
],
9952 snd_rounded
+ 8, i
);
9953 if (srdis_mask
^ srdis_multi
) {
9956 srdis_mask
= (srdis_mask
<< i
) | srdis_mask
;
9963 if (rsize
< TARGET_PAGE_BITS
) {
9964 *page_size
= 1 << rsize
;
9969 if (n
== -1) { /* no hits */
9970 if (!pmsav7_use_background_region(cpu
, mmu_idx
, is_user
)) {
9971 /* background fault */
9972 fi
->type
= ARMFault_Background
;
9975 get_phys_addr_pmsav7_default(env
, mmu_idx
, address
, prot
);
9976 } else { /* a MPU hit! */
9977 uint32_t ap
= extract32(env
->pmsav7
.dracr
[n
], 8, 3);
9978 uint32_t xn
= extract32(env
->pmsav7
.dracr
[n
], 12, 1);
9980 if (m_is_system_region(env
, address
)) {
9981 /* System space is always execute never */
9985 if (is_user
) { /* User mode AP bit decoding */
9990 break; /* no access */
9992 *prot
|= PAGE_WRITE
;
9996 *prot
|= PAGE_READ
| PAGE_EXEC
;
9999 /* for v7M, same as 6; for R profile a reserved value */
10000 if (arm_feature(env
, ARM_FEATURE_M
)) {
10001 *prot
|= PAGE_READ
| PAGE_EXEC
;
10006 qemu_log_mask(LOG_GUEST_ERROR
,
10007 "DRACR[%d]: Bad value for AP bits: 0x%"
10008 PRIx32
"\n", n
, ap
);
10010 } else { /* Priv. mode AP bits decoding */
10013 break; /* no access */
10017 *prot
|= PAGE_WRITE
;
10021 *prot
|= PAGE_READ
| PAGE_EXEC
;
10024 /* for v7M, same as 6; for R profile a reserved value */
10025 if (arm_feature(env
, ARM_FEATURE_M
)) {
10026 *prot
|= PAGE_READ
| PAGE_EXEC
;
10031 qemu_log_mask(LOG_GUEST_ERROR
,
10032 "DRACR[%d]: Bad value for AP bits: 0x%"
10033 PRIx32
"\n", n
, ap
);
10037 /* execute never */
10039 *prot
&= ~PAGE_EXEC
;
10044 fi
->type
= ARMFault_Permission
;
10046 return !(*prot
& (1 << access_type
));
10049 static bool v8m_is_sau_exempt(CPUARMState
*env
,
10050 uint32_t address
, MMUAccessType access_type
)
10052 /* The architecture specifies that certain address ranges are
10053 * exempt from v8M SAU/IDAU checks.
10056 (access_type
== MMU_INST_FETCH
&& m_is_system_region(env
, address
)) ||
10057 (address
>= 0xe0000000 && address
<= 0xe0002fff) ||
10058 (address
>= 0xe000e000 && address
<= 0xe000efff) ||
10059 (address
>= 0xe002e000 && address
<= 0xe002efff) ||
10060 (address
>= 0xe0040000 && address
<= 0xe0041fff) ||
10061 (address
>= 0xe00ff000 && address
<= 0xe00fffff);
10064 static void v8m_security_lookup(CPUARMState
*env
, uint32_t address
,
10065 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
10066 V8M_SAttributes
*sattrs
)
10068 /* Look up the security attributes for this address. Compare the
10069 * pseudocode SecurityCheck() function.
10070 * We assume the caller has zero-initialized *sattrs.
10072 ARMCPU
*cpu
= arm_env_get_cpu(env
);
10074 bool idau_exempt
= false, idau_ns
= true, idau_nsc
= true;
10075 int idau_region
= IREGION_NOTVALID
;
10076 uint32_t addr_page_base
= address
& TARGET_PAGE_MASK
;
10077 uint32_t addr_page_limit
= addr_page_base
+ (TARGET_PAGE_SIZE
- 1);
10080 IDAUInterfaceClass
*iic
= IDAU_INTERFACE_GET_CLASS(cpu
->idau
);
10081 IDAUInterface
*ii
= IDAU_INTERFACE(cpu
->idau
);
10083 iic
->check(ii
, address
, &idau_region
, &idau_exempt
, &idau_ns
,
10087 if (access_type
== MMU_INST_FETCH
&& extract32(address
, 28, 4) == 0xf) {
10088 /* 0xf0000000..0xffffffff is always S for insn fetches */
10092 if (idau_exempt
|| v8m_is_sau_exempt(env
, address
, access_type
)) {
10093 sattrs
->ns
= !regime_is_secure(env
, mmu_idx
);
10097 if (idau_region
!= IREGION_NOTVALID
) {
10098 sattrs
->irvalid
= true;
10099 sattrs
->iregion
= idau_region
;
10102 switch (env
->sau
.ctrl
& 3) {
10103 case 0: /* SAU.ENABLE == 0, SAU.ALLNS == 0 */
10105 case 2: /* SAU.ENABLE == 0, SAU.ALLNS == 1 */
10108 default: /* SAU.ENABLE == 1 */
10109 for (r
= 0; r
< cpu
->sau_sregion
; r
++) {
10110 if (env
->sau
.rlar
[r
] & 1) {
10111 uint32_t base
= env
->sau
.rbar
[r
] & ~0x1f;
10112 uint32_t limit
= env
->sau
.rlar
[r
] | 0x1f;
10114 if (base
<= address
&& limit
>= address
) {
10115 if (base
> addr_page_base
|| limit
< addr_page_limit
) {
10116 sattrs
->subpage
= true;
10118 if (sattrs
->srvalid
) {
10119 /* If we hit in more than one region then we must report
10120 * as Secure, not NS-Callable, with no valid region
10123 sattrs
->ns
= false;
10124 sattrs
->nsc
= false;
10125 sattrs
->sregion
= 0;
10126 sattrs
->srvalid
= false;
10129 if (env
->sau
.rlar
[r
] & 2) {
10130 sattrs
->nsc
= true;
10134 sattrs
->srvalid
= true;
10135 sattrs
->sregion
= r
;
10139 * Address not in this region. We must check whether the
10140 * region covers addresses in the same page as our address.
10141 * In that case we must not report a size that covers the
10142 * whole page for a subsequent hit against a different MPU
10143 * region or the background region, because it would result
10144 * in incorrect TLB hits for subsequent accesses to
10145 * addresses that are in this MPU region.
10147 if (limit
>= base
&&
10148 ranges_overlap(base
, limit
- base
+ 1,
10150 TARGET_PAGE_SIZE
)) {
10151 sattrs
->subpage
= true;
10157 /* The IDAU will override the SAU lookup results if it specifies
10158 * higher security than the SAU does.
10161 if (sattrs
->ns
|| (!idau_nsc
&& sattrs
->nsc
)) {
10162 sattrs
->ns
= false;
10163 sattrs
->nsc
= idau_nsc
;
10170 static bool pmsav8_mpu_lookup(CPUARMState
*env
, uint32_t address
,
10171 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
10172 hwaddr
*phys_ptr
, MemTxAttrs
*txattrs
,
10173 int *prot
, bool *is_subpage
,
10174 ARMMMUFaultInfo
*fi
, uint32_t *mregion
)
10176 /* Perform a PMSAv8 MPU lookup (without also doing the SAU check
10177 * that a full phys-to-virt translation does).
10178 * mregion is (if not NULL) set to the region number which matched,
10179 * or -1 if no region number is returned (MPU off, address did not
10180 * hit a region, address hit in multiple regions).
10181 * We set is_subpage to true if the region hit doesn't cover the
10182 * entire TARGET_PAGE the address is within.
10184 ARMCPU
*cpu
= arm_env_get_cpu(env
);
10185 bool is_user
= regime_is_user(env
, mmu_idx
);
10186 uint32_t secure
= regime_is_secure(env
, mmu_idx
);
10188 int matchregion
= -1;
10190 uint32_t addr_page_base
= address
& TARGET_PAGE_MASK
;
10191 uint32_t addr_page_limit
= addr_page_base
+ (TARGET_PAGE_SIZE
- 1);
10193 *is_subpage
= false;
10194 *phys_ptr
= address
;
10200 /* Unlike the ARM ARM pseudocode, we don't need to check whether this
10201 * was an exception vector read from the vector table (which is always
10202 * done using the default system address map), because those accesses
10203 * are done in arm_v7m_load_vector(), which always does a direct
10204 * read using address_space_ldl(), rather than going via this function.
10206 if (regime_translation_disabled(env
, mmu_idx
)) { /* MPU disabled */
10208 } else if (m_is_ppb_region(env
, address
)) {
10210 } else if (pmsav7_use_background_region(cpu
, mmu_idx
, is_user
)) {
10213 for (n
= (int)cpu
->pmsav7_dregion
- 1; n
>= 0; n
--) {
10214 /* region search */
10215 /* Note that the base address is bits [31:5] from the register
10216 * with bits [4:0] all zeroes, but the limit address is bits
10217 * [31:5] from the register with bits [4:0] all ones.
10219 uint32_t base
= env
->pmsav8
.rbar
[secure
][n
] & ~0x1f;
10220 uint32_t limit
= env
->pmsav8
.rlar
[secure
][n
] | 0x1f;
10222 if (!(env
->pmsav8
.rlar
[secure
][n
] & 0x1)) {
10223 /* Region disabled */
10227 if (address
< base
|| address
> limit
) {
10229 * Address not in this region. We must check whether the
10230 * region covers addresses in the same page as our address.
10231 * In that case we must not report a size that covers the
10232 * whole page for a subsequent hit against a different MPU
10233 * region or the background region, because it would result in
10234 * incorrect TLB hits for subsequent accesses to addresses that
10235 * are in this MPU region.
10237 if (limit
>= base
&&
10238 ranges_overlap(base
, limit
- base
+ 1,
10240 TARGET_PAGE_SIZE
)) {
10241 *is_subpage
= true;
10246 if (base
> addr_page_base
|| limit
< addr_page_limit
) {
10247 *is_subpage
= true;
10251 /* Multiple regions match -- always a failure (unlike
10252 * PMSAv7 where highest-numbered-region wins)
10254 fi
->type
= ARMFault_Permission
;
10265 /* background fault */
10266 fi
->type
= ARMFault_Background
;
10270 if (matchregion
== -1) {
10271 /* hit using the background region */
10272 get_phys_addr_pmsav7_default(env
, mmu_idx
, address
, prot
);
10274 uint32_t ap
= extract32(env
->pmsav8
.rbar
[secure
][matchregion
], 1, 2);
10275 uint32_t xn
= extract32(env
->pmsav8
.rbar
[secure
][matchregion
], 0, 1);
10277 if (m_is_system_region(env
, address
)) {
10278 /* System space is always execute never */
10282 *prot
= simple_ap_to_rw_prot(env
, mmu_idx
, ap
);
10283 if (*prot
&& !xn
) {
10284 *prot
|= PAGE_EXEC
;
10286 /* We don't need to look the attribute up in the MAIR0/MAIR1
10287 * registers because that only tells us about cacheability.
10290 *mregion
= matchregion
;
10294 fi
->type
= ARMFault_Permission
;
10296 return !(*prot
& (1 << access_type
));
10300 static bool get_phys_addr_pmsav8(CPUARMState
*env
, uint32_t address
,
10301 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
10302 hwaddr
*phys_ptr
, MemTxAttrs
*txattrs
,
10303 int *prot
, target_ulong
*page_size
,
10304 ARMMMUFaultInfo
*fi
)
10306 uint32_t secure
= regime_is_secure(env
, mmu_idx
);
10307 V8M_SAttributes sattrs
= {};
10309 bool mpu_is_subpage
;
10311 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
10312 v8m_security_lookup(env
, address
, access_type
, mmu_idx
, &sattrs
);
10313 if (access_type
== MMU_INST_FETCH
) {
10314 /* Instruction fetches always use the MMU bank and the
10315 * transaction attribute determined by the fetch address,
10316 * regardless of CPU state. This is painful for QEMU
10317 * to handle, because it would mean we need to encode
10318 * into the mmu_idx not just the (user, negpri) information
10319 * for the current security state but also that for the
10320 * other security state, which would balloon the number
10321 * of mmu_idx values needed alarmingly.
10322 * Fortunately we can avoid this because it's not actually
10323 * possible to arbitrarily execute code from memory with
10324 * the wrong security attribute: it will always generate
10325 * an exception of some kind or another, apart from the
10326 * special case of an NS CPU executing an SG instruction
10327 * in S&NSC memory. So we always just fail the translation
10328 * here and sort things out in the exception handler
10329 * (including possibly emulating an SG instruction).
10331 if (sattrs
.ns
!= !secure
) {
10333 fi
->type
= ARMFault_QEMU_NSCExec
;
10335 fi
->type
= ARMFault_QEMU_SFault
;
10337 *page_size
= sattrs
.subpage
? 1 : TARGET_PAGE_SIZE
;
10338 *phys_ptr
= address
;
10343 /* For data accesses we always use the MMU bank indicated
10344 * by the current CPU state, but the security attributes
10345 * might downgrade a secure access to nonsecure.
10348 txattrs
->secure
= false;
10349 } else if (!secure
) {
10350 /* NS access to S memory must fault.
10351 * Architecturally we should first check whether the
10352 * MPU information for this address indicates that we
10353 * are doing an unaligned access to Device memory, which
10354 * should generate a UsageFault instead. QEMU does not
10355 * currently check for that kind of unaligned access though.
10356 * If we added it we would need to do so as a special case
10357 * for M_FAKE_FSR_SFAULT in arm_v7m_cpu_do_interrupt().
10359 fi
->type
= ARMFault_QEMU_SFault
;
10360 *page_size
= sattrs
.subpage
? 1 : TARGET_PAGE_SIZE
;
10361 *phys_ptr
= address
;
10368 ret
= pmsav8_mpu_lookup(env
, address
, access_type
, mmu_idx
, phys_ptr
,
10369 txattrs
, prot
, &mpu_is_subpage
, fi
, NULL
);
10371 * TODO: this is a temporary hack to ignore the fact that the SAU region
10372 * is smaller than a page if this is an executable region. We never
10373 * supported small MPU regions, but we did (accidentally) allow small
10374 * SAU regions, and if we now made small SAU regions not be executable
10375 * then this would break previously working guest code. We can't
10376 * remove this until/unless we implement support for execution from
10379 if (*prot
& PAGE_EXEC
) {
10380 sattrs
.subpage
= false;
10382 *page_size
= sattrs
.subpage
|| mpu_is_subpage
? 1 : TARGET_PAGE_SIZE
;
10386 static bool get_phys_addr_pmsav5(CPUARMState
*env
, uint32_t address
,
10387 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
10388 hwaddr
*phys_ptr
, int *prot
,
10389 ARMMMUFaultInfo
*fi
)
10394 bool is_user
= regime_is_user(env
, mmu_idx
);
10396 if (regime_translation_disabled(env
, mmu_idx
)) {
10397 /* MPU disabled. */
10398 *phys_ptr
= address
;
10399 *prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
10403 *phys_ptr
= address
;
10404 for (n
= 7; n
>= 0; n
--) {
10405 base
= env
->cp15
.c6_region
[n
];
10406 if ((base
& 1) == 0) {
10409 mask
= 1 << ((base
>> 1) & 0x1f);
10410 /* Keep this shift separate from the above to avoid an
10411 (undefined) << 32. */
10412 mask
= (mask
<< 1) - 1;
10413 if (((base
^ address
) & ~mask
) == 0) {
10418 fi
->type
= ARMFault_Background
;
10422 if (access_type
== MMU_INST_FETCH
) {
10423 mask
= env
->cp15
.pmsav5_insn_ap
;
10425 mask
= env
->cp15
.pmsav5_data_ap
;
10427 mask
= (mask
>> (n
* 4)) & 0xf;
10430 fi
->type
= ARMFault_Permission
;
10435 fi
->type
= ARMFault_Permission
;
10439 *prot
= PAGE_READ
| PAGE_WRITE
;
10444 *prot
|= PAGE_WRITE
;
10448 *prot
= PAGE_READ
| PAGE_WRITE
;
10452 fi
->type
= ARMFault_Permission
;
10462 /* Bad permission. */
10463 fi
->type
= ARMFault_Permission
;
10467 *prot
|= PAGE_EXEC
;
10471 /* Combine either inner or outer cacheability attributes for normal
10472 * memory, according to table D4-42 and pseudocode procedure
10473 * CombineS1S2AttrHints() of ARM DDI 0487B.b (the ARMv8 ARM).
10475 * NB: only stage 1 includes allocation hints (RW bits), leading to
10478 static uint8_t combine_cacheattr_nibble(uint8_t s1
, uint8_t s2
)
10480 if (s1
== 4 || s2
== 4) {
10481 /* non-cacheable has precedence */
10483 } else if (extract32(s1
, 2, 2) == 0 || extract32(s1
, 2, 2) == 2) {
10484 /* stage 1 write-through takes precedence */
10486 } else if (extract32(s2
, 2, 2) == 2) {
10487 /* stage 2 write-through takes precedence, but the allocation hint
10488 * is still taken from stage 1
10490 return (2 << 2) | extract32(s1
, 0, 2);
10491 } else { /* write-back */
10496 /* Combine S1 and S2 cacheability/shareability attributes, per D4.5.4
10497 * and CombineS1S2Desc()
10499 * @s1: Attributes from stage 1 walk
10500 * @s2: Attributes from stage 2 walk
10502 static ARMCacheAttrs
combine_cacheattrs(ARMCacheAttrs s1
, ARMCacheAttrs s2
)
10504 uint8_t s1lo
= extract32(s1
.attrs
, 0, 4), s2lo
= extract32(s2
.attrs
, 0, 4);
10505 uint8_t s1hi
= extract32(s1
.attrs
, 4, 4), s2hi
= extract32(s2
.attrs
, 4, 4);
10508 /* Combine shareability attributes (table D4-43) */
10509 if (s1
.shareability
== 2 || s2
.shareability
== 2) {
10510 /* if either are outer-shareable, the result is outer-shareable */
10511 ret
.shareability
= 2;
10512 } else if (s1
.shareability
== 3 || s2
.shareability
== 3) {
10513 /* if either are inner-shareable, the result is inner-shareable */
10514 ret
.shareability
= 3;
10516 /* both non-shareable */
10517 ret
.shareability
= 0;
10520 /* Combine memory type and cacheability attributes */
10521 if (s1hi
== 0 || s2hi
== 0) {
10522 /* Device has precedence over normal */
10523 if (s1lo
== 0 || s2lo
== 0) {
10524 /* nGnRnE has precedence over anything */
10526 } else if (s1lo
== 4 || s2lo
== 4) {
10527 /* non-Reordering has precedence over Reordering */
10528 ret
.attrs
= 4; /* nGnRE */
10529 } else if (s1lo
== 8 || s2lo
== 8) {
10530 /* non-Gathering has precedence over Gathering */
10531 ret
.attrs
= 8; /* nGRE */
10533 ret
.attrs
= 0xc; /* GRE */
10536 /* Any location for which the resultant memory type is any
10537 * type of Device memory is always treated as Outer Shareable.
10539 ret
.shareability
= 2;
10540 } else { /* Normal memory */
10541 /* Outer/inner cacheability combine independently */
10542 ret
.attrs
= combine_cacheattr_nibble(s1hi
, s2hi
) << 4
10543 | combine_cacheattr_nibble(s1lo
, s2lo
);
10545 if (ret
.attrs
== 0x44) {
10546 /* Any location for which the resultant memory type is Normal
10547 * Inner Non-cacheable, Outer Non-cacheable is always treated
10548 * as Outer Shareable.
10550 ret
.shareability
= 2;
10558 /* get_phys_addr - get the physical address for this virtual address
10560 * Find the physical address corresponding to the given virtual address,
10561 * by doing a translation table walk on MMU based systems or using the
10562 * MPU state on MPU based systems.
10564 * Returns false if the translation was successful. Otherwise, phys_ptr, attrs,
10565 * prot and page_size may not be filled in, and the populated fsr value provides
10566 * information on why the translation aborted, in the format of a
10567 * DFSR/IFSR fault register, with the following caveats:
10568 * * we honour the short vs long DFSR format differences.
10569 * * the WnR bit is never set (the caller must do this).
10570 * * for PSMAv5 based systems we don't bother to return a full FSR format
10573 * @env: CPUARMState
10574 * @address: virtual address to get physical address for
10575 * @access_type: 0 for read, 1 for write, 2 for execute
10576 * @mmu_idx: MMU index indicating required translation regime
10577 * @phys_ptr: set to the physical address corresponding to the virtual address
10578 * @attrs: set to the memory transaction attributes to use
10579 * @prot: set to the permissions for the page containing phys_ptr
10580 * @page_size: set to the size of the page containing phys_ptr
10581 * @fi: set to fault info if the translation fails
10582 * @cacheattrs: (if non-NULL) set to the cacheability/shareability attributes
10584 static bool get_phys_addr(CPUARMState
*env
, target_ulong address
,
10585 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
10586 hwaddr
*phys_ptr
, MemTxAttrs
*attrs
, int *prot
,
10587 target_ulong
*page_size
,
10588 ARMMMUFaultInfo
*fi
, ARMCacheAttrs
*cacheattrs
)
10590 if (mmu_idx
== ARMMMUIdx_S12NSE0
|| mmu_idx
== ARMMMUIdx_S12NSE1
) {
10591 /* Call ourselves recursively to do the stage 1 and then stage 2
10594 if (arm_feature(env
, ARM_FEATURE_EL2
)) {
10598 ARMCacheAttrs cacheattrs2
= {};
10600 ret
= get_phys_addr(env
, address
, access_type
,
10601 stage_1_mmu_idx(mmu_idx
), &ipa
, attrs
,
10602 prot
, page_size
, fi
, cacheattrs
);
10604 /* If S1 fails or S2 is disabled, return early. */
10605 if (ret
|| regime_translation_disabled(env
, ARMMMUIdx_S2NS
)) {
10610 /* S1 is done. Now do S2 translation. */
10611 ret
= get_phys_addr_lpae(env
, ipa
, access_type
, ARMMMUIdx_S2NS
,
10612 phys_ptr
, attrs
, &s2_prot
,
10614 cacheattrs
!= NULL
? &cacheattrs2
: NULL
);
10616 /* Combine the S1 and S2 perms. */
10619 /* Combine the S1 and S2 cache attributes, if needed */
10620 if (!ret
&& cacheattrs
!= NULL
) {
10621 *cacheattrs
= combine_cacheattrs(*cacheattrs
, cacheattrs2
);
10627 * For non-EL2 CPUs a stage1+stage2 translation is just stage 1.
10629 mmu_idx
= stage_1_mmu_idx(mmu_idx
);
10633 /* The page table entries may downgrade secure to non-secure, but
10634 * cannot upgrade an non-secure translation regime's attributes
10637 attrs
->secure
= regime_is_secure(env
, mmu_idx
);
10638 attrs
->user
= regime_is_user(env
, mmu_idx
);
10640 /* Fast Context Switch Extension. This doesn't exist at all in v8.
10641 * In v7 and earlier it affects all stage 1 translations.
10643 if (address
< 0x02000000 && mmu_idx
!= ARMMMUIdx_S2NS
10644 && !arm_feature(env
, ARM_FEATURE_V8
)) {
10645 if (regime_el(env
, mmu_idx
) == 3) {
10646 address
+= env
->cp15
.fcseidr_s
;
10648 address
+= env
->cp15
.fcseidr_ns
;
10652 if (arm_feature(env
, ARM_FEATURE_PMSA
)) {
10654 *page_size
= TARGET_PAGE_SIZE
;
10656 if (arm_feature(env
, ARM_FEATURE_V8
)) {
10658 ret
= get_phys_addr_pmsav8(env
, address
, access_type
, mmu_idx
,
10659 phys_ptr
, attrs
, prot
, page_size
, fi
);
10660 } else if (arm_feature(env
, ARM_FEATURE_V7
)) {
10662 ret
= get_phys_addr_pmsav7(env
, address
, access_type
, mmu_idx
,
10663 phys_ptr
, prot
, page_size
, fi
);
10666 ret
= get_phys_addr_pmsav5(env
, address
, access_type
, mmu_idx
,
10667 phys_ptr
, prot
, fi
);
10669 qemu_log_mask(CPU_LOG_MMU
, "PMSA MPU lookup for %s at 0x%08" PRIx32
10670 " mmu_idx %u -> %s (prot %c%c%c)\n",
10671 access_type
== MMU_DATA_LOAD
? "reading" :
10672 (access_type
== MMU_DATA_STORE
? "writing" : "execute"),
10673 (uint32_t)address
, mmu_idx
,
10674 ret
? "Miss" : "Hit",
10675 *prot
& PAGE_READ
? 'r' : '-',
10676 *prot
& PAGE_WRITE
? 'w' : '-',
10677 *prot
& PAGE_EXEC
? 'x' : '-');
10682 /* Definitely a real MMU, not an MPU */
10684 if (regime_translation_disabled(env
, mmu_idx
)) {
10685 /* MMU disabled. */
10686 *phys_ptr
= address
;
10687 *prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
10688 *page_size
= TARGET_PAGE_SIZE
;
10692 if (regime_using_lpae_format(env
, mmu_idx
)) {
10693 return get_phys_addr_lpae(env
, address
, access_type
, mmu_idx
,
10694 phys_ptr
, attrs
, prot
, page_size
,
10696 } else if (regime_sctlr(env
, mmu_idx
) & SCTLR_XP
) {
10697 return get_phys_addr_v6(env
, address
, access_type
, mmu_idx
,
10698 phys_ptr
, attrs
, prot
, page_size
, fi
);
10700 return get_phys_addr_v5(env
, address
, access_type
, mmu_idx
,
10701 phys_ptr
, prot
, page_size
, fi
);
10705 /* Walk the page table and (if the mapping exists) add the page
10706 * to the TLB. Return false on success, or true on failure. Populate
10707 * fsr with ARM DFSR/IFSR fault register format value on failure.
10709 bool arm_tlb_fill(CPUState
*cs
, vaddr address
,
10710 MMUAccessType access_type
, int mmu_idx
,
10711 ARMMMUFaultInfo
*fi
)
10713 ARMCPU
*cpu
= ARM_CPU(cs
);
10714 CPUARMState
*env
= &cpu
->env
;
10716 target_ulong page_size
;
10719 MemTxAttrs attrs
= {};
10721 ret
= get_phys_addr(env
, address
, access_type
,
10722 core_to_arm_mmu_idx(env
, mmu_idx
), &phys_addr
,
10723 &attrs
, &prot
, &page_size
, fi
, NULL
);
10726 * Map a single [sub]page. Regions smaller than our declared
10727 * target page size are handled specially, so for those we
10728 * pass in the exact addresses.
10730 if (page_size
>= TARGET_PAGE_SIZE
) {
10731 phys_addr
&= TARGET_PAGE_MASK
;
10732 address
&= TARGET_PAGE_MASK
;
10734 tlb_set_page_with_attrs(cs
, address
, phys_addr
, attrs
,
10735 prot
, mmu_idx
, page_size
);
10742 hwaddr
arm_cpu_get_phys_page_attrs_debug(CPUState
*cs
, vaddr addr
,
10745 ARMCPU
*cpu
= ARM_CPU(cs
);
10746 CPUARMState
*env
= &cpu
->env
;
10748 target_ulong page_size
;
10751 ARMMMUFaultInfo fi
= {};
10752 ARMMMUIdx mmu_idx
= core_to_arm_mmu_idx(env
, cpu_mmu_index(env
, false));
10754 *attrs
= (MemTxAttrs
) {};
10756 ret
= get_phys_addr(env
, addr
, 0, mmu_idx
, &phys_addr
,
10757 attrs
, &prot
, &page_size
, &fi
, NULL
);
10765 uint32_t HELPER(v7m_mrs
)(CPUARMState
*env
, uint32_t reg
)
10768 unsigned el
= arm_current_el(env
);
10770 /* First handle registers which unprivileged can read */
10773 case 0 ... 7: /* xPSR sub-fields */
10775 if ((reg
& 1) && el
) {
10776 mask
|= XPSR_EXCP
; /* IPSR (unpriv. reads as zero) */
10779 mask
|= XPSR_NZCV
| XPSR_Q
; /* APSR */
10781 /* EPSR reads as zero */
10782 return xpsr_read(env
) & mask
;
10784 case 20: /* CONTROL */
10785 return env
->v7m
.control
[env
->v7m
.secure
];
10786 case 0x94: /* CONTROL_NS */
10787 /* We have to handle this here because unprivileged Secure code
10788 * can read the NS CONTROL register.
10790 if (!env
->v7m
.secure
) {
10793 return env
->v7m
.control
[M_REG_NS
];
10797 return 0; /* unprivileged reads others as zero */
10800 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
10802 case 0x88: /* MSP_NS */
10803 if (!env
->v7m
.secure
) {
10806 return env
->v7m
.other_ss_msp
;
10807 case 0x89: /* PSP_NS */
10808 if (!env
->v7m
.secure
) {
10811 return env
->v7m
.other_ss_psp
;
10812 case 0x8a: /* MSPLIM_NS */
10813 if (!env
->v7m
.secure
) {
10816 return env
->v7m
.msplim
[M_REG_NS
];
10817 case 0x8b: /* PSPLIM_NS */
10818 if (!env
->v7m
.secure
) {
10821 return env
->v7m
.psplim
[M_REG_NS
];
10822 case 0x90: /* PRIMASK_NS */
10823 if (!env
->v7m
.secure
) {
10826 return env
->v7m
.primask
[M_REG_NS
];
10827 case 0x91: /* BASEPRI_NS */
10828 if (!env
->v7m
.secure
) {
10831 return env
->v7m
.basepri
[M_REG_NS
];
10832 case 0x93: /* FAULTMASK_NS */
10833 if (!env
->v7m
.secure
) {
10836 return env
->v7m
.faultmask
[M_REG_NS
];
10837 case 0x98: /* SP_NS */
10839 /* This gives the non-secure SP selected based on whether we're
10840 * currently in handler mode or not, using the NS CONTROL.SPSEL.
10842 bool spsel
= env
->v7m
.control
[M_REG_NS
] & R_V7M_CONTROL_SPSEL_MASK
;
10844 if (!env
->v7m
.secure
) {
10847 if (!arm_v7m_is_handler_mode(env
) && spsel
) {
10848 return env
->v7m
.other_ss_psp
;
10850 return env
->v7m
.other_ss_msp
;
10860 return v7m_using_psp(env
) ? env
->v7m
.other_sp
: env
->regs
[13];
10862 return v7m_using_psp(env
) ? env
->regs
[13] : env
->v7m
.other_sp
;
10863 case 10: /* MSPLIM */
10864 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
10867 return env
->v7m
.msplim
[env
->v7m
.secure
];
10868 case 11: /* PSPLIM */
10869 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
10872 return env
->v7m
.psplim
[env
->v7m
.secure
];
10873 case 16: /* PRIMASK */
10874 return env
->v7m
.primask
[env
->v7m
.secure
];
10875 case 17: /* BASEPRI */
10876 case 18: /* BASEPRI_MAX */
10877 return env
->v7m
.basepri
[env
->v7m
.secure
];
10878 case 19: /* FAULTMASK */
10879 return env
->v7m
.faultmask
[env
->v7m
.secure
];
10882 qemu_log_mask(LOG_GUEST_ERROR
, "Attempt to read unknown special"
10883 " register %d\n", reg
);
10888 void HELPER(v7m_msr
)(CPUARMState
*env
, uint32_t maskreg
, uint32_t val
)
10890 /* We're passed bits [11..0] of the instruction; extract
10891 * SYSm and the mask bits.
10892 * Invalid combinations of SYSm and mask are UNPREDICTABLE;
10893 * we choose to treat them as if the mask bits were valid.
10894 * NB that the pseudocode 'mask' variable is bits [11..10],
10895 * whereas ours is [11..8].
10897 uint32_t mask
= extract32(maskreg
, 8, 4);
10898 uint32_t reg
= extract32(maskreg
, 0, 8);
10900 if (arm_current_el(env
) == 0 && reg
> 7) {
10901 /* only xPSR sub-fields may be written by unprivileged */
10905 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
10907 case 0x88: /* MSP_NS */
10908 if (!env
->v7m
.secure
) {
10911 env
->v7m
.other_ss_msp
= val
;
10913 case 0x89: /* PSP_NS */
10914 if (!env
->v7m
.secure
) {
10917 env
->v7m
.other_ss_psp
= val
;
10919 case 0x8a: /* MSPLIM_NS */
10920 if (!env
->v7m
.secure
) {
10923 env
->v7m
.msplim
[M_REG_NS
] = val
& ~7;
10925 case 0x8b: /* PSPLIM_NS */
10926 if (!env
->v7m
.secure
) {
10929 env
->v7m
.psplim
[M_REG_NS
] = val
& ~7;
10931 case 0x90: /* PRIMASK_NS */
10932 if (!env
->v7m
.secure
) {
10935 env
->v7m
.primask
[M_REG_NS
] = val
& 1;
10937 case 0x91: /* BASEPRI_NS */
10938 if (!env
->v7m
.secure
|| !arm_feature(env
, ARM_FEATURE_M_MAIN
)) {
10941 env
->v7m
.basepri
[M_REG_NS
] = val
& 0xff;
10943 case 0x93: /* FAULTMASK_NS */
10944 if (!env
->v7m
.secure
|| !arm_feature(env
, ARM_FEATURE_M_MAIN
)) {
10947 env
->v7m
.faultmask
[M_REG_NS
] = val
& 1;
10949 case 0x94: /* CONTROL_NS */
10950 if (!env
->v7m
.secure
) {
10953 write_v7m_control_spsel_for_secstate(env
,
10954 val
& R_V7M_CONTROL_SPSEL_MASK
,
10956 if (arm_feature(env
, ARM_FEATURE_M_MAIN
)) {
10957 env
->v7m
.control
[M_REG_NS
] &= ~R_V7M_CONTROL_NPRIV_MASK
;
10958 env
->v7m
.control
[M_REG_NS
] |= val
& R_V7M_CONTROL_NPRIV_MASK
;
10961 case 0x98: /* SP_NS */
10963 /* This gives the non-secure SP selected based on whether we're
10964 * currently in handler mode or not, using the NS CONTROL.SPSEL.
10966 bool spsel
= env
->v7m
.control
[M_REG_NS
] & R_V7M_CONTROL_SPSEL_MASK
;
10968 if (!env
->v7m
.secure
) {
10971 if (!arm_v7m_is_handler_mode(env
) && spsel
) {
10972 env
->v7m
.other_ss_psp
= val
;
10974 env
->v7m
.other_ss_msp
= val
;
10984 case 0 ... 7: /* xPSR sub-fields */
10985 /* only APSR is actually writable */
10987 uint32_t apsrmask
= 0;
10990 apsrmask
|= XPSR_NZCV
| XPSR_Q
;
10992 if ((mask
& 4) && arm_feature(env
, ARM_FEATURE_THUMB_DSP
)) {
10993 apsrmask
|= XPSR_GE
;
10995 xpsr_write(env
, val
, apsrmask
);
10999 if (v7m_using_psp(env
)) {
11000 env
->v7m
.other_sp
= val
;
11002 env
->regs
[13] = val
;
11006 if (v7m_using_psp(env
)) {
11007 env
->regs
[13] = val
;
11009 env
->v7m
.other_sp
= val
;
11012 case 10: /* MSPLIM */
11013 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
11016 env
->v7m
.msplim
[env
->v7m
.secure
] = val
& ~7;
11018 case 11: /* PSPLIM */
11019 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
11022 env
->v7m
.psplim
[env
->v7m
.secure
] = val
& ~7;
11024 case 16: /* PRIMASK */
11025 env
->v7m
.primask
[env
->v7m
.secure
] = val
& 1;
11027 case 17: /* BASEPRI */
11028 if (!arm_feature(env
, ARM_FEATURE_M_MAIN
)) {
11031 env
->v7m
.basepri
[env
->v7m
.secure
] = val
& 0xff;
11033 case 18: /* BASEPRI_MAX */
11034 if (!arm_feature(env
, ARM_FEATURE_M_MAIN
)) {
11038 if (val
!= 0 && (val
< env
->v7m
.basepri
[env
->v7m
.secure
]
11039 || env
->v7m
.basepri
[env
->v7m
.secure
] == 0)) {
11040 env
->v7m
.basepri
[env
->v7m
.secure
] = val
;
11043 case 19: /* FAULTMASK */
11044 if (!arm_feature(env
, ARM_FEATURE_M_MAIN
)) {
11047 env
->v7m
.faultmask
[env
->v7m
.secure
] = val
& 1;
11049 case 20: /* CONTROL */
11050 /* Writing to the SPSEL bit only has an effect if we are in
11051 * thread mode; other bits can be updated by any privileged code.
11052 * write_v7m_control_spsel() deals with updating the SPSEL bit in
11053 * env->v7m.control, so we only need update the others.
11054 * For v7M, we must just ignore explicit writes to SPSEL in handler
11055 * mode; for v8M the write is permitted but will have no effect.
11057 if (arm_feature(env
, ARM_FEATURE_V8
) ||
11058 !arm_v7m_is_handler_mode(env
)) {
11059 write_v7m_control_spsel(env
, (val
& R_V7M_CONTROL_SPSEL_MASK
) != 0);
11061 if (arm_feature(env
, ARM_FEATURE_M_MAIN
)) {
11062 env
->v7m
.control
[env
->v7m
.secure
] &= ~R_V7M_CONTROL_NPRIV_MASK
;
11063 env
->v7m
.control
[env
->v7m
.secure
] |= val
& R_V7M_CONTROL_NPRIV_MASK
;
11068 qemu_log_mask(LOG_GUEST_ERROR
, "Attempt to write unknown special"
11069 " register %d\n", reg
);
11074 uint32_t HELPER(v7m_tt
)(CPUARMState
*env
, uint32_t addr
, uint32_t op
)
11076 /* Implement the TT instruction. op is bits [7:6] of the insn. */
11077 bool forceunpriv
= op
& 1;
11079 V8M_SAttributes sattrs
= {};
11081 bool r
, rw
, nsr
, nsrw
, mrvalid
;
11083 ARMMMUFaultInfo fi
= {};
11084 MemTxAttrs attrs
= {};
11089 bool targetsec
= env
->v7m
.secure
;
11092 /* Work out what the security state and privilege level we're
11093 * interested in is...
11096 targetsec
= !targetsec
;
11100 targetpriv
= false;
11102 targetpriv
= arm_v7m_is_handler_mode(env
) ||
11103 !(env
->v7m
.control
[targetsec
] & R_V7M_CONTROL_NPRIV_MASK
);
11106 /* ...and then figure out which MMU index this is */
11107 mmu_idx
= arm_v7m_mmu_idx_for_secstate_and_priv(env
, targetsec
, targetpriv
);
11109 /* We know that the MPU and SAU don't care about the access type
11110 * for our purposes beyond that we don't want to claim to be
11111 * an insn fetch, so we arbitrarily call this a read.
11114 /* MPU region info only available for privileged or if
11115 * inspecting the other MPU state.
11117 if (arm_current_el(env
) != 0 || alt
) {
11118 /* We can ignore the return value as prot is always set */
11119 pmsav8_mpu_lookup(env
, addr
, MMU_DATA_LOAD
, mmu_idx
,
11120 &phys_addr
, &attrs
, &prot
, &is_subpage
,
11122 if (mregion
== -1) {
11128 r
= prot
& PAGE_READ
;
11129 rw
= prot
& PAGE_WRITE
;
11137 if (env
->v7m
.secure
) {
11138 v8m_security_lookup(env
, addr
, MMU_DATA_LOAD
, mmu_idx
, &sattrs
);
11139 nsr
= sattrs
.ns
&& r
;
11140 nsrw
= sattrs
.ns
&& rw
;
11147 tt_resp
= (sattrs
.iregion
<< 24) |
11148 (sattrs
.irvalid
<< 23) |
11149 ((!sattrs
.ns
) << 22) |
11154 (sattrs
.srvalid
<< 17) |
11156 (sattrs
.sregion
<< 8) |
11164 void HELPER(dc_zva
)(CPUARMState
*env
, uint64_t vaddr_in
)
11166 /* Implement DC ZVA, which zeroes a fixed-length block of memory.
11167 * Note that we do not implement the (architecturally mandated)
11168 * alignment fault for attempts to use this on Device memory
11169 * (which matches the usual QEMU behaviour of not implementing either
11170 * alignment faults or any memory attribute handling).
11173 ARMCPU
*cpu
= arm_env_get_cpu(env
);
11174 uint64_t blocklen
= 4 << cpu
->dcz_blocksize
;
11175 uint64_t vaddr
= vaddr_in
& ~(blocklen
- 1);
11177 #ifndef CONFIG_USER_ONLY
11179 /* Slightly awkwardly, QEMU's TARGET_PAGE_SIZE may be less than
11180 * the block size so we might have to do more than one TLB lookup.
11181 * We know that in fact for any v8 CPU the page size is at least 4K
11182 * and the block size must be 2K or less, but TARGET_PAGE_SIZE is only
11183 * 1K as an artefact of legacy v5 subpage support being present in the
11184 * same QEMU executable.
11186 int maxidx
= DIV_ROUND_UP(blocklen
, TARGET_PAGE_SIZE
);
11187 void *hostaddr
[maxidx
];
11189 unsigned mmu_idx
= cpu_mmu_index(env
, false);
11190 TCGMemOpIdx oi
= make_memop_idx(MO_UB
, mmu_idx
);
11192 for (try = 0; try < 2; try++) {
11194 for (i
= 0; i
< maxidx
; i
++) {
11195 hostaddr
[i
] = tlb_vaddr_to_host(env
,
11196 vaddr
+ TARGET_PAGE_SIZE
* i
,
11198 if (!hostaddr
[i
]) {
11203 /* If it's all in the TLB it's fair game for just writing to;
11204 * we know we don't need to update dirty status, etc.
11206 for (i
= 0; i
< maxidx
- 1; i
++) {
11207 memset(hostaddr
[i
], 0, TARGET_PAGE_SIZE
);
11209 memset(hostaddr
[i
], 0, blocklen
- (i
* TARGET_PAGE_SIZE
));
11212 /* OK, try a store and see if we can populate the tlb. This
11213 * might cause an exception if the memory isn't writable,
11214 * in which case we will longjmp out of here. We must for
11215 * this purpose use the actual register value passed to us
11216 * so that we get the fault address right.
11218 helper_ret_stb_mmu(env
, vaddr_in
, 0, oi
, GETPC());
11219 /* Now we can populate the other TLB entries, if any */
11220 for (i
= 0; i
< maxidx
; i
++) {
11221 uint64_t va
= vaddr
+ TARGET_PAGE_SIZE
* i
;
11222 if (va
!= (vaddr_in
& TARGET_PAGE_MASK
)) {
11223 helper_ret_stb_mmu(env
, va
, 0, oi
, GETPC());
11228 /* Slow path (probably attempt to do this to an I/O device or
11229 * similar, or clearing of a block of code we have translations
11230 * cached for). Just do a series of byte writes as the architecture
11231 * demands. It's not worth trying to use a cpu_physical_memory_map(),
11232 * memset(), unmap() sequence here because:
11233 * + we'd need to account for the blocksize being larger than a page
11234 * + the direct-RAM access case is almost always going to be dealt
11235 * with in the fastpath code above, so there's no speed benefit
11236 * + we would have to deal with the map returning NULL because the
11237 * bounce buffer was in use
11239 for (i
= 0; i
< blocklen
; i
++) {
11240 helper_ret_stb_mmu(env
, vaddr
+ i
, 0, oi
, GETPC());
11244 memset(g2h(vaddr
), 0, blocklen
);
11248 /* Note that signed overflow is undefined in C. The following routines are
11249 careful to use unsigned types where modulo arithmetic is required.
11250 Failure to do so _will_ break on newer gcc. */
11252 /* Signed saturating arithmetic. */
11254 /* Perform 16-bit signed saturating addition. */
11255 static inline uint16_t add16_sat(uint16_t a
, uint16_t b
)
11260 if (((res
^ a
) & 0x8000) && !((a
^ b
) & 0x8000)) {
11269 /* Perform 8-bit signed saturating addition. */
11270 static inline uint8_t add8_sat(uint8_t a
, uint8_t b
)
11275 if (((res
^ a
) & 0x80) && !((a
^ b
) & 0x80)) {
11284 /* Perform 16-bit signed saturating subtraction. */
11285 static inline uint16_t sub16_sat(uint16_t a
, uint16_t b
)
11290 if (((res
^ a
) & 0x8000) && ((a
^ b
) & 0x8000)) {
11299 /* Perform 8-bit signed saturating subtraction. */
11300 static inline uint8_t sub8_sat(uint8_t a
, uint8_t b
)
11305 if (((res
^ a
) & 0x80) && ((a
^ b
) & 0x80)) {
11314 #define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16);
11315 #define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16);
11316 #define ADD8(a, b, n) RESULT(add8_sat(a, b), n, 8);
11317 #define SUB8(a, b, n) RESULT(sub8_sat(a, b), n, 8);
11320 #include "op_addsub.h"
11322 /* Unsigned saturating arithmetic. */
11323 static inline uint16_t add16_usat(uint16_t a
, uint16_t b
)
11332 static inline uint16_t sub16_usat(uint16_t a
, uint16_t b
)
11340 static inline uint8_t add8_usat(uint8_t a
, uint8_t b
)
11349 static inline uint8_t sub8_usat(uint8_t a
, uint8_t b
)
11357 #define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16);
11358 #define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16);
11359 #define ADD8(a, b, n) RESULT(add8_usat(a, b), n, 8);
11360 #define SUB8(a, b, n) RESULT(sub8_usat(a, b), n, 8);
11363 #include "op_addsub.h"
11365 /* Signed modulo arithmetic. */
11366 #define SARITH16(a, b, n, op) do { \
11368 sum = (int32_t)(int16_t)(a) op (int32_t)(int16_t)(b); \
11369 RESULT(sum, n, 16); \
11371 ge |= 3 << (n * 2); \
11374 #define SARITH8(a, b, n, op) do { \
11376 sum = (int32_t)(int8_t)(a) op (int32_t)(int8_t)(b); \
11377 RESULT(sum, n, 8); \
11383 #define ADD16(a, b, n) SARITH16(a, b, n, +)
11384 #define SUB16(a, b, n) SARITH16(a, b, n, -)
11385 #define ADD8(a, b, n) SARITH8(a, b, n, +)
11386 #define SUB8(a, b, n) SARITH8(a, b, n, -)
11390 #include "op_addsub.h"
11392 /* Unsigned modulo arithmetic. */
11393 #define ADD16(a, b, n) do { \
11395 sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \
11396 RESULT(sum, n, 16); \
11397 if ((sum >> 16) == 1) \
11398 ge |= 3 << (n * 2); \
11401 #define ADD8(a, b, n) do { \
11403 sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \
11404 RESULT(sum, n, 8); \
11405 if ((sum >> 8) == 1) \
11409 #define SUB16(a, b, n) do { \
11411 sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \
11412 RESULT(sum, n, 16); \
11413 if ((sum >> 16) == 0) \
11414 ge |= 3 << (n * 2); \
11417 #define SUB8(a, b, n) do { \
11419 sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \
11420 RESULT(sum, n, 8); \
11421 if ((sum >> 8) == 0) \
11428 #include "op_addsub.h"
11430 /* Halved signed arithmetic. */
11431 #define ADD16(a, b, n) \
11432 RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16)
11433 #define SUB16(a, b, n) \
11434 RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16)
11435 #define ADD8(a, b, n) \
11436 RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8)
11437 #define SUB8(a, b, n) \
11438 RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8)
11441 #include "op_addsub.h"
11443 /* Halved unsigned arithmetic. */
11444 #define ADD16(a, b, n) \
11445 RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16)
11446 #define SUB16(a, b, n) \
11447 RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16)
11448 #define ADD8(a, b, n) \
11449 RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8)
11450 #define SUB8(a, b, n) \
11451 RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8)
11454 #include "op_addsub.h"
11456 static inline uint8_t do_usad(uint8_t a
, uint8_t b
)
11464 /* Unsigned sum of absolute byte differences. */
11465 uint32_t HELPER(usad8
)(uint32_t a
, uint32_t b
)
11468 sum
= do_usad(a
, b
);
11469 sum
+= do_usad(a
>> 8, b
>> 8);
11470 sum
+= do_usad(a
>> 16, b
>>16);
11471 sum
+= do_usad(a
>> 24, b
>> 24);
11475 /* For ARMv6 SEL instruction. */
11476 uint32_t HELPER(sel_flags
)(uint32_t flags
, uint32_t a
, uint32_t b
)
11488 mask
|= 0xff000000;
11489 return (a
& mask
) | (b
& ~mask
);
11492 /* VFP support. We follow the convention used for VFP instructions:
11493 Single precision routines have a "s" suffix, double precision a
11496 /* Convert host exception flags to vfp form. */
11497 static inline int vfp_exceptbits_from_host(int host_bits
)
11499 int target_bits
= 0;
11501 if (host_bits
& float_flag_invalid
)
11503 if (host_bits
& float_flag_divbyzero
)
11505 if (host_bits
& float_flag_overflow
)
11507 if (host_bits
& (float_flag_underflow
| float_flag_output_denormal
))
11509 if (host_bits
& float_flag_inexact
)
11510 target_bits
|= 0x10;
11511 if (host_bits
& float_flag_input_denormal
)
11512 target_bits
|= 0x80;
11513 return target_bits
;
11516 uint32_t HELPER(vfp_get_fpscr
)(CPUARMState
*env
)
11521 fpscr
= (env
->vfp
.xregs
[ARM_VFP_FPSCR
] & 0xffc8ffff)
11522 | (env
->vfp
.vec_len
<< 16)
11523 | (env
->vfp
.vec_stride
<< 20);
11525 i
= get_float_exception_flags(&env
->vfp
.fp_status
);
11526 i
|= get_float_exception_flags(&env
->vfp
.standard_fp_status
);
11527 /* FZ16 does not generate an input denormal exception. */
11528 i
|= (get_float_exception_flags(&env
->vfp
.fp_status_f16
)
11529 & ~float_flag_input_denormal
);
11531 fpscr
|= vfp_exceptbits_from_host(i
);
11535 uint32_t vfp_get_fpscr(CPUARMState
*env
)
11537 return HELPER(vfp_get_fpscr
)(env
);
11540 /* Convert vfp exception flags to target form. */
11541 static inline int vfp_exceptbits_to_host(int target_bits
)
11545 if (target_bits
& 1)
11546 host_bits
|= float_flag_invalid
;
11547 if (target_bits
& 2)
11548 host_bits
|= float_flag_divbyzero
;
11549 if (target_bits
& 4)
11550 host_bits
|= float_flag_overflow
;
11551 if (target_bits
& 8)
11552 host_bits
|= float_flag_underflow
;
11553 if (target_bits
& 0x10)
11554 host_bits
|= float_flag_inexact
;
11555 if (target_bits
& 0x80)
11556 host_bits
|= float_flag_input_denormal
;
11560 void HELPER(vfp_set_fpscr
)(CPUARMState
*env
, uint32_t val
)
11565 /* When ARMv8.2-FP16 is not supported, FZ16 is RES0. */
11566 if (!arm_feature(env
, ARM_FEATURE_V8_FP16
)) {
11570 changed
= env
->vfp
.xregs
[ARM_VFP_FPSCR
];
11571 env
->vfp
.xregs
[ARM_VFP_FPSCR
] = (val
& 0xffc8ffff);
11572 env
->vfp
.vec_len
= (val
>> 16) & 7;
11573 env
->vfp
.vec_stride
= (val
>> 20) & 3;
11576 if (changed
& (3 << 22)) {
11577 i
= (val
>> 22) & 3;
11579 case FPROUNDING_TIEEVEN
:
11580 i
= float_round_nearest_even
;
11582 case FPROUNDING_POSINF
:
11583 i
= float_round_up
;
11585 case FPROUNDING_NEGINF
:
11586 i
= float_round_down
;
11588 case FPROUNDING_ZERO
:
11589 i
= float_round_to_zero
;
11592 set_float_rounding_mode(i
, &env
->vfp
.fp_status
);
11593 set_float_rounding_mode(i
, &env
->vfp
.fp_status_f16
);
11595 if (changed
& FPCR_FZ16
) {
11596 bool ftz_enabled
= val
& FPCR_FZ16
;
11597 set_flush_to_zero(ftz_enabled
, &env
->vfp
.fp_status_f16
);
11598 set_flush_inputs_to_zero(ftz_enabled
, &env
->vfp
.fp_status_f16
);
11600 if (changed
& FPCR_FZ
) {
11601 bool ftz_enabled
= val
& FPCR_FZ
;
11602 set_flush_to_zero(ftz_enabled
, &env
->vfp
.fp_status
);
11603 set_flush_inputs_to_zero(ftz_enabled
, &env
->vfp
.fp_status
);
11605 if (changed
& FPCR_DN
) {
11606 bool dnan_enabled
= val
& FPCR_DN
;
11607 set_default_nan_mode(dnan_enabled
, &env
->vfp
.fp_status
);
11608 set_default_nan_mode(dnan_enabled
, &env
->vfp
.fp_status_f16
);
11611 /* The exception flags are ORed together when we read fpscr so we
11612 * only need to preserve the current state in one of our
11613 * float_status values.
11615 i
= vfp_exceptbits_to_host(val
);
11616 set_float_exception_flags(i
, &env
->vfp
.fp_status
);
11617 set_float_exception_flags(0, &env
->vfp
.fp_status_f16
);
11618 set_float_exception_flags(0, &env
->vfp
.standard_fp_status
);
11621 void vfp_set_fpscr(CPUARMState
*env
, uint32_t val
)
11623 HELPER(vfp_set_fpscr
)(env
, val
);
11626 #define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p))
11628 #define VFP_BINOP(name) \
11629 float32 VFP_HELPER(name, s)(float32 a, float32 b, void *fpstp) \
11631 float_status *fpst = fpstp; \
11632 return float32_ ## name(a, b, fpst); \
11634 float64 VFP_HELPER(name, d)(float64 a, float64 b, void *fpstp) \
11636 float_status *fpst = fpstp; \
11637 return float64_ ## name(a, b, fpst); \
11649 float32
VFP_HELPER(neg
, s
)(float32 a
)
11651 return float32_chs(a
);
11654 float64
VFP_HELPER(neg
, d
)(float64 a
)
11656 return float64_chs(a
);
11659 float32
VFP_HELPER(abs
, s
)(float32 a
)
11661 return float32_abs(a
);
11664 float64
VFP_HELPER(abs
, d
)(float64 a
)
11666 return float64_abs(a
);
11669 float32
VFP_HELPER(sqrt
, s
)(float32 a
, CPUARMState
*env
)
11671 return float32_sqrt(a
, &env
->vfp
.fp_status
);
11674 float64
VFP_HELPER(sqrt
, d
)(float64 a
, CPUARMState
*env
)
11676 return float64_sqrt(a
, &env
->vfp
.fp_status
);
11679 /* XXX: check quiet/signaling case */
11680 #define DO_VFP_cmp(p, type) \
11681 void VFP_HELPER(cmp, p)(type a, type b, CPUARMState *env) \
11684 switch(type ## _compare_quiet(a, b, &env->vfp.fp_status)) { \
11685 case 0: flags = 0x6; break; \
11686 case -1: flags = 0x8; break; \
11687 case 1: flags = 0x2; break; \
11688 default: case 2: flags = 0x3; break; \
11690 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
11691 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
11693 void VFP_HELPER(cmpe, p)(type a, type b, CPUARMState *env) \
11696 switch(type ## _compare(a, b, &env->vfp.fp_status)) { \
11697 case 0: flags = 0x6; break; \
11698 case -1: flags = 0x8; break; \
11699 case 1: flags = 0x2; break; \
11700 default: case 2: flags = 0x3; break; \
11702 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
11703 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
11705 DO_VFP_cmp(s
, float32
)
11706 DO_VFP_cmp(d
, float64
)
11709 /* Integer to float and float to integer conversions */
11711 #define CONV_ITOF(name, ftype, fsz, sign) \
11712 ftype HELPER(name)(uint32_t x, void *fpstp) \
11714 float_status *fpst = fpstp; \
11715 return sign##int32_to_##float##fsz((sign##int32_t)x, fpst); \
11718 #define CONV_FTOI(name, ftype, fsz, sign, round) \
11719 sign##int32_t HELPER(name)(ftype x, void *fpstp) \
11721 float_status *fpst = fpstp; \
11722 if (float##fsz##_is_any_nan(x)) { \
11723 float_raise(float_flag_invalid, fpst); \
11726 return float##fsz##_to_##sign##int32##round(x, fpst); \
11729 #define FLOAT_CONVS(name, p, ftype, fsz, sign) \
11730 CONV_ITOF(vfp_##name##to##p, ftype, fsz, sign) \
11731 CONV_FTOI(vfp_to##name##p, ftype, fsz, sign, ) \
11732 CONV_FTOI(vfp_to##name##z##p, ftype, fsz, sign, _round_to_zero)
11734 FLOAT_CONVS(si
, h
, uint32_t, 16, )
11735 FLOAT_CONVS(si
, s
, float32
, 32, )
11736 FLOAT_CONVS(si
, d
, float64
, 64, )
11737 FLOAT_CONVS(ui
, h
, uint32_t, 16, u
)
11738 FLOAT_CONVS(ui
, s
, float32
, 32, u
)
11739 FLOAT_CONVS(ui
, d
, float64
, 64, u
)
11745 /* floating point conversion */
11746 float64
VFP_HELPER(fcvtd
, s
)(float32 x
, CPUARMState
*env
)
11748 return float32_to_float64(x
, &env
->vfp
.fp_status
);
11751 float32
VFP_HELPER(fcvts
, d
)(float64 x
, CPUARMState
*env
)
11753 return float64_to_float32(x
, &env
->vfp
.fp_status
);
11756 /* VFP3 fixed point conversion. */
11757 #define VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \
11758 float##fsz HELPER(vfp_##name##to##p)(uint##isz##_t x, uint32_t shift, \
11760 { return itype##_to_##float##fsz##_scalbn(x, -shift, fpstp); }
11762 #define VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, ROUND, suff) \
11763 uint##isz##_t HELPER(vfp_to##name##p##suff)(float##fsz x, uint32_t shift, \
11766 if (unlikely(float##fsz##_is_any_nan(x))) { \
11767 float_raise(float_flag_invalid, fpst); \
11770 return float##fsz##_to_##itype##_scalbn(x, ROUND, shift, fpst); \
11773 #define VFP_CONV_FIX(name, p, fsz, isz, itype) \
11774 VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \
11775 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, \
11776 float_round_to_zero, _round_to_zero) \
11777 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, \
11778 get_float_rounding_mode(fpst), )
11780 #define VFP_CONV_FIX_A64(name, p, fsz, isz, itype) \
11781 VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \
11782 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, \
11783 get_float_rounding_mode(fpst), )
11785 VFP_CONV_FIX(sh
, d
, 64, 64, int16
)
11786 VFP_CONV_FIX(sl
, d
, 64, 64, int32
)
11787 VFP_CONV_FIX_A64(sq
, d
, 64, 64, int64
)
11788 VFP_CONV_FIX(uh
, d
, 64, 64, uint16
)
11789 VFP_CONV_FIX(ul
, d
, 64, 64, uint32
)
11790 VFP_CONV_FIX_A64(uq
, d
, 64, 64, uint64
)
11791 VFP_CONV_FIX(sh
, s
, 32, 32, int16
)
11792 VFP_CONV_FIX(sl
, s
, 32, 32, int32
)
11793 VFP_CONV_FIX_A64(sq
, s
, 32, 64, int64
)
11794 VFP_CONV_FIX(uh
, s
, 32, 32, uint16
)
11795 VFP_CONV_FIX(ul
, s
, 32, 32, uint32
)
11796 VFP_CONV_FIX_A64(uq
, s
, 32, 64, uint64
)
11798 #undef VFP_CONV_FIX
11799 #undef VFP_CONV_FIX_FLOAT
11800 #undef VFP_CONV_FLOAT_FIX_ROUND
11801 #undef VFP_CONV_FIX_A64
11803 uint32_t HELPER(vfp_sltoh
)(uint32_t x
, uint32_t shift
, void *fpst
)
11805 return int32_to_float16_scalbn(x
, -shift
, fpst
);
11808 uint32_t HELPER(vfp_ultoh
)(uint32_t x
, uint32_t shift
, void *fpst
)
11810 return uint32_to_float16_scalbn(x
, -shift
, fpst
);
11813 uint32_t HELPER(vfp_sqtoh
)(uint64_t x
, uint32_t shift
, void *fpst
)
11815 return int64_to_float16_scalbn(x
, -shift
, fpst
);
11818 uint32_t HELPER(vfp_uqtoh
)(uint64_t x
, uint32_t shift
, void *fpst
)
11820 return uint64_to_float16_scalbn(x
, -shift
, fpst
);
11823 uint32_t HELPER(vfp_toshh
)(uint32_t x
, uint32_t shift
, void *fpst
)
11825 if (unlikely(float16_is_any_nan(x
))) {
11826 float_raise(float_flag_invalid
, fpst
);
11829 return float16_to_int16_scalbn(x
, get_float_rounding_mode(fpst
),
11833 uint32_t HELPER(vfp_touhh
)(uint32_t x
, uint32_t shift
, void *fpst
)
11835 if (unlikely(float16_is_any_nan(x
))) {
11836 float_raise(float_flag_invalid
, fpst
);
11839 return float16_to_uint16_scalbn(x
, get_float_rounding_mode(fpst
),
11843 uint32_t HELPER(vfp_toslh
)(uint32_t x
, uint32_t shift
, void *fpst
)
11845 if (unlikely(float16_is_any_nan(x
))) {
11846 float_raise(float_flag_invalid
, fpst
);
11849 return float16_to_int32_scalbn(x
, get_float_rounding_mode(fpst
),
11853 uint32_t HELPER(vfp_toulh
)(uint32_t x
, uint32_t shift
, void *fpst
)
11855 if (unlikely(float16_is_any_nan(x
))) {
11856 float_raise(float_flag_invalid
, fpst
);
11859 return float16_to_uint32_scalbn(x
, get_float_rounding_mode(fpst
),
11863 uint64_t HELPER(vfp_tosqh
)(uint32_t x
, uint32_t shift
, void *fpst
)
11865 if (unlikely(float16_is_any_nan(x
))) {
11866 float_raise(float_flag_invalid
, fpst
);
11869 return float16_to_int64_scalbn(x
, get_float_rounding_mode(fpst
),
11873 uint64_t HELPER(vfp_touqh
)(uint32_t x
, uint32_t shift
, void *fpst
)
11875 if (unlikely(float16_is_any_nan(x
))) {
11876 float_raise(float_flag_invalid
, fpst
);
11879 return float16_to_uint64_scalbn(x
, get_float_rounding_mode(fpst
),
11883 /* Set the current fp rounding mode and return the old one.
11884 * The argument is a softfloat float_round_ value.
11886 uint32_t HELPER(set_rmode
)(uint32_t rmode
, void *fpstp
)
11888 float_status
*fp_status
= fpstp
;
11890 uint32_t prev_rmode
= get_float_rounding_mode(fp_status
);
11891 set_float_rounding_mode(rmode
, fp_status
);
11896 /* Set the current fp rounding mode in the standard fp status and return
11897 * the old one. This is for NEON instructions that need to change the
11898 * rounding mode but wish to use the standard FPSCR values for everything
11899 * else. Always set the rounding mode back to the correct value after
11901 * The argument is a softfloat float_round_ value.
11903 uint32_t HELPER(set_neon_rmode
)(uint32_t rmode
, CPUARMState
*env
)
11905 float_status
*fp_status
= &env
->vfp
.standard_fp_status
;
11907 uint32_t prev_rmode
= get_float_rounding_mode(fp_status
);
11908 set_float_rounding_mode(rmode
, fp_status
);
11913 /* Half precision conversions. */
11914 float32
HELPER(vfp_fcvt_f16_to_f32
)(uint32_t a
, void *fpstp
, uint32_t ahp_mode
)
11916 /* Squash FZ16 to 0 for the duration of conversion. In this case,
11917 * it would affect flushing input denormals.
11919 float_status
*fpst
= fpstp
;
11920 flag save
= get_flush_inputs_to_zero(fpst
);
11921 set_flush_inputs_to_zero(false, fpst
);
11922 float32 r
= float16_to_float32(a
, !ahp_mode
, fpst
);
11923 set_flush_inputs_to_zero(save
, fpst
);
11927 uint32_t HELPER(vfp_fcvt_f32_to_f16
)(float32 a
, void *fpstp
, uint32_t ahp_mode
)
11929 /* Squash FZ16 to 0 for the duration of conversion. In this case,
11930 * it would affect flushing output denormals.
11932 float_status
*fpst
= fpstp
;
11933 flag save
= get_flush_to_zero(fpst
);
11934 set_flush_to_zero(false, fpst
);
11935 float16 r
= float32_to_float16(a
, !ahp_mode
, fpst
);
11936 set_flush_to_zero(save
, fpst
);
11940 float64
HELPER(vfp_fcvt_f16_to_f64
)(uint32_t a
, void *fpstp
, uint32_t ahp_mode
)
11942 /* Squash FZ16 to 0 for the duration of conversion. In this case,
11943 * it would affect flushing input denormals.
11945 float_status
*fpst
= fpstp
;
11946 flag save
= get_flush_inputs_to_zero(fpst
);
11947 set_flush_inputs_to_zero(false, fpst
);
11948 float64 r
= float16_to_float64(a
, !ahp_mode
, fpst
);
11949 set_flush_inputs_to_zero(save
, fpst
);
11953 uint32_t HELPER(vfp_fcvt_f64_to_f16
)(float64 a
, void *fpstp
, uint32_t ahp_mode
)
11955 /* Squash FZ16 to 0 for the duration of conversion. In this case,
11956 * it would affect flushing output denormals.
11958 float_status
*fpst
= fpstp
;
11959 flag save
= get_flush_to_zero(fpst
);
11960 set_flush_to_zero(false, fpst
);
11961 float16 r
= float64_to_float16(a
, !ahp_mode
, fpst
);
11962 set_flush_to_zero(save
, fpst
);
11966 #define float32_two make_float32(0x40000000)
11967 #define float32_three make_float32(0x40400000)
11968 #define float32_one_point_five make_float32(0x3fc00000)
11970 float32
HELPER(recps_f32
)(float32 a
, float32 b
, CPUARMState
*env
)
11972 float_status
*s
= &env
->vfp
.standard_fp_status
;
11973 if ((float32_is_infinity(a
) && float32_is_zero_or_denormal(b
)) ||
11974 (float32_is_infinity(b
) && float32_is_zero_or_denormal(a
))) {
11975 if (!(float32_is_zero(a
) || float32_is_zero(b
))) {
11976 float_raise(float_flag_input_denormal
, s
);
11978 return float32_two
;
11980 return float32_sub(float32_two
, float32_mul(a
, b
, s
), s
);
11983 float32
HELPER(rsqrts_f32
)(float32 a
, float32 b
, CPUARMState
*env
)
11985 float_status
*s
= &env
->vfp
.standard_fp_status
;
11987 if ((float32_is_infinity(a
) && float32_is_zero_or_denormal(b
)) ||
11988 (float32_is_infinity(b
) && float32_is_zero_or_denormal(a
))) {
11989 if (!(float32_is_zero(a
) || float32_is_zero(b
))) {
11990 float_raise(float_flag_input_denormal
, s
);
11992 return float32_one_point_five
;
11994 product
= float32_mul(a
, b
, s
);
11995 return float32_div(float32_sub(float32_three
, product
, s
), float32_two
, s
);
11998 /* NEON helpers. */
12000 /* Constants 256 and 512 are used in some helpers; we avoid relying on
12001 * int->float conversions at run-time. */
12002 #define float64_256 make_float64(0x4070000000000000LL)
12003 #define float64_512 make_float64(0x4080000000000000LL)
12004 #define float16_maxnorm make_float16(0x7bff)
12005 #define float32_maxnorm make_float32(0x7f7fffff)
12006 #define float64_maxnorm make_float64(0x7fefffffffffffffLL)
12008 /* Reciprocal functions
12010 * The algorithm that must be used to calculate the estimate
12011 * is specified by the ARM ARM, see FPRecipEstimate()/RecipEstimate
12014 /* See RecipEstimate()
12016 * input is a 9 bit fixed point number
12017 * input range 256 .. 511 for a number from 0.5 <= x < 1.0.
12018 * result range 256 .. 511 for a number from 1.0 to 511/256.
12021 static int recip_estimate(int input
)
12024 assert(256 <= input
&& input
< 512);
12025 a
= (input
* 2) + 1;
12028 assert(256 <= r
&& r
< 512);
12033 * Common wrapper to call recip_estimate
12035 * The parameters are exponent and 64 bit fraction (without implicit
12036 * bit) where the binary point is nominally at bit 52. Returns a
12037 * float64 which can then be rounded to the appropriate size by the
12041 static uint64_t call_recip_estimate(int *exp
, int exp_off
, uint64_t frac
)
12043 uint32_t scaled
, estimate
;
12044 uint64_t result_frac
;
12047 /* Handle sub-normals */
12049 if (extract64(frac
, 51, 1) == 0) {
12057 /* scaled = UInt('1':fraction<51:44>) */
12058 scaled
= deposit32(1 << 8, 0, 8, extract64(frac
, 44, 8));
12059 estimate
= recip_estimate(scaled
);
12061 result_exp
= exp_off
- *exp
;
12062 result_frac
= deposit64(0, 44, 8, estimate
);
12063 if (result_exp
== 0) {
12064 result_frac
= deposit64(result_frac
>> 1, 51, 1, 1);
12065 } else if (result_exp
== -1) {
12066 result_frac
= deposit64(result_frac
>> 2, 50, 2, 1);
12072 return result_frac
;
12075 static bool round_to_inf(float_status
*fpst
, bool sign_bit
)
12077 switch (fpst
->float_rounding_mode
) {
12078 case float_round_nearest_even
: /* Round to Nearest */
12080 case float_round_up
: /* Round to +Inf */
12082 case float_round_down
: /* Round to -Inf */
12084 case float_round_to_zero
: /* Round to Zero */
12088 g_assert_not_reached();
12091 uint32_t HELPER(recpe_f16
)(uint32_t input
, void *fpstp
)
12093 float_status
*fpst
= fpstp
;
12094 float16 f16
= float16_squash_input_denormal(input
, fpst
);
12095 uint32_t f16_val
= float16_val(f16
);
12096 uint32_t f16_sign
= float16_is_neg(f16
);
12097 int f16_exp
= extract32(f16_val
, 10, 5);
12098 uint32_t f16_frac
= extract32(f16_val
, 0, 10);
12101 if (float16_is_any_nan(f16
)) {
12103 if (float16_is_signaling_nan(f16
, fpst
)) {
12104 float_raise(float_flag_invalid
, fpst
);
12105 nan
= float16_silence_nan(f16
, fpst
);
12107 if (fpst
->default_nan_mode
) {
12108 nan
= float16_default_nan(fpst
);
12111 } else if (float16_is_infinity(f16
)) {
12112 return float16_set_sign(float16_zero
, float16_is_neg(f16
));
12113 } else if (float16_is_zero(f16
)) {
12114 float_raise(float_flag_divbyzero
, fpst
);
12115 return float16_set_sign(float16_infinity
, float16_is_neg(f16
));
12116 } else if (float16_abs(f16
) < (1 << 8)) {
12117 /* Abs(value) < 2.0^-16 */
12118 float_raise(float_flag_overflow
| float_flag_inexact
, fpst
);
12119 if (round_to_inf(fpst
, f16_sign
)) {
12120 return float16_set_sign(float16_infinity
, f16_sign
);
12122 return float16_set_sign(float16_maxnorm
, f16_sign
);
12124 } else if (f16_exp
>= 29 && fpst
->flush_to_zero
) {
12125 float_raise(float_flag_underflow
, fpst
);
12126 return float16_set_sign(float16_zero
, float16_is_neg(f16
));
12129 f64_frac
= call_recip_estimate(&f16_exp
, 29,
12130 ((uint64_t) f16_frac
) << (52 - 10));
12132 /* result = sign : result_exp<4:0> : fraction<51:42> */
12133 f16_val
= deposit32(0, 15, 1, f16_sign
);
12134 f16_val
= deposit32(f16_val
, 10, 5, f16_exp
);
12135 f16_val
= deposit32(f16_val
, 0, 10, extract64(f64_frac
, 52 - 10, 10));
12136 return make_float16(f16_val
);
12139 float32
HELPER(recpe_f32
)(float32 input
, void *fpstp
)
12141 float_status
*fpst
= fpstp
;
12142 float32 f32
= float32_squash_input_denormal(input
, fpst
);
12143 uint32_t f32_val
= float32_val(f32
);
12144 bool f32_sign
= float32_is_neg(f32
);
12145 int f32_exp
= extract32(f32_val
, 23, 8);
12146 uint32_t f32_frac
= extract32(f32_val
, 0, 23);
12149 if (float32_is_any_nan(f32
)) {
12151 if (float32_is_signaling_nan(f32
, fpst
)) {
12152 float_raise(float_flag_invalid
, fpst
);
12153 nan
= float32_silence_nan(f32
, fpst
);
12155 if (fpst
->default_nan_mode
) {
12156 nan
= float32_default_nan(fpst
);
12159 } else if (float32_is_infinity(f32
)) {
12160 return float32_set_sign(float32_zero
, float32_is_neg(f32
));
12161 } else if (float32_is_zero(f32
)) {
12162 float_raise(float_flag_divbyzero
, fpst
);
12163 return float32_set_sign(float32_infinity
, float32_is_neg(f32
));
12164 } else if (float32_abs(f32
) < (1ULL << 21)) {
12165 /* Abs(value) < 2.0^-128 */
12166 float_raise(float_flag_overflow
| float_flag_inexact
, fpst
);
12167 if (round_to_inf(fpst
, f32_sign
)) {
12168 return float32_set_sign(float32_infinity
, f32_sign
);
12170 return float32_set_sign(float32_maxnorm
, f32_sign
);
12172 } else if (f32_exp
>= 253 && fpst
->flush_to_zero
) {
12173 float_raise(float_flag_underflow
, fpst
);
12174 return float32_set_sign(float32_zero
, float32_is_neg(f32
));
12177 f64_frac
= call_recip_estimate(&f32_exp
, 253,
12178 ((uint64_t) f32_frac
) << (52 - 23));
12180 /* result = sign : result_exp<7:0> : fraction<51:29> */
12181 f32_val
= deposit32(0, 31, 1, f32_sign
);
12182 f32_val
= deposit32(f32_val
, 23, 8, f32_exp
);
12183 f32_val
= deposit32(f32_val
, 0, 23, extract64(f64_frac
, 52 - 23, 23));
12184 return make_float32(f32_val
);
12187 float64
HELPER(recpe_f64
)(float64 input
, void *fpstp
)
12189 float_status
*fpst
= fpstp
;
12190 float64 f64
= float64_squash_input_denormal(input
, fpst
);
12191 uint64_t f64_val
= float64_val(f64
);
12192 bool f64_sign
= float64_is_neg(f64
);
12193 int f64_exp
= extract64(f64_val
, 52, 11);
12194 uint64_t f64_frac
= extract64(f64_val
, 0, 52);
12196 /* Deal with any special cases */
12197 if (float64_is_any_nan(f64
)) {
12199 if (float64_is_signaling_nan(f64
, fpst
)) {
12200 float_raise(float_flag_invalid
, fpst
);
12201 nan
= float64_silence_nan(f64
, fpst
);
12203 if (fpst
->default_nan_mode
) {
12204 nan
= float64_default_nan(fpst
);
12207 } else if (float64_is_infinity(f64
)) {
12208 return float64_set_sign(float64_zero
, float64_is_neg(f64
));
12209 } else if (float64_is_zero(f64
)) {
12210 float_raise(float_flag_divbyzero
, fpst
);
12211 return float64_set_sign(float64_infinity
, float64_is_neg(f64
));
12212 } else if ((f64_val
& ~(1ULL << 63)) < (1ULL << 50)) {
12213 /* Abs(value) < 2.0^-1024 */
12214 float_raise(float_flag_overflow
| float_flag_inexact
, fpst
);
12215 if (round_to_inf(fpst
, f64_sign
)) {
12216 return float64_set_sign(float64_infinity
, f64_sign
);
12218 return float64_set_sign(float64_maxnorm
, f64_sign
);
12220 } else if (f64_exp
>= 2045 && fpst
->flush_to_zero
) {
12221 float_raise(float_flag_underflow
, fpst
);
12222 return float64_set_sign(float64_zero
, float64_is_neg(f64
));
12225 f64_frac
= call_recip_estimate(&f64_exp
, 2045, f64_frac
);
12227 /* result = sign : result_exp<10:0> : fraction<51:0>; */
12228 f64_val
= deposit64(0, 63, 1, f64_sign
);
12229 f64_val
= deposit64(f64_val
, 52, 11, f64_exp
);
12230 f64_val
= deposit64(f64_val
, 0, 52, f64_frac
);
12231 return make_float64(f64_val
);
12234 /* The algorithm that must be used to calculate the estimate
12235 * is specified by the ARM ARM.
12238 static int do_recip_sqrt_estimate(int a
)
12242 assert(128 <= a
&& a
< 512);
12250 while (a
* (b
+ 1) * (b
+ 1) < (1 << 28)) {
12253 estimate
= (b
+ 1) / 2;
12254 assert(256 <= estimate
&& estimate
< 512);
12260 static uint64_t recip_sqrt_estimate(int *exp
, int exp_off
, uint64_t frac
)
12266 while (extract64(frac
, 51, 1) == 0) {
12270 frac
= extract64(frac
, 0, 51) << 1;
12274 /* scaled = UInt('01':fraction<51:45>) */
12275 scaled
= deposit32(1 << 7, 0, 7, extract64(frac
, 45, 7));
12277 /* scaled = UInt('1':fraction<51:44>) */
12278 scaled
= deposit32(1 << 8, 0, 8, extract64(frac
, 44, 8));
12280 estimate
= do_recip_sqrt_estimate(scaled
);
12282 *exp
= (exp_off
- *exp
) / 2;
12283 return extract64(estimate
, 0, 8) << 44;
12286 uint32_t HELPER(rsqrte_f16
)(uint32_t input
, void *fpstp
)
12288 float_status
*s
= fpstp
;
12289 float16 f16
= float16_squash_input_denormal(input
, s
);
12290 uint16_t val
= float16_val(f16
);
12291 bool f16_sign
= float16_is_neg(f16
);
12292 int f16_exp
= extract32(val
, 10, 5);
12293 uint16_t f16_frac
= extract32(val
, 0, 10);
12296 if (float16_is_any_nan(f16
)) {
12298 if (float16_is_signaling_nan(f16
, s
)) {
12299 float_raise(float_flag_invalid
, s
);
12300 nan
= float16_silence_nan(f16
, s
);
12302 if (s
->default_nan_mode
) {
12303 nan
= float16_default_nan(s
);
12306 } else if (float16_is_zero(f16
)) {
12307 float_raise(float_flag_divbyzero
, s
);
12308 return float16_set_sign(float16_infinity
, f16_sign
);
12309 } else if (f16_sign
) {
12310 float_raise(float_flag_invalid
, s
);
12311 return float16_default_nan(s
);
12312 } else if (float16_is_infinity(f16
)) {
12313 return float16_zero
;
12316 /* Scale and normalize to a double-precision value between 0.25 and 1.0,
12317 * preserving the parity of the exponent. */
12319 f64_frac
= ((uint64_t) f16_frac
) << (52 - 10);
12321 f64_frac
= recip_sqrt_estimate(&f16_exp
, 44, f64_frac
);
12323 /* result = sign : result_exp<4:0> : estimate<7:0> : Zeros(2) */
12324 val
= deposit32(0, 15, 1, f16_sign
);
12325 val
= deposit32(val
, 10, 5, f16_exp
);
12326 val
= deposit32(val
, 2, 8, extract64(f64_frac
, 52 - 8, 8));
12327 return make_float16(val
);
12330 float32
HELPER(rsqrte_f32
)(float32 input
, void *fpstp
)
12332 float_status
*s
= fpstp
;
12333 float32 f32
= float32_squash_input_denormal(input
, s
);
12334 uint32_t val
= float32_val(f32
);
12335 uint32_t f32_sign
= float32_is_neg(f32
);
12336 int f32_exp
= extract32(val
, 23, 8);
12337 uint32_t f32_frac
= extract32(val
, 0, 23);
12340 if (float32_is_any_nan(f32
)) {
12342 if (float32_is_signaling_nan(f32
, s
)) {
12343 float_raise(float_flag_invalid
, s
);
12344 nan
= float32_silence_nan(f32
, s
);
12346 if (s
->default_nan_mode
) {
12347 nan
= float32_default_nan(s
);
12350 } else if (float32_is_zero(f32
)) {
12351 float_raise(float_flag_divbyzero
, s
);
12352 return float32_set_sign(float32_infinity
, float32_is_neg(f32
));
12353 } else if (float32_is_neg(f32
)) {
12354 float_raise(float_flag_invalid
, s
);
12355 return float32_default_nan(s
);
12356 } else if (float32_is_infinity(f32
)) {
12357 return float32_zero
;
12360 /* Scale and normalize to a double-precision value between 0.25 and 1.0,
12361 * preserving the parity of the exponent. */
12363 f64_frac
= ((uint64_t) f32_frac
) << 29;
12365 f64_frac
= recip_sqrt_estimate(&f32_exp
, 380, f64_frac
);
12367 /* result = sign : result_exp<4:0> : estimate<7:0> : Zeros(15) */
12368 val
= deposit32(0, 31, 1, f32_sign
);
12369 val
= deposit32(val
, 23, 8, f32_exp
);
12370 val
= deposit32(val
, 15, 8, extract64(f64_frac
, 52 - 8, 8));
12371 return make_float32(val
);
12374 float64
HELPER(rsqrte_f64
)(float64 input
, void *fpstp
)
12376 float_status
*s
= fpstp
;
12377 float64 f64
= float64_squash_input_denormal(input
, s
);
12378 uint64_t val
= float64_val(f64
);
12379 bool f64_sign
= float64_is_neg(f64
);
12380 int f64_exp
= extract64(val
, 52, 11);
12381 uint64_t f64_frac
= extract64(val
, 0, 52);
12383 if (float64_is_any_nan(f64
)) {
12385 if (float64_is_signaling_nan(f64
, s
)) {
12386 float_raise(float_flag_invalid
, s
);
12387 nan
= float64_silence_nan(f64
, s
);
12389 if (s
->default_nan_mode
) {
12390 nan
= float64_default_nan(s
);
12393 } else if (float64_is_zero(f64
)) {
12394 float_raise(float_flag_divbyzero
, s
);
12395 return float64_set_sign(float64_infinity
, float64_is_neg(f64
));
12396 } else if (float64_is_neg(f64
)) {
12397 float_raise(float_flag_invalid
, s
);
12398 return float64_default_nan(s
);
12399 } else if (float64_is_infinity(f64
)) {
12400 return float64_zero
;
12403 f64_frac
= recip_sqrt_estimate(&f64_exp
, 3068, f64_frac
);
12405 /* result = sign : result_exp<4:0> : estimate<7:0> : Zeros(44) */
12406 val
= deposit64(0, 61, 1, f64_sign
);
12407 val
= deposit64(val
, 52, 11, f64_exp
);
12408 val
= deposit64(val
, 44, 8, extract64(f64_frac
, 52 - 8, 8));
12409 return make_float64(val
);
12412 uint32_t HELPER(recpe_u32
)(uint32_t a
, void *fpstp
)
12414 /* float_status *s = fpstp; */
12415 int input
, estimate
;
12417 if ((a
& 0x80000000) == 0) {
12421 input
= extract32(a
, 23, 9);
12422 estimate
= recip_estimate(input
);
12424 return deposit32(0, (32 - 9), 9, estimate
);
12427 uint32_t HELPER(rsqrte_u32
)(uint32_t a
, void *fpstp
)
12431 if ((a
& 0xc0000000) == 0) {
12435 estimate
= do_recip_sqrt_estimate(extract32(a
, 23, 9));
12437 return deposit32(0, 23, 9, estimate
);
12440 /* VFPv4 fused multiply-accumulate */
12441 float32
VFP_HELPER(muladd
, s
)(float32 a
, float32 b
, float32 c
, void *fpstp
)
12443 float_status
*fpst
= fpstp
;
12444 return float32_muladd(a
, b
, c
, 0, fpst
);
12447 float64
VFP_HELPER(muladd
, d
)(float64 a
, float64 b
, float64 c
, void *fpstp
)
12449 float_status
*fpst
= fpstp
;
12450 return float64_muladd(a
, b
, c
, 0, fpst
);
12453 /* ARMv8 round to integral */
12454 float32
HELPER(rints_exact
)(float32 x
, void *fp_status
)
12456 return float32_round_to_int(x
, fp_status
);
12459 float64
HELPER(rintd_exact
)(float64 x
, void *fp_status
)
12461 return float64_round_to_int(x
, fp_status
);
12464 float32
HELPER(rints
)(float32 x
, void *fp_status
)
12466 int old_flags
= get_float_exception_flags(fp_status
), new_flags
;
12469 ret
= float32_round_to_int(x
, fp_status
);
12471 /* Suppress any inexact exceptions the conversion produced */
12472 if (!(old_flags
& float_flag_inexact
)) {
12473 new_flags
= get_float_exception_flags(fp_status
);
12474 set_float_exception_flags(new_flags
& ~float_flag_inexact
, fp_status
);
12480 float64
HELPER(rintd
)(float64 x
, void *fp_status
)
12482 int old_flags
= get_float_exception_flags(fp_status
), new_flags
;
12485 ret
= float64_round_to_int(x
, fp_status
);
12487 new_flags
= get_float_exception_flags(fp_status
);
12489 /* Suppress any inexact exceptions the conversion produced */
12490 if (!(old_flags
& float_flag_inexact
)) {
12491 new_flags
= get_float_exception_flags(fp_status
);
12492 set_float_exception_flags(new_flags
& ~float_flag_inexact
, fp_status
);
12498 /* Convert ARM rounding mode to softfloat */
12499 int arm_rmode_to_sf(int rmode
)
12502 case FPROUNDING_TIEAWAY
:
12503 rmode
= float_round_ties_away
;
12505 case FPROUNDING_ODD
:
12506 /* FIXME: add support for TIEAWAY and ODD */
12507 qemu_log_mask(LOG_UNIMP
, "arm: unimplemented rounding mode: %d\n",
12509 /* fall through for now */
12510 case FPROUNDING_TIEEVEN
:
12512 rmode
= float_round_nearest_even
;
12514 case FPROUNDING_POSINF
:
12515 rmode
= float_round_up
;
12517 case FPROUNDING_NEGINF
:
12518 rmode
= float_round_down
;
12520 case FPROUNDING_ZERO
:
12521 rmode
= float_round_to_zero
;
12528 * The upper bytes of val (above the number specified by 'bytes') must have
12529 * been zeroed out by the caller.
12531 uint32_t HELPER(crc32
)(uint32_t acc
, uint32_t val
, uint32_t bytes
)
12535 stl_le_p(buf
, val
);
12537 /* zlib crc32 converts the accumulator and output to one's complement. */
12538 return crc32(acc
^ 0xffffffff, buf
, bytes
) ^ 0xffffffff;
12541 uint32_t HELPER(crc32c
)(uint32_t acc
, uint32_t val
, uint32_t bytes
)
12545 stl_le_p(buf
, val
);
12547 /* Linux crc32c converts the output to one's complement. */
12548 return crc32c(acc
, buf
, bytes
) ^ 0xffffffff;
12551 /* Return the exception level to which FP-disabled exceptions should
12552 * be taken, or 0 if FP is enabled.
12554 int fp_exception_el(CPUARMState
*env
, int cur_el
)
12556 #ifndef CONFIG_USER_ONLY
12559 /* CPACR and the CPTR registers don't exist before v6, so FP is
12560 * always accessible
12562 if (!arm_feature(env
, ARM_FEATURE_V6
)) {
12566 /* The CPACR controls traps to EL1, or PL1 if we're 32 bit:
12567 * 0, 2 : trap EL0 and EL1/PL1 accesses
12568 * 1 : trap only EL0 accesses
12569 * 3 : trap no accesses
12571 fpen
= extract32(env
->cp15
.cpacr_el1
, 20, 2);
12575 if (cur_el
== 0 || cur_el
== 1) {
12576 /* Trap to PL1, which might be EL1 or EL3 */
12577 if (arm_is_secure(env
) && !arm_el_is_aa64(env
, 3)) {
12582 if (cur_el
== 3 && !is_a64(env
)) {
12583 /* Secure PL1 running at EL3 */
12596 /* For the CPTR registers we don't need to guard with an ARM_FEATURE
12597 * check because zero bits in the registers mean "don't trap".
12600 /* CPTR_EL2 : present in v7VE or v8 */
12601 if (cur_el
<= 2 && extract32(env
->cp15
.cptr_el
[2], 10, 1)
12602 && !arm_is_secure_below_el3(env
)) {
12603 /* Trap FP ops at EL2, NS-EL1 or NS-EL0 to EL2 */
12607 /* CPTR_EL3 : present in v8 */
12608 if (extract32(env
->cp15
.cptr_el
[3], 10, 1)) {
12609 /* Trap all FP ops to EL3 */
12616 void cpu_get_tb_cpu_state(CPUARMState
*env
, target_ulong
*pc
,
12617 target_ulong
*cs_base
, uint32_t *pflags
)
12619 ARMMMUIdx mmu_idx
= core_to_arm_mmu_idx(env
, cpu_mmu_index(env
, false));
12620 int current_el
= arm_current_el(env
);
12621 int fp_el
= fp_exception_el(env
, current_el
);
12626 flags
= ARM_TBFLAG_AARCH64_STATE_MASK
;
12627 /* Get control bits for tagged addresses */
12628 flags
|= (arm_regime_tbi0(env
, mmu_idx
) << ARM_TBFLAG_TBI0_SHIFT
);
12629 flags
|= (arm_regime_tbi1(env
, mmu_idx
) << ARM_TBFLAG_TBI1_SHIFT
);
12631 if (arm_feature(env
, ARM_FEATURE_SVE
)) {
12632 int sve_el
= sve_exception_el(env
, current_el
);
12635 /* If SVE is disabled, but FP is enabled,
12636 * then the effective len is 0.
12638 if (sve_el
!= 0 && fp_el
== 0) {
12641 zcr_len
= sve_zcr_len_for_el(env
, current_el
);
12643 flags
|= sve_el
<< ARM_TBFLAG_SVEEXC_EL_SHIFT
;
12644 flags
|= zcr_len
<< ARM_TBFLAG_ZCR_LEN_SHIFT
;
12647 *pc
= env
->regs
[15];
12648 flags
= (env
->thumb
<< ARM_TBFLAG_THUMB_SHIFT
)
12649 | (env
->vfp
.vec_len
<< ARM_TBFLAG_VECLEN_SHIFT
)
12650 | (env
->vfp
.vec_stride
<< ARM_TBFLAG_VECSTRIDE_SHIFT
)
12651 | (env
->condexec_bits
<< ARM_TBFLAG_CONDEXEC_SHIFT
)
12652 | (arm_sctlr_b(env
) << ARM_TBFLAG_SCTLR_B_SHIFT
);
12653 if (!(access_secure_reg(env
))) {
12654 flags
|= ARM_TBFLAG_NS_MASK
;
12656 if (env
->vfp
.xregs
[ARM_VFP_FPEXC
] & (1 << 30)
12657 || arm_el_is_aa64(env
, 1)) {
12658 flags
|= ARM_TBFLAG_VFPEN_MASK
;
12660 flags
|= (extract32(env
->cp15
.c15_cpar
, 0, 2)
12661 << ARM_TBFLAG_XSCALE_CPAR_SHIFT
);
12664 flags
|= (arm_to_core_mmu_idx(mmu_idx
) << ARM_TBFLAG_MMUIDX_SHIFT
);
12666 /* The SS_ACTIVE and PSTATE_SS bits correspond to the state machine
12667 * states defined in the ARM ARM for software singlestep:
12668 * SS_ACTIVE PSTATE.SS State
12669 * 0 x Inactive (the TB flag for SS is always 0)
12670 * 1 0 Active-pending
12671 * 1 1 Active-not-pending
12673 if (arm_singlestep_active(env
)) {
12674 flags
|= ARM_TBFLAG_SS_ACTIVE_MASK
;
12676 if (env
->pstate
& PSTATE_SS
) {
12677 flags
|= ARM_TBFLAG_PSTATE_SS_MASK
;
12680 if (env
->uncached_cpsr
& PSTATE_SS
) {
12681 flags
|= ARM_TBFLAG_PSTATE_SS_MASK
;
12685 if (arm_cpu_data_is_big_endian(env
)) {
12686 flags
|= ARM_TBFLAG_BE_DATA_MASK
;
12688 flags
|= fp_el
<< ARM_TBFLAG_FPEXC_EL_SHIFT
;
12690 if (arm_v7m_is_handler_mode(env
)) {
12691 flags
|= ARM_TBFLAG_HANDLER_MASK
;
12694 /* v8M always applies stack limit checks unless CCR.STKOFHFNMIGN is
12695 * suppressing them because the requested execution priority is less than 0.
12697 if (arm_feature(env
, ARM_FEATURE_V8
) &&
12698 arm_feature(env
, ARM_FEATURE_M
) &&
12699 !((mmu_idx
& ARM_MMU_IDX_M_NEGPRI
) &&
12700 (env
->v7m
.ccr
[env
->v7m
.secure
] & R_V7M_CCR_STKOFHFNMIGN_MASK
))) {
12701 flags
|= ARM_TBFLAG_STACKCHECK_MASK
;
12708 #ifdef TARGET_AARCH64
12710 * The manual says that when SVE is enabled and VQ is widened the
12711 * implementation is allowed to zero the previously inaccessible
12712 * portion of the registers. The corollary to that is that when
12713 * SVE is enabled and VQ is narrowed we are also allowed to zero
12714 * the now inaccessible portion of the registers.
12716 * The intent of this is that no predicate bit beyond VQ is ever set.
12717 * Which means that some operations on predicate registers themselves
12718 * may operate on full uint64_t or even unrolled across the maximum
12719 * uint64_t[4]. Performing 4 bits of host arithmetic unconditionally
12720 * may well be cheaper than conditionals to restrict the operation
12721 * to the relevant portion of a uint16_t[16].
12723 void aarch64_sve_narrow_vq(CPUARMState
*env
, unsigned vq
)
12728 assert(vq
>= 1 && vq
<= ARM_MAX_VQ
);
12729 assert(vq
<= arm_env_get_cpu(env
)->sve_max_vq
);
12731 /* Zap the high bits of the zregs. */
12732 for (i
= 0; i
< 32; i
++) {
12733 memset(&env
->vfp
.zregs
[i
].d
[2 * vq
], 0, 16 * (ARM_MAX_VQ
- vq
));
12736 /* Zap the high bits of the pregs and ffr. */
12739 pmask
= ~(-1ULL << (16 * (vq
& 3)));
12741 for (j
= vq
/ 4; j
< ARM_MAX_VQ
/ 4; j
++) {
12742 for (i
= 0; i
< 17; ++i
) {
12743 env
->vfp
.pregs
[i
].p
[j
] &= pmask
;
12750 * Notice a change in SVE vector size when changing EL.
12752 void aarch64_sve_change_el(CPUARMState
*env
, int old_el
, int new_el
)
12754 int old_len
, new_len
;
12756 /* Nothing to do if no SVE. */
12757 if (!arm_feature(env
, ARM_FEATURE_SVE
)) {
12761 /* Nothing to do if FP is disabled in either EL. */
12762 if (fp_exception_el(env
, old_el
) || fp_exception_el(env
, new_el
)) {
12767 * DDI0584A.d sec 3.2: "If SVE instructions are disabled or trapped
12768 * at ELx, or not available because the EL is in AArch32 state, then
12769 * for all purposes other than a direct read, the ZCR_ELx.LEN field
12770 * has an effective value of 0".
12772 * Consider EL2 (aa64, vq=4) -> EL0 (aa32) -> EL1 (aa64, vq=0).
12773 * If we ignore aa32 state, we would fail to see the vq4->vq0 transition
12774 * from EL2->EL1. Thus we go ahead and narrow when entering aa32 so that
12775 * we already have the correct register contents when encountering the
12776 * vq0->vq0 transition between EL0->EL1.
12778 old_len
= (arm_el_is_aa64(env
, old_el
) && !sve_exception_el(env
, old_el
)
12779 ? sve_zcr_len_for_el(env
, old_el
) : 0);
12780 new_len
= (arm_el_is_aa64(env
, new_el
) && !sve_exception_el(env
, new_el
)
12781 ? sve_zcr_len_for_el(env
, new_el
) : 0);
12783 /* When changing vector length, clear inaccessible state. */
12784 if (new_len
< old_len
) {
12785 aarch64_sve_narrow_vq(env
, new_len
+ 1);