2 * Tiny Code Generator for QEMU
4 * Copyright (c) 2008 Andrzej Zaborowski
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 #if defined(__ARM_ARCH_7__) || \
26 defined(__ARM_ARCH_7A__) || \
27 defined(__ARM_ARCH_7EM__) || \
28 defined(__ARM_ARCH_7M__) || \
29 defined(__ARM_ARCH_7R__)
30 #define USE_ARMV7_INSTRUCTIONS
33 #if defined(USE_ARMV7_INSTRUCTIONS) || \
34 defined(__ARM_ARCH_6J__) || \
35 defined(__ARM_ARCH_6K__) || \
36 defined(__ARM_ARCH_6T2__) || \
37 defined(__ARM_ARCH_6Z__) || \
38 defined(__ARM_ARCH_6ZK__)
39 #define USE_ARMV6_INSTRUCTIONS
42 #if defined(USE_ARMV6_INSTRUCTIONS) || \
43 defined(__ARM_ARCH_5T__) || \
44 defined(__ARM_ARCH_5TE__) || \
45 defined(__ARM_ARCH_5TEJ__)
46 #define USE_ARMV5_INSTRUCTIONS
49 #ifdef USE_ARMV5_INSTRUCTIONS
50 static const int use_armv5_instructions
= 1;
52 static const int use_armv5_instructions
= 0;
54 #undef USE_ARMV5_INSTRUCTIONS
56 #ifdef USE_ARMV6_INSTRUCTIONS
57 static const int use_armv6_instructions
= 1;
59 static const int use_armv6_instructions
= 0;
61 #undef USE_ARMV6_INSTRUCTIONS
63 #ifdef USE_ARMV7_INSTRUCTIONS
64 static const int use_armv7_instructions
= 1;
66 static const int use_armv7_instructions
= 0;
68 #undef USE_ARMV7_INSTRUCTIONS
71 static const char * const tcg_target_reg_names
[TCG_TARGET_NB_REGS
] = {
91 static const int tcg_target_reg_alloc_order
[] = {
109 static const int tcg_target_call_iarg_regs
[4] = {
110 TCG_REG_R0
, TCG_REG_R1
, TCG_REG_R2
, TCG_REG_R3
112 static const int tcg_target_call_oarg_regs
[2] = {
113 TCG_REG_R0
, TCG_REG_R1
116 static inline void reloc_abs32(void *code_ptr
, tcg_target_long target
)
118 *(uint32_t *) code_ptr
= target
;
121 static inline void reloc_pc24(void *code_ptr
, tcg_target_long target
)
123 uint32_t offset
= ((target
- ((tcg_target_long
) code_ptr
+ 8)) >> 2);
125 *(uint32_t *) code_ptr
= ((*(uint32_t *) code_ptr
) & ~0xffffff)
126 | (offset
& 0xffffff);
129 static void patch_reloc(uint8_t *code_ptr
, int type
,
130 tcg_target_long value
, tcg_target_long addend
)
134 reloc_abs32(code_ptr
, value
);
143 reloc_pc24(code_ptr
, value
);
148 /* maximum number of register used for input function arguments */
149 static inline int tcg_target_get_call_iarg_regs_count(int flags
)
154 /* parse target specific constraints */
155 static int target_parse_constraint(TCGArgConstraint
*ct
, const char **pct_str
)
162 ct
->ct
|= TCG_CT_CONST_ARM
;
166 ct
->ct
|= TCG_CT_REG
;
167 tcg_regset_set32(ct
->u
.regs
, 0, (1 << TCG_TARGET_NB_REGS
) - 1);
170 /* qemu_ld address */
172 ct
->ct
|= TCG_CT_REG
;
173 tcg_regset_set32(ct
->u
.regs
, 0, (1 << TCG_TARGET_NB_REGS
) - 1);
174 #ifdef CONFIG_SOFTMMU
175 /* r0 and r1 will be overwritten when reading the tlb entry,
176 so don't use these. */
177 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_R0
);
178 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_R1
);
182 ct
->ct
|= TCG_CT_REG
;
183 tcg_regset_set32(ct
->u
.regs
, 0, (1 << TCG_TARGET_NB_REGS
) - 1);
184 #ifdef CONFIG_SOFTMMU
185 /* r1 is still needed to load data_reg or data_reg2,
187 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_R1
);
191 /* qemu_st address & data_reg */
193 ct
->ct
|= TCG_CT_REG
;
194 tcg_regset_set32(ct
->u
.regs
, 0, (1 << TCG_TARGET_NB_REGS
) - 1);
195 /* r0 and r1 will be overwritten when reading the tlb entry
196 (softmmu only) and doing the byte swapping, so don't
198 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_R0
);
199 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_R1
);
201 /* qemu_st64 data_reg2 */
203 ct
->ct
|= TCG_CT_REG
;
204 tcg_regset_set32(ct
->u
.regs
, 0, (1 << TCG_TARGET_NB_REGS
) - 1);
205 /* r0 and r1 will be overwritten when reading the tlb entry
206 (softmmu only) and doing the byte swapping, so don't
208 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_R0
);
209 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_R1
);
210 #ifdef CONFIG_SOFTMMU
211 /* r2 is still needed to load data_reg, so don't use it. */
212 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_R2
);
225 static inline uint32_t rotl(uint32_t val
, int n
)
227 return (val
<< n
) | (val
>> (32 - n
));
230 /* ARM immediates for ALU instructions are made of an unsigned 8-bit
231 right-rotated by an even amount between 0 and 30. */
232 static inline int encode_imm(uint32_t imm
)
236 /* simple case, only lower bits */
237 if ((imm
& ~0xff) == 0)
239 /* then try a simple even shift */
240 shift
= ctz32(imm
) & ~1;
241 if (((imm
>> shift
) & ~0xff) == 0)
243 /* now try harder with rotations */
244 if ((rotl(imm
, 2) & ~0xff) == 0)
246 if ((rotl(imm
, 4) & ~0xff) == 0)
248 if ((rotl(imm
, 6) & ~0xff) == 0)
250 /* imm can't be encoded */
254 static inline int check_fit_imm(uint32_t imm
)
256 return encode_imm(imm
) >= 0;
259 /* Test if a constant matches the constraint.
260 * TODO: define constraints for:
262 * ldr/str offset: between -0xfff and 0xfff
263 * ldrh/strh offset: between -0xff and 0xff
264 * mov operand2: values represented with x << (2 * y), x < 0x100
265 * add, sub, eor...: ditto
267 static inline int tcg_target_const_match(tcg_target_long val
,
268 const TCGArgConstraint
*arg_ct
)
272 if (ct
& TCG_CT_CONST
)
274 else if ((ct
& TCG_CT_CONST_ARM
) && check_fit_imm(val
))
280 enum arm_data_opc_e
{
298 #define TO_CPSR(opc) \
299 ((opc == ARITH_CMP || opc == ARITH_CMN || opc == ARITH_TST) << 20)
301 #define SHIFT_IMM_LSL(im) (((im) << 7) | 0x00)
302 #define SHIFT_IMM_LSR(im) (((im) << 7) | 0x20)
303 #define SHIFT_IMM_ASR(im) (((im) << 7) | 0x40)
304 #define SHIFT_IMM_ROR(im) (((im) << 7) | 0x60)
305 #define SHIFT_REG_LSL(rs) (((rs) << 8) | 0x10)
306 #define SHIFT_REG_LSR(rs) (((rs) << 8) | 0x30)
307 #define SHIFT_REG_ASR(rs) (((rs) << 8) | 0x50)
308 #define SHIFT_REG_ROR(rs) (((rs) << 8) | 0x70)
310 enum arm_cond_code_e
{
313 COND_CS
= 0x2, /* Unsigned greater or equal */
314 COND_CC
= 0x3, /* Unsigned less than */
315 COND_MI
= 0x4, /* Negative */
316 COND_PL
= 0x5, /* Zero or greater */
317 COND_VS
= 0x6, /* Overflow */
318 COND_VC
= 0x7, /* No overflow */
319 COND_HI
= 0x8, /* Unsigned greater than */
320 COND_LS
= 0x9, /* Unsigned less or equal */
328 static const uint8_t tcg_cond_to_arm_cond
[10] = {
329 [TCG_COND_EQ
] = COND_EQ
,
330 [TCG_COND_NE
] = COND_NE
,
331 [TCG_COND_LT
] = COND_LT
,
332 [TCG_COND_GE
] = COND_GE
,
333 [TCG_COND_LE
] = COND_LE
,
334 [TCG_COND_GT
] = COND_GT
,
336 [TCG_COND_LTU
] = COND_CC
,
337 [TCG_COND_GEU
] = COND_CS
,
338 [TCG_COND_LEU
] = COND_LS
,
339 [TCG_COND_GTU
] = COND_HI
,
342 static inline void tcg_out_bx(TCGContext
*s
, int cond
, int rn
)
344 tcg_out32(s
, (cond
<< 28) | 0x012fff10 | rn
);
347 static inline void tcg_out_b(TCGContext
*s
, int cond
, int32_t offset
)
349 tcg_out32(s
, (cond
<< 28) | 0x0a000000 |
350 (((offset
- 8) >> 2) & 0x00ffffff));
353 static inline void tcg_out_b_noaddr(TCGContext
*s
, int cond
)
355 /* We pay attention here to not modify the branch target by skipping
356 the corresponding bytes. This ensure that caches and memory are
357 kept coherent during retranslation. */
358 #ifdef HOST_WORDS_BIGENDIAN
359 tcg_out8(s
, (cond
<< 4) | 0x0a);
363 tcg_out8(s
, (cond
<< 4) | 0x0a);
367 static inline void tcg_out_bl(TCGContext
*s
, int cond
, int32_t offset
)
369 tcg_out32(s
, (cond
<< 28) | 0x0b000000 |
370 (((offset
- 8) >> 2) & 0x00ffffff));
373 static inline void tcg_out_blx(TCGContext
*s
, int cond
, int rn
)
375 tcg_out32(s
, (cond
<< 28) | 0x012fff30 | rn
);
378 static inline void tcg_out_blx_imm(TCGContext
*s
, int32_t offset
)
380 tcg_out32(s
, 0xfa000000 | ((offset
& 2) << 23) |
381 (((offset
- 8) >> 2) & 0x00ffffff));
384 static inline void tcg_out_dat_reg(TCGContext
*s
,
385 int cond
, int opc
, int rd
, int rn
, int rm
, int shift
)
387 tcg_out32(s
, (cond
<< 28) | (0 << 25) | (opc
<< 21) | TO_CPSR(opc
) |
388 (rn
<< 16) | (rd
<< 12) | shift
| rm
);
391 static inline void tcg_out_dat_reg2(TCGContext
*s
,
392 int cond
, int opc0
, int opc1
, int rd0
, int rd1
,
393 int rn0
, int rn1
, int rm0
, int rm1
, int shift
)
395 if (rd0
== rn1
|| rd0
== rm1
) {
396 tcg_out32(s
, (cond
<< 28) | (0 << 25) | (opc0
<< 21) | (1 << 20) |
397 (rn0
<< 16) | (8 << 12) | shift
| rm0
);
398 tcg_out32(s
, (cond
<< 28) | (0 << 25) | (opc1
<< 21) |
399 (rn1
<< 16) | (rd1
<< 12) | shift
| rm1
);
400 tcg_out_dat_reg(s
, cond
, ARITH_MOV
,
401 rd0
, 0, TCG_REG_R8
, SHIFT_IMM_LSL(0));
403 tcg_out32(s
, (cond
<< 28) | (0 << 25) | (opc0
<< 21) | (1 << 20) |
404 (rn0
<< 16) | (rd0
<< 12) | shift
| rm0
);
405 tcg_out32(s
, (cond
<< 28) | (0 << 25) | (opc1
<< 21) |
406 (rn1
<< 16) | (rd1
<< 12) | shift
| rm1
);
410 static inline void tcg_out_dat_imm(TCGContext
*s
,
411 int cond
, int opc
, int rd
, int rn
, int im
)
413 tcg_out32(s
, (cond
<< 28) | (1 << 25) | (opc
<< 21) | TO_CPSR(opc
) |
414 (rn
<< 16) | (rd
<< 12) | im
);
417 static inline void tcg_out_movi32(TCGContext
*s
,
418 int cond
, int rd
, uint32_t arg
)
420 /* TODO: This is very suboptimal, we can easily have a constant
421 * pool somewhere after all the instructions. */
422 if ((int)arg
< 0 && (int)arg
>= -0x100) {
423 tcg_out_dat_imm(s
, cond
, ARITH_MVN
, rd
, 0, (~arg
) & 0xff);
424 } else if (use_armv7_instructions
) {
427 tcg_out32(s
, (cond
<< 28) | 0x03000000 | (rd
<< 12)
428 | ((arg
<< 4) & 0x000f0000) | (arg
& 0xfff));
429 if (arg
& 0xffff0000) {
431 tcg_out32(s
, (cond
<< 28) | 0x03400000 | (rd
<< 12)
432 | ((arg
>> 12) & 0x000f0000) | ((arg
>> 16) & 0xfff));
442 rot
= ((32 - i
) << 7) & 0xf00;
443 tcg_out_dat_imm(s
, cond
, opc
, rd
, rn
, ((arg
>> i
) & 0xff) | rot
);
452 static inline void tcg_out_mul32(TCGContext
*s
,
453 int cond
, int rd
, int rs
, int rm
)
456 tcg_out32(s
, (cond
<< 28) | (rd
<< 16) | (0 << 12) |
457 (rs
<< 8) | 0x90 | rm
);
459 tcg_out32(s
, (cond
<< 28) | (rd
<< 16) | (0 << 12) |
460 (rm
<< 8) | 0x90 | rs
);
462 tcg_out32(s
, (cond
<< 28) | ( 8 << 16) | (0 << 12) |
463 (rs
<< 8) | 0x90 | rm
);
464 tcg_out_dat_reg(s
, cond
, ARITH_MOV
,
465 rd
, 0, TCG_REG_R8
, SHIFT_IMM_LSL(0));
469 static inline void tcg_out_umull32(TCGContext
*s
,
470 int cond
, int rd0
, int rd1
, int rs
, int rm
)
472 if (rd0
!= rm
&& rd1
!= rm
)
473 tcg_out32(s
, (cond
<< 28) | 0x800090 |
474 (rd1
<< 16) | (rd0
<< 12) | (rs
<< 8) | rm
);
475 else if (rd0
!= rs
&& rd1
!= rs
)
476 tcg_out32(s
, (cond
<< 28) | 0x800090 |
477 (rd1
<< 16) | (rd0
<< 12) | (rm
<< 8) | rs
);
479 tcg_out_dat_reg(s
, cond
, ARITH_MOV
,
480 TCG_REG_R8
, 0, rm
, SHIFT_IMM_LSL(0));
481 tcg_out32(s
, (cond
<< 28) | 0x800098 |
482 (rd1
<< 16) | (rd0
<< 12) | (rs
<< 8));
486 static inline void tcg_out_smull32(TCGContext
*s
,
487 int cond
, int rd0
, int rd1
, int rs
, int rm
)
489 if (rd0
!= rm
&& rd1
!= rm
)
490 tcg_out32(s
, (cond
<< 28) | 0xc00090 |
491 (rd1
<< 16) | (rd0
<< 12) | (rs
<< 8) | rm
);
492 else if (rd0
!= rs
&& rd1
!= rs
)
493 tcg_out32(s
, (cond
<< 28) | 0xc00090 |
494 (rd1
<< 16) | (rd0
<< 12) | (rm
<< 8) | rs
);
496 tcg_out_dat_reg(s
, cond
, ARITH_MOV
,
497 TCG_REG_R8
, 0, rm
, SHIFT_IMM_LSL(0));
498 tcg_out32(s
, (cond
<< 28) | 0xc00098 |
499 (rd1
<< 16) | (rd0
<< 12) | (rs
<< 8));
503 static inline void tcg_out_ext8s(TCGContext
*s
, int cond
,
506 if (use_armv6_instructions
) {
508 tcg_out32(s
, 0x06af0070 | (cond
<< 28) | (rd
<< 12) | rn
);
510 tcg_out_dat_reg(s
, cond
, ARITH_MOV
,
511 rd
, 0, rn
, SHIFT_IMM_LSL(24));
512 tcg_out_dat_reg(s
, cond
, ARITH_MOV
,
513 rd
, 0, rd
, SHIFT_IMM_ASR(24));
517 static inline void tcg_out_ext8u(TCGContext
*s
, int cond
,
520 tcg_out_dat_imm(s
, cond
, ARITH_AND
, rd
, rn
, 0xff);
523 static inline void tcg_out_ext16s(TCGContext
*s
, int cond
,
526 if (use_armv6_instructions
) {
528 tcg_out32(s
, 0x06bf0070 | (cond
<< 28) | (rd
<< 12) | rn
);
530 tcg_out_dat_reg(s
, cond
, ARITH_MOV
,
531 rd
, 0, rn
, SHIFT_IMM_LSL(16));
532 tcg_out_dat_reg(s
, cond
, ARITH_MOV
,
533 rd
, 0, rd
, SHIFT_IMM_ASR(16));
537 static inline void tcg_out_ext16u(TCGContext
*s
, int cond
,
540 if (use_armv6_instructions
) {
542 tcg_out32(s
, 0x06ff0070 | (cond
<< 28) | (rd
<< 12) | rn
);
544 tcg_out_dat_reg(s
, cond
, ARITH_MOV
,
545 rd
, 0, rn
, SHIFT_IMM_LSL(16));
546 tcg_out_dat_reg(s
, cond
, ARITH_MOV
,
547 rd
, 0, rd
, SHIFT_IMM_LSR(16));
551 static inline void tcg_out_bswap16s(TCGContext
*s
, int cond
, int rd
, int rn
)
553 if (use_armv6_instructions
) {
555 tcg_out32(s
, 0x06ff0fb0 | (cond
<< 28) | (rd
<< 12) | rn
);
557 tcg_out_dat_reg(s
, cond
, ARITH_MOV
,
558 TCG_REG_R8
, 0, rn
, SHIFT_IMM_LSL(24));
559 tcg_out_dat_reg(s
, cond
, ARITH_MOV
,
560 TCG_REG_R8
, 0, TCG_REG_R8
, SHIFT_IMM_ASR(16));
561 tcg_out_dat_reg(s
, cond
, ARITH_ORR
,
562 rd
, TCG_REG_R8
, rn
, SHIFT_IMM_LSR(8));
566 static inline void tcg_out_bswap16(TCGContext
*s
, int cond
, int rd
, int rn
)
568 if (use_armv6_instructions
) {
570 tcg_out32(s
, 0x06bf0fb0 | (cond
<< 28) | (rd
<< 12) | rn
);
572 tcg_out_dat_reg(s
, cond
, ARITH_MOV
,
573 TCG_REG_R8
, 0, rn
, SHIFT_IMM_LSL(24));
574 tcg_out_dat_reg(s
, cond
, ARITH_MOV
,
575 TCG_REG_R8
, 0, TCG_REG_R8
, SHIFT_IMM_LSR(16));
576 tcg_out_dat_reg(s
, cond
, ARITH_ORR
,
577 rd
, TCG_REG_R8
, rn
, SHIFT_IMM_LSR(8));
581 static inline void tcg_out_bswap32(TCGContext
*s
, int cond
, int rd
, int rn
)
583 if (use_armv6_instructions
) {
585 tcg_out32(s
, 0x06bf0f30 | (cond
<< 28) | (rd
<< 12) | rn
);
587 tcg_out_dat_reg(s
, cond
, ARITH_EOR
,
588 TCG_REG_R8
, rn
, rn
, SHIFT_IMM_ROR(16));
589 tcg_out_dat_imm(s
, cond
, ARITH_BIC
,
590 TCG_REG_R8
, TCG_REG_R8
, 0xff | 0x800);
591 tcg_out_dat_reg(s
, cond
, ARITH_MOV
,
592 rd
, 0, rn
, SHIFT_IMM_ROR(8));
593 tcg_out_dat_reg(s
, cond
, ARITH_EOR
,
594 rd
, rd
, TCG_REG_R8
, SHIFT_IMM_LSR(8));
598 static inline void tcg_out_ld32_12(TCGContext
*s
, int cond
,
599 int rd
, int rn
, tcg_target_long im
)
602 tcg_out32(s
, (cond
<< 28) | 0x05900000 |
603 (rn
<< 16) | (rd
<< 12) | (im
& 0xfff));
605 tcg_out32(s
, (cond
<< 28) | 0x05100000 |
606 (rn
<< 16) | (rd
<< 12) | ((-im
) & 0xfff));
609 static inline void tcg_out_st32_12(TCGContext
*s
, int cond
,
610 int rd
, int rn
, tcg_target_long im
)
613 tcg_out32(s
, (cond
<< 28) | 0x05800000 |
614 (rn
<< 16) | (rd
<< 12) | (im
& 0xfff));
616 tcg_out32(s
, (cond
<< 28) | 0x05000000 |
617 (rn
<< 16) | (rd
<< 12) | ((-im
) & 0xfff));
620 static inline void tcg_out_ld32_r(TCGContext
*s
, int cond
,
621 int rd
, int rn
, int rm
)
623 tcg_out32(s
, (cond
<< 28) | 0x07900000 |
624 (rn
<< 16) | (rd
<< 12) | rm
);
627 static inline void tcg_out_st32_r(TCGContext
*s
, int cond
,
628 int rd
, int rn
, int rm
)
630 tcg_out32(s
, (cond
<< 28) | 0x07800000 |
631 (rn
<< 16) | (rd
<< 12) | rm
);
634 /* Register pre-increment with base writeback. */
635 static inline void tcg_out_ld32_rwb(TCGContext
*s
, int cond
,
636 int rd
, int rn
, int rm
)
638 tcg_out32(s
, (cond
<< 28) | 0x07b00000 |
639 (rn
<< 16) | (rd
<< 12) | rm
);
642 static inline void tcg_out_st32_rwb(TCGContext
*s
, int cond
,
643 int rd
, int rn
, int rm
)
645 tcg_out32(s
, (cond
<< 28) | 0x07a00000 |
646 (rn
<< 16) | (rd
<< 12) | rm
);
649 static inline void tcg_out_ld16u_8(TCGContext
*s
, int cond
,
650 int rd
, int rn
, tcg_target_long im
)
653 tcg_out32(s
, (cond
<< 28) | 0x01d000b0 |
654 (rn
<< 16) | (rd
<< 12) |
655 ((im
& 0xf0) << 4) | (im
& 0xf));
657 tcg_out32(s
, (cond
<< 28) | 0x015000b0 |
658 (rn
<< 16) | (rd
<< 12) |
659 (((-im
) & 0xf0) << 4) | ((-im
) & 0xf));
662 static inline void tcg_out_st16_8(TCGContext
*s
, int cond
,
663 int rd
, int rn
, tcg_target_long im
)
666 tcg_out32(s
, (cond
<< 28) | 0x01c000b0 |
667 (rn
<< 16) | (rd
<< 12) |
668 ((im
& 0xf0) << 4) | (im
& 0xf));
670 tcg_out32(s
, (cond
<< 28) | 0x014000b0 |
671 (rn
<< 16) | (rd
<< 12) |
672 (((-im
) & 0xf0) << 4) | ((-im
) & 0xf));
675 static inline void tcg_out_ld16u_r(TCGContext
*s
, int cond
,
676 int rd
, int rn
, int rm
)
678 tcg_out32(s
, (cond
<< 28) | 0x019000b0 |
679 (rn
<< 16) | (rd
<< 12) | rm
);
682 static inline void tcg_out_st16_r(TCGContext
*s
, int cond
,
683 int rd
, int rn
, int rm
)
685 tcg_out32(s
, (cond
<< 28) | 0x018000b0 |
686 (rn
<< 16) | (rd
<< 12) | rm
);
689 static inline void tcg_out_ld16s_8(TCGContext
*s
, int cond
,
690 int rd
, int rn
, tcg_target_long im
)
693 tcg_out32(s
, (cond
<< 28) | 0x01d000f0 |
694 (rn
<< 16) | (rd
<< 12) |
695 ((im
& 0xf0) << 4) | (im
& 0xf));
697 tcg_out32(s
, (cond
<< 28) | 0x015000f0 |
698 (rn
<< 16) | (rd
<< 12) |
699 (((-im
) & 0xf0) << 4) | ((-im
) & 0xf));
702 static inline void tcg_out_ld16s_r(TCGContext
*s
, int cond
,
703 int rd
, int rn
, int rm
)
705 tcg_out32(s
, (cond
<< 28) | 0x019000f0 |
706 (rn
<< 16) | (rd
<< 12) | rm
);
709 static inline void tcg_out_ld8_12(TCGContext
*s
, int cond
,
710 int rd
, int rn
, tcg_target_long im
)
713 tcg_out32(s
, (cond
<< 28) | 0x05d00000 |
714 (rn
<< 16) | (rd
<< 12) | (im
& 0xfff));
716 tcg_out32(s
, (cond
<< 28) | 0x05500000 |
717 (rn
<< 16) | (rd
<< 12) | ((-im
) & 0xfff));
720 static inline void tcg_out_st8_12(TCGContext
*s
, int cond
,
721 int rd
, int rn
, tcg_target_long im
)
724 tcg_out32(s
, (cond
<< 28) | 0x05c00000 |
725 (rn
<< 16) | (rd
<< 12) | (im
& 0xfff));
727 tcg_out32(s
, (cond
<< 28) | 0x05400000 |
728 (rn
<< 16) | (rd
<< 12) | ((-im
) & 0xfff));
731 static inline void tcg_out_ld8_r(TCGContext
*s
, int cond
,
732 int rd
, int rn
, int rm
)
734 tcg_out32(s
, (cond
<< 28) | 0x07d00000 |
735 (rn
<< 16) | (rd
<< 12) | rm
);
738 static inline void tcg_out_st8_r(TCGContext
*s
, int cond
,
739 int rd
, int rn
, int rm
)
741 tcg_out32(s
, (cond
<< 28) | 0x07c00000 |
742 (rn
<< 16) | (rd
<< 12) | rm
);
745 static inline void tcg_out_ld8s_8(TCGContext
*s
, int cond
,
746 int rd
, int rn
, tcg_target_long im
)
749 tcg_out32(s
, (cond
<< 28) | 0x01d000d0 |
750 (rn
<< 16) | (rd
<< 12) |
751 ((im
& 0xf0) << 4) | (im
& 0xf));
753 tcg_out32(s
, (cond
<< 28) | 0x015000d0 |
754 (rn
<< 16) | (rd
<< 12) |
755 (((-im
) & 0xf0) << 4) | ((-im
) & 0xf));
758 static inline void tcg_out_ld8s_r(TCGContext
*s
, int cond
,
759 int rd
, int rn
, int rm
)
761 tcg_out32(s
, (cond
<< 28) | 0x019000d0 |
762 (rn
<< 16) | (rd
<< 12) | rm
);
765 static inline void tcg_out_ld32u(TCGContext
*s
, int cond
,
766 int rd
, int rn
, int32_t offset
)
768 if (offset
> 0xfff || offset
< -0xfff) {
769 tcg_out_movi32(s
, cond
, TCG_REG_R8
, offset
);
770 tcg_out_ld32_r(s
, cond
, rd
, rn
, TCG_REG_R8
);
772 tcg_out_ld32_12(s
, cond
, rd
, rn
, offset
);
775 static inline void tcg_out_st32(TCGContext
*s
, int cond
,
776 int rd
, int rn
, int32_t offset
)
778 if (offset
> 0xfff || offset
< -0xfff) {
779 tcg_out_movi32(s
, cond
, TCG_REG_R8
, offset
);
780 tcg_out_st32_r(s
, cond
, rd
, rn
, TCG_REG_R8
);
782 tcg_out_st32_12(s
, cond
, rd
, rn
, offset
);
785 static inline void tcg_out_ld16u(TCGContext
*s
, int cond
,
786 int rd
, int rn
, int32_t offset
)
788 if (offset
> 0xff || offset
< -0xff) {
789 tcg_out_movi32(s
, cond
, TCG_REG_R8
, offset
);
790 tcg_out_ld16u_r(s
, cond
, rd
, rn
, TCG_REG_R8
);
792 tcg_out_ld16u_8(s
, cond
, rd
, rn
, offset
);
795 static inline void tcg_out_ld16s(TCGContext
*s
, int cond
,
796 int rd
, int rn
, int32_t offset
)
798 if (offset
> 0xff || offset
< -0xff) {
799 tcg_out_movi32(s
, cond
, TCG_REG_R8
, offset
);
800 tcg_out_ld16s_r(s
, cond
, rd
, rn
, TCG_REG_R8
);
802 tcg_out_ld16s_8(s
, cond
, rd
, rn
, offset
);
805 static inline void tcg_out_st16(TCGContext
*s
, int cond
,
806 int rd
, int rn
, int32_t offset
)
808 if (offset
> 0xff || offset
< -0xff) {
809 tcg_out_movi32(s
, cond
, TCG_REG_R8
, offset
);
810 tcg_out_st16_r(s
, cond
, rd
, rn
, TCG_REG_R8
);
812 tcg_out_st16_8(s
, cond
, rd
, rn
, offset
);
815 static inline void tcg_out_ld8u(TCGContext
*s
, int cond
,
816 int rd
, int rn
, int32_t offset
)
818 if (offset
> 0xfff || offset
< -0xfff) {
819 tcg_out_movi32(s
, cond
, TCG_REG_R8
, offset
);
820 tcg_out_ld8_r(s
, cond
, rd
, rn
, TCG_REG_R8
);
822 tcg_out_ld8_12(s
, cond
, rd
, rn
, offset
);
825 static inline void tcg_out_ld8s(TCGContext
*s
, int cond
,
826 int rd
, int rn
, int32_t offset
)
828 if (offset
> 0xff || offset
< -0xff) {
829 tcg_out_movi32(s
, cond
, TCG_REG_R8
, offset
);
830 tcg_out_ld8s_r(s
, cond
, rd
, rn
, TCG_REG_R8
);
832 tcg_out_ld8s_8(s
, cond
, rd
, rn
, offset
);
835 static inline void tcg_out_st8(TCGContext
*s
, int cond
,
836 int rd
, int rn
, int32_t offset
)
838 if (offset
> 0xfff || offset
< -0xfff) {
839 tcg_out_movi32(s
, cond
, TCG_REG_R8
, offset
);
840 tcg_out_st8_r(s
, cond
, rd
, rn
, TCG_REG_R8
);
842 tcg_out_st8_12(s
, cond
, rd
, rn
, offset
);
845 static inline void tcg_out_goto(TCGContext
*s
, int cond
, uint32_t addr
)
850 /* goto to a Thumb destination isn't supported */
854 val
= addr
- (tcg_target_long
) s
->code_ptr
;
855 if (val
- 8 < 0x01fffffd && val
- 8 > -0x01fffffd)
856 tcg_out_b(s
, cond
, val
);
861 if (cond
== COND_AL
) {
862 tcg_out_ld32_12(s
, COND_AL
, TCG_REG_PC
, TCG_REG_PC
, -4);
863 tcg_out32(s
, addr
); /* XXX: This is l->u.value, can we use it? */
865 tcg_out_movi32(s
, cond
, TCG_REG_R8
, val
- 8);
866 tcg_out_dat_reg(s
, cond
, ARITH_ADD
,
867 TCG_REG_PC
, TCG_REG_PC
,
868 TCG_REG_R8
, SHIFT_IMM_LSL(0));
874 static inline void tcg_out_call(TCGContext
*s
, uint32_t addr
)
878 val
= addr
- (tcg_target_long
) s
->code_ptr
;
879 if (val
- 8 < 0x02000000 && val
- 8 >= -0x02000000) {
881 /* Use BLX if the target is in Thumb mode */
882 if (!use_armv5_instructions
) {
885 tcg_out_blx_imm(s
, val
);
887 tcg_out_bl(s
, COND_AL
, val
);
893 if (cond
== COND_AL
) {
894 tcg_out_dat_imm(s
, cond
, ARITH_ADD
, TCG_REG_R14
, TCG_REG_PC
, 4);
895 tcg_out_ld32_12(s
, COND_AL
, TCG_REG_PC
, TCG_REG_PC
, -4);
896 tcg_out32(s
, addr
); /* XXX: This is l->u.value, can we use it? */
898 tcg_out_movi32(s
, cond
, TCG_REG_R9
, addr
);
899 tcg_out_dat_reg(s
, cond
, ARITH_MOV
, TCG_REG_R14
, 0,
900 TCG_REG_PC
, SHIFT_IMM_LSL(0));
901 tcg_out_bx(s
, cond
, TCG_REG_R9
);
907 static inline void tcg_out_callr(TCGContext
*s
, int cond
, int arg
)
909 if (use_armv5_instructions
) {
910 tcg_out_blx(s
, cond
, arg
);
912 tcg_out_dat_reg(s
, cond
, ARITH_MOV
, TCG_REG_R14
, 0,
913 TCG_REG_PC
, SHIFT_IMM_LSL(0));
914 tcg_out_bx(s
, cond
, arg
);
918 static inline void tcg_out_goto_label(TCGContext
*s
, int cond
, int label_index
)
920 TCGLabel
*l
= &s
->labels
[label_index
];
923 tcg_out_goto(s
, cond
, l
->u
.value
);
924 else if (cond
== COND_AL
) {
925 tcg_out_ld32_12(s
, COND_AL
, TCG_REG_PC
, TCG_REG_PC
, -4);
926 tcg_out_reloc(s
, s
->code_ptr
, R_ARM_ABS32
, label_index
, 31337);
929 /* Probably this should be preferred even for COND_AL... */
930 tcg_out_reloc(s
, s
->code_ptr
, R_ARM_PC24
, label_index
, 31337);
931 tcg_out_b_noaddr(s
, cond
);
935 #ifdef CONFIG_SOFTMMU
937 #include "../../softmmu_defs.h"
939 static void *qemu_ld_helpers
[4] = {
946 static void *qemu_st_helpers
[4] = {
954 #define TLB_SHIFT (CPU_TLB_ENTRY_BITS + CPU_TLB_BITS)
956 static inline void tcg_out_qemu_ld(TCGContext
*s
, const TCGArg
*args
, int opc
)
958 int addr_reg
, data_reg
, data_reg2
, bswap
;
959 #ifdef CONFIG_SOFTMMU
960 int mem_index
, s_bits
;
961 # if TARGET_LONG_BITS == 64
967 #ifdef TARGET_WORDS_BIGENDIAN
976 data_reg2
= 0; /* suppress warning */
978 #ifdef CONFIG_SOFTMMU
979 # if TARGET_LONG_BITS == 64
985 /* Should generate something like the following:
986 * shr r8, addr_reg, #TARGET_PAGE_BITS
987 * and r0, r8, #(CPU_TLB_SIZE - 1) @ Assumption: CPU_TLB_BITS <= 8
988 * add r0, env, r0 lsl #CPU_TLB_ENTRY_BITS
990 # if CPU_TLB_BITS > 8
993 tcg_out_dat_reg(s
, COND_AL
, ARITH_MOV
, TCG_REG_R8
,
994 0, addr_reg
, SHIFT_IMM_LSR(TARGET_PAGE_BITS
));
995 tcg_out_dat_imm(s
, COND_AL
, ARITH_AND
,
996 TCG_REG_R0
, TCG_REG_R8
, CPU_TLB_SIZE
- 1);
997 tcg_out_dat_reg(s
, COND_AL
, ARITH_ADD
, TCG_REG_R0
, TCG_AREG0
,
998 TCG_REG_R0
, SHIFT_IMM_LSL(CPU_TLB_ENTRY_BITS
));
1000 * ldr r1 [r0, #(offsetof(CPUState, tlb_table[mem_index][0].addr_read))]
1001 * below, the offset is likely to exceed 12 bits if mem_index != 0 and
1002 * not exceed otherwise, so use an
1003 * add r0, r0, #(mem_index * sizeof *CPUState.tlb_table)
1007 tcg_out_dat_imm(s
, COND_AL
, ARITH_ADD
, TCG_REG_R0
, TCG_REG_R0
,
1008 (mem_index
<< (TLB_SHIFT
& 1)) |
1009 ((16 - (TLB_SHIFT
>> 1)) << 8));
1010 tcg_out_ld32_12(s
, COND_AL
, TCG_REG_R1
, TCG_REG_R0
,
1011 offsetof(CPUState
, tlb_table
[0][0].addr_read
));
1012 tcg_out_dat_reg(s
, COND_AL
, ARITH_CMP
, 0, TCG_REG_R1
,
1013 TCG_REG_R8
, SHIFT_IMM_LSL(TARGET_PAGE_BITS
));
1014 /* Check alignment. */
1016 tcg_out_dat_imm(s
, COND_EQ
, ARITH_TST
,
1017 0, addr_reg
, (1 << s_bits
) - 1);
1018 # if TARGET_LONG_BITS == 64
1019 /* XXX: possibly we could use a block data load or writeback in
1020 * the first access. */
1021 tcg_out_ld32_12(s
, COND_EQ
, TCG_REG_R1
, TCG_REG_R0
,
1022 offsetof(CPUState
, tlb_table
[0][0].addr_read
) + 4);
1023 tcg_out_dat_reg(s
, COND_EQ
, ARITH_CMP
, 0,
1024 TCG_REG_R1
, addr_reg2
, SHIFT_IMM_LSL(0));
1026 tcg_out_ld32_12(s
, COND_EQ
, TCG_REG_R1
, TCG_REG_R0
,
1027 offsetof(CPUState
, tlb_table
[0][0].addend
));
1031 tcg_out_ld8_r(s
, COND_EQ
, data_reg
, addr_reg
, TCG_REG_R1
);
1034 tcg_out_ld8s_r(s
, COND_EQ
, data_reg
, addr_reg
, TCG_REG_R1
);
1037 tcg_out_ld16u_r(s
, COND_EQ
, data_reg
, addr_reg
, TCG_REG_R1
);
1039 tcg_out_bswap16(s
, COND_EQ
, data_reg
, data_reg
);
1044 tcg_out_ld16u_r(s
, COND_EQ
, data_reg
, addr_reg
, TCG_REG_R1
);
1045 tcg_out_bswap16s(s
, COND_EQ
, data_reg
, data_reg
);
1047 tcg_out_ld16s_r(s
, COND_EQ
, data_reg
, addr_reg
, TCG_REG_R1
);
1052 tcg_out_ld32_r(s
, COND_EQ
, data_reg
, addr_reg
, TCG_REG_R1
);
1054 tcg_out_bswap32(s
, COND_EQ
, data_reg
, data_reg
);
1059 tcg_out_ld32_rwb(s
, COND_EQ
, data_reg2
, TCG_REG_R1
, addr_reg
);
1060 tcg_out_ld32_12(s
, COND_EQ
, data_reg
, TCG_REG_R1
, 4);
1061 tcg_out_bswap32(s
, COND_EQ
, data_reg2
, data_reg2
);
1062 tcg_out_bswap32(s
, COND_EQ
, data_reg
, data_reg
);
1064 tcg_out_ld32_rwb(s
, COND_EQ
, data_reg
, TCG_REG_R1
, addr_reg
);
1065 tcg_out_ld32_12(s
, COND_EQ
, data_reg2
, TCG_REG_R1
, 4);
1070 label_ptr
= (void *) s
->code_ptr
;
1071 tcg_out_b_noaddr(s
, COND_EQ
);
1073 /* TODO: move this code to where the constants pool will be */
1074 if (addr_reg
!= TCG_REG_R0
) {
1075 tcg_out_dat_reg(s
, COND_AL
, ARITH_MOV
,
1076 TCG_REG_R0
, 0, addr_reg
, SHIFT_IMM_LSL(0));
1078 # if TARGET_LONG_BITS == 32
1079 tcg_out_dat_imm(s
, COND_AL
, ARITH_MOV
, TCG_REG_R1
, 0, mem_index
);
1081 tcg_out_dat_reg(s
, COND_AL
, ARITH_MOV
,
1082 TCG_REG_R1
, 0, addr_reg2
, SHIFT_IMM_LSL(0));
1083 tcg_out_dat_imm(s
, COND_AL
, ARITH_MOV
, TCG_REG_R2
, 0, mem_index
);
1085 tcg_out_call(s
, (tcg_target_long
) qemu_ld_helpers
[s_bits
]);
1089 tcg_out_ext8s(s
, COND_AL
, data_reg
, TCG_REG_R0
);
1092 tcg_out_ext16s(s
, COND_AL
, data_reg
, TCG_REG_R0
);
1098 if (data_reg
!= TCG_REG_R0
) {
1099 tcg_out_dat_reg(s
, COND_AL
, ARITH_MOV
,
1100 data_reg
, 0, TCG_REG_R0
, SHIFT_IMM_LSL(0));
1104 if (data_reg
!= TCG_REG_R0
) {
1105 tcg_out_dat_reg(s
, COND_AL
, ARITH_MOV
,
1106 data_reg
, 0, TCG_REG_R0
, SHIFT_IMM_LSL(0));
1108 if (data_reg2
!= TCG_REG_R1
) {
1109 tcg_out_dat_reg(s
, COND_AL
, ARITH_MOV
,
1110 data_reg2
, 0, TCG_REG_R1
, SHIFT_IMM_LSL(0));
1115 reloc_pc24(label_ptr
, (tcg_target_long
)s
->code_ptr
);
1116 #else /* !CONFIG_SOFTMMU */
1118 uint32_t offset
= GUEST_BASE
;
1123 i
= ctz32(offset
) & ~1;
1124 rot
= ((32 - i
) << 7) & 0xf00;
1126 tcg_out_dat_imm(s
, COND_AL
, ARITH_ADD
, TCG_REG_R8
, addr_reg
,
1127 ((offset
>> i
) & 0xff) | rot
);
1128 addr_reg
= TCG_REG_R8
;
1129 offset
&= ~(0xff << i
);
1134 tcg_out_ld8_12(s
, COND_AL
, data_reg
, addr_reg
, 0);
1137 tcg_out_ld8s_8(s
, COND_AL
, data_reg
, addr_reg
, 0);
1140 tcg_out_ld16u_8(s
, COND_AL
, data_reg
, addr_reg
, 0);
1142 tcg_out_bswap16(s
, COND_AL
, data_reg
, data_reg
);
1147 tcg_out_ld16u_8(s
, COND_AL
, data_reg
, addr_reg
, 0);
1148 tcg_out_bswap16s(s
, COND_AL
, data_reg
, data_reg
);
1150 tcg_out_ld16s_8(s
, COND_AL
, data_reg
, addr_reg
, 0);
1155 tcg_out_ld32_12(s
, COND_AL
, data_reg
, addr_reg
, 0);
1157 tcg_out_bswap32(s
, COND_AL
, data_reg
, data_reg
);
1161 /* TODO: use block load -
1162 * check that data_reg2 > data_reg or the other way */
1163 if (data_reg
== addr_reg
) {
1164 tcg_out_ld32_12(s
, COND_AL
, data_reg2
, addr_reg
, bswap
? 0 : 4);
1165 tcg_out_ld32_12(s
, COND_AL
, data_reg
, addr_reg
, bswap
? 4 : 0);
1167 tcg_out_ld32_12(s
, COND_AL
, data_reg
, addr_reg
, bswap
? 4 : 0);
1168 tcg_out_ld32_12(s
, COND_AL
, data_reg2
, addr_reg
, bswap
? 0 : 4);
1171 tcg_out_bswap32(s
, COND_AL
, data_reg
, data_reg
);
1172 tcg_out_bswap32(s
, COND_AL
, data_reg2
, data_reg2
);
1179 static inline void tcg_out_qemu_st(TCGContext
*s
, const TCGArg
*args
, int opc
)
1181 int addr_reg
, data_reg
, data_reg2
, bswap
;
1182 #ifdef CONFIG_SOFTMMU
1183 int mem_index
, s_bits
;
1184 # if TARGET_LONG_BITS == 64
1187 uint32_t *label_ptr
;
1190 #ifdef TARGET_WORDS_BIGENDIAN
1197 data_reg2
= *args
++;
1199 data_reg2
= 0; /* suppress warning */
1201 #ifdef CONFIG_SOFTMMU
1202 # if TARGET_LONG_BITS == 64
1203 addr_reg2
= *args
++;
1208 /* Should generate something like the following:
1209 * shr r8, addr_reg, #TARGET_PAGE_BITS
1210 * and r0, r8, #(CPU_TLB_SIZE - 1) @ Assumption: CPU_TLB_BITS <= 8
1211 * add r0, env, r0 lsl #CPU_TLB_ENTRY_BITS
1213 tcg_out_dat_reg(s
, COND_AL
, ARITH_MOV
,
1214 TCG_REG_R8
, 0, addr_reg
, SHIFT_IMM_LSR(TARGET_PAGE_BITS
));
1215 tcg_out_dat_imm(s
, COND_AL
, ARITH_AND
,
1216 TCG_REG_R0
, TCG_REG_R8
, CPU_TLB_SIZE
- 1);
1217 tcg_out_dat_reg(s
, COND_AL
, ARITH_ADD
, TCG_REG_R0
,
1218 TCG_AREG0
, TCG_REG_R0
, SHIFT_IMM_LSL(CPU_TLB_ENTRY_BITS
));
1220 * ldr r1 [r0, #(offsetof(CPUState, tlb_table[mem_index][0].addr_write))]
1221 * below, the offset is likely to exceed 12 bits if mem_index != 0 and
1222 * not exceed otherwise, so use an
1223 * add r0, r0, #(mem_index * sizeof *CPUState.tlb_table)
1227 tcg_out_dat_imm(s
, COND_AL
, ARITH_ADD
, TCG_REG_R0
, TCG_REG_R0
,
1228 (mem_index
<< (TLB_SHIFT
& 1)) |
1229 ((16 - (TLB_SHIFT
>> 1)) << 8));
1230 tcg_out_ld32_12(s
, COND_AL
, TCG_REG_R1
, TCG_REG_R0
,
1231 offsetof(CPUState
, tlb_table
[0][0].addr_write
));
1232 tcg_out_dat_reg(s
, COND_AL
, ARITH_CMP
, 0, TCG_REG_R1
,
1233 TCG_REG_R8
, SHIFT_IMM_LSL(TARGET_PAGE_BITS
));
1234 /* Check alignment. */
1236 tcg_out_dat_imm(s
, COND_EQ
, ARITH_TST
,
1237 0, addr_reg
, (1 << s_bits
) - 1);
1238 # if TARGET_LONG_BITS == 64
1239 /* XXX: possibly we could use a block data load or writeback in
1240 * the first access. */
1241 tcg_out_ld32_12(s
, COND_EQ
, TCG_REG_R1
, TCG_REG_R0
,
1242 offsetof(CPUState
, tlb_table
[0][0].addr_write
) + 4);
1243 tcg_out_dat_reg(s
, COND_EQ
, ARITH_CMP
, 0,
1244 TCG_REG_R1
, addr_reg2
, SHIFT_IMM_LSL(0));
1246 tcg_out_ld32_12(s
, COND_EQ
, TCG_REG_R1
, TCG_REG_R0
,
1247 offsetof(CPUState
, tlb_table
[0][0].addend
));
1251 tcg_out_st8_r(s
, COND_EQ
, data_reg
, addr_reg
, TCG_REG_R1
);
1255 tcg_out_bswap16(s
, COND_EQ
, TCG_REG_R0
, data_reg
);
1256 tcg_out_st16_r(s
, COND_EQ
, TCG_REG_R0
, addr_reg
, TCG_REG_R1
);
1258 tcg_out_st16_r(s
, COND_EQ
, data_reg
, addr_reg
, TCG_REG_R1
);
1264 tcg_out_bswap32(s
, COND_EQ
, TCG_REG_R0
, data_reg
);
1265 tcg_out_st32_r(s
, COND_EQ
, TCG_REG_R0
, addr_reg
, TCG_REG_R1
);
1267 tcg_out_st32_r(s
, COND_EQ
, data_reg
, addr_reg
, TCG_REG_R1
);
1272 tcg_out_bswap32(s
, COND_EQ
, TCG_REG_R0
, data_reg2
);
1273 tcg_out_st32_rwb(s
, COND_EQ
, TCG_REG_R0
, TCG_REG_R1
, addr_reg
);
1274 tcg_out_bswap32(s
, COND_EQ
, TCG_REG_R0
, data_reg
);
1275 tcg_out_st32_12(s
, COND_EQ
, TCG_REG_R0
, TCG_REG_R1
, 4);
1277 tcg_out_st32_rwb(s
, COND_EQ
, data_reg
, TCG_REG_R1
, addr_reg
);
1278 tcg_out_st32_12(s
, COND_EQ
, data_reg2
, TCG_REG_R1
, 4);
1283 label_ptr
= (void *) s
->code_ptr
;
1284 tcg_out_b_noaddr(s
, COND_EQ
);
1286 /* TODO: move this code to where the constants pool will be */
1287 tcg_out_dat_reg(s
, COND_AL
, ARITH_MOV
,
1288 TCG_REG_R0
, 0, addr_reg
, SHIFT_IMM_LSL(0));
1289 # if TARGET_LONG_BITS == 32
1292 tcg_out_ext8u(s
, COND_AL
, TCG_REG_R1
, data_reg
);
1293 tcg_out_dat_imm(s
, COND_AL
, ARITH_MOV
, TCG_REG_R2
, 0, mem_index
);
1296 tcg_out_ext16u(s
, COND_AL
, TCG_REG_R1
, data_reg
);
1297 tcg_out_dat_imm(s
, COND_AL
, ARITH_MOV
, TCG_REG_R2
, 0, mem_index
);
1300 tcg_out_dat_reg(s
, COND_AL
, ARITH_MOV
,
1301 TCG_REG_R1
, 0, data_reg
, SHIFT_IMM_LSL(0));
1302 tcg_out_dat_imm(s
, COND_AL
, ARITH_MOV
, TCG_REG_R2
, 0, mem_index
);
1305 tcg_out_dat_imm(s
, COND_AL
, ARITH_MOV
, TCG_REG_R8
, 0, mem_index
);
1306 tcg_out32(s
, (COND_AL
<< 28) | 0x052d8010); /* str r8, [sp, #-0x10]! */
1307 if (data_reg
!= TCG_REG_R2
) {
1308 tcg_out_dat_reg(s
, COND_AL
, ARITH_MOV
,
1309 TCG_REG_R2
, 0, data_reg
, SHIFT_IMM_LSL(0));
1311 if (data_reg2
!= TCG_REG_R3
) {
1312 tcg_out_dat_reg(s
, COND_AL
, ARITH_MOV
,
1313 TCG_REG_R3
, 0, data_reg2
, SHIFT_IMM_LSL(0));
1318 tcg_out_dat_reg(s
, COND_AL
, ARITH_MOV
,
1319 TCG_REG_R1
, 0, addr_reg2
, SHIFT_IMM_LSL(0));
1322 tcg_out_ext8u(s
, COND_AL
, TCG_REG_R2
, data_reg
);
1323 tcg_out_dat_imm(s
, COND_AL
, ARITH_MOV
, TCG_REG_R3
, 0, mem_index
);
1326 tcg_out_ext16u(s
, COND_AL
, TCG_REG_R2
, data_reg
);
1327 tcg_out_dat_imm(s
, COND_AL
, ARITH_MOV
, TCG_REG_R3
, 0, mem_index
);
1330 if (data_reg
!= TCG_REG_R2
) {
1331 tcg_out_dat_reg(s
, COND_AL
, ARITH_MOV
,
1332 TCG_REG_R2
, 0, data_reg
, SHIFT_IMM_LSL(0));
1334 tcg_out_dat_imm(s
, COND_AL
, ARITH_MOV
, TCG_REG_R3
, 0, mem_index
);
1337 tcg_out_dat_imm(s
, COND_AL
, ARITH_MOV
, TCG_REG_R8
, 0, mem_index
);
1338 tcg_out32(s
, (COND_AL
<< 28) | 0x052d8010); /* str r8, [sp, #-0x10]! */
1339 if (data_reg
!= TCG_REG_R2
) {
1340 tcg_out_dat_reg(s
, COND_AL
, ARITH_MOV
,
1341 TCG_REG_R2
, 0, data_reg
, SHIFT_IMM_LSL(0));
1343 if (data_reg2
!= TCG_REG_R3
) {
1344 tcg_out_dat_reg(s
, COND_AL
, ARITH_MOV
,
1345 TCG_REG_R3
, 0, data_reg2
, SHIFT_IMM_LSL(0));
1351 tcg_out_call(s
, (tcg_target_long
) qemu_st_helpers
[s_bits
]);
1353 tcg_out_dat_imm(s
, COND_AL
, ARITH_ADD
, TCG_REG_R13
, TCG_REG_R13
, 0x10);
1355 reloc_pc24(label_ptr
, (tcg_target_long
)s
->code_ptr
);
1356 #else /* !CONFIG_SOFTMMU */
1358 uint32_t offset
= GUEST_BASE
;
1363 i
= ctz32(offset
) & ~1;
1364 rot
= ((32 - i
) << 7) & 0xf00;
1366 tcg_out_dat_imm(s
, COND_AL
, ARITH_ADD
, TCG_REG_R1
, addr_reg
,
1367 ((offset
>> i
) & 0xff) | rot
);
1368 addr_reg
= TCG_REG_R1
;
1369 offset
&= ~(0xff << i
);
1374 tcg_out_st8_12(s
, COND_AL
, data_reg
, addr_reg
, 0);
1378 tcg_out_bswap16(s
, COND_AL
, TCG_REG_R0
, data_reg
);
1379 tcg_out_st16_8(s
, COND_AL
, TCG_REG_R0
, addr_reg
, 0);
1381 tcg_out_st16_8(s
, COND_AL
, data_reg
, addr_reg
, 0);
1387 tcg_out_bswap32(s
, COND_AL
, TCG_REG_R0
, data_reg
);
1388 tcg_out_st32_12(s
, COND_AL
, TCG_REG_R0
, addr_reg
, 0);
1390 tcg_out_st32_12(s
, COND_AL
, data_reg
, addr_reg
, 0);
1394 /* TODO: use block store -
1395 * check that data_reg2 > data_reg or the other way */
1397 tcg_out_bswap32(s
, COND_AL
, TCG_REG_R0
, data_reg2
);
1398 tcg_out_st32_12(s
, COND_AL
, TCG_REG_R0
, addr_reg
, 0);
1399 tcg_out_bswap32(s
, COND_AL
, TCG_REG_R0
, data_reg
);
1400 tcg_out_st32_12(s
, COND_AL
, TCG_REG_R0
, addr_reg
, 4);
1402 tcg_out_st32_12(s
, COND_AL
, data_reg
, addr_reg
, 0);
1403 tcg_out_st32_12(s
, COND_AL
, data_reg2
, addr_reg
, 4);
1410 static uint8_t *tb_ret_addr
;
1412 static inline void tcg_out_op(TCGContext
*s
, TCGOpcode opc
,
1413 const TCGArg
*args
, const int *const_args
)
1418 case INDEX_op_exit_tb
:
1420 uint8_t *ld_ptr
= s
->code_ptr
;
1422 tcg_out_ld32_12(s
, COND_AL
, TCG_REG_R0
, TCG_REG_PC
, 0);
1424 tcg_out_dat_imm(s
, COND_AL
, ARITH_MOV
, TCG_REG_R0
, 0, args
[0]);
1425 tcg_out_goto(s
, COND_AL
, (tcg_target_ulong
) tb_ret_addr
);
1427 *ld_ptr
= (uint8_t) (s
->code_ptr
- ld_ptr
) - 8;
1428 tcg_out32(s
, args
[0]);
1432 case INDEX_op_goto_tb
:
1433 if (s
->tb_jmp_offset
) {
1434 /* Direct jump method */
1435 #if defined(USE_DIRECT_JUMP)
1436 s
->tb_jmp_offset
[args
[0]] = s
->code_ptr
- s
->code_buf
;
1437 tcg_out_b_noaddr(s
, COND_AL
);
1439 tcg_out_ld32_12(s
, COND_AL
, TCG_REG_PC
, TCG_REG_PC
, -4);
1440 s
->tb_jmp_offset
[args
[0]] = s
->code_ptr
- s
->code_buf
;
1444 /* Indirect jump method */
1446 c
= (int) (s
->tb_next
+ args
[0]) - ((int) s
->code_ptr
+ 8);
1447 if (c
> 0xfff || c
< -0xfff) {
1448 tcg_out_movi32(s
, COND_AL
, TCG_REG_R0
,
1449 (tcg_target_long
) (s
->tb_next
+ args
[0]));
1450 tcg_out_ld32_12(s
, COND_AL
, TCG_REG_PC
, TCG_REG_R0
, 0);
1452 tcg_out_ld32_12(s
, COND_AL
, TCG_REG_PC
, TCG_REG_PC
, c
);
1454 tcg_out_ld32_12(s
, COND_AL
, TCG_REG_R0
, TCG_REG_PC
, 0);
1455 tcg_out_ld32_12(s
, COND_AL
, TCG_REG_PC
, TCG_REG_R0
, 0);
1456 tcg_out32(s
, (tcg_target_long
) (s
->tb_next
+ args
[0]));
1459 s
->tb_next_offset
[args
[0]] = s
->code_ptr
- s
->code_buf
;
1463 tcg_out_call(s
, args
[0]);
1465 tcg_out_callr(s
, COND_AL
, args
[0]);
1469 tcg_out_goto(s
, COND_AL
, args
[0]);
1471 tcg_out_bx(s
, COND_AL
, args
[0]);
1474 tcg_out_goto_label(s
, COND_AL
, args
[0]);
1477 case INDEX_op_ld8u_i32
:
1478 tcg_out_ld8u(s
, COND_AL
, args
[0], args
[1], args
[2]);
1480 case INDEX_op_ld8s_i32
:
1481 tcg_out_ld8s(s
, COND_AL
, args
[0], args
[1], args
[2]);
1483 case INDEX_op_ld16u_i32
:
1484 tcg_out_ld16u(s
, COND_AL
, args
[0], args
[1], args
[2]);
1486 case INDEX_op_ld16s_i32
:
1487 tcg_out_ld16s(s
, COND_AL
, args
[0], args
[1], args
[2]);
1489 case INDEX_op_ld_i32
:
1490 tcg_out_ld32u(s
, COND_AL
, args
[0], args
[1], args
[2]);
1492 case INDEX_op_st8_i32
:
1493 tcg_out_st8(s
, COND_AL
, args
[0], args
[1], args
[2]);
1495 case INDEX_op_st16_i32
:
1496 tcg_out_st16(s
, COND_AL
, args
[0], args
[1], args
[2]);
1498 case INDEX_op_st_i32
:
1499 tcg_out_st32(s
, COND_AL
, args
[0], args
[1], args
[2]);
1502 case INDEX_op_mov_i32
:
1503 tcg_out_dat_reg(s
, COND_AL
, ARITH_MOV
,
1504 args
[0], 0, args
[1], SHIFT_IMM_LSL(0));
1506 case INDEX_op_movi_i32
:
1507 tcg_out_movi32(s
, COND_AL
, args
[0], args
[1]);
1509 case INDEX_op_add_i32
:
1512 case INDEX_op_sub_i32
:
1515 case INDEX_op_and_i32
:
1518 case INDEX_op_andc_i32
:
1521 case INDEX_op_or_i32
:
1524 case INDEX_op_xor_i32
:
1528 if (const_args
[2]) {
1530 rot
= encode_imm(args
[2]);
1531 tcg_out_dat_imm(s
, COND_AL
, c
,
1532 args
[0], args
[1], rotl(args
[2], rot
) | (rot
<< 7));
1534 tcg_out_dat_reg(s
, COND_AL
, c
,
1535 args
[0], args
[1], args
[2], SHIFT_IMM_LSL(0));
1537 case INDEX_op_add2_i32
:
1538 tcg_out_dat_reg2(s
, COND_AL
, ARITH_ADD
, ARITH_ADC
,
1539 args
[0], args
[1], args
[2], args
[3],
1540 args
[4], args
[5], SHIFT_IMM_LSL(0));
1542 case INDEX_op_sub2_i32
:
1543 tcg_out_dat_reg2(s
, COND_AL
, ARITH_SUB
, ARITH_SBC
,
1544 args
[0], args
[1], args
[2], args
[3],
1545 args
[4], args
[5], SHIFT_IMM_LSL(0));
1547 case INDEX_op_neg_i32
:
1548 tcg_out_dat_imm(s
, COND_AL
, ARITH_RSB
, args
[0], args
[1], 0);
1550 case INDEX_op_not_i32
:
1551 tcg_out_dat_reg(s
, COND_AL
,
1552 ARITH_MVN
, args
[0], 0, args
[1], SHIFT_IMM_LSL(0));
1554 case INDEX_op_mul_i32
:
1555 tcg_out_mul32(s
, COND_AL
, args
[0], args
[1], args
[2]);
1557 case INDEX_op_mulu2_i32
:
1558 tcg_out_umull32(s
, COND_AL
, args
[0], args
[1], args
[2], args
[3]);
1560 /* XXX: Perhaps args[2] & 0x1f is wrong */
1561 case INDEX_op_shl_i32
:
1563 SHIFT_IMM_LSL(args
[2] & 0x1f) : SHIFT_REG_LSL(args
[2]);
1565 case INDEX_op_shr_i32
:
1566 c
= const_args
[2] ? (args
[2] & 0x1f) ? SHIFT_IMM_LSR(args
[2] & 0x1f) :
1567 SHIFT_IMM_LSL(0) : SHIFT_REG_LSR(args
[2]);
1569 case INDEX_op_sar_i32
:
1570 c
= const_args
[2] ? (args
[2] & 0x1f) ? SHIFT_IMM_ASR(args
[2] & 0x1f) :
1571 SHIFT_IMM_LSL(0) : SHIFT_REG_ASR(args
[2]);
1573 case INDEX_op_rotr_i32
:
1574 c
= const_args
[2] ? (args
[2] & 0x1f) ? SHIFT_IMM_ROR(args
[2] & 0x1f) :
1575 SHIFT_IMM_LSL(0) : SHIFT_REG_ROR(args
[2]);
1578 tcg_out_dat_reg(s
, COND_AL
, ARITH_MOV
, args
[0], 0, args
[1], c
);
1581 case INDEX_op_rotl_i32
:
1582 if (const_args
[2]) {
1583 tcg_out_dat_reg(s
, COND_AL
, ARITH_MOV
, args
[0], 0, args
[1],
1584 ((0x20 - args
[2]) & 0x1f) ?
1585 SHIFT_IMM_ROR((0x20 - args
[2]) & 0x1f) :
1588 tcg_out_dat_imm(s
, COND_AL
, ARITH_RSB
, TCG_REG_R8
, args
[1], 0x20);
1589 tcg_out_dat_reg(s
, COND_AL
, ARITH_MOV
, args
[0], 0, args
[1],
1590 SHIFT_REG_ROR(TCG_REG_R8
));
1594 case INDEX_op_brcond_i32
:
1595 if (const_args
[1]) {
1597 rot
= encode_imm(args
[1]);
1598 tcg_out_dat_imm(s
, COND_AL
, ARITH_CMP
, 0,
1599 args
[0], rotl(args
[1], rot
) | (rot
<< 7));
1601 tcg_out_dat_reg(s
, COND_AL
, ARITH_CMP
, 0,
1602 args
[0], args
[1], SHIFT_IMM_LSL(0));
1604 tcg_out_goto_label(s
, tcg_cond_to_arm_cond
[args
[2]], args
[3]);
1606 case INDEX_op_brcond2_i32
:
1607 /* The resulting conditions are:
1608 * TCG_COND_EQ --> a0 == a2 && a1 == a3,
1609 * TCG_COND_NE --> (a0 != a2 && a1 == a3) || a1 != a3,
1610 * TCG_COND_LT(U) --> (a0 < a2 && a1 == a3) || a1 < a3,
1611 * TCG_COND_GE(U) --> (a0 >= a2 && a1 == a3) || (a1 >= a3 && a1 != a3),
1612 * TCG_COND_LE(U) --> (a0 <= a2 && a1 == a3) || (a1 <= a3 && a1 != a3),
1613 * TCG_COND_GT(U) --> (a0 > a2 && a1 == a3) || a1 > a3,
1615 tcg_out_dat_reg(s
, COND_AL
, ARITH_CMP
, 0,
1616 args
[1], args
[3], SHIFT_IMM_LSL(0));
1617 tcg_out_dat_reg(s
, COND_EQ
, ARITH_CMP
, 0,
1618 args
[0], args
[2], SHIFT_IMM_LSL(0));
1619 tcg_out_goto_label(s
, tcg_cond_to_arm_cond
[args
[4]], args
[5]);
1621 case INDEX_op_setcond_i32
:
1622 if (const_args
[2]) {
1624 rot
= encode_imm(args
[2]);
1625 tcg_out_dat_imm(s
, COND_AL
, ARITH_CMP
, 0,
1626 args
[1], rotl(args
[2], rot
) | (rot
<< 7));
1628 tcg_out_dat_reg(s
, COND_AL
, ARITH_CMP
, 0,
1629 args
[1], args
[2], SHIFT_IMM_LSL(0));
1631 tcg_out_dat_imm(s
, tcg_cond_to_arm_cond
[args
[3]],
1632 ARITH_MOV
, args
[0], 0, 1);
1633 tcg_out_dat_imm(s
, tcg_cond_to_arm_cond
[tcg_invert_cond(args
[3])],
1634 ARITH_MOV
, args
[0], 0, 0);
1636 case INDEX_op_setcond2_i32
:
1637 /* See brcond2_i32 comment */
1638 tcg_out_dat_reg(s
, COND_AL
, ARITH_CMP
, 0,
1639 args
[2], args
[4], SHIFT_IMM_LSL(0));
1640 tcg_out_dat_reg(s
, COND_EQ
, ARITH_CMP
, 0,
1641 args
[1], args
[3], SHIFT_IMM_LSL(0));
1642 tcg_out_dat_imm(s
, tcg_cond_to_arm_cond
[args
[5]],
1643 ARITH_MOV
, args
[0], 0, 1);
1644 tcg_out_dat_imm(s
, tcg_cond_to_arm_cond
[tcg_invert_cond(args
[5])],
1645 ARITH_MOV
, args
[0], 0, 0);
1648 case INDEX_op_qemu_ld8u
:
1649 tcg_out_qemu_ld(s
, args
, 0);
1651 case INDEX_op_qemu_ld8s
:
1652 tcg_out_qemu_ld(s
, args
, 0 | 4);
1654 case INDEX_op_qemu_ld16u
:
1655 tcg_out_qemu_ld(s
, args
, 1);
1657 case INDEX_op_qemu_ld16s
:
1658 tcg_out_qemu_ld(s
, args
, 1 | 4);
1660 case INDEX_op_qemu_ld32
:
1661 tcg_out_qemu_ld(s
, args
, 2);
1663 case INDEX_op_qemu_ld64
:
1664 tcg_out_qemu_ld(s
, args
, 3);
1667 case INDEX_op_qemu_st8
:
1668 tcg_out_qemu_st(s
, args
, 0);
1670 case INDEX_op_qemu_st16
:
1671 tcg_out_qemu_st(s
, args
, 1);
1673 case INDEX_op_qemu_st32
:
1674 tcg_out_qemu_st(s
, args
, 2);
1676 case INDEX_op_qemu_st64
:
1677 tcg_out_qemu_st(s
, args
, 3);
1680 case INDEX_op_bswap16_i32
:
1681 tcg_out_bswap16(s
, COND_AL
, args
[0], args
[1]);
1683 case INDEX_op_bswap32_i32
:
1684 tcg_out_bswap32(s
, COND_AL
, args
[0], args
[1]);
1687 case INDEX_op_ext8s_i32
:
1688 tcg_out_ext8s(s
, COND_AL
, args
[0], args
[1]);
1690 case INDEX_op_ext16s_i32
:
1691 tcg_out_ext16s(s
, COND_AL
, args
[0], args
[1]);
1693 case INDEX_op_ext16u_i32
:
1694 tcg_out_ext16u(s
, COND_AL
, args
[0], args
[1]);
1702 static const TCGTargetOpDef arm_op_defs
[] = {
1703 { INDEX_op_exit_tb
, { } },
1704 { INDEX_op_goto_tb
, { } },
1705 { INDEX_op_call
, { "ri" } },
1706 { INDEX_op_jmp
, { "ri" } },
1707 { INDEX_op_br
, { } },
1709 { INDEX_op_mov_i32
, { "r", "r" } },
1710 { INDEX_op_movi_i32
, { "r" } },
1712 { INDEX_op_ld8u_i32
, { "r", "r" } },
1713 { INDEX_op_ld8s_i32
, { "r", "r" } },
1714 { INDEX_op_ld16u_i32
, { "r", "r" } },
1715 { INDEX_op_ld16s_i32
, { "r", "r" } },
1716 { INDEX_op_ld_i32
, { "r", "r" } },
1717 { INDEX_op_st8_i32
, { "r", "r" } },
1718 { INDEX_op_st16_i32
, { "r", "r" } },
1719 { INDEX_op_st_i32
, { "r", "r" } },
1721 /* TODO: "r", "r", "ri" */
1722 { INDEX_op_add_i32
, { "r", "r", "rI" } },
1723 { INDEX_op_sub_i32
, { "r", "r", "rI" } },
1724 { INDEX_op_mul_i32
, { "r", "r", "r" } },
1725 { INDEX_op_mulu2_i32
, { "r", "r", "r", "r" } },
1726 { INDEX_op_and_i32
, { "r", "r", "rI" } },
1727 { INDEX_op_andc_i32
, { "r", "r", "rI" } },
1728 { INDEX_op_or_i32
, { "r", "r", "rI" } },
1729 { INDEX_op_xor_i32
, { "r", "r", "rI" } },
1730 { INDEX_op_neg_i32
, { "r", "r" } },
1731 { INDEX_op_not_i32
, { "r", "r" } },
1733 { INDEX_op_shl_i32
, { "r", "r", "ri" } },
1734 { INDEX_op_shr_i32
, { "r", "r", "ri" } },
1735 { INDEX_op_sar_i32
, { "r", "r", "ri" } },
1736 { INDEX_op_rotl_i32
, { "r", "r", "ri" } },
1737 { INDEX_op_rotr_i32
, { "r", "r", "ri" } },
1739 { INDEX_op_brcond_i32
, { "r", "rI" } },
1740 { INDEX_op_setcond_i32
, { "r", "r", "rI" } },
1742 /* TODO: "r", "r", "r", "r", "ri", "ri" */
1743 { INDEX_op_add2_i32
, { "r", "r", "r", "r", "r", "r" } },
1744 { INDEX_op_sub2_i32
, { "r", "r", "r", "r", "r", "r" } },
1745 { INDEX_op_brcond2_i32
, { "r", "r", "r", "r" } },
1746 { INDEX_op_setcond2_i32
, { "r", "r", "r", "r", "r" } },
1748 #if TARGET_LONG_BITS == 32
1749 { INDEX_op_qemu_ld8u
, { "r", "l" } },
1750 { INDEX_op_qemu_ld8s
, { "r", "l" } },
1751 { INDEX_op_qemu_ld16u
, { "r", "l" } },
1752 { INDEX_op_qemu_ld16s
, { "r", "l" } },
1753 { INDEX_op_qemu_ld32
, { "r", "l" } },
1754 { INDEX_op_qemu_ld64
, { "L", "L", "l" } },
1756 { INDEX_op_qemu_st8
, { "s", "s" } },
1757 { INDEX_op_qemu_st16
, { "s", "s" } },
1758 { INDEX_op_qemu_st32
, { "s", "s" } },
1759 { INDEX_op_qemu_st64
, { "S", "S", "s" } },
1761 { INDEX_op_qemu_ld8u
, { "r", "l", "l" } },
1762 { INDEX_op_qemu_ld8s
, { "r", "l", "l" } },
1763 { INDEX_op_qemu_ld16u
, { "r", "l", "l" } },
1764 { INDEX_op_qemu_ld16s
, { "r", "l", "l" } },
1765 { INDEX_op_qemu_ld32
, { "r", "l", "l" } },
1766 { INDEX_op_qemu_ld64
, { "L", "L", "l", "l" } },
1768 { INDEX_op_qemu_st8
, { "s", "s", "s" } },
1769 { INDEX_op_qemu_st16
, { "s", "s", "s" } },
1770 { INDEX_op_qemu_st32
, { "s", "s", "s" } },
1771 { INDEX_op_qemu_st64
, { "S", "S", "s", "s" } },
1774 { INDEX_op_bswap16_i32
, { "r", "r" } },
1775 { INDEX_op_bswap32_i32
, { "r", "r" } },
1777 { INDEX_op_ext8s_i32
, { "r", "r" } },
1778 { INDEX_op_ext16s_i32
, { "r", "r" } },
1779 { INDEX_op_ext16u_i32
, { "r", "r" } },
1784 static void tcg_target_init(TCGContext
*s
)
1786 #if !defined(CONFIG_USER_ONLY)
1788 if ((1 << CPU_TLB_ENTRY_BITS
) != sizeof(CPUTLBEntry
))
1792 tcg_regset_set32(tcg_target_available_regs
[TCG_TYPE_I32
], 0, 0xffff);
1793 tcg_regset_set32(tcg_target_call_clobber_regs
, 0,
1798 (1 << TCG_REG_R12
) |
1799 (1 << TCG_REG_R14
));
1801 tcg_regset_clear(s
->reserved_regs
);
1802 tcg_regset_set_reg(s
->reserved_regs
, TCG_REG_CALL_STACK
);
1803 tcg_regset_set_reg(s
->reserved_regs
, TCG_REG_R8
);
1804 tcg_regset_set_reg(s
->reserved_regs
, TCG_REG_PC
);
1806 tcg_add_target_add_op_defs(arm_op_defs
);
1807 tcg_set_frame(s
, TCG_AREG0
, offsetof(CPUState
, temp_buf
),
1808 CPU_TEMP_BUF_NLONGS
* sizeof(long));
1811 static inline void tcg_out_ld(TCGContext
*s
, TCGType type
, int arg
,
1812 int arg1
, tcg_target_long arg2
)
1814 tcg_out_ld32u(s
, COND_AL
, arg
, arg1
, arg2
);
1817 static inline void tcg_out_st(TCGContext
*s
, TCGType type
, int arg
,
1818 int arg1
, tcg_target_long arg2
)
1820 tcg_out_st32(s
, COND_AL
, arg
, arg1
, arg2
);
1823 static inline void tcg_out_mov(TCGContext
*s
, TCGType type
, int ret
, int arg
)
1825 tcg_out_dat_reg(s
, COND_AL
, ARITH_MOV
, ret
, 0, arg
, SHIFT_IMM_LSL(0));
1828 static inline void tcg_out_movi(TCGContext
*s
, TCGType type
,
1829 int ret
, tcg_target_long arg
)
1831 tcg_out_movi32(s
, COND_AL
, ret
, arg
);
1834 static void tcg_target_qemu_prologue(TCGContext
*s
)
1836 /* Calling convention requires us to save r4-r11 and lr;
1837 * save also r12 to maintain stack 8-alignment.
1840 /* stmdb sp!, { r4 - r12, lr } */
1841 tcg_out32(s
, (COND_AL
<< 28) | 0x092d5ff0);
1843 tcg_out_mov(s
, TCG_TYPE_PTR
, TCG_AREG0
, tcg_target_call_iarg_regs
[0]);
1845 tcg_out_bx(s
, COND_AL
, tcg_target_call_iarg_regs
[1]);
1846 tb_ret_addr
= s
->code_ptr
;
1848 /* ldmia sp!, { r4 - r12, pc } */
1849 tcg_out32(s
, (COND_AL
<< 28) | 0x08bd9ff0);