hw/pci/msi.c

   1 /*
   2  * msi.c
   3  *
   4  * Copyright (c) 2010 Isaku Yamahata <yamahata at valinux co jp>
   5  *                    VA Linux Systems Japan K.K.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16
  17  * You should have received a copy of the GNU General Public License along
  18  * with this program; if not, see <http://www.gnu.org/licenses/>.
  19  */
  20
  21 #include "qemu/osdep.h"
  22 #include "hw/pci/msi.h"
  23 #include "hw/xen/xen.h"
  24 #include "qemu/range.h"
  25
  26 /* PCI_MSI_ADDRESS_LO */
  27 #define PCI_MSI_ADDRESS_LO_MASK         (~0x3)
  28
  29 /* If we get rid of cap allocator, we won't need those. */
  30 #define PCI_MSI_32_SIZEOF       0x0a
  31 #define PCI_MSI_64_SIZEOF       0x0e
  32 #define PCI_MSI_32M_SIZEOF      0x14
  33 #define PCI_MSI_64M_SIZEOF      0x18
  34
  35 #define PCI_MSI_VECTORS_MAX     32
  36
  37 /*
  38  * Flag for interrupt controllers to declare broken MSI/MSI-X support.
  39  * values: false - broken; true - non-broken.
  40  *
  41  * Setting this flag to false will remove MSI/MSI-X capability from all devices.
  42  *
  43  * It is preferable for controllers to set this to true (non-broken) even if
  44  * they do not actually support MSI/MSI-X: guests normally probe the controller
  45  * type and do not attempt to enable MSI/MSI-X with interrupt controllers not
  46  * supporting such, so removing the capability is not required, and
  47  * it seems cleaner to have a given device look the same for all boards.
  48  *
  49  * TODO: some existing controllers violate the above rule. Identify and fix them.
  50  */
  51 bool msi_nonbroken;
  52
  53 /* If we get rid of cap allocator, we won't need this. */
  54 static inline uint8_t msi_cap_sizeof(uint16_t flags)
  55 {
  56     switch (flags & (PCI_MSI_FLAGS_MASKBIT | PCI_MSI_FLAGS_64BIT)) {
  57     case PCI_MSI_FLAGS_MASKBIT | PCI_MSI_FLAGS_64BIT:
  58         return PCI_MSI_64M_SIZEOF;
  59     case PCI_MSI_FLAGS_64BIT:
  60         return PCI_MSI_64_SIZEOF;
  61     case PCI_MSI_FLAGS_MASKBIT:
  62         return PCI_MSI_32M_SIZEOF;
  63     case 0:
  64         return PCI_MSI_32_SIZEOF;
  65     default:
  66         abort();
  67         break;
  68     }
  69     return 0;
  70 }
  71
  72 //#define MSI_DEBUG
  73
  74 #ifdef MSI_DEBUG
  75 # define MSI_DPRINTF(fmt, ...)                                          \
  76     fprintf(stderr, "%s:%d " fmt, __func__, __LINE__, ## __VA_ARGS__)
  77 #else
  78 # define MSI_DPRINTF(fmt, ...)  do { } while (0)
  79 #endif
  80 #define MSI_DEV_PRINTF(dev, fmt, ...)                                   \
  81     MSI_DPRINTF("%s:%x " fmt, (dev)->name, (dev)->devfn, ## __VA_ARGS__)
  82
  83 static inline unsigned int msi_nr_vectors(uint16_t flags)
  84 {
  85     return 1U <<
  86         ((flags & PCI_MSI_FLAGS_QSIZE) >> ctz32(PCI_MSI_FLAGS_QSIZE));
  87 }
  88
  89 static inline uint8_t msi_flags_off(const PCIDevice* dev)
  90 {
  91     return dev->msi_cap + PCI_MSI_FLAGS;
  92 }
  93
  94 static inline uint8_t msi_address_lo_off(const PCIDevice* dev)
  95 {
  96     return dev->msi_cap + PCI_MSI_ADDRESS_LO;
  97 }
  98
  99 static inline uint8_t msi_address_hi_off(const PCIDevice* dev)
 100 {
 101     return dev->msi_cap + PCI_MSI_ADDRESS_HI;
 102 }
 103
 104 static inline uint8_t msi_data_off(const PCIDevice* dev, bool msi64bit)
 105 {
 106     return dev->msi_cap + (msi64bit ? PCI_MSI_DATA_64 : PCI_MSI_DATA_32);
 107 }
 108
 109 static inline uint8_t msi_mask_off(const PCIDevice* dev, bool msi64bit)
 110 {
 111     return dev->msi_cap + (msi64bit ? PCI_MSI_MASK_64 : PCI_MSI_MASK_32);
 112 }
 113
 114 static inline uint8_t msi_pending_off(const PCIDevice* dev, bool msi64bit)
 115 {
 116     return dev->msi_cap + (msi64bit ? PCI_MSI_PENDING_64 : PCI_MSI_PENDING_32);
 117 }
 118
 119 /*
 120  * Special API for POWER to configure the vectors through
 121  * a side channel. Should never be used by devices.
 122  */
 123 void msi_set_message(PCIDevice *dev, MSIMessage msg)
 124 {
 125     uint16_t flags = pci_get_word(dev->config + msi_flags_off(dev));
 126     bool msi64bit = flags & PCI_MSI_FLAGS_64BIT;
 127
 128     if (msi64bit) {
 129         pci_set_quad(dev->config + msi_address_lo_off(dev), msg.address);
 130     } else {
 131         pci_set_long(dev->config + msi_address_lo_off(dev), msg.address);
 132     }
 133     pci_set_word(dev->config + msi_data_off(dev, msi64bit), msg.data);
 134 }
 135
 136 MSIMessage msi_get_message(PCIDevice *dev, unsigned int vector)
 137 {
 138     uint16_t flags = pci_get_word(dev->config + msi_flags_off(dev));
 139     bool msi64bit = flags & PCI_MSI_FLAGS_64BIT;
 140     unsigned int nr_vectors = msi_nr_vectors(flags);
 141     MSIMessage msg;
 142
 143     assert(vector < nr_vectors);
 144
 145     if (msi64bit) {
 146         msg.address = pci_get_quad(dev->config + msi_address_lo_off(dev));
 147     } else {
 148         msg.address = pci_get_long(dev->config + msi_address_lo_off(dev));
 149     }
 150
 151     /* upper bit 31:16 is zero */
 152     msg.data = pci_get_word(dev->config + msi_data_off(dev, msi64bit));
 153     if (nr_vectors > 1) {
 154         msg.data &= ~(nr_vectors - 1);
 155         msg.data |= vector;
 156     }
 157
 158     return msg;
 159 }
 160
 161 bool msi_enabled(const PCIDevice *dev)
 162 {
 163     return msi_present(dev) &&
 164         (pci_get_word(dev->config + msi_flags_off(dev)) &
 165          PCI_MSI_FLAGS_ENABLE);
 166 }
 167
 168 /*
 169  * Make PCI device @dev MSI-capable.
 170  * Non-zero @offset puts capability MSI at that offset in PCI config
 171  * space.
 172  * @nr_vectors is the number of MSI vectors (1, 2, 4, 8, 16 or 32).
 173  * If @msi64bit, make the device capable of sending a 64-bit message
 174  * address.
 175  * If @msi_per_vector_mask, make the device support per-vector masking.
 176  * Return 0 on success, return -errno on error.
 177  *
 178  * -ENOTSUP means lacking msi support for a msi-capable platform.
 179  * -EINVAL means capability overlap, happens when @offset is non-zero,
 180  *  also means a programming error, except device assignment, which can check
 181  *  if a real HW is broken.
 182  */
 183 int msi_init(struct PCIDevice *dev, uint8_t offset,
 184              unsigned int nr_vectors, bool msi64bit, bool msi_per_vector_mask)
 185 {
 186     unsigned int vectors_order;
 187     uint16_t flags;
 188     uint8_t cap_size;
 189     int config_offset;
 190
 191     if (!msi_nonbroken) {
 192         return -ENOTSUP;
 193     }
 194
 195     MSI_DEV_PRINTF(dev,
 196                    "init offset: 0x%"PRIx8" vector: %"PRId8
 197                    " 64bit %d mask %d\n",
 198                    offset, nr_vectors, msi64bit, msi_per_vector_mask);
 199
 200     assert(!(nr_vectors & (nr_vectors - 1)));   /* power of 2 */
 201     assert(nr_vectors > 0);
 202     assert(nr_vectors <= PCI_MSI_VECTORS_MAX);
 203     /* the nr of MSI vectors is up to 32 */
 204     vectors_order = ctz32(nr_vectors);
 205
 206     flags = vectors_order << ctz32(PCI_MSI_FLAGS_QMASK);
 207     if (msi64bit) {
 208         flags |= PCI_MSI_FLAGS_64BIT;
 209     }
 210     if (msi_per_vector_mask) {
 211         flags |= PCI_MSI_FLAGS_MASKBIT;
 212     }
 213
 214     cap_size = msi_cap_sizeof(flags);
 215     config_offset = pci_add_capability(dev, PCI_CAP_ID_MSI, offset, cap_size);
 216     if (config_offset < 0) {
 217         return config_offset;
 218     }
 219
 220     dev->msi_cap = config_offset;
 221     dev->cap_present |= QEMU_PCI_CAP_MSI;
 222
 223     pci_set_word(dev->config + msi_flags_off(dev), flags);
 224     pci_set_word(dev->wmask + msi_flags_off(dev),
 225                  PCI_MSI_FLAGS_QSIZE | PCI_MSI_FLAGS_ENABLE);
 226     pci_set_long(dev->wmask + msi_address_lo_off(dev),
 227                  PCI_MSI_ADDRESS_LO_MASK);
 228     if (msi64bit) {
 229         pci_set_long(dev->wmask + msi_address_hi_off(dev), 0xffffffff);
 230     }
 231     pci_set_word(dev->wmask + msi_data_off(dev, msi64bit), 0xffff);
 232
 233     if (msi_per_vector_mask) {
 234         /* Make mask bits 0 to nr_vectors - 1 writable. */
 235         pci_set_long(dev->wmask + msi_mask_off(dev, msi64bit),
 236                      0xffffffff >> (PCI_MSI_VECTORS_MAX - nr_vectors));
 237     }
 238
 239     return 0;
 240 }
 241
 242 void msi_uninit(struct PCIDevice *dev)
 243 {
 244     uint16_t flags;
 245     uint8_t cap_size;
 246
 247     if (!msi_present(dev)) {
 248         return;
 249     }
 250     flags = pci_get_word(dev->config + msi_flags_off(dev));
 251     cap_size = msi_cap_sizeof(flags);
 252     pci_del_capability(dev, PCI_CAP_ID_MSI, cap_size);
 253     dev->cap_present &= ~QEMU_PCI_CAP_MSI;
 254
 255     MSI_DEV_PRINTF(dev, "uninit\n");
 256 }
 257
 258 void msi_reset(PCIDevice *dev)
 259 {
 260     uint16_t flags;
 261     bool msi64bit;
 262
 263     if (!msi_present(dev)) {
 264         return;
 265     }
 266
 267     flags = pci_get_word(dev->config + msi_flags_off(dev));
 268     flags &= ~(PCI_MSI_FLAGS_QSIZE | PCI_MSI_FLAGS_ENABLE);
 269     msi64bit = flags & PCI_MSI_FLAGS_64BIT;
 270
 271     pci_set_word(dev->config + msi_flags_off(dev), flags);
 272     pci_set_long(dev->config + msi_address_lo_off(dev), 0);
 273     if (msi64bit) {
 274         pci_set_long(dev->config + msi_address_hi_off(dev), 0);
 275     }
 276     pci_set_word(dev->config + msi_data_off(dev, msi64bit), 0);
 277     if (flags & PCI_MSI_FLAGS_MASKBIT) {
 278         pci_set_long(dev->config + msi_mask_off(dev, msi64bit), 0);
 279         pci_set_long(dev->config + msi_pending_off(dev, msi64bit), 0);
 280     }
 281     MSI_DEV_PRINTF(dev, "reset\n");
 282 }
 283
 284 static bool msi_is_masked(const PCIDevice *dev, unsigned int vector)
 285 {
 286     uint16_t flags = pci_get_word(dev->config + msi_flags_off(dev));
 287     uint32_t mask, data;
 288     bool msi64bit = flags & PCI_MSI_FLAGS_64BIT;
 289     assert(vector < PCI_MSI_VECTORS_MAX);
 290
 291     if (!(flags & PCI_MSI_FLAGS_MASKBIT)) {
 292         return false;
 293     }
 294
 295     data = pci_get_word(dev->config + msi_data_off(dev, msi64bit));
 296     if (xen_is_pirq_msi(data)) {
 297         return false;
 298     }
 299
 300     mask = pci_get_long(dev->config +
 301                         msi_mask_off(dev, flags & PCI_MSI_FLAGS_64BIT));
 302     return mask & (1U << vector);
 303 }
 304
 305 void msi_notify(PCIDevice *dev, unsigned int vector)
 306 {
 307     uint16_t flags = pci_get_word(dev->config + msi_flags_off(dev));
 308     bool msi64bit = flags & PCI_MSI_FLAGS_64BIT;
 309     unsigned int nr_vectors = msi_nr_vectors(flags);
 310     MSIMessage msg;
 311
 312     assert(vector < nr_vectors);
 313     if (msi_is_masked(dev, vector)) {
 314         assert(flags & PCI_MSI_FLAGS_MASKBIT);
 315         pci_long_test_and_set_mask(
 316             dev->config + msi_pending_off(dev, msi64bit), 1U << vector);
 317         MSI_DEV_PRINTF(dev, "pending vector 0x%x\n", vector);
 318         return;
 319     }
 320
 321     msg = msi_get_message(dev, vector);
 322
 323     MSI_DEV_PRINTF(dev,
 324                    "notify vector 0x%x"
 325                    " address: 0x%"PRIx64" data: 0x%"PRIx32"\n",
 326                    vector, msg.address, msg.data);
 327     msi_send_message(dev, msg);
 328 }
 329
 330 void msi_send_message(PCIDevice *dev, MSIMessage msg)
 331 {
 332     MemTxAttrs attrs = {};
 333
 334     attrs.requester_id = pci_requester_id(dev);
 335     address_space_stl_le(&dev->bus_master_as, msg.address, msg.data,
 336                          attrs, NULL);
 337 }
 338
 339 /* Normally called by pci_default_write_config(). */
 340 void msi_write_config(PCIDevice *dev, uint32_t addr, uint32_t val, int len)
 341 {
 342     uint16_t flags = pci_get_word(dev->config + msi_flags_off(dev));
 343     bool msi64bit = flags & PCI_MSI_FLAGS_64BIT;
 344     bool msi_per_vector_mask = flags & PCI_MSI_FLAGS_MASKBIT;
 345     unsigned int nr_vectors;
 346     uint8_t log_num_vecs;
 347     uint8_t log_max_vecs;
 348     unsigned int vector;
 349     uint32_t pending;
 350
 351     if (!msi_present(dev) ||
 352         !ranges_overlap(addr, len, dev->msi_cap, msi_cap_sizeof(flags))) {
 353         return;
 354     }
 355
 356 #ifdef MSI_DEBUG
 357     MSI_DEV_PRINTF(dev, "addr 0x%"PRIx32" val 0x%"PRIx32" len %d\n",
 358                    addr, val, len);
 359     MSI_DEV_PRINTF(dev, "ctrl: 0x%"PRIx16" address: 0x%"PRIx32,
 360                    flags,
 361                    pci_get_long(dev->config + msi_address_lo_off(dev)));
 362     if (msi64bit) {
 363         fprintf(stderr, " address-hi: 0x%"PRIx32,
 364                 pci_get_long(dev->config + msi_address_hi_off(dev)));
 365     }
 366     fprintf(stderr, " data: 0x%"PRIx16,
 367             pci_get_word(dev->config + msi_data_off(dev, msi64bit)));
 368     if (flags & PCI_MSI_FLAGS_MASKBIT) {
 369         fprintf(stderr, " mask 0x%"PRIx32" pending 0x%"PRIx32,
 370                 pci_get_long(dev->config + msi_mask_off(dev, msi64bit)),
 371                 pci_get_long(dev->config + msi_pending_off(dev, msi64bit)));
 372     }
 373     fprintf(stderr, "\n");
 374 #endif
 375
 376     if (!(flags & PCI_MSI_FLAGS_ENABLE)) {
 377         return;
 378     }
 379
 380     /*
 381      * Now MSI is enabled, clear INTx# interrupts.
 382      * the driver is prohibited from writing enable bit to mask
 383      * a service request. But the guest OS could do this.
 384      * So we just discard the interrupts as moderate fallback.
 385      *
 386      * 6.8.3.3. Enabling Operation
 387      *   While enabled for MSI or MSI-X operation, a function is prohibited
 388      *   from using its INTx# pin (if implemented) to request
 389      *   service (MSI, MSI-X, and INTx# are mutually exclusive).
 390      */
 391     pci_device_deassert_intx(dev);
 392
 393     /*
 394      * nr_vectors might be set bigger than capable. So clamp it.
 395      * This is not legal by spec, so we can do anything we like,
 396      * just don't crash the host
 397      */
 398     log_num_vecs =
 399         (flags & PCI_MSI_FLAGS_QSIZE) >> ctz32(PCI_MSI_FLAGS_QSIZE);
 400     log_max_vecs =
 401         (flags & PCI_MSI_FLAGS_QMASK) >> ctz32(PCI_MSI_FLAGS_QMASK);
 402     if (log_num_vecs > log_max_vecs) {
 403         flags &= ~PCI_MSI_FLAGS_QSIZE;
 404         flags |= log_max_vecs << ctz32(PCI_MSI_FLAGS_QSIZE);
 405         pci_set_word(dev->config + msi_flags_off(dev), flags);
 406     }
 407
 408     if (!msi_per_vector_mask) {
 409         /* if per vector masking isn't supported,
 410            there is no pending interrupt. */
 411         return;
 412     }
 413
 414     nr_vectors = msi_nr_vectors(flags);
 415
 416     /* This will discard pending interrupts, if any. */
 417     pending = pci_get_long(dev->config + msi_pending_off(dev, msi64bit));
 418     pending &= 0xffffffff >> (PCI_MSI_VECTORS_MAX - nr_vectors);
 419     pci_set_long(dev->config + msi_pending_off(dev, msi64bit), pending);
 420
 421     /* deliver pending interrupts which are unmasked */
 422     for (vector = 0; vector < nr_vectors; ++vector) {
 423         if (msi_is_masked(dev, vector) || !(pending & (1U << vector))) {
 424             continue;
 425         }
 426
 427         pci_long_test_and_clear_mask(
 428             dev->config + msi_pending_off(dev, msi64bit), 1U << vector);
 429         msi_notify(dev, vector);
 430     }
 431 }
 432
 433 unsigned int msi_nr_vectors_allocated(const PCIDevice *dev)
 434 {
 435     uint16_t flags = pci_get_word(dev->config + msi_flags_off(dev));
 436     return msi_nr_vectors(flags);
 437 }