hw/arm/xlnx-versal: Connect the OSPI flash memory controller model
[qemu.git] / hw / nvram / fw_cfg.c
blobe5f3c981841d04778849bb5e6df1cfb055e907f4
1 /*
2 * QEMU Firmware configuration device emulation
4 * Copyright (c) 2008 Gleb Natapov
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
25 #include "qemu/osdep.h"
26 #include "qemu-common.h"
27 #include "qemu/datadir.h"
28 #include "sysemu/sysemu.h"
29 #include "sysemu/dma.h"
30 #include "sysemu/reset.h"
31 #include "hw/boards.h"
32 #include "hw/nvram/fw_cfg.h"
33 #include "hw/qdev-properties.h"
34 #include "hw/sysbus.h"
35 #include "migration/qemu-file-types.h"
36 #include "migration/vmstate.h"
37 #include "trace.h"
38 #include "qemu/error-report.h"
39 #include "qemu/option.h"
40 #include "qemu/config-file.h"
41 #include "qemu/cutils.h"
42 #include "qapi/error.h"
43 #include "hw/acpi/aml-build.h"
44 #include "hw/pci/pci_bus.h"
46 #define FW_CFG_FILE_SLOTS_DFLT 0x20
48 /* FW_CFG_VERSION bits */
49 #define FW_CFG_VERSION 0x01
50 #define FW_CFG_VERSION_DMA 0x02
52 /* FW_CFG_DMA_CONTROL bits */
53 #define FW_CFG_DMA_CTL_ERROR 0x01
54 #define FW_CFG_DMA_CTL_READ 0x02
55 #define FW_CFG_DMA_CTL_SKIP 0x04
56 #define FW_CFG_DMA_CTL_SELECT 0x08
57 #define FW_CFG_DMA_CTL_WRITE 0x10
59 #define FW_CFG_DMA_SIGNATURE 0x51454d5520434647ULL /* "QEMU CFG" */
61 struct FWCfgEntry {
62 uint32_t len;
63 bool allow_write;
64 uint8_t *data;
65 void *callback_opaque;
66 FWCfgCallback select_cb;
67 FWCfgWriteCallback write_cb;
70 /**
71 * key_name:
73 * @key: The uint16 selector key.
75 * Returns: The stringified name if the selector refers to a well-known
76 * numerically defined item, or NULL on key lookup failure.
78 static const char *key_name(uint16_t key)
80 static const char *fw_cfg_wellknown_keys[FW_CFG_FILE_FIRST] = {
81 [FW_CFG_SIGNATURE] = "signature",
82 [FW_CFG_ID] = "id",
83 [FW_CFG_UUID] = "uuid",
84 [FW_CFG_RAM_SIZE] = "ram_size",
85 [FW_CFG_NOGRAPHIC] = "nographic",
86 [FW_CFG_NB_CPUS] = "nb_cpus",
87 [FW_CFG_MACHINE_ID] = "machine_id",
88 [FW_CFG_KERNEL_ADDR] = "kernel_addr",
89 [FW_CFG_KERNEL_SIZE] = "kernel_size",
90 [FW_CFG_KERNEL_CMDLINE] = "kernel_cmdline",
91 [FW_CFG_INITRD_ADDR] = "initrd_addr",
92 [FW_CFG_INITRD_SIZE] = "initdr_size",
93 [FW_CFG_BOOT_DEVICE] = "boot_device",
94 [FW_CFG_NUMA] = "numa",
95 [FW_CFG_BOOT_MENU] = "boot_menu",
96 [FW_CFG_MAX_CPUS] = "max_cpus",
97 [FW_CFG_KERNEL_ENTRY] = "kernel_entry",
98 [FW_CFG_KERNEL_DATA] = "kernel_data",
99 [FW_CFG_INITRD_DATA] = "initrd_data",
100 [FW_CFG_CMDLINE_ADDR] = "cmdline_addr",
101 [FW_CFG_CMDLINE_SIZE] = "cmdline_size",
102 [FW_CFG_CMDLINE_DATA] = "cmdline_data",
103 [FW_CFG_SETUP_ADDR] = "setup_addr",
104 [FW_CFG_SETUP_SIZE] = "setup_size",
105 [FW_CFG_SETUP_DATA] = "setup_data",
106 [FW_CFG_FILE_DIR] = "file_dir",
109 if (key & FW_CFG_ARCH_LOCAL) {
110 return fw_cfg_arch_key_name(key);
112 if (key < FW_CFG_FILE_FIRST) {
113 return fw_cfg_wellknown_keys[key];
116 return NULL;
119 static inline const char *trace_key_name(uint16_t key)
121 const char *name = key_name(key);
123 return name ? name : "unknown";
126 #define JPG_FILE 0
127 #define BMP_FILE 1
129 static char *read_splashfile(char *filename, gsize *file_sizep,
130 int *file_typep)
132 GError *err = NULL;
133 gchar *content;
134 int file_type;
135 unsigned int filehead;
136 int bmp_bpp;
138 if (!g_file_get_contents(filename, &content, file_sizep, &err)) {
139 error_report("failed to read splash file '%s': %s",
140 filename, err->message);
141 g_error_free(err);
142 return NULL;
145 /* check file size */
146 if (*file_sizep < 30) {
147 goto error;
150 /* check magic ID */
151 filehead = lduw_le_p(content);
152 if (filehead == 0xd8ff) {
153 file_type = JPG_FILE;
154 } else if (filehead == 0x4d42) {
155 file_type = BMP_FILE;
156 } else {
157 goto error;
160 /* check BMP bpp */
161 if (file_type == BMP_FILE) {
162 bmp_bpp = lduw_le_p(&content[28]);
163 if (bmp_bpp != 24) {
164 goto error;
168 /* return values */
169 *file_typep = file_type;
171 return content;
173 error:
174 error_report("splash file '%s' format not recognized; must be JPEG "
175 "or 24 bit BMP", filename);
176 g_free(content);
177 return NULL;
180 static void fw_cfg_bootsplash(FWCfgState *s)
182 const char *boot_splash_filename = NULL;
183 const char *boot_splash_time = NULL;
184 char *filename, *file_data;
185 gsize file_size;
186 int file_type;
188 /* get user configuration */
189 QemuOptsList *plist = qemu_find_opts("boot-opts");
190 QemuOpts *opts = QTAILQ_FIRST(&plist->head);
191 boot_splash_filename = qemu_opt_get(opts, "splash");
192 boot_splash_time = qemu_opt_get(opts, "splash-time");
194 /* insert splash time if user configurated */
195 if (boot_splash_time) {
196 int64_t bst_val = qemu_opt_get_number(opts, "splash-time", -1);
197 uint16_t bst_le16;
199 /* validate the input */
200 if (bst_val < 0 || bst_val > 0xffff) {
201 error_report("splash-time is invalid,"
202 "it should be a value between 0 and 65535");
203 exit(1);
205 /* use little endian format */
206 bst_le16 = cpu_to_le16(bst_val);
207 fw_cfg_add_file(s, "etc/boot-menu-wait",
208 g_memdup(&bst_le16, sizeof bst_le16), sizeof bst_le16);
211 /* insert splash file if user configurated */
212 if (boot_splash_filename) {
213 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, boot_splash_filename);
214 if (filename == NULL) {
215 error_report("failed to find file '%s'", boot_splash_filename);
216 return;
219 /* loading file data */
220 file_data = read_splashfile(filename, &file_size, &file_type);
221 if (file_data == NULL) {
222 g_free(filename);
223 return;
225 g_free(boot_splash_filedata);
226 boot_splash_filedata = (uint8_t *)file_data;
228 /* insert data */
229 if (file_type == JPG_FILE) {
230 fw_cfg_add_file(s, "bootsplash.jpg",
231 boot_splash_filedata, file_size);
232 } else {
233 fw_cfg_add_file(s, "bootsplash.bmp",
234 boot_splash_filedata, file_size);
236 g_free(filename);
240 static void fw_cfg_reboot(FWCfgState *s)
242 const char *reboot_timeout = NULL;
243 uint64_t rt_val = -1;
244 uint32_t rt_le32;
246 /* get user configuration */
247 QemuOptsList *plist = qemu_find_opts("boot-opts");
248 QemuOpts *opts = QTAILQ_FIRST(&plist->head);
249 reboot_timeout = qemu_opt_get(opts, "reboot-timeout");
251 if (reboot_timeout) {
252 rt_val = qemu_opt_get_number(opts, "reboot-timeout", -1);
254 /* validate the input */
255 if (rt_val > 0xffff && rt_val != (uint64_t)-1) {
256 error_report("reboot timeout is invalid,"
257 "it should be a value between -1 and 65535");
258 exit(1);
262 rt_le32 = cpu_to_le32(rt_val);
263 fw_cfg_add_file(s, "etc/boot-fail-wait", g_memdup(&rt_le32, 4), 4);
266 static void fw_cfg_write(FWCfgState *s, uint8_t value)
268 /* nothing, write support removed in QEMU v2.4+ */
271 static inline uint16_t fw_cfg_file_slots(const FWCfgState *s)
273 return s->file_slots;
276 /* Note: this function returns an exclusive limit. */
277 static inline uint32_t fw_cfg_max_entry(const FWCfgState *s)
279 return FW_CFG_FILE_FIRST + fw_cfg_file_slots(s);
282 static int fw_cfg_select(FWCfgState *s, uint16_t key)
284 int arch, ret;
285 FWCfgEntry *e;
287 s->cur_offset = 0;
288 if ((key & FW_CFG_ENTRY_MASK) >= fw_cfg_max_entry(s)) {
289 s->cur_entry = FW_CFG_INVALID;
290 ret = 0;
291 } else {
292 s->cur_entry = key;
293 ret = 1;
294 /* entry successfully selected, now run callback if present */
295 arch = !!(key & FW_CFG_ARCH_LOCAL);
296 e = &s->entries[arch][key & FW_CFG_ENTRY_MASK];
297 if (e->select_cb) {
298 e->select_cb(e->callback_opaque);
302 trace_fw_cfg_select(s, key, trace_key_name(key), ret);
303 return ret;
306 static uint64_t fw_cfg_data_read(void *opaque, hwaddr addr, unsigned size)
308 FWCfgState *s = opaque;
309 int arch = !!(s->cur_entry & FW_CFG_ARCH_LOCAL);
310 FWCfgEntry *e = (s->cur_entry == FW_CFG_INVALID) ? NULL :
311 &s->entries[arch][s->cur_entry & FW_CFG_ENTRY_MASK];
312 uint64_t value = 0;
314 assert(size > 0 && size <= sizeof(value));
315 if (s->cur_entry != FW_CFG_INVALID && e->data && s->cur_offset < e->len) {
316 /* The least significant 'size' bytes of the return value are
317 * expected to contain a string preserving portion of the item
318 * data, padded with zeros on the right in case we run out early.
319 * In technical terms, we're composing the host-endian representation
320 * of the big endian interpretation of the fw_cfg string.
322 do {
323 value = (value << 8) | e->data[s->cur_offset++];
324 } while (--size && s->cur_offset < e->len);
325 /* If size is still not zero, we *did* run out early, so continue
326 * left-shifting, to add the appropriate number of padding zeros
327 * on the right.
329 value <<= 8 * size;
332 trace_fw_cfg_read(s, value);
333 return value;
336 static void fw_cfg_data_mem_write(void *opaque, hwaddr addr,
337 uint64_t value, unsigned size)
339 FWCfgState *s = opaque;
340 unsigned i = size;
342 do {
343 fw_cfg_write(s, value >> (8 * --i));
344 } while (i);
347 static void fw_cfg_dma_transfer(FWCfgState *s)
349 dma_addr_t len;
350 FWCfgDmaAccess dma;
351 int arch;
352 FWCfgEntry *e;
353 int read = 0, write = 0;
354 dma_addr_t dma_addr;
356 /* Reset the address before the next access */
357 dma_addr = s->dma_addr;
358 s->dma_addr = 0;
360 if (dma_memory_read(s->dma_as, dma_addr,
361 &dma, sizeof(dma), MEMTXATTRS_UNSPECIFIED)) {
362 stl_be_dma(s->dma_as, dma_addr + offsetof(FWCfgDmaAccess, control),
363 FW_CFG_DMA_CTL_ERROR, MEMTXATTRS_UNSPECIFIED);
364 return;
367 dma.address = be64_to_cpu(dma.address);
368 dma.length = be32_to_cpu(dma.length);
369 dma.control = be32_to_cpu(dma.control);
371 if (dma.control & FW_CFG_DMA_CTL_SELECT) {
372 fw_cfg_select(s, dma.control >> 16);
375 arch = !!(s->cur_entry & FW_CFG_ARCH_LOCAL);
376 e = (s->cur_entry == FW_CFG_INVALID) ? NULL :
377 &s->entries[arch][s->cur_entry & FW_CFG_ENTRY_MASK];
379 if (dma.control & FW_CFG_DMA_CTL_READ) {
380 read = 1;
381 write = 0;
382 } else if (dma.control & FW_CFG_DMA_CTL_WRITE) {
383 read = 0;
384 write = 1;
385 } else if (dma.control & FW_CFG_DMA_CTL_SKIP) {
386 read = 0;
387 write = 0;
388 } else {
389 dma.length = 0;
392 dma.control = 0;
394 while (dma.length > 0 && !(dma.control & FW_CFG_DMA_CTL_ERROR)) {
395 if (s->cur_entry == FW_CFG_INVALID || !e->data ||
396 s->cur_offset >= e->len) {
397 len = dma.length;
399 /* If the access is not a read access, it will be a skip access,
400 * tested before.
402 if (read) {
403 if (dma_memory_set(s->dma_as, dma.address, 0, len,
404 MEMTXATTRS_UNSPECIFIED)) {
405 dma.control |= FW_CFG_DMA_CTL_ERROR;
408 if (write) {
409 dma.control |= FW_CFG_DMA_CTL_ERROR;
411 } else {
412 if (dma.length <= (e->len - s->cur_offset)) {
413 len = dma.length;
414 } else {
415 len = (e->len - s->cur_offset);
418 /* If the access is not a read access, it will be a skip access,
419 * tested before.
421 if (read) {
422 if (dma_memory_write(s->dma_as, dma.address,
423 &e->data[s->cur_offset], len,
424 MEMTXATTRS_UNSPECIFIED)) {
425 dma.control |= FW_CFG_DMA_CTL_ERROR;
428 if (write) {
429 if (!e->allow_write ||
430 len != dma.length ||
431 dma_memory_read(s->dma_as, dma.address,
432 &e->data[s->cur_offset], len,
433 MEMTXATTRS_UNSPECIFIED)) {
434 dma.control |= FW_CFG_DMA_CTL_ERROR;
435 } else if (e->write_cb) {
436 e->write_cb(e->callback_opaque, s->cur_offset, len);
440 s->cur_offset += len;
443 dma.address += len;
444 dma.length -= len;
448 stl_be_dma(s->dma_as, dma_addr + offsetof(FWCfgDmaAccess, control),
449 dma.control, MEMTXATTRS_UNSPECIFIED);
451 trace_fw_cfg_read(s, 0);
454 static uint64_t fw_cfg_dma_mem_read(void *opaque, hwaddr addr,
455 unsigned size)
457 /* Return a signature value (and handle various read sizes) */
458 return extract64(FW_CFG_DMA_SIGNATURE, (8 - addr - size) * 8, size * 8);
461 static void fw_cfg_dma_mem_write(void *opaque, hwaddr addr,
462 uint64_t value, unsigned size)
464 FWCfgState *s = opaque;
466 if (size == 4) {
467 if (addr == 0) {
468 /* FWCfgDmaAccess high address */
469 s->dma_addr = value << 32;
470 } else if (addr == 4) {
471 /* FWCfgDmaAccess low address */
472 s->dma_addr |= value;
473 fw_cfg_dma_transfer(s);
475 } else if (size == 8 && addr == 0) {
476 s->dma_addr = value;
477 fw_cfg_dma_transfer(s);
481 static bool fw_cfg_dma_mem_valid(void *opaque, hwaddr addr,
482 unsigned size, bool is_write,
483 MemTxAttrs attrs)
485 return !is_write || ((size == 4 && (addr == 0 || addr == 4)) ||
486 (size == 8 && addr == 0));
489 static bool fw_cfg_data_mem_valid(void *opaque, hwaddr addr,
490 unsigned size, bool is_write,
491 MemTxAttrs attrs)
493 return addr == 0;
496 static uint64_t fw_cfg_ctl_mem_read(void *opaque, hwaddr addr, unsigned size)
498 return 0;
501 static void fw_cfg_ctl_mem_write(void *opaque, hwaddr addr,
502 uint64_t value, unsigned size)
504 fw_cfg_select(opaque, (uint16_t)value);
507 static bool fw_cfg_ctl_mem_valid(void *opaque, hwaddr addr,
508 unsigned size, bool is_write,
509 MemTxAttrs attrs)
511 return is_write && size == 2;
514 static void fw_cfg_comb_write(void *opaque, hwaddr addr,
515 uint64_t value, unsigned size)
517 switch (size) {
518 case 1:
519 fw_cfg_write(opaque, (uint8_t)value);
520 break;
521 case 2:
522 fw_cfg_select(opaque, (uint16_t)value);
523 break;
527 static bool fw_cfg_comb_valid(void *opaque, hwaddr addr,
528 unsigned size, bool is_write,
529 MemTxAttrs attrs)
531 return (size == 1) || (is_write && size == 2);
534 static const MemoryRegionOps fw_cfg_ctl_mem_ops = {
535 .read = fw_cfg_ctl_mem_read,
536 .write = fw_cfg_ctl_mem_write,
537 .endianness = DEVICE_BIG_ENDIAN,
538 .valid.accepts = fw_cfg_ctl_mem_valid,
541 static const MemoryRegionOps fw_cfg_data_mem_ops = {
542 .read = fw_cfg_data_read,
543 .write = fw_cfg_data_mem_write,
544 .endianness = DEVICE_BIG_ENDIAN,
545 .valid = {
546 .min_access_size = 1,
547 .max_access_size = 1,
548 .accepts = fw_cfg_data_mem_valid,
552 static const MemoryRegionOps fw_cfg_comb_mem_ops = {
553 .read = fw_cfg_data_read,
554 .write = fw_cfg_comb_write,
555 .endianness = DEVICE_LITTLE_ENDIAN,
556 .valid.accepts = fw_cfg_comb_valid,
559 static const MemoryRegionOps fw_cfg_dma_mem_ops = {
560 .read = fw_cfg_dma_mem_read,
561 .write = fw_cfg_dma_mem_write,
562 .endianness = DEVICE_BIG_ENDIAN,
563 .valid.accepts = fw_cfg_dma_mem_valid,
564 .valid.max_access_size = 8,
565 .impl.max_access_size = 8,
568 static void fw_cfg_reset(DeviceState *d)
570 FWCfgState *s = FW_CFG(d);
572 /* we never register a read callback for FW_CFG_SIGNATURE */
573 fw_cfg_select(s, FW_CFG_SIGNATURE);
576 /* Save restore 32 bit int as uint16_t
577 This is a Big hack, but it is how the old state did it.
578 Or we broke compatibility in the state, or we can't use struct tm
581 static int get_uint32_as_uint16(QEMUFile *f, void *pv, size_t size,
582 const VMStateField *field)
584 uint32_t *v = pv;
585 *v = qemu_get_be16(f);
586 return 0;
589 static int put_unused(QEMUFile *f, void *pv, size_t size,
590 const VMStateField *field, JSONWriter *vmdesc)
592 fprintf(stderr, "uint32_as_uint16 is only used for backward compatibility.\n");
593 fprintf(stderr, "This functions shouldn't be called.\n");
595 return 0;
598 static const VMStateInfo vmstate_hack_uint32_as_uint16 = {
599 .name = "int32_as_uint16",
600 .get = get_uint32_as_uint16,
601 .put = put_unused,
604 #define VMSTATE_UINT16_HACK(_f, _s, _t) \
605 VMSTATE_SINGLE_TEST(_f, _s, _t, 0, vmstate_hack_uint32_as_uint16, uint32_t)
608 static bool is_version_1(void *opaque, int version_id)
610 return version_id == 1;
613 bool fw_cfg_dma_enabled(void *opaque)
615 FWCfgState *s = opaque;
617 return s->dma_enabled;
620 static bool fw_cfg_acpi_mr_restore(void *opaque)
622 FWCfgState *s = opaque;
623 bool mr_aligned;
625 mr_aligned = QEMU_IS_ALIGNED(s->table_mr_size, qemu_real_host_page_size) &&
626 QEMU_IS_ALIGNED(s->linker_mr_size, qemu_real_host_page_size) &&
627 QEMU_IS_ALIGNED(s->rsdp_mr_size, qemu_real_host_page_size);
628 return s->acpi_mr_restore && !mr_aligned;
631 static void fw_cfg_update_mr(FWCfgState *s, uint16_t key, size_t size)
633 MemoryRegion *mr;
634 ram_addr_t offset;
635 int arch = !!(key & FW_CFG_ARCH_LOCAL);
636 void *ptr;
638 key &= FW_CFG_ENTRY_MASK;
639 assert(key < fw_cfg_max_entry(s));
641 ptr = s->entries[arch][key].data;
642 mr = memory_region_from_host(ptr, &offset);
644 memory_region_ram_resize(mr, size, &error_abort);
647 static int fw_cfg_acpi_mr_restore_post_load(void *opaque, int version_id)
649 FWCfgState *s = opaque;
650 int i, index;
652 assert(s->files);
654 index = be32_to_cpu(s->files->count);
656 for (i = 0; i < index; i++) {
657 if (!strcmp(s->files->f[i].name, ACPI_BUILD_TABLE_FILE)) {
658 fw_cfg_update_mr(s, FW_CFG_FILE_FIRST + i, s->table_mr_size);
659 } else if (!strcmp(s->files->f[i].name, ACPI_BUILD_LOADER_FILE)) {
660 fw_cfg_update_mr(s, FW_CFG_FILE_FIRST + i, s->linker_mr_size);
661 } else if (!strcmp(s->files->f[i].name, ACPI_BUILD_RSDP_FILE)) {
662 fw_cfg_update_mr(s, FW_CFG_FILE_FIRST + i, s->rsdp_mr_size);
666 return 0;
669 static const VMStateDescription vmstate_fw_cfg_dma = {
670 .name = "fw_cfg/dma",
671 .needed = fw_cfg_dma_enabled,
672 .fields = (VMStateField[]) {
673 VMSTATE_UINT64(dma_addr, FWCfgState),
674 VMSTATE_END_OF_LIST()
678 static const VMStateDescription vmstate_fw_cfg_acpi_mr = {
679 .name = "fw_cfg/acpi_mr",
680 .version_id = 1,
681 .minimum_version_id = 1,
682 .needed = fw_cfg_acpi_mr_restore,
683 .post_load = fw_cfg_acpi_mr_restore_post_load,
684 .fields = (VMStateField[]) {
685 VMSTATE_UINT64(table_mr_size, FWCfgState),
686 VMSTATE_UINT64(linker_mr_size, FWCfgState),
687 VMSTATE_UINT64(rsdp_mr_size, FWCfgState),
688 VMSTATE_END_OF_LIST()
692 static const VMStateDescription vmstate_fw_cfg = {
693 .name = "fw_cfg",
694 .version_id = 2,
695 .minimum_version_id = 1,
696 .fields = (VMStateField[]) {
697 VMSTATE_UINT16(cur_entry, FWCfgState),
698 VMSTATE_UINT16_HACK(cur_offset, FWCfgState, is_version_1),
699 VMSTATE_UINT32_V(cur_offset, FWCfgState, 2),
700 VMSTATE_END_OF_LIST()
702 .subsections = (const VMStateDescription*[]) {
703 &vmstate_fw_cfg_dma,
704 &vmstate_fw_cfg_acpi_mr,
705 NULL,
709 static void fw_cfg_add_bytes_callback(FWCfgState *s, uint16_t key,
710 FWCfgCallback select_cb,
711 FWCfgWriteCallback write_cb,
712 void *callback_opaque,
713 void *data, size_t len,
714 bool read_only)
716 int arch = !!(key & FW_CFG_ARCH_LOCAL);
718 key &= FW_CFG_ENTRY_MASK;
720 assert(key < fw_cfg_max_entry(s) && len < UINT32_MAX);
721 assert(s->entries[arch][key].data == NULL); /* avoid key conflict */
723 s->entries[arch][key].data = data;
724 s->entries[arch][key].len = (uint32_t)len;
725 s->entries[arch][key].select_cb = select_cb;
726 s->entries[arch][key].write_cb = write_cb;
727 s->entries[arch][key].callback_opaque = callback_opaque;
728 s->entries[arch][key].allow_write = !read_only;
731 static void *fw_cfg_modify_bytes_read(FWCfgState *s, uint16_t key,
732 void *data, size_t len)
734 void *ptr;
735 int arch = !!(key & FW_CFG_ARCH_LOCAL);
737 key &= FW_CFG_ENTRY_MASK;
739 assert(key < fw_cfg_max_entry(s) && len < UINT32_MAX);
741 /* return the old data to the function caller, avoid memory leak */
742 ptr = s->entries[arch][key].data;
743 s->entries[arch][key].data = data;
744 s->entries[arch][key].len = len;
745 s->entries[arch][key].callback_opaque = NULL;
746 s->entries[arch][key].allow_write = false;
748 return ptr;
751 void fw_cfg_add_bytes(FWCfgState *s, uint16_t key, void *data, size_t len)
753 trace_fw_cfg_add_bytes(key, trace_key_name(key), len);
754 fw_cfg_add_bytes_callback(s, key, NULL, NULL, NULL, data, len, true);
757 void fw_cfg_add_string(FWCfgState *s, uint16_t key, const char *value)
759 size_t sz = strlen(value) + 1;
761 trace_fw_cfg_add_string(key, trace_key_name(key), value);
762 fw_cfg_add_bytes(s, key, g_memdup(value, sz), sz);
765 void fw_cfg_modify_string(FWCfgState *s, uint16_t key, const char *value)
767 size_t sz = strlen(value) + 1;
768 char *old;
770 old = fw_cfg_modify_bytes_read(s, key, g_memdup(value, sz), sz);
771 g_free(old);
774 void fw_cfg_add_i16(FWCfgState *s, uint16_t key, uint16_t value)
776 uint16_t *copy;
778 copy = g_malloc(sizeof(value));
779 *copy = cpu_to_le16(value);
780 trace_fw_cfg_add_i16(key, trace_key_name(key), value);
781 fw_cfg_add_bytes(s, key, copy, sizeof(value));
784 void fw_cfg_modify_i16(FWCfgState *s, uint16_t key, uint16_t value)
786 uint16_t *copy, *old;
788 copy = g_malloc(sizeof(value));
789 *copy = cpu_to_le16(value);
790 old = fw_cfg_modify_bytes_read(s, key, copy, sizeof(value));
791 g_free(old);
794 void fw_cfg_add_i32(FWCfgState *s, uint16_t key, uint32_t value)
796 uint32_t *copy;
798 copy = g_malloc(sizeof(value));
799 *copy = cpu_to_le32(value);
800 trace_fw_cfg_add_i32(key, trace_key_name(key), value);
801 fw_cfg_add_bytes(s, key, copy, sizeof(value));
804 void fw_cfg_modify_i32(FWCfgState *s, uint16_t key, uint32_t value)
806 uint32_t *copy, *old;
808 copy = g_malloc(sizeof(value));
809 *copy = cpu_to_le32(value);
810 old = fw_cfg_modify_bytes_read(s, key, copy, sizeof(value));
811 g_free(old);
814 void fw_cfg_add_i64(FWCfgState *s, uint16_t key, uint64_t value)
816 uint64_t *copy;
818 copy = g_malloc(sizeof(value));
819 *copy = cpu_to_le64(value);
820 trace_fw_cfg_add_i64(key, trace_key_name(key), value);
821 fw_cfg_add_bytes(s, key, copy, sizeof(value));
824 void fw_cfg_modify_i64(FWCfgState *s, uint16_t key, uint64_t value)
826 uint64_t *copy, *old;
828 copy = g_malloc(sizeof(value));
829 *copy = cpu_to_le64(value);
830 old = fw_cfg_modify_bytes_read(s, key, copy, sizeof(value));
831 g_free(old);
834 void fw_cfg_set_order_override(FWCfgState *s, int order)
836 assert(s->fw_cfg_order_override == 0);
837 s->fw_cfg_order_override = order;
840 void fw_cfg_reset_order_override(FWCfgState *s)
842 assert(s->fw_cfg_order_override != 0);
843 s->fw_cfg_order_override = 0;
847 * This is the legacy order list. For legacy systems, files are in
848 * the fw_cfg in the order defined below, by the "order" value. Note
849 * that some entries (VGA ROMs, NIC option ROMS, etc.) go into a
850 * specific area, but there may be more than one and they occur in the
851 * order that the user specifies them on the command line. Those are
852 * handled in a special manner, using the order override above.
854 * For non-legacy, the files are sorted by filename to avoid this kind
855 * of complexity in the future.
857 * This is only for x86, other arches don't implement versioning so
858 * they won't set legacy mode.
860 static struct {
861 const char *name;
862 int order;
863 } fw_cfg_order[] = {
864 { "etc/boot-menu-wait", 10 },
865 { "bootsplash.jpg", 11 },
866 { "bootsplash.bmp", 12 },
867 { "etc/boot-fail-wait", 15 },
868 { "etc/smbios/smbios-tables", 20 },
869 { "etc/smbios/smbios-anchor", 30 },
870 { "etc/e820", 40 },
871 { "etc/reserved-memory-end", 50 },
872 { "genroms/kvmvapic.bin", 55 },
873 { "genroms/linuxboot.bin", 60 },
874 { }, /* VGA ROMs from pc_vga_init come here, 70. */
875 { }, /* NIC option ROMs from pc_nic_init come here, 80. */
876 { "etc/system-states", 90 },
877 { }, /* User ROMs come here, 100. */
878 { }, /* Device FW comes here, 110. */
879 { "etc/extra-pci-roots", 120 },
880 { "etc/acpi/tables", 130 },
881 { "etc/table-loader", 140 },
882 { "etc/tpm/log", 150 },
883 { "etc/acpi/rsdp", 160 },
884 { "bootorder", 170 },
885 { "etc/msr_feature_control", 180 },
887 #define FW_CFG_ORDER_OVERRIDE_LAST 200
891 * Any sub-page size update to these table MRs will be lost during migration,
892 * as we use aligned size in ram_load_precopy() -> qemu_ram_resize() path.
893 * In order to avoid the inconsistency in sizes save them seperately and
894 * migrate over in vmstate post_load().
896 static void fw_cfg_acpi_mr_save(FWCfgState *s, const char *filename, size_t len)
898 if (!strcmp(filename, ACPI_BUILD_TABLE_FILE)) {
899 s->table_mr_size = len;
900 } else if (!strcmp(filename, ACPI_BUILD_LOADER_FILE)) {
901 s->linker_mr_size = len;
902 } else if (!strcmp(filename, ACPI_BUILD_RSDP_FILE)) {
903 s->rsdp_mr_size = len;
907 static int get_fw_cfg_order(FWCfgState *s, const char *name)
909 int i;
911 if (s->fw_cfg_order_override > 0) {
912 return s->fw_cfg_order_override;
915 for (i = 0; i < ARRAY_SIZE(fw_cfg_order); i++) {
916 if (fw_cfg_order[i].name == NULL) {
917 continue;
920 if (strcmp(name, fw_cfg_order[i].name) == 0) {
921 return fw_cfg_order[i].order;
925 /* Stick unknown stuff at the end. */
926 warn_report("Unknown firmware file in legacy mode: %s", name);
927 return FW_CFG_ORDER_OVERRIDE_LAST;
930 void fw_cfg_add_file_callback(FWCfgState *s, const char *filename,
931 FWCfgCallback select_cb,
932 FWCfgWriteCallback write_cb,
933 void *callback_opaque,
934 void *data, size_t len, bool read_only)
936 int i, index, count;
937 size_t dsize;
938 MachineClass *mc = MACHINE_GET_CLASS(qdev_get_machine());
939 int order = 0;
941 if (!s->files) {
942 dsize = sizeof(uint32_t) + sizeof(FWCfgFile) * fw_cfg_file_slots(s);
943 s->files = g_malloc0(dsize);
944 fw_cfg_add_bytes(s, FW_CFG_FILE_DIR, s->files, dsize);
947 count = be32_to_cpu(s->files->count);
948 assert(count < fw_cfg_file_slots(s));
950 /* Find the insertion point. */
951 if (mc->legacy_fw_cfg_order) {
953 * Sort by order. For files with the same order, we keep them
954 * in the sequence in which they were added.
956 order = get_fw_cfg_order(s, filename);
957 for (index = count;
958 index > 0 && order < s->entry_order[index - 1];
959 index--);
960 } else {
961 /* Sort by file name. */
962 for (index = count;
963 index > 0 && strcmp(filename, s->files->f[index - 1].name) < 0;
964 index--);
968 * Move all the entries from the index point and after down one
969 * to create a slot for the new entry. Because calculations are
970 * being done with the index, make it so that "i" is the current
971 * index and "i - 1" is the one being copied from, thus the
972 * unusual start and end in the for statement.
974 for (i = count; i > index; i--) {
975 s->files->f[i] = s->files->f[i - 1];
976 s->files->f[i].select = cpu_to_be16(FW_CFG_FILE_FIRST + i);
977 s->entries[0][FW_CFG_FILE_FIRST + i] =
978 s->entries[0][FW_CFG_FILE_FIRST + i - 1];
979 s->entry_order[i] = s->entry_order[i - 1];
982 memset(&s->files->f[index], 0, sizeof(FWCfgFile));
983 memset(&s->entries[0][FW_CFG_FILE_FIRST + index], 0, sizeof(FWCfgEntry));
985 pstrcpy(s->files->f[index].name, sizeof(s->files->f[index].name), filename);
986 for (i = 0; i <= count; i++) {
987 if (i != index &&
988 strcmp(s->files->f[index].name, s->files->f[i].name) == 0) {
989 error_report("duplicate fw_cfg file name: %s",
990 s->files->f[index].name);
991 exit(1);
995 fw_cfg_add_bytes_callback(s, FW_CFG_FILE_FIRST + index,
996 select_cb, write_cb,
997 callback_opaque, data, len,
998 read_only);
1000 s->files->f[index].size = cpu_to_be32(len);
1001 s->files->f[index].select = cpu_to_be16(FW_CFG_FILE_FIRST + index);
1002 s->entry_order[index] = order;
1003 trace_fw_cfg_add_file(s, index, s->files->f[index].name, len);
1005 s->files->count = cpu_to_be32(count+1);
1006 fw_cfg_acpi_mr_save(s, filename, len);
1009 void fw_cfg_add_file(FWCfgState *s, const char *filename,
1010 void *data, size_t len)
1012 fw_cfg_add_file_callback(s, filename, NULL, NULL, NULL, data, len, true);
1015 void *fw_cfg_modify_file(FWCfgState *s, const char *filename,
1016 void *data, size_t len)
1018 int i, index;
1019 void *ptr = NULL;
1021 assert(s->files);
1023 index = be32_to_cpu(s->files->count);
1025 for (i = 0; i < index; i++) {
1026 if (strcmp(filename, s->files->f[i].name) == 0) {
1027 ptr = fw_cfg_modify_bytes_read(s, FW_CFG_FILE_FIRST + i,
1028 data, len);
1029 s->files->f[i].size = cpu_to_be32(len);
1030 fw_cfg_acpi_mr_save(s, filename, len);
1031 return ptr;
1035 assert(index < fw_cfg_file_slots(s));
1037 /* add new one */
1038 fw_cfg_add_file_callback(s, filename, NULL, NULL, NULL, data, len, true);
1039 return NULL;
1042 bool fw_cfg_add_from_generator(FWCfgState *s, const char *filename,
1043 const char *gen_id, Error **errp)
1045 FWCfgDataGeneratorClass *klass;
1046 GByteArray *array;
1047 Object *obj;
1048 gsize size;
1050 obj = object_resolve_path_component(object_get_objects_root(), gen_id);
1051 if (!obj) {
1052 error_setg(errp, "Cannot find object ID '%s'", gen_id);
1053 return false;
1055 if (!object_dynamic_cast(obj, TYPE_FW_CFG_DATA_GENERATOR_INTERFACE)) {
1056 error_setg(errp, "Object ID '%s' is not a '%s' subclass",
1057 gen_id, TYPE_FW_CFG_DATA_GENERATOR_INTERFACE);
1058 return false;
1060 klass = FW_CFG_DATA_GENERATOR_GET_CLASS(obj);
1061 array = klass->get_data(obj, errp);
1062 if (!array) {
1063 return false;
1065 size = array->len;
1066 fw_cfg_add_file(s, filename, g_byte_array_free(array, FALSE), size);
1068 return true;
1071 void fw_cfg_add_extra_pci_roots(PCIBus *bus, FWCfgState *s)
1073 int extra_hosts = 0;
1075 if (!bus) {
1076 return;
1079 QLIST_FOREACH(bus, &bus->child, sibling) {
1080 /* look for expander root buses */
1081 if (pci_bus_is_root(bus)) {
1082 extra_hosts++;
1086 if (extra_hosts && s) {
1087 uint64_t *val = g_malloc(sizeof(*val));
1088 *val = cpu_to_le64(extra_hosts);
1089 fw_cfg_add_file(s, "etc/extra-pci-roots", val, sizeof(*val));
1093 static void fw_cfg_machine_reset(void *opaque)
1095 MachineClass *mc = MACHINE_GET_CLASS(qdev_get_machine());
1096 FWCfgState *s = opaque;
1097 void *ptr;
1098 size_t len;
1099 char *buf;
1101 buf = get_boot_devices_list(&len);
1102 ptr = fw_cfg_modify_file(s, "bootorder", (uint8_t *)buf, len);
1103 g_free(ptr);
1105 if (!mc->legacy_fw_cfg_order) {
1106 buf = get_boot_devices_lchs_list(&len);
1107 ptr = fw_cfg_modify_file(s, "bios-geometry", (uint8_t *)buf, len);
1108 g_free(ptr);
1112 static void fw_cfg_machine_ready(struct Notifier *n, void *data)
1114 FWCfgState *s = container_of(n, FWCfgState, machine_ready);
1115 qemu_register_reset(fw_cfg_machine_reset, s);
1118 static Property fw_cfg_properties[] = {
1119 DEFINE_PROP_BOOL("acpi-mr-restore", FWCfgState, acpi_mr_restore, true),
1120 DEFINE_PROP_END_OF_LIST(),
1123 static void fw_cfg_common_realize(DeviceState *dev, Error **errp)
1125 FWCfgState *s = FW_CFG(dev);
1126 MachineState *machine = MACHINE(qdev_get_machine());
1127 uint32_t version = FW_CFG_VERSION;
1129 if (!fw_cfg_find()) {
1130 error_setg(errp, "at most one %s device is permitted", TYPE_FW_CFG);
1131 return;
1134 fw_cfg_add_bytes(s, FW_CFG_SIGNATURE, (char *)"QEMU", 4);
1135 fw_cfg_add_bytes(s, FW_CFG_UUID, &qemu_uuid, 16);
1136 fw_cfg_add_i16(s, FW_CFG_NOGRAPHIC, (uint16_t)!machine->enable_graphics);
1137 fw_cfg_add_i16(s, FW_CFG_BOOT_MENU, (uint16_t)boot_menu);
1138 fw_cfg_bootsplash(s);
1139 fw_cfg_reboot(s);
1141 if (s->dma_enabled) {
1142 version |= FW_CFG_VERSION_DMA;
1145 fw_cfg_add_i32(s, FW_CFG_ID, version);
1147 s->machine_ready.notify = fw_cfg_machine_ready;
1148 qemu_add_machine_init_done_notifier(&s->machine_ready);
1151 FWCfgState *fw_cfg_init_io_dma(uint32_t iobase, uint32_t dma_iobase,
1152 AddressSpace *dma_as)
1154 DeviceState *dev;
1155 SysBusDevice *sbd;
1156 FWCfgIoState *ios;
1157 FWCfgState *s;
1158 bool dma_requested = dma_iobase && dma_as;
1160 dev = qdev_new(TYPE_FW_CFG_IO);
1161 if (!dma_requested) {
1162 qdev_prop_set_bit(dev, "dma_enabled", false);
1165 object_property_add_child(OBJECT(qdev_get_machine()), TYPE_FW_CFG,
1166 OBJECT(dev));
1168 sbd = SYS_BUS_DEVICE(dev);
1169 sysbus_realize_and_unref(sbd, &error_fatal);
1170 ios = FW_CFG_IO(dev);
1171 sysbus_add_io(sbd, iobase, &ios->comb_iomem);
1173 s = FW_CFG(dev);
1175 if (s->dma_enabled) {
1176 /* 64 bits for the address field */
1177 s->dma_as = dma_as;
1178 s->dma_addr = 0;
1179 sysbus_add_io(sbd, dma_iobase, &s->dma_iomem);
1182 return s;
1185 FWCfgState *fw_cfg_init_io(uint32_t iobase)
1187 return fw_cfg_init_io_dma(iobase, 0, NULL);
1190 FWCfgState *fw_cfg_init_mem_wide(hwaddr ctl_addr,
1191 hwaddr data_addr, uint32_t data_width,
1192 hwaddr dma_addr, AddressSpace *dma_as)
1194 DeviceState *dev;
1195 SysBusDevice *sbd;
1196 FWCfgState *s;
1197 bool dma_requested = dma_addr && dma_as;
1199 dev = qdev_new(TYPE_FW_CFG_MEM);
1200 qdev_prop_set_uint32(dev, "data_width", data_width);
1201 if (!dma_requested) {
1202 qdev_prop_set_bit(dev, "dma_enabled", false);
1205 object_property_add_child(OBJECT(qdev_get_machine()), TYPE_FW_CFG,
1206 OBJECT(dev));
1208 sbd = SYS_BUS_DEVICE(dev);
1209 sysbus_realize_and_unref(sbd, &error_fatal);
1210 sysbus_mmio_map(sbd, 0, ctl_addr);
1211 sysbus_mmio_map(sbd, 1, data_addr);
1213 s = FW_CFG(dev);
1215 if (s->dma_enabled) {
1216 s->dma_as = dma_as;
1217 s->dma_addr = 0;
1218 sysbus_mmio_map(sbd, 2, dma_addr);
1221 return s;
1224 FWCfgState *fw_cfg_init_mem(hwaddr ctl_addr, hwaddr data_addr)
1226 return fw_cfg_init_mem_wide(ctl_addr, data_addr,
1227 fw_cfg_data_mem_ops.valid.max_access_size,
1228 0, NULL);
1232 FWCfgState *fw_cfg_find(void)
1234 /* Returns NULL unless there is exactly one fw_cfg device */
1235 return FW_CFG(object_resolve_path_type("", TYPE_FW_CFG, NULL));
1239 static void fw_cfg_class_init(ObjectClass *klass, void *data)
1241 DeviceClass *dc = DEVICE_CLASS(klass);
1243 dc->reset = fw_cfg_reset;
1244 dc->vmsd = &vmstate_fw_cfg;
1246 device_class_set_props(dc, fw_cfg_properties);
1249 static const TypeInfo fw_cfg_info = {
1250 .name = TYPE_FW_CFG,
1251 .parent = TYPE_SYS_BUS_DEVICE,
1252 .abstract = true,
1253 .instance_size = sizeof(FWCfgState),
1254 .class_init = fw_cfg_class_init,
1257 static void fw_cfg_file_slots_allocate(FWCfgState *s, Error **errp)
1259 uint16_t file_slots_max;
1261 if (fw_cfg_file_slots(s) < FW_CFG_FILE_SLOTS_MIN) {
1262 error_setg(errp, "\"file_slots\" must be at least 0x%x",
1263 FW_CFG_FILE_SLOTS_MIN);
1264 return;
1267 /* (UINT16_MAX & FW_CFG_ENTRY_MASK) is the highest inclusive selector value
1268 * that we permit. The actual (exclusive) value coming from the
1269 * configuration is (FW_CFG_FILE_FIRST + fw_cfg_file_slots(s)). */
1270 file_slots_max = (UINT16_MAX & FW_CFG_ENTRY_MASK) - FW_CFG_FILE_FIRST + 1;
1271 if (fw_cfg_file_slots(s) > file_slots_max) {
1272 error_setg(errp, "\"file_slots\" must not exceed 0x%" PRIx16,
1273 file_slots_max);
1274 return;
1277 s->entries[0] = g_new0(FWCfgEntry, fw_cfg_max_entry(s));
1278 s->entries[1] = g_new0(FWCfgEntry, fw_cfg_max_entry(s));
1279 s->entry_order = g_new0(int, fw_cfg_max_entry(s));
1282 static Property fw_cfg_io_properties[] = {
1283 DEFINE_PROP_BOOL("dma_enabled", FWCfgIoState, parent_obj.dma_enabled,
1284 true),
1285 DEFINE_PROP_UINT16("x-file-slots", FWCfgIoState, parent_obj.file_slots,
1286 FW_CFG_FILE_SLOTS_DFLT),
1287 DEFINE_PROP_END_OF_LIST(),
1290 static void fw_cfg_io_realize(DeviceState *dev, Error **errp)
1292 ERRP_GUARD();
1293 FWCfgIoState *s = FW_CFG_IO(dev);
1295 fw_cfg_file_slots_allocate(FW_CFG(s), errp);
1296 if (*errp) {
1297 return;
1300 /* when using port i/o, the 8-bit data register ALWAYS overlaps
1301 * with half of the 16-bit control register. Hence, the total size
1302 * of the i/o region used is FW_CFG_CTL_SIZE */
1303 memory_region_init_io(&s->comb_iomem, OBJECT(s), &fw_cfg_comb_mem_ops,
1304 FW_CFG(s), "fwcfg", FW_CFG_CTL_SIZE);
1306 if (FW_CFG(s)->dma_enabled) {
1307 memory_region_init_io(&FW_CFG(s)->dma_iomem, OBJECT(s),
1308 &fw_cfg_dma_mem_ops, FW_CFG(s), "fwcfg.dma",
1309 sizeof(dma_addr_t));
1312 fw_cfg_common_realize(dev, errp);
1315 static void fw_cfg_io_class_init(ObjectClass *klass, void *data)
1317 DeviceClass *dc = DEVICE_CLASS(klass);
1319 dc->realize = fw_cfg_io_realize;
1320 device_class_set_props(dc, fw_cfg_io_properties);
1323 static const TypeInfo fw_cfg_io_info = {
1324 .name = TYPE_FW_CFG_IO,
1325 .parent = TYPE_FW_CFG,
1326 .instance_size = sizeof(FWCfgIoState),
1327 .class_init = fw_cfg_io_class_init,
1331 static Property fw_cfg_mem_properties[] = {
1332 DEFINE_PROP_UINT32("data_width", FWCfgMemState, data_width, -1),
1333 DEFINE_PROP_BOOL("dma_enabled", FWCfgMemState, parent_obj.dma_enabled,
1334 true),
1335 DEFINE_PROP_UINT16("x-file-slots", FWCfgMemState, parent_obj.file_slots,
1336 FW_CFG_FILE_SLOTS_DFLT),
1337 DEFINE_PROP_END_OF_LIST(),
1340 static void fw_cfg_mem_realize(DeviceState *dev, Error **errp)
1342 ERRP_GUARD();
1343 FWCfgMemState *s = FW_CFG_MEM(dev);
1344 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
1345 const MemoryRegionOps *data_ops = &fw_cfg_data_mem_ops;
1347 fw_cfg_file_slots_allocate(FW_CFG(s), errp);
1348 if (*errp) {
1349 return;
1352 memory_region_init_io(&s->ctl_iomem, OBJECT(s), &fw_cfg_ctl_mem_ops,
1353 FW_CFG(s), "fwcfg.ctl", FW_CFG_CTL_SIZE);
1354 sysbus_init_mmio(sbd, &s->ctl_iomem);
1356 if (s->data_width > data_ops->valid.max_access_size) {
1357 s->wide_data_ops = *data_ops;
1359 s->wide_data_ops.valid.max_access_size = s->data_width;
1360 s->wide_data_ops.impl.max_access_size = s->data_width;
1361 data_ops = &s->wide_data_ops;
1363 memory_region_init_io(&s->data_iomem, OBJECT(s), data_ops, FW_CFG(s),
1364 "fwcfg.data", data_ops->valid.max_access_size);
1365 sysbus_init_mmio(sbd, &s->data_iomem);
1367 if (FW_CFG(s)->dma_enabled) {
1368 memory_region_init_io(&FW_CFG(s)->dma_iomem, OBJECT(s),
1369 &fw_cfg_dma_mem_ops, FW_CFG(s), "fwcfg.dma",
1370 sizeof(dma_addr_t));
1371 sysbus_init_mmio(sbd, &FW_CFG(s)->dma_iomem);
1374 fw_cfg_common_realize(dev, errp);
1377 static void fw_cfg_mem_class_init(ObjectClass *klass, void *data)
1379 DeviceClass *dc = DEVICE_CLASS(klass);
1381 dc->realize = fw_cfg_mem_realize;
1382 device_class_set_props(dc, fw_cfg_mem_properties);
1385 static const TypeInfo fw_cfg_mem_info = {
1386 .name = TYPE_FW_CFG_MEM,
1387 .parent = TYPE_FW_CFG,
1388 .instance_size = sizeof(FWCfgMemState),
1389 .class_init = fw_cfg_mem_class_init,
1392 static void fw_cfg_register_types(void)
1394 type_register_static(&fw_cfg_info);
1395 type_register_static(&fw_cfg_io_info);
1396 type_register_static(&fw_cfg_mem_info);
1399 type_init(fw_cfg_register_types)