hw/arm/highbank.c

   1 /*
   2  * Calxeda Highbank SoC emulation
   3  *
   4  * Copyright (c) 2010-2012 Calxeda
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2 or later, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along with
  16  * this program.  If not, see <http://www.gnu.org/licenses/>.
  17  *
  18  */
  19
  20 #include "qemu/osdep.h"
  21 #include "qemu/datadir.h"
  22 #include "qapi/error.h"
  23 #include "hw/sysbus.h"
  24 #include "migration/vmstate.h"
  25 #include "hw/arm/boot.h"
  26 #include "hw/loader.h"
  27 #include "net/net.h"
  28 #include "sysemu/runstate.h"
  29 #include "sysemu/sysemu.h"
  30 #include "hw/boards.h"
  31 #include "qemu/error-report.h"
  32 #include "hw/char/pl011.h"
  33 #include "hw/ide/ahci.h"
  34 #include "hw/cpu/a9mpcore.h"
  35 #include "hw/cpu/a15mpcore.h"
  36 #include "qemu/log.h"
  37 #include "qom/object.h"
  38 #include "cpu.h"
  39
  40 #define SMP_BOOT_ADDR           0x100
  41 #define SMP_BOOT_REG            0x40
  42 #define MPCORE_PERIPHBASE       0xfff10000
  43
  44 #define MVBAR_ADDR              0x200
  45 #define BOARD_SETUP_ADDR        (MVBAR_ADDR + 8 * sizeof(uint32_t))
  46
  47 #define NIRQ_GIC                160
  48
  49 /* Board init.  */
  50
  51 static void hb_write_board_setup(ARMCPU *cpu,
  52                                  const struct arm_boot_info *info)
  53 {
  54     arm_write_secure_board_setup_dummy_smc(cpu, info, MVBAR_ADDR);
  55 }
  56
  57 static void hb_write_secondary(ARMCPU *cpu, const struct arm_boot_info *info)
  58 {
  59     int n;
  60     uint32_t smpboot[] = {
  61         0xee100fb0, /* mrc p15, 0, r0, c0, c0, 5 - read current core id */
  62         0xe210000f, /* ands r0, r0, #0x0f */
  63         0xe3a03040, /* mov r3, #0x40 - jump address is 0x40 + 0x10 * core id */
  64         0xe0830200, /* add r0, r3, r0, lsl #4 */
  65         0xe59f2024, /* ldr r2, privbase */
  66         0xe3a01001, /* mov r1, #1 */
  67         0xe5821100, /* str r1, [r2, #256] - set GICC_CTLR.Enable */
  68         0xe3a010ff, /* mov r1, #0xff */
  69         0xe5821104, /* str r1, [r2, #260] - set GICC_PMR.Priority to 0xff */
  70         0xf57ff04f, /* dsb */
  71         0xe320f003, /* wfi */
  72         0xe5901000, /* ldr     r1, [r0] */
  73         0xe1110001, /* tst     r1, r1 */
  74         0x0afffffb, /* beq     <wfi> */
  75         0xe12fff11, /* bx      r1 */
  76         MPCORE_PERIPHBASE   /* privbase: MPCore peripheral base address.  */
  77     };
  78     for (n = 0; n < ARRAY_SIZE(smpboot); n++) {
  79         smpboot[n] = tswap32(smpboot[n]);
  80     }
  81     rom_add_blob_fixed_as("smpboot", smpboot, sizeof(smpboot), SMP_BOOT_ADDR,
  82                           arm_boot_address_space(cpu, info));
  83 }
  84
  85 static void hb_reset_secondary(ARMCPU *cpu, const struct arm_boot_info *info)
  86 {
  87     CPUARMState *env = &cpu->env;
  88
  89     switch (info->nb_cpus) {
  90     case 4:
  91         address_space_stl_notdirty(&address_space_memory,
  92                                    SMP_BOOT_REG + 0x30, 0,
  93                                    MEMTXATTRS_UNSPECIFIED, NULL);
  94         /* fallthrough */
  95     case 3:
  96         address_space_stl_notdirty(&address_space_memory,
  97                                    SMP_BOOT_REG + 0x20, 0,
  98                                    MEMTXATTRS_UNSPECIFIED, NULL);
  99         /* fallthrough */
 100     case 2:
 101         address_space_stl_notdirty(&address_space_memory,
 102                                    SMP_BOOT_REG + 0x10, 0,
 103                                    MEMTXATTRS_UNSPECIFIED, NULL);
 104         env->regs[15] = SMP_BOOT_ADDR;
 105         break;
 106     default:
 107         break;
 108     }
 109 }
 110
 111 #define NUM_REGS      0x200
 112 static void hb_regs_write(void *opaque, hwaddr offset,
 113                           uint64_t value, unsigned size)
 114 {
 115     uint32_t *regs = opaque;
 116
 117     if (offset == 0xf00) {
 118         if (value == 1 || value == 2) {
 119             qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
 120         } else if (value == 3) {
 121             qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
 122         }
 123     }
 124
 125     if (offset / 4 >= NUM_REGS) {
 126         qemu_log_mask(LOG_GUEST_ERROR,
 127                   "highbank: bad write offset 0x%" HWADDR_PRIx "\n", offset);
 128         return;
 129     }
 130     regs[offset / 4] = value;
 131 }
 132
 133 static uint64_t hb_regs_read(void *opaque, hwaddr offset,
 134                              unsigned size)
 135 {
 136     uint32_t value;
 137     uint32_t *regs = opaque;
 138
 139     if (offset / 4 >= NUM_REGS) {
 140         qemu_log_mask(LOG_GUEST_ERROR,
 141                   "highbank: bad read offset 0x%" HWADDR_PRIx "\n", offset);
 142         return 0;
 143     }
 144     value = regs[offset / 4];
 145
 146     if ((offset == 0x100) || (offset == 0x108) || (offset == 0x10C)) {
 147         value |= 0x30000000;
 148     }
 149
 150     return value;
 151 }
 152
 153 static const MemoryRegionOps hb_mem_ops = {
 154     .read = hb_regs_read,
 155     .write = hb_regs_write,
 156     .endianness = DEVICE_NATIVE_ENDIAN,
 157 };
 158
 159 #define TYPE_HIGHBANK_REGISTERS "highbank-regs"
 160 OBJECT_DECLARE_SIMPLE_TYPE(HighbankRegsState, HIGHBANK_REGISTERS)
 161
 162 struct HighbankRegsState {
 163     /*< private >*/
 164     SysBusDevice parent_obj;
 165     /*< public >*/
 166
 167     MemoryRegion iomem;
 168     uint32_t regs[NUM_REGS];
 169 };
 170
 171 static const VMStateDescription vmstate_highbank_regs = {
 172     .name = "highbank-regs",
 173     .version_id = 0,
 174     .minimum_version_id = 0,
 175     .fields = (VMStateField[]) {
 176         VMSTATE_UINT32_ARRAY(regs, HighbankRegsState, NUM_REGS),
 177         VMSTATE_END_OF_LIST(),
 178     },
 179 };
 180
 181 static void highbank_regs_reset(DeviceState *dev)
 182 {
 183     HighbankRegsState *s = HIGHBANK_REGISTERS(dev);
 184
 185     s->regs[0x40] = 0x05F20121;
 186     s->regs[0x41] = 0x2;
 187     s->regs[0x42] = 0x05F30121;
 188     s->regs[0x43] = 0x05F40121;
 189 }
 190
 191 static void highbank_regs_init(Object *obj)
 192 {
 193     HighbankRegsState *s = HIGHBANK_REGISTERS(obj);
 194     SysBusDevice *dev = SYS_BUS_DEVICE(obj);
 195
 196     memory_region_init_io(&s->iomem, obj, &hb_mem_ops, s->regs,
 197                           "highbank_regs", 0x1000);
 198     sysbus_init_mmio(dev, &s->iomem);
 199 }
 200
 201 static void highbank_regs_class_init(ObjectClass *klass, void *data)
 202 {
 203     DeviceClass *dc = DEVICE_CLASS(klass);
 204
 205     dc->desc = "Calxeda Highbank registers";
 206     dc->vmsd = &vmstate_highbank_regs;
 207     dc->reset = highbank_regs_reset;
 208 }
 209
 210 static const TypeInfo highbank_regs_info = {
 211     .name          = TYPE_HIGHBANK_REGISTERS,
 212     .parent        = TYPE_SYS_BUS_DEVICE,
 213     .instance_size = sizeof(HighbankRegsState),
 214     .instance_init = highbank_regs_init,
 215     .class_init    = highbank_regs_class_init,
 216 };
 217
 218 static void highbank_regs_register_types(void)
 219 {
 220     type_register_static(&highbank_regs_info);
 221 }
 222
 223 type_init(highbank_regs_register_types)
 224
 225 static struct arm_boot_info highbank_binfo;
 226
 227 enum cxmachines {
 228     CALXEDA_HIGHBANK,
 229     CALXEDA_MIDWAY,
 230 };
 231
 232 /* ram_size must be set to match the upper bound of memory in the
 233  * device tree (linux/arch/arm/boot/dts/highbank.dts), which is
 234  * normally 0xff900000 or -m 4089. When running this board on a
 235  * 32-bit host, set the reg value of memory to 0xf7ff00000 in the
 236  * device tree and pass -m 2047 to QEMU.
 237  */
 238 static void calxeda_init(MachineState *machine, enum cxmachines machine_id)
 239 {
 240     DeviceState *dev = NULL;
 241     SysBusDevice *busdev;
 242     qemu_irq pic[128];
 243     int n;
 244     unsigned int smp_cpus = machine->smp.cpus;
 245     qemu_irq cpu_irq[4];
 246     qemu_irq cpu_fiq[4];
 247     qemu_irq cpu_virq[4];
 248     qemu_irq cpu_vfiq[4];
 249     MemoryRegion *sysram;
 250     MemoryRegion *sysmem;
 251     char *sysboot_filename;
 252
 253     switch (machine_id) {
 254     case CALXEDA_HIGHBANK:
 255         machine->cpu_type = ARM_CPU_TYPE_NAME("cortex-a9");
 256         break;
 257     case CALXEDA_MIDWAY:
 258         machine->cpu_type = ARM_CPU_TYPE_NAME("cortex-a15");
 259         break;
 260     default:
 261         assert(0);
 262     }
 263
 264     for (n = 0; n < smp_cpus; n++) {
 265         Object *cpuobj;
 266         ARMCPU *cpu;
 267
 268         cpuobj = object_new(machine->cpu_type);
 269         cpu = ARM_CPU(cpuobj);
 270
 271         object_property_set_int(cpuobj, "psci-conduit", QEMU_PSCI_CONDUIT_SMC,
 272                                 &error_abort);
 273
 274         if (n) {
 275             /* Secondary CPUs start in PSCI powered-down state */
 276             object_property_set_bool(cpuobj, "start-powered-off", true,
 277                                      &error_abort);
 278         }
 279
 280         if (object_property_find(cpuobj, "reset-cbar")) {
 281             object_property_set_int(cpuobj, "reset-cbar", MPCORE_PERIPHBASE,
 282                                     &error_abort);
 283         }
 284         qdev_realize(DEVICE(cpuobj), NULL, &error_fatal);
 285         cpu_irq[n] = qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ);
 286         cpu_fiq[n] = qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_FIQ);
 287         cpu_virq[n] = qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_VIRQ);
 288         cpu_vfiq[n] = qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_VFIQ);
 289     }
 290
 291     sysmem = get_system_memory();
 292     /* SDRAM at address zero.  */
 293     memory_region_add_subregion(sysmem, 0, machine->ram);
 294
 295     sysram = g_new(MemoryRegion, 1);
 296     memory_region_init_ram(sysram, NULL, "highbank.sysram", 0x8000,
 297                            &error_fatal);
 298     memory_region_add_subregion(sysmem, 0xfff88000, sysram);
 299     if (machine->firmware != NULL) {
 300         sysboot_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, machine->firmware);
 301         if (sysboot_filename != NULL) {
 302             if (load_image_targphys(sysboot_filename, 0xfff88000, 0x8000) < 0) {
 303                 error_report("Unable to load %s", machine->firmware);
 304                 exit(1);
 305             }
 306             g_free(sysboot_filename);
 307         } else {
 308             error_report("Unable to find %s", machine->firmware);
 309             exit(1);
 310         }
 311     }
 312
 313     switch (machine_id) {
 314     case CALXEDA_HIGHBANK:
 315         dev = qdev_new("l2x0");
 316         busdev = SYS_BUS_DEVICE(dev);
 317         sysbus_realize_and_unref(busdev, &error_fatal);
 318         sysbus_mmio_map(busdev, 0, 0xfff12000);
 319
 320         dev = qdev_new(TYPE_A9MPCORE_PRIV);
 321         break;
 322     case CALXEDA_MIDWAY:
 323         dev = qdev_new(TYPE_A15MPCORE_PRIV);
 324         break;
 325     }
 326     qdev_prop_set_uint32(dev, "num-cpu", smp_cpus);
 327     qdev_prop_set_uint32(dev, "num-irq", NIRQ_GIC);
 328     busdev = SYS_BUS_DEVICE(dev);
 329     sysbus_realize_and_unref(busdev, &error_fatal);
 330     sysbus_mmio_map(busdev, 0, MPCORE_PERIPHBASE);
 331     for (n = 0; n < smp_cpus; n++) {
 332         sysbus_connect_irq(busdev, n, cpu_irq[n]);
 333         sysbus_connect_irq(busdev, n + smp_cpus, cpu_fiq[n]);
 334         sysbus_connect_irq(busdev, n + 2 * smp_cpus, cpu_virq[n]);
 335         sysbus_connect_irq(busdev, n + 3 * smp_cpus, cpu_vfiq[n]);
 336     }
 337
 338     for (n = 0; n < 128; n++) {
 339         pic[n] = qdev_get_gpio_in(dev, n);
 340     }
 341
 342     dev = qdev_new("sp804");
 343     qdev_prop_set_uint32(dev, "freq0", 150000000);
 344     qdev_prop_set_uint32(dev, "freq1", 150000000);
 345     busdev = SYS_BUS_DEVICE(dev);
 346     sysbus_realize_and_unref(busdev, &error_fatal);
 347     sysbus_mmio_map(busdev, 0, 0xfff34000);
 348     sysbus_connect_irq(busdev, 0, pic[18]);
 349     pl011_create(0xfff36000, pic[20], serial_hd(0));
 350
 351     dev = qdev_new(TYPE_HIGHBANK_REGISTERS);
 352     busdev = SYS_BUS_DEVICE(dev);
 353     sysbus_realize_and_unref(busdev, &error_fatal);
 354     sysbus_mmio_map(busdev, 0, 0xfff3c000);
 355
 356     sysbus_create_simple("pl061", 0xfff30000, pic[14]);
 357     sysbus_create_simple("pl061", 0xfff31000, pic[15]);
 358     sysbus_create_simple("pl061", 0xfff32000, pic[16]);
 359     sysbus_create_simple("pl061", 0xfff33000, pic[17]);
 360     sysbus_create_simple("pl031", 0xfff35000, pic[19]);
 361     sysbus_create_simple("pl022", 0xfff39000, pic[23]);
 362
 363     sysbus_create_simple(TYPE_SYSBUS_AHCI, 0xffe08000, pic[83]);
 364
 365     if (nd_table[0].used) {
 366         qemu_check_nic_model(&nd_table[0], "xgmac");
 367         dev = qdev_new("xgmac");
 368         qdev_set_nic_properties(dev, &nd_table[0]);
 369         sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
 370         sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xfff50000);
 371         sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[77]);
 372         sysbus_connect_irq(SYS_BUS_DEVICE(dev), 1, pic[78]);
 373         sysbus_connect_irq(SYS_BUS_DEVICE(dev), 2, pic[79]);
 374
 375         qemu_check_nic_model(&nd_table[1], "xgmac");
 376         dev = qdev_new("xgmac");
 377         qdev_set_nic_properties(dev, &nd_table[1]);
 378         sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
 379         sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xfff51000);
 380         sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[80]);
 381         sysbus_connect_irq(SYS_BUS_DEVICE(dev), 1, pic[81]);
 382         sysbus_connect_irq(SYS_BUS_DEVICE(dev), 2, pic[82]);
 383     }
 384
 385     /* TODO create and connect IDE devices for ide_drive_get() */
 386
 387     highbank_binfo.ram_size = machine->ram_size;
 388     /* highbank requires a dtb in order to boot, and the dtb will override
 389      * the board ID. The following value is ignored, so set it to -1 to be
 390      * clear that the value is meaningless.
 391      */
 392     highbank_binfo.board_id = -1;
 393     highbank_binfo.nb_cpus = smp_cpus;
 394     highbank_binfo.loader_start = 0;
 395     highbank_binfo.write_secondary_boot = hb_write_secondary;
 396     highbank_binfo.secondary_cpu_reset_hook = hb_reset_secondary;
 397     highbank_binfo.board_setup_addr = BOARD_SETUP_ADDR;
 398     highbank_binfo.write_board_setup = hb_write_board_setup;
 399     highbank_binfo.secure_board_setup = true;
 400
 401     arm_load_kernel(ARM_CPU(first_cpu), machine, &highbank_binfo);
 402 }
 403
 404 static void highbank_init(MachineState *machine)
 405 {
 406     calxeda_init(machine, CALXEDA_HIGHBANK);
 407 }
 408
 409 static void midway_init(MachineState *machine)
 410 {
 411     calxeda_init(machine, CALXEDA_MIDWAY);
 412 }
 413
 414 static void highbank_class_init(ObjectClass *oc, void *data)
 415 {
 416     MachineClass *mc = MACHINE_CLASS(oc);
 417
 418     mc->desc = "Calxeda Highbank (ECX-1000)";
 419     mc->init = highbank_init;
 420     mc->block_default_type = IF_IDE;
 421     mc->units_per_default_bus = 1;
 422     mc->max_cpus = 4;
 423     mc->ignore_memory_transaction_failures = true;
 424     mc->default_ram_id = "highbank.dram";
 425 }
 426
 427 static const TypeInfo highbank_type = {
 428     .name = MACHINE_TYPE_NAME("highbank"),
 429     .parent = TYPE_MACHINE,
 430     .class_init = highbank_class_init,
 431 };
 432
 433 static void midway_class_init(ObjectClass *oc, void *data)
 434 {
 435     MachineClass *mc = MACHINE_CLASS(oc);
 436
 437     mc->desc = "Calxeda Midway (ECX-2000)";
 438     mc->init = midway_init;
 439     mc->block_default_type = IF_IDE;
 440     mc->units_per_default_bus = 1;
 441     mc->max_cpus = 4;
 442     mc->ignore_memory_transaction_failures = true;
 443     mc->default_ram_id = "highbank.dram";
 444 }
 445
 446 static const TypeInfo midway_type = {
 447     .name = MACHINE_TYPE_NAME("midway"),
 448     .parent = TYPE_MACHINE,
 449     .class_init = midway_class_init,
 450 };
 451
 452 static void calxeda_machines_init(void)
 453 {
 454     type_register_static(&highbank_type);
 455     type_register_static(&midway_type);
 456 }
 457
 458 type_init(calxeda_machines_init)